Screening method and device of key layout, equipment and medium

Abstract

The invention discloses a key layout screening method and device, equipment and a medium, and belongs to the field of chip design. The method comprises the following steps: dividing a chip layout into a plurality of candidate layouts; for each candidate layout in the plurality of candidate layouts, collecting layout characteristics of each candidate layout; based on the layout characteristics of each candidate layout, the dispersion degree of each candidate layout is calculated, and the dispersion degree is used for indicating the minimum dot product distance between each candidate layout and other candidate layouts except the candidate layout; and selecting the key layout based on the dispersity of each candidate layout. The dispersion degree of each candidate layout is calculated based on a statistical mode, so that the calculation amount can be effectively reduced. Under the condition that a candidate layout obtained by dividing a chip layout reaches millions to hundred millions, the calculation efficiency is improved in order of magnitude.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip design, and in particular to a method, device, equipment and medium for screening a key layout. Background Art

[0002] As the feature size of very large-scale integrated circuits continues to shrink and has reached the nanometer scale, it is already far below the wavelength of the light source used in the photolithography process, which significantly enhances the interference and diffraction effects, causing the imaging pattern exposed on the wafer through the mask to be distorted and blurred, thereby greatly reducing chip performance and yield.

[0003] Performing optical proximity correction (OPC) on the chip layout to obtain the corresponding photolithography mask is a key technology to solve this problem. Efficient and accurate OPC requires accurate photolithography simulation modeling, that is, establishing an optical model for the optical imaging system, a photoresist model for the post-bake and development process, and an etching model for the etching process. Before modeling, engineers need to screen out a small number of key graphics from the chip layout for experimental measurement to determine the target data for modeling fitting. In order to ensure the efficiency of modeling, the number of screened key layouts needs to be far less than the number of all chip layouts. At the same time, in order to balance the accuracy of modeling, the screened key layouts need to be able to cover the optical properties and geometric features of the entire layout to the maximum extent.

[0004] How to screen key layouts has become an urgent problem that needs to be solved. Summary of the invention

[0005] The present application provides a method, device, equipment and medium for screening a key layout, and the technical solution includes the following contents.

[0006] In one aspect, a method for screening a key layout is provided, the method comprising:

[0007] Divide the chip layout into multiple candidate layouts;

[0008] For each candidate layout among the multiple candidate layouts, collecting layout features of each candidate layout;

[0009] Based on the layout features of each candidate layout, calculating the dispersion of each candidate layout, wherein the dispersion is used to indicate the minimum dot product distance between each candidate layout and other candidate layouts except itself;

[0010] Based on the dispersion of each candidate layout, the key layout is selected.

[0011] On the other hand, a method for screening a key subgraph is provided, the method comprising:

[0012] Divide the original image into multiple candidate sub-images;

[0013] For each candidate subgraph among the multiple candidate subgraphs, collecting subgraph features of each candidate subgraph;

[0014] Based on the subgraph features of each candidate subgraph, calculating the dispersion of each candidate subgraph, wherein the dispersion is used to indicate the minimum dot product distance between each candidate subgraph and other candidate subgraphs except itself;

[0015] The key subgraph is selected based on the dispersion of each candidate subgraph.

[0016] On the other hand, a device for screening a key layout is provided, the device comprising:

[0017] A partitioning module, used for partitioning a chip layout into multiple candidate layouts;

[0018] A feature module, used for collecting layout features of each candidate layout among the multiple candidate layouts;

[0019] A calculation module, used for calculating the dispersion of each candidate layout based on the layout features of each candidate layout, wherein the dispersion is used to indicate the minimum dot product distance between each candidate layout and other candidate layouts except itself;

[0020] A screening module is used to select the key layout based on the dispersion of each candidate layout.

[0021] On the other hand, a device for screening key subgraphs is provided, the device comprising:

[0022] A partitioning module, used for partitioning the original image into multiple candidate sub-images;

[0023] A feature module, configured to collect subgraph features of each candidate subgraph among the multiple candidate subgraphs;

[0024] A calculation module, used to calculate the dispersion of each candidate subgraph based on the subgraph feature of each candidate subgraph, wherein the dispersion is used to indicate the minimum dot product distance between each candidate subgraph and other candidate subgraphs except itself;

[0025] A screening module is used to select the key subgraph based on the dispersion of each candidate subgraph.

[0026] On the other hand, a computer device is provided, comprising a processor and a memory, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor so that the computer device implements the above-mentioned method for screening key graphs, or the method for screening key subgraphs.

[0027] On the other hand, a computer-readable storage medium is also provided, in which at least one computer program is stored, and the at least one computer program is loaded and executed by a processor so that a computer device implements any of the above-mentioned methods for screening key graphs or methods for screening key subgraphs.

[0028] On the other hand, a computer program is also provided, wherein at least one computer program is loaded and executed by a processor so that a computer device implements any of the above-mentioned key layout screening methods.

[0029] On the other hand, a computer program product is also provided, wherein at least one computer program is stored in the computer program product, and the at least one computer program is loaded and executed by a processor so that a computer device implements any of the above-mentioned key layout screening methods.

[0030] The technical solution provided by this application brings at least the following beneficial effects:

[0031] By collecting the layout features of each candidate layout, the dispersion of each candidate layout is calculated based on the layout features of each candidate layout, and then the key layout is selected based on the dispersion. Since the dispersion of each candidate layout is calculated based on a statistical method, compared with the screening method using deep neural networks in related technologies, it can effectively reduce the amount of calculation and increase the calculation speed. When the number of candidate layouts obtained by dividing a chip layout is as high as millions to hundreds of millions, the calculation efficiency is improved by orders of magnitude. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a schematic diagram of a computer system provided in an embodiment of the present application;

[0034] Figure 2 It is a flow chart of a method for screening a key layout provided in an embodiment of the present application;

[0035] Figure 3 It is a schematic diagram of a key layout screening method provided in an embodiment of the present application;

[0036] Figure 4 It is a flow chart of a method for screening a key layout provided in an embodiment of the present application;

[0037] Figure 5 It is a schematic diagram of dividing a chip layout provided in an embodiment of the present application;

[0038] Figure 6 This is a schematic diagram of a checkpoint selection provided by an embodiment of the present application;

[0039] Figure 7 This is a sampling schematic diagram of concentric circle areas provided in an embodiment of the present application;

[0040] Figure 8 It is a schematic diagram of extracting layout features of a candidate layout provided in an embodiment of the present application;

[0041] Fig. 9 It is a performance comparison diagram of a key layout screening method provided in an embodiment of the present application;

[0042] Fig.10 It is a flowchart of a key subgraph screening method provided in an embodiment of the present application;

[0043] Fig.11 It is a flowchart of a key subgraph screening method provided in an embodiment of the present application;

[0044] Fig.12 It is a structural schematic diagram of a key layout screening device provided in an embodiment of the present application;

[0045] Fig.13 It is a structural diagram of a terminal device provided in an embodiment of the present application;

[0046] Fig.14 It is a structural diagram of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0048] Photolithography modeling is to establish an optical model for the optical imaging system, a photoresist model for the post-baking and developing process, and an etching model for the etching process. Before modeling, engineers need to screen out a small number of key layouts (or key layout blocks, key layout areas) from the complete chip layout for experimental measurement to determine the target data for modeling fitting. In order to ensure the efficiency of modeling, the number of key layouts screened must be much less than the number of multiple layout blocks after the chip layout is divided (usually reaching millions to hundreds of millions). At the same time, in order to balance the accuracy of modeling, the screened key layouts need to be able to cover all optical properties and geometric features of the chip layout to the maximum extent.

[0049] Optimizing the mask alone can no longer meet the requirements of integrated circuit manufacturing at nodes below 28nm. Therefore, the industry has proposed the Source and Mask Optimization (SMO) technology to simultaneously optimize the illumination source and the mask pattern, thereby further improving the lithography resolution and increasing the process window. In order to ensure the speed of full-chip SMO, the number of key layouts screened out needs to be far less than the number of all chip layouts. At the same time, in order to balance the effect of full-chip SMO, the key layouts screened out need to be able to cover the lithography imaging characteristics of all layouts to the maximum extent. The screening technology of key layouts will affect the optimization speed and effect of full-chip SMO, and is one of the key technologies of full-chip SMO.

[0050] The parameters in lithography simulation have a significant impact on the final result. However, the amount of calculation for simulation parameter optimization based on the full-chip layout is extremely large and cannot be performed. Therefore, it is necessary to screen out a small number of key graphics from the full-chip layout for simulation parameter optimization. At the same time, in order to ensure the generalization and reliability of the simulation parameters, the screened key layout needs to be able to cover the optical properties and geometric features of the entire layout to the maximum extent.

[0051] Therefore, whether it is lithography modeling, SMO, or parameter optimization of lithography simulation, the screening technology of key layouts is the key technology to ensure the speed and effect of lithography simulation.

[0052] The embodiment of the present application provides a method for screening key layouts, which can quickly complete the screening of key layouts using less calculation amount.

[0053] Figure 1 is a schematic diagram of a computer system provided by some exemplary embodiments of the present application, such as Figure 1 As shown, the system includes a terminal device 101 and a server 102. The method for screening key layouts / key sub-graphs in the embodiment of the present application can be executed by the terminal device 101, can be executed by the server 102, or can be executed by the terminal device 101 and the server 102 together.

[0054] The terminal device 101 may be a smart phone, a desktop computer, a tablet computer, a laptop computer, etc. For example, the terminal device 101 is a computer used by an engineer.

[0055] The server 102 may be a single server, or a server cluster consisting of multiple servers, or any one of a cloud computing platform and a virtualization center, which is not limited in the embodiments of the present application. The server 102 may be connected to the terminal device 101 through a wired network or a wireless network. The server 102 may have functions such as data processing, data storage, and data transmission and reception, which are not limited in the embodiments of the present application. For example, the server 102 stores multiple chip layouts. The terminal device 101 may obtain at least one chip layout from the server 102. For another example, the server 102 stores multiple satellite remote sensing images. The terminal device 101 may obtain at least one remote sensing image from the server 102.

[0056] The number of terminal devices 101 and servers 102 is not limited and can be one or more.

[0057] Figure 2 1 is a flowchart of a method for screening key layouts provided by some exemplary embodiments of the present application. This embodiment is illustrated by taking the method being executed by a computer device as an example. The method includes:

[0058] Step 120: Divide the chip layout into multiple candidate layouts;

[0059] Chip layout includes but is not limited to design layout, mask plate layout, wafer layout, etc. Design layout is also called integrated circuit (IC) design layout. Generally, based on the design layout, the mask plate is photolithographically processed to obtain the mask layout, and based on the mask layout, the wafer is photolithographically processed to obtain the wafer layout.

[0060] The complete chip layout is relatively large, and the chip layout is divided into multiple candidate layouts by a preset method. Each candidate layout is a part of the chip layout. In some embodiments, among the multiple candidate layouts, different candidate layouts do not have an intersection, or different candidate layouts have an intersection, or there is a part of the candidate layouts that do not have an intersection, and another part of the candidate layouts that have an intersection. In some embodiments, the full set of multiple candidate layouts covers all areas of the chip layout.

[0061] In some embodiments, the preset method is a division method of dividing a large image into multiple sub-images. The preset method includes: a matrix division method, a grid division method, an artificial intelligence (AI) division method, etc., which is not limited in the embodiments of the present application.

[0062] The above chip layout is a pixelated layout. Accordingly, the multiple candidate layouts are all pixelated.

[0063] Step 140: for each candidate layout among the multiple candidate layouts, collecting layout features of each candidate layout;

[0064] For each candidate layout among the multiple candidate layouts, layout features of each candidate layout are collected based on features of pixels in each candidate layout.

[0065] The layout feature is used to indicate a graphic feature in a candidate layout. Optionally, the layout feature is used to indicate a graphic feature of an integrated circuit device located in a candidate layout. In some embodiments, the layout feature is rotationally invariant.

[0066] Among them, rotation invariance means that the image features collected when the candidate layout is at the current angle are the same as the image features collected after the candidate layout is rotated by a certain angle.

[0067] Combined with reference Figure 3 When collecting layout features of each candidate layout, the concentric circle area uniform sampling method can be used to collect layout features in each candidate layout. Since the concentric circle area is rotationally invariant, the layout features obtained by uniformly sampling the concentric circle area are also rotationally invariant.

[0068] Step 160: Calculate the dispersion of each candidate layout based on the layout features of each candidate layout;

[0069] The dispersion is used to indicate the minimum dot product distance between each candidate layout and other candidate layouts except itself.

[0070] The layout features of each candidate layout can be expressed as tensor layout features. For each candidate layout, the dot product distance between the candidate layout and other candidate layouts except itself is calculated, and the smallest dot product distance is selected as the dispersion of the candidate layout.

[0071] Step 180: Select a key layout based on the dispersion of each candidate layout.

[0072] Based on the dispersion of each candidate layout, they are arranged in descending order, and the top N candidate layouts are selected as key layouts.

[0073] In summary, the method provided in this embodiment collects the layout features of each candidate layout, calculates the dispersion of each candidate layout based on the layout features of each candidate layout, and then selects the key layout based on the dispersion. Since the dispersion of each candidate layout is calculated based on a statistical method, compared with the AI ​​screening method, it can effectively reduce the amount of calculation and improve the calculation speed. When the candidate layouts obtained by dividing a chip layout are as many as millions to hundreds of millions, the calculation efficiency is significantly improved.

[0074] Figure 4 A flowchart of a method for screening a key layout of an exemplary embodiment of the present application is shown. This embodiment is illustrated by an example in which the method is executed by a computer device. The method includes:

[0075] Step 120: Divide the chip layout into multiple candidate layouts;

[0076] The chip layout includes but is not limited to the design layout, mask plate map, wafer layout, etc. In general, the mask plate is photolithographically processed based on the design layout to obtain the mask layout, and the wafer is photolithographically processed based on the mask layout to obtain the wafer layout.

[0077] The complete chip layout is relatively large, and the chip layout is divided into multiple candidate layouts by a preset method. Each candidate layout is a part of the chip layout. In some embodiments, among the multiple candidate layouts, different candidate layouts do not have an intersection, or different candidate layouts have an intersection, or there is a part of the candidate layouts that do not have an intersection, and another part of the candidate layouts that have an intersection. In some embodiments, the full set of multiple candidate layouts covers all areas of the chip layout.

[0078] In some embodiments, the chip layout is a pixelated layout. Accordingly, multiple candidate layouts are all pixel maps. In some embodiments, the chip layout is a vector map. After being split into multiple candidate layouts, each candidate layout is represented by pixels. In this way, various types of chip layouts such as VIA (contact hole) type chip layouts, logic layouts, and dense line layouts can be represented by pixels. The minimum pixel size is the wavelength of the light source / (4×numerical aperture), which needs to meet the minimum resolution of the lithography machine. Among them, the numerical aperture is the product of the refractive index (n) of the medium between the lens and the object being inspected and the sine of half the aperture angle (2α).

[0079] In some embodiments, a first group of candidate layouts are divided from the chip layout in a grid division manner; a second group of candidate layouts are divided from the chip layout according to the intersection of two adjacent candidate layouts in the first group of candidate layouts as the central axis; and the first group of candidate layouts and the second group of candidate layouts are merged into multiple candidate layouts. Figure 5 , the above method includes at least one of the following divisions:

[0080] Method (1). Divide the chip layout with a length of L1 and a height of H1 into multiple candidate layouts, each of which has a length of L2 and a height of H2. L2 is a divisor of L1, and H2 is a divisor of H1;

[0081] Taking k1=L1 / L2=2, k2=H1 / H2=2 as an example, the chip layout will be divided into four candidate layouts: Figure 1 , Candidate Release Figure 2 , Candidate Release Figure 3 , Candidate Release Figure 4 .

[0082] But since the candidate version Figure 1 , Candidate Release Figure 2 , Candidate Release Figure 3 , Candidate Release Figure 4 There is a boundary line between each of them. If a breakpoint is located exactly on the boundary line, the division method of method (1) may miss the feature extraction of the breakpoint, so at least one of the methods (2) and (3) can be selected. The breakpoint refers to a point where there is a defect on the chip layout.

[0083] Method (2): Using the horizontal boundary line as the central axis, divide k1*(k2-1) candidate layouts;

[0084] The horizontal boundary is the boundary between two adjacent candidate layouts in the upper and lower rows. When k2 rows of candidate layouts are divided in method (1), there are (k2-1) horizontal boundary lines.

[0085] Taking k1 = L1 / L2 = 2, k2 = H1 / H2 = 2 as an example, according to method (2), two candidate layouts will be divided: candidate layout Figure 5 , Candidate Release Figure 6 .

[0086] Method (3). Taking the vertical boundary line as the central axis, divide (k1-1)*(k2) candidate layouts;

[0087] The vertical boundary is the boundary between two adjacent candidate layouts in the left and right columns. When k1 columns of candidate layouts are divided by method (1), there are (k1-1) vertical boundary lines.

[0088] Taking k1 = L1 / L2 = 2, k2 = H1 / H2 = 2 as an example, two candidate layouts will be divided according to method (3): candidate layout Figure 7 , Candidate Release Figure 8 .

[0089] by Figure 5 For example, the chip layout is divided into 8 candidate layouts.

[0090] Optionally, the sizes of multiple candidate layouts are the same, but the situation where the sizes of all or part of the candidate layouts are different is not excluded.

[0091] In some embodiments, the chip layout is converted into a pixel map of pixel representation in advance.

[0092] Step 142: collecting a feature matrix of n checkpoints for each of the multiple candidate layouts, where n is a positive integer;

[0093] The checkpoint is a portion of pixels sampled from each candidate layout. The feature matrix of each checkpoint is used to indicate the pixel features of the current checkpoint, or to indicate the pixel features of the area where the current checkpoint is located. Optionally, this step includes the following sub-steps:

[0094] Step 142-1: for each candidate layout among the plurality of candidate layouts, determine n checkpoints;

[0095] The first number is the number of checkpoints sampled in each candidate layout, which is set to n. In some embodiments, the number of checkpoints sampled in different candidate layouts is the same.

[0096] The n is a preset value or a dynamically determined value. In some embodiments, the n is an empirical value. In some embodiments, the n is determined based on at least one factor of the size of the candidate layout and the average number of devices in the candidate layout. The larger the size of the candidate layout, the larger the n; the smaller the size of the candidate layout, the smaller the n. The more the average number of devices in the candidate layout, the larger the n; the fewer the average number of devices in the candidate layout, the smaller the n. The average number of devices is the average number of integrated circuit devices located in each candidate layout.

[0097] In some embodiments, Figure 6 As shown in each candidate release Fig.12 The edge 122 of the integrated circuit device 121 in the embodiment is sampled to obtain n check points 123.

[0098] For each of the multiple candidate layouts, multiple candidate checkpoints are determined on the edge lines of each candidate layout, and the candidate checkpoints include: at least one of uniformly sampled points and feature points; and n checkpoints are extracted from the multiple candidate checkpoints. That is, the sampling method can be at least one of uniform sampling and feature point sampling. Feature points can be corner points, points with preset pixel features, key points, etc.

[0099] The uniform sampling method may mean: after determining n, obtaining the total edge length of the integrated circuit device in each candidate layout, taking the quotient of the total edge length and n as the step length, uniformly sampling on the edge of the integrated circuit device in each candidate layout to obtain n check points.

[0100] Step 142-2: for the i-th checkpoint among the n checkpoints, determine m concentric circles with the i-th checkpoint as the center;

[0101] For each i checkpoint among the n checkpoints, a second number of concentric circles is determined with the i-th checkpoint as the center. The value range of i is 1 to n. The second number corresponding to different checkpoints is the same, set to m. For example Figure 7 The three concentric circles 124 in FIG.

[0102] The radii of the m concentric circles are all different. Optionally, the radius differences between adjacent concentric circles are the same. Optionally, the radius differences between adjacent concentric circles are different. Exemplarily, in order from the inside to the outside, the radius difference between every two adjacent concentric circles increases according to a geometric progression or an arithmetic progression.

[0103] In some embodiments, the radius difference between some adjacent concentric circles is the same, and the radius difference between some adjacent concentric circles is different. Exemplarily, the multiple concentric circles of each checkpoint include two groups: an inner circle group and an outer circle group. The first radius difference between adjacent concentric circles in the inner circle group is smaller, and the second radius difference between adjacent concentric circles in the outer circle group is larger, that is, the first radius difference is smaller than the second radius difference. The radius of the smallest concentric circle belonging to the outer circle group is larger than the radius of the largest concentric circle belonging to the inner circle group. When the inner circle group includes at least two concentric circles, the radius difference between two adjacent concentric circles is inc1; when the outer circle group includes at least two concentric circles, the radius difference between two adjacent concentric circles is inc2. Among them, inc1 is smaller than inc2.

[0104] In some embodiments, the number of concentric circles m is determined according to the following process:

[0105]

[0106] Here, l is the maximum diameter of the concentric circles belonging to the outer group and is an adjustable parameter, which can be set to 600nm. inc1 and inc2 are the increments of the concentric circle radii of the inner group and the outer group, respectively, which can be set to 5nm and 10nm, in order to comply with the optical proximity effect in lithography. in is the maximum radius of the concentric circles belonging to the inner circle group, which can be selected as 60nm, so the calculated m is 37.

[0107] Step 142-3: On each of the m concentric circles, sample pixel features of p sampling points at equal angles to form a row in the feature matrix of the i-th check point;

[0108] The third quantity is the number of sampling points on each concentric circle, which is set to p. The pixel features of p sampling points are sampled at equal angles on each of the m concentric circles to form a row in the feature matrix of the i-th checkpoint. This step may include the following sub-steps:

[0109] S1. Sample p sampling points at equal angles on each of the m concentric circles;

[0110] For example, 8, 16 or 32 sampling points are sampled on each concentric circle. Figure 7 A plurality of sampling points 125 sampled on each concentric circle in .

[0111] S2. For each of the p sampling points, the statistical value of all pixel values ​​within the surrounding range centered at the sampling point is used as the pixel feature of the sampling point;

[0112] The surrounding range is a circular range, a rectangular range or a square range. In this embodiment, the surrounding range is centered at each sampling point and has a radius of r. s The statistical value of the pixel values ​​of all pixels within.

[0113] Optionally, the statistical value is a summed value or an average value.

[0114] S3. The pixel features of the P sampling points are arranged in the sampling order to form a row in the feature matrix of the i-th checkpoint.

[0115] Step 142-4: Repeat the previous step until a feature matrix with m rows for the i-th checkpoint is obtained.

[0116] refer to Figure 8 , each checkpoint corresponds to m concentric circles, and p sampling points are sampled at equal angles on each of the m concentric circles, and each p sampling point corresponds to a row in the feature matrix. Therefore, the feature matrix of each checkpoint is m*p.

[0117] Step 144: concatenate the feature matrices of the n checkpoints of each candidate layout into layout features of each candidate layout;

[0118] Each release candidate Fig.12 There are n checkpoints, which are spliced ​​into the layout features of each candidate layout in the order of the checkpoints. The number of rows of the layout features is n*m and the number of columns is p.

[0119] Among them, the layout feature of each candidate layout can be represented as a tensor-type layout feature, and the tensor dimension of the tensor-type layout feature is n×m×p.

[0120] Step 162: Calculate the dot product distance between the layout features of each candidate layout and the layout features of other candidate layouts except itself;

[0121] Step 164: For each candidate layout, taking the minimum value of the multiple calculated dot product distances as the dispersion of each candidate layout;

[0122] Calculate the dispersion d of the i-th layout i , the expression is as follows:

[0123]

[0124]

[0125] For example, x i is the one-dimensional feature vector of the layout features of the i-th candidate layout after flattening, x j is the one-dimensional feature vector of the j-th candidate layout after flattening, dist ij is the dot product distance of the one-dimensional feature vectors of the i-th candidate layout and the j-th candidate layout, which is a number. The dispersion d of the i-th candidate layout i It is the minimum dot product distance between the one-dimensional feature vector of the candidate layout and the one-dimensional feature vector of other candidate layouts (such as the j-th candidate layout).

[0126] Step 182: sorting multiple candidate layouts based on the dispersion of each candidate layout;

[0127] Step 184: Determine a predetermined number of candidate layouts ranked in front as key layouts corresponding to the chip layout.

[0128] Exemplarily, T candidate layouts with the largest dispersion are selected as the key layouts for final screening.

[0129] Wherein, T is a fixed value or a dynamic value. In some embodiments, T is a fixed value, such as 1000. In some embodiments, T is determined based on the total number of multiple candidate layouts, such as taking 20% ​​of the total number as the key layout.

[0130] In summary, the method provided in this embodiment collects the layout features of each candidate layout, calculates the dispersion of each candidate layout based on the layout features of each candidate layout, and then selects the key layout based on the dispersion. Since the dispersion of each candidate layout is calculated based on a statistical method, compared with the AI ​​screening method, it can effectively reduce the amount of calculation and improve the calculation speed. When the candidate layouts obtained by dividing a chip layout are as many as millions to hundreds of millions, the calculation efficiency is significantly improved.

[0131] The screening method of key layouts in related technologies usually uses the "deep learning features + Kmeans clustering sampling" method, referred to as "DL+Kmeans"; the embodiment of the present application adopts the "concentric circle area sampling + dispersion sampling" method, referred to as "MCCAS+Diversity". Fig. 9 A schematic diagram comparing the screening method of the related art and the screening method of the embodiment of the present application is shown.

[0132] In order to verify the effect of the above method, the open source chip layout dataset GAN-OPC: (Mask optimization with lithography-guided generative adversarial nets.) is used. Download address: DOI: https: / / doi.org / 10.1145 / 3195970.3196056.

[0133] In order to verify the effectiveness of the above method, this application screened out key layouts from the above open source chip layout data set, and then optimized the OPC parameters based on them to improve the process window, and finally used the optimized OPC parameters to calculate the process window of the mask corresponding to all candidate layouts. The mainstream deep learning feature extraction in related technologies combined with the Kmeans unsupervised clustering sampling method was used as a benchmark to compare the process window and calculation time. Fig. 9 (a) shows the exposure dose deviation versus focus deviation curves of different methods, that is, the maximum focus deviation allowed to ensure imaging fidelity under a fixed exposure dose deviation; the exposure dose deviation allowed to ensure imaging quality under a fixed focus deviation. Therefore, the larger the area enclosed by the curve, the more robust the mask is to changes in the lithography process, and the higher the manufacturing yield can be. Fig. 9 As shown in (a), the process window of the method of the present application is much higher than that of the former. The quantitative results show that when the exposure dose deviation range is within 5%, the focus deviation of the mask generated by the method of the present application must be controlled to be no more than 128.75nm, which is 4.6% higher than the former 123.06nm. When the focus is 0nm, the exposure dose deviation of the mask generated by the method of the present application must be controlled to be no more than 24.3%, which is 5.2% higher than the former 23.1nm. Fig. 9 (b) shows the exposure dose-focus process window of the mask generated by different methods. The photolithography process parameters within the closed curve can guarantee the imaging quality. Therefore, the larger the area, the less sensitive the mask is to the changes in the photolithography process parameters. It can be seen that the mask generated by the method of the present application allows a larger range of changes in the photolithography process parameters than the former. Fig. 9As shown in (c) and (d), the computational efficiency of tensor-based concentric circle area sampling feature extraction and dispersion sampling is 1-2 orders of magnitude higher than that of deep learning feature extraction and Kmeans clustering center sampling, respectively.

[0134] The features extracted by this method are based on concentric circle area sampling, so the rotation invariance of the layout can be guaranteed, so that the screening results are not redundant. This method does not require any expensive and time-consuming machine learning training, which significantly improves the screening efficiency. In addition, this method can greatly reduce the workload of lithography simulation practitioners in manually selecting layouts, and avoid the interference of subjective experience and random blind selection on the final results. This method is based on pixelated chip layouts, so it is suitable for various types of chip layouts such as logic layouts, dense line layouts, and VIA layouts, and has a very high universality. As a new method for efficient image data screening, this method can be extended to image recognition, industrial quality inspection and other fields that require screening of large amounts of image data.

[0135] Based on the same inventive concept, Fig.10 1 is a flowchart of a method for screening key subgraphs provided by some exemplary embodiments of the present application. This embodiment is illustrated by taking the method being executed by a computer device as an example. The method includes:

[0136] Step 220: Divide the original image into a plurality of candidate sub-images;

[0137] The original image may be any one of an input image in the field of image recognition, an image in the field of industrial quality inspection, and an image in the field of satellite remote sensing. The size of the original image is greater than the size threshold.

[0138] The complete original image is relatively large, and the original image is divided into multiple candidate sub-images in a preset manner. Each candidate sub-image is a part of the original image. In some embodiments, among the multiple candidate sub-images, different candidate sub-images do not have intersections, or different candidate sub-images have intersections, or some candidate sub-images do not have intersections, and another part of the candidate sub-images have intersections. In some embodiments, the full set of multiple candidate sub-images covers all areas of the original image.

[0139] In some embodiments, the preset method is a division method of dividing a large image into multiple sub-images. The preset method includes: a matrix division method, a grid division method, an AI division method, etc., which is not limited in the embodiments of the present application.

[0140] The above original image is a pixelated sub-image. Accordingly, the multiple candidate sub-images are all pixelated images.

[0141] Step 240: for each candidate subgraph among the multiple candidate subgraphs, collect subgraph features of each candidate subgraph;

[0142] For each candidate sub-image among the multiple candidate sub-images, a sub-image feature of each candidate sub-image is collected based on features of pixels in each candidate sub-image.

[0143] The sub-image feature is used to indicate a graphic feature in a candidate sub-image. Optionally, the sub-image feature is used to indicate a graphic feature of a pattern texture located in a candidate sub-image. In some embodiments, the sub-image feature has rotation invariance.

[0144] The rotation invariance means that the image features collected when the candidate sub-image is at the current angle are the same as the image features collected after the candidate sub-image is rotated by a certain angle.

[0145] Step 260: Calculate the dispersion of each candidate subgraph based on the subgraph feature of each candidate subgraph;

[0146] The dispersion is used to indicate the minimum dot product distance between each candidate subgraph and other candidate subgraphs except itself.

[0147] The subgraph feature of each candidate subgraph can be expressed as a tensor subgraph feature. For each candidate subgraph, the dot product distance between the candidate subgraph and other candidate subgraphs except itself is calculated, and the smallest dot product distance is selected as the dispersion of the candidate subgraph.

[0148] Step 280: Select a key subgraph based on the dispersion of each candidate subgraph.

[0149] Based on the dispersion of each candidate subgraph, they are arranged in descending order, and the top N candidate subgraphs are selected as key subgraphs.

[0150] In summary, the method provided in this embodiment collects the sub-image features of each candidate sub-image, calculates the dispersion of each candidate sub-image based on the sub-image features of each candidate sub-image, and then selects the key sub-image based on the dispersion. Since the dispersion of each candidate sub-image is calculated based on a statistical method, compared with the neural network method, it can effectively reduce the amount of calculation and improve the calculation speed. When the number of candidate sub-images obtained by dividing an original image is as high as millions to hundreds of millions, the calculation efficiency is significantly improved.

[0151] Fig.11 A flowchart of a method for screening key subgraphs of an exemplary embodiment of the present application is shown. This embodiment is illustrated by taking the method being executed by a computer device as an example. The method includes:

[0152] Step 220: Divide the original image into a plurality of candidate sub-images;

[0153] The original image may be any one of an input image in the field of image recognition, an image in the field of industrial quality inspection, and an image in the field of satellite remote sensing. The size of the original image is greater than the size threshold.

[0154] The complete original image is relatively large, and the original image is divided into multiple candidate sub-images in a preset manner. Each candidate sub-image is a part of the original image. In some embodiments, among the multiple candidate sub-images, different candidate sub-images do not have intersections, or different candidate sub-images have intersections, or some candidate sub-images do not have intersections, and another part of the candidate sub-images have intersections. In some embodiments, the full set of multiple candidate sub-images covers all areas of the original image.

[0155] In some embodiments, the original image is a pixelated sub-image. Accordingly, the plurality of candidate sub-images are all pixel images. In some embodiments, the original image is a vector image, and after being split into a plurality of candidate sub-images, each candidate sub-image is represented by pixelation.

[0156] In some embodiments, a first group of candidate sub-images is divided from the original image in a grid division manner; a second group of candidate sub-images is divided from the original image with a boundary line between two adjacent candidate sub-images in the first group of candidate sub-images as a central axis; and the first group of candidate sub-images and the second group of candidate sub-images are merged into multiple candidate sub-images.

[0157] Step 242: collecting a feature matrix of n checkpoints for each candidate subgraph in the plurality of candidate subgraphs, where n is a positive integer;

[0158] The checkpoint is a portion of pixel points sampled from each candidate sub-image. The feature matrix of each checkpoint is used to indicate the pixel features of the current checkpoint, or to indicate the pixel features of the area where the current checkpoint is located. Optionally, this step includes the following sub-steps:

[0159] Step 242-1: for each candidate subgraph in the plurality of candidate subgraphs, determine n checkpoints;

[0160] The first number is the number of checkpoints sampled in each candidate subgraph, which is set to n. In some embodiments, the number of checkpoints sampled in different candidate subgraphs is the same.

[0161] The n is a preset value or a dynamically determined value. In some embodiments, the n is an empirical value. In some embodiments, the n is determined based on at least one factor of the size of the candidate subgraph and the number of patterns in the candidate subgraph. The larger the size of the candidate subgraph, the larger the n; the smaller the size of the candidate subgraph, the smaller the n. The more the number of clusters in the candidate subgraph, the larger the n; the fewer the number of patterns in the candidate subgraph, the smaller the n.

[0162] In some embodiments, the edge of the pattern texture in each candidate sub-image is sampled to obtain n check points 123. The sampling method can be at least one of uniform sampling and feature point sampling. The feature point can be a corner point or a point with a preset pixel feature.

[0163] For each of the multiple candidate layouts, multiple candidate checkpoints are determined on the edge lines of each candidate layout, and the candidate checkpoints include: at least one of uniformly sampled points and feature points; and n checkpoints are extracted from the multiple candidate checkpoints. That is, the sampling method can be at least one of uniform sampling and feature point sampling. Feature points can be corner points, points with preset pixel features, key points, etc.

[0164] The uniform sampling method may mean that after determining n, the total edge length of the pattern texture in each candidate sub-image is obtained, and n check points are uniformly sampled on the edge of the pattern texture in each candidate sub-image using the quotient of the total edge length and n as the step length.

[0165] Step 242-2: for the i-th checkpoint among the n checkpoints, determine m concentric circles with the i-th checkpoint as the center;

[0166] For each i checkpoint among the n checkpoints, a second number of concentric circles is determined. The value range of i is 1 to n. The second number corresponding to different checkpoints is the same, and is set to m.

[0167] The radii of the m concentric circles are all different. Optionally, the radius differences between adjacent concentric circles are the same. Optionally, the radius differences between adjacent concentric circles are different. Exemplarily, in order from the inside to the outside, the radius difference between every two adjacent concentric circles increases according to a geometric progression or an arithmetic progression.

[0168] In some embodiments, the radius difference between some adjacent concentric circles is the same, and the radius difference between some adjacent concentric circles is different. Exemplarily, the multiple concentric circles of each checkpoint include two groups: an inner circle group and an outer circle group. The radius of the smallest concentric circle belonging to the outer circle group is greater than the radius of the largest concentric circle belonging to the inner circle group. When the inner circle group includes at least two concentric circles, the radius difference between the two adjacent concentric circles is inc1; when the outer circle group includes at least two concentric circles, the radius difference between the two adjacent concentric circles is inc2. Among them, inc1 is smaller than inc2.

[0169] In some embodiments, the number of concentric circles m is determined as follows:

[0170]

[0171] Here, l is the maximum diameter of the concentric circles belonging to the outer group and is an adjustable parameter. inc1 and inc2 are the increments of the radii of the concentric circles of the inner group and the outer group, respectively. in is the maximum radius of the concentric circles belonging to the inner group.

[0172] Step 242-3: On each of the m concentric circles, sample pixel features of P sampling points at equal angles to form a row in the feature matrix of the i-th check point;

[0173] The third quantity is the number of sampling points on each concentric circle, which is set to p. The pixel features of p sampling points are sampled at equal angles on each of the m concentric circles to form a row in the feature matrix of the i-th checkpoint. This step may include the following sub-steps:

[0174] S1. Sample p sampling points at equal angles on each of the m concentric circles;

[0175] Exemplarily, 8, 16 or 32 sampling points are sampled on each concentric circle.

[0176] S2. For each of the p sampling points, the statistical value of all pixel values ​​within the surrounding range centered at the sampling point is used as the pixel feature of the sampling point;

[0177] The surrounding range is a circular range, a rectangular range or a square range. In this embodiment, the surrounding range is centered at each sampling point and has a radius of r. s The statistical value of the pixel values ​​of all pixels within.

[0178] Optionally, the statistical value is a summed value or an average value.

[0179] S3. The pixel features of the P sampling points are arranged in the sampling order to form a row in the feature matrix of the i-th checkpoint.

[0180] Step 242-4: Repeat the previous step until a feature matrix with m rows for the i-th checkpoint is obtained.

[0181] refer to Figure 8 , each checkpoint corresponds to m concentric circles, and p sampling points are sampled at equal angles on each of the m concentric circles, and each p sampling point corresponds to a row in the feature matrix. Therefore, the feature matrix of each checkpoint is m*p.

[0182] Step 244: concatenate the feature matrices of the n checkpoints of each candidate subgraph into the subgraph features of each candidate subgraph;

[0183] Each candidate subgraph has n checkpoints, which are spliced ​​into the subgraph features of each candidate subgraph in the sorting order of the checkpoints. The number of rows of the subgraph features is n*m and the number of columns is p.

[0184] The subgraph feature of each candidate subgraph can be represented as a tensor-type subgraph feature, and the tensor dimension of the tensor-type subgraph feature is n×m×p.

[0185] Step 262: Calculate the dot product distance between the sub-graph feature of each candidate sub-graph and the sub-graph features of other candidate sub-graphs except itself;

[0186] Step 264: For each candidate subgraph, take the minimum value of the multiple calculated dot product distances as the dispersion degree of each candidate subgraph;

[0187] Calculate the dispersion d of the i-th subgraph i , the expression is as follows:

[0188]

[0189]

[0190] For example, x i is the one-dimensional feature vector of the subgraph feature of the i-th candidate subgraph after flattening, x j is the one-dimensional feature vector of the j-th candidate layout after flattening, dist ij is the dot product distance between the one-dimensional feature vectors of the i-th candidate subgraph and the j-th candidate subgraph, which is a number. The dispersion degree d of the i-th candidate subgraph i It is the minimum dot product distance between the one-dimensional feature vector of the candidate subgraph and the one-dimensional feature vectors of other candidate subgraphs.

[0191] Step 282: sorting the multiple candidate subgraphs based on the dispersion of each candidate subgraph;

[0192] Step 284: Determine a predetermined number of candidate sub-images ranked in front as key sub-images corresponding to the original image.

[0193] Exemplarily, T candidate subgraphs with the largest dispersion are selected as the key subgraphs for final screening.

[0194] Wherein, T is a fixed value or a dynamic value. In some embodiments, T is a fixed value, such as 1000. In some embodiments, T is determined based on the total number of multiple candidate subgraphs, such as taking 20% ​​of the total number as key subgraphs.

[0195] In summary, the method provided in this embodiment collects the sub-image features of each candidate sub-image, calculates the dispersion of each candidate sub-image based on the sub-image features of each candidate sub-image, and then selects the key sub-image based on the dispersion. Since the dispersion of each candidate sub-image is calculated based on a statistical method, compared with the AI ​​screening method, it can effectively reduce the amount of calculation and increase the calculation speed. When the number of candidate sub-images obtained by dividing an original image is as high as millions to hundreds of millions, the calculation efficiency is significantly improved.

[0196] In the above embodiment, the chip layout or the original image is divided by grid division as an example. However, different splitting methods may cause some layouts with bad points to be unrecognized, such as when the bad points are exactly on the splitting line. Therefore, the self-attention supervised machine learning method is used to intelligently split the chip layout or the original image, so that each sub-image split out contains the layout with bad points as much as possible, so that the key layout screening can well contain the layout with bad points, thereby improving the efficiency and accuracy of lithography simulation.

[0197] Fig.12 The structure block diagram of a key layout screening device 1200 provided by an exemplary embodiment of the present application is shown. The device includes:

[0198] A division module 1220 is used to divide the chip layout into multiple candidate layouts;

[0199] A feature module 1240 is used to collect layout features of each candidate layout among the multiple candidate layouts;

[0200] A calculation module 1260, configured to calculate the dispersion of each candidate layout based on the layout features of each candidate layout, wherein the dispersion is used to indicate the minimum dot product distance between each candidate layout and other candidate layouts except itself;

[0201] The screening module 1280 is used to select the key layout based on the dispersion of each candidate layout.

[0202] In some embodiments, the feature module 1240 is used to collect a feature matrix of n checkpoints for each candidate layout among the multiple candidate layouts, where n is a positive integer; and to splice the feature matrix of the n checkpoints of each candidate layout into the layout features of each candidate layout.

[0203] In some embodiments, the feature module 1240 is used to determine n checkpoints for each candidate layout among the multiple candidate layouts; for the ith checkpoint among the first number of checkpoints, determine m concentric circles with the ith checkpoint as the center; the value range of i is 1 to n; pixel features of P sampling points are sampled at equal angles on each concentric circle among the m concentric circles to form a row in the feature matrix of the ith checkpoint; repeat the previous step until the feature matrix of the ith checkpoint is obtained.

[0204] In some embodiments, the feature module 1240 is used to determine, for each candidate layout among the multiple candidate layouts, multiple candidate checkpoints on the edge lines of each candidate layout, wherein the candidate checkpoints include: at least one of uniformly sampled points and feature points; and extract n checkpoints from the multiple candidate checkpoints.

[0205] In some embodiments, the feature module 1240 is used to sample P sampling points at equal angles on each of the m concentric circles; for each of the p sampling points, a statistical value of all pixel values ​​within a surrounding range centered on the sampling point is used as a pixel feature of the sampling point; the pixel features of the p sampling points are used to form a row in the feature matrix of the i-th checkpoint in a sampling order; wherein the surrounding range is a circular range, a rectangular range, or a square range.

[0206] In some embodiments, the calculation module 1260 is used to calculate the dot product distance between the layout features of each candidate layout and the layout features of other candidate layouts other than itself; for each candidate layout, the minimum value of the multiple dot product distances calculated is taken as the dispersion of each candidate layout.

[0207] In some embodiments, the screening module 1280 is used to sort the multiple candidate layouts based on the dispersion of each candidate layout; and determine a predetermined number of candidate layouts ranked in front as key layouts corresponding to the chip layout.

[0208] In some embodiments, the partitioning module 1220 is used to partition the chip layout into a first group of candidate layouts in a grid partitioning manner;

[0209] According to the boundary line between two adjacent candidate layouts in the first group of candidate layouts as the central axis, a second group of candidate layouts is divided from the chip layout;

[0210] The first group of candidate layouts and the second group of candidate layouts are merged into the multiple candidate layouts.

[0211] In some embodiments, the device further includes: a conversion module, configured to convert the chip layout into a pixel map of pixel representation.

[0212] It should be understood that the above Fig.12 When the device provided realizes its functions, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0213] In another embodiment, Fig.12 The provided device can be replaced to become a screening device for key subgraphs. The above chip layout can be replaced to become an original image, the above candidate layout can be replaced to become a candidate subgraph, and the above key layout can be replaced to become a key subgraph. The original image can be any one of the input images in the field of image recognition, the images in the field of industrial quality inspection, and the images in the field of satellite remote sensing.

[0214] Fig.13 The structure block diagram of a terminal device 1300 provided by an exemplary embodiment of the present application is shown. The terminal device 1300 includes: a processor 1301 and a memory 1302 .

[0215] The processor 1301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1301 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programable Gate Array), and PLA (Programable Logic Array). The processor 1301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 1301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1301 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0216] The memory 1302 may include one or more computer-readable storage media, which may be non-transitory. The memory 1302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1302 is used to store at least one computer program, which is executed by the processor 1301 to implement the key layout screening method provided in the method embodiment of the present application.

[0217] In some embodiments, the terminal device 1300 may also optionally include: a peripheral device interface 1303 and at least one peripheral device. The processor 1301, the memory 1302 and the peripheral device interface 1303 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 1303 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit 1304, a display screen 1305, a camera assembly 1306, an audio circuit 1307 and a power supply 1308.

[0218] The peripheral device interface 1303 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 1301 and the memory 1302. In some embodiments, the processor 1301, the memory 1302, and the peripheral device interface 1303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 1301, the memory 1302, and the peripheral device interface 1303 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0219] The radio frequency circuit 1304 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 1304 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 1304 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 1304 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The radio frequency circuit 1304 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: the World Wide Web, a metropolitan area network, an intranet, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 1304 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0220] The display screen 1305 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 1305 is a touch display screen, the display screen 1305 also has the ability to collect touch signals on the surface or above the surface of the display screen 1305. The touch signal can be input to the processor 1301 as a control signal for processing. At this time, the display screen 1305 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 1305 can be one, which is set on the front panel of the terminal device 1300; in other embodiments, the display screen 1305 can be at least two, which are respectively set on different surfaces of the terminal device 1300 or are folded; in other embodiments, the display screen 1305 can be a flexible display screen, which is set on the curved surface or folded surface of the terminal device 1300. Even, the display screen 1305 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 1305 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0221] The camera assembly 1306 is used to capture images or videos. Optionally, the camera assembly 1306 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize the panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 1306 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0222] The audio circuit 1307 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 1301 for processing, or input them into the RF circuit 1304 to achieve voice communication. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal device 1300. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 1301 or the RF circuit 1304 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 1307 may also include a headphone jack.

[0223] The power supply 1308 is used to power various components in the terminal device 1300. The power supply 1308 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 1308 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery charged through a wired line, and a wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0224] In some embodiments, the terminal device 1300 further includes one or more sensors 1309 , including but not limited to: an acceleration sensor 1311 , a gyroscope sensor 1312 , a pressure sensor 1313 , an optical sensor 1314 , and a proximity sensor 1315 .

[0225] The acceleration sensor 1311 can detect the magnitude of acceleration on the three coordinate axes of the coordinate system established by the terminal device 1300. For example, the acceleration sensor 1311 can be used to detect the components of gravity acceleration on the three coordinate axes. The processor 1301 can control the display screen 1305 to display the user interface in a horizontal view or a vertical view according to the gravity acceleration signal collected by the acceleration sensor 1311. The acceleration sensor 1311 can also be used to collect motion data of games or users.

[0226] The gyroscope sensor 1312 can detect the body direction and rotation angle of the terminal device 1300, and the gyroscope sensor 1312 can cooperate with the acceleration sensor 1311 to collect the user's 3D actions on the terminal device 1300. The processor 1301 can implement the following functions based on the data collected by the gyroscope sensor 1312: motion sensing (such as changing the UI according to the user's tilt operation), image stabilization during shooting, game control, and inertial navigation.

[0227] The pressure sensor 1313 can be set on the side frame of the terminal device 1300 and / or the lower layer of the display screen 1305. When the pressure sensor 1313 is set on the side frame of the terminal device 1300, the user's holding signal of the terminal device 1300 can be detected, and the processor 1301 performs left and right hand recognition or shortcut operations according to the holding signal collected by the pressure sensor 1313. When the pressure sensor 1313 is set on the lower layer of the display screen 1305, the processor 1301 controls the operability controls on the UI interface according to the user's pressure operation on the display screen 1305. The operability controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0228] The optical sensor 1314 is used to collect the ambient light intensity. In one embodiment, the processor 1301 can control the display brightness of the display screen 1305 according to the ambient light intensity collected by the optical sensor 1314. Specifically, when the ambient light intensity is high, the display brightness of the display screen 1305 is increased; when the ambient light intensity is low, the display brightness of the display screen 1305 is reduced. In another embodiment, the processor 1301 can also dynamically adjust the shooting parameters of the camera assembly 1306 according to the ambient light intensity collected by the optical sensor 1314.

[0229] The proximity sensor 1315, also called a distance sensor, is usually arranged on the front panel of the terminal device 1300. The proximity sensor 1315 is used to collect the distance between the user and the front of the terminal device 1300. In one embodiment, when the proximity sensor 1315 detects that the distance between the user and the front of the terminal device 1300 is gradually decreasing, the processor 1301 controls the display screen 1305 to switch from the screen-on state to the screen-off state; when the proximity sensor 1315 detects that the distance between the user and the front of the terminal device 1300 is gradually increasing, the processor 1301 controls the display screen 1305 to switch from the screen-off state to the screen-on state.

[0230] Those skilled in the art will understand that Fig.13 The structure shown in the figure does not constitute a limitation on the terminal device 1300, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0231] Fig.14 The schematic diagram of the structure of the server provided in the embodiment of the present application, the server 1400 may have relatively large differences due to different configurations or performances, and may include one or more processors 1401 and one or more memories 1402, wherein the one or more memories 1402 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 1401 to implement the key layout screening method provided by the above-mentioned various method embodiments. Exemplarily, the processor 1401 is a CPU. Of course, the server 1400 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 1400 may also include other components for implementing device functions, which will not be described in detail here.

[0232] In an exemplary embodiment, a computer-readable storage medium is also provided, in which at least one computer program is stored. The at least one computer program is loaded and executed by a processor so that a computer device implements any of the above-mentioned key layout screening methods or key sub-graph screening methods.

[0233] In an exemplary embodiment, a computer program is also provided. The computer program is at least one, and the at least one computer program is loaded and executed by a processor to enable a computer device to implement any of the above-mentioned key layout screening methods or key sub-graph screening methods.

[0234] In an exemplary embodiment, a computer program product is also provided, in which at least one computer program is stored, and the at least one computer program is loaded and executed by a processor so that a computer device implements any of the above-mentioned key layout screening methods or key sub-graph screening methods.

[0235] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0236] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0237] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for screening a key layout, characterized in that: The method comprises: Divide the chip layout into multiple candidate layouts; For each candidate layout among the multiple candidate layouts, collecting layout features of each candidate layout; Based on the layout features of each candidate layout, calculating the dispersion of each candidate layout, wherein the dispersion is used to indicate the minimum dot product distance between each candidate layout and other candidate layouts except itself; Based on the dispersion of each candidate layout, the key layout is selected.

2. The method according to claim 1, characterized in that The collecting of layout features of each candidate layout among the plurality of candidate layouts includes: Collecting a feature matrix of n checkpoints for each of the multiple candidate layouts, where n is a positive integer; The feature matrices of the n checkpoints of each candidate layout are concatenated into layout features of each candidate layout.

3. The method according to claim 2, characterized in that The step of collecting a feature matrix of n checkpoints for each of the plurality of candidate layouts includes: For each candidate layout among the multiple candidate layouts, determining n checkpoints; For the i-th checkpoint among the n checkpoints, m concentric circles with the i-th checkpoint as the center are determined; i is an integer not greater than n, and m is a positive integer; Sample pixel features of P sampling points at equal angles on each concentric circle in the m-th concentric circle to form a row in the feature matrix of the i-th check point, where P is a positive integer; Repeat the previous step until the feature matrix of the i-th checkpoint is obtained.

4. The method according to claim 3, characterized in that The pixel features of P sampling points sampled at equal angles on each of the m concentric circles constitute a row in the feature matrix of the i-th check point, including: Sampling P sampling points at equal angles on each of the m concentric circles; For each of the P sampling points, a statistical value of all pixel values ​​within a range around the sampling point as a pixel feature of the sampling point; The pixel features of the P sampling points are used to form a row in the feature matrix of the i-th check point according to the sampling order; The circumferential range is one of a circular range, a rectangular range and a square range.

5. The method according to claim 2, characterized in that: Determining n checkpoints for each candidate layout among the multiple candidate layouts includes: For each candidate layout among the multiple candidate layouts, determining multiple candidate check points on edge lines of each candidate layout, wherein the candidate check points include: at least one of uniformly sampled points and feature points; From the multiple candidate checkpoints, n checkpoints are extracted.

6. The method according to any one of claims 1 to 4, characterized in that: The calculating the dispersion of each candidate layout based on the layout features of each candidate layout includes: Calculating the dot product distance between the layout features of each candidate layout and the layout features of other candidate layouts except itself; For each candidate layout, the minimum value among the multiple calculated dot product distances is taken as the dispersion degree of each candidate layout.

7. The method according to any one of claims 1 to 4, characterized in that: The step of selecting the key layout based on the dispersion of each candidate layout comprises: Sorting the multiple candidate layouts based on the dispersion of each candidate layout; A predetermined number of candidate layouts ranked in front are determined as key layouts corresponding to the chip layout.

8. The method according to any one of claims 1 to 4, characterized in that: The step of dividing the chip layout into a plurality of candidate layouts includes: Divide the chip layout into a first group of candidate layouts according to a grid division method; According to the boundary line between two adjacent candidate layouts in the first group of candidate layouts as the central axis, a second group of candidate layouts is divided from the chip layout; The first group of candidate layouts and the second group of candidate layouts are merged into the multiple candidate layouts.

9. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: The chip layout is converted into a pixel map of a pixelated representation.

10. A method for screening key subgraphs, characterized in that: The method comprises: Divide the original image into multiple candidate sub-images; For each candidate sub-graph in the plurality of candidate layouts, collecting sub-graph features of each candidate sub-graph; Based on the subgraph features of each candidate subgraph, calculating the dispersion of each candidate subgraph, wherein the dispersion is used to indicate the minimum dot product distance between each candidate subgraph and other candidate subgraphs except itself; The key subgraph is selected based on the dispersion of each candidate subgraph.

11. A device for screening key layouts, characterized in that: The device comprises: A partitioning module, used for partitioning a chip layout into multiple candidate layouts; A feature module, used for collecting layout features of each candidate layout among the multiple candidate layouts; A calculation module, used for calculating the dispersion of each candidate layout based on the layout features of each candidate layout, wherein the dispersion is used to indicate the minimum dot product distance between each candidate layout and other candidate layouts except itself; A screening module is used to select the key layout based on the dispersion of each candidate layout.

12. A device for screening key subgraphs, characterized in that: The device comprises: A partitioning module, used for partitioning the original image into multiple candidate sub-images; A feature module, configured to collect subgraph features of each candidate subgraph among the multiple candidate subgraphs; A calculation module, used to calculate the dispersion of each candidate subgraph based on the subgraph feature of each candidate subgraph, wherein the dispersion is used to indicate the minimum dot product distance between each candidate subgraph and other candidate subgraphs except itself; A screening module is used to select the key subgraph based on the dispersion of each candidate subgraph.

13. A computer device, characterized in that: The computer device includes a processor and a memory, wherein at least one computer program is stored in the memory, and the at least one computer program is loaded and executed by the processor so that the computer device implements the key layout screening method as described in any one of claims 1 to 9, or the key subgraph screening method as described in claim 10.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by the processor so that the computer device implements the key layout screening method as described in any one of claims 1 to 9, or the key sub-graph screening method as described in claim 10.

15. A computer program product, characterized in that The computer program product stores at least one computer program, and the at least one computer program is loaded and executed by a processor so that a computer device implements a method for screening key layouts as described in any one of claims 1 to 9, or a method for screening key subgraphs as described in claim 10.

Images