Standard cell layout generation method, library establishment method, device, equipment and medium

Abstract

The invention provides a standard cell layout generation method and device, a library establishment method and device, equipment and a medium, and relates to the technical field of computers. The standard cell layout generation method comprises the following steps: acquiring a hardware description language and a driving capability of a to-be-drawn standard cell; compiling the hardware description language based on a preset sub-logic structure library to obtain a sub-logic combination netlist file of the to-be-drawn standard unit; wherein the sub-logic combination netlist file is used for describing sub-logic structures forming the standard unit to be drawn and the combination relation between the sub-logic structures; the sub-logic structure library comprises a plurality of sub-logic structures, the sub-logic structures are obtained by splitting a logic unit, each sub-logic structure corresponds to description data, and the description data comprises a sub-logic structure netlist file and a sub-logic structure layout file; and obtaining the layout of the standard unit to be drawn based on the sub-logic combination netlist file, the sub-logic structure library and the driving capability.

Description

Technical Field

[0001] The present application relates to the technical field of computers, and in particular to a standard cell layout generation method, library establishment method, device, equipment and medium. Background Art

[0002] In the current integrated circuit design in the industry, standard cells composed of a certain number of transistors are considered to be the smallest building blocks of VLSI design. Among them, standard cells include inverters, AND gates, registers, selectors, full adders and other basic units. When drawing the integrated circuit layout, the layout of each standard cell in the preset standard cell library can be directly combined to obtain the integrated circuit layout.

[0003] However, for the same standard cell, the standard cell library usually only stores a few commonly used implementation methods and corresponding layouts, but these commonly used implementation methods may not meet actual usage requirements. Summary of the invention

[0004] The present application provides a standard cell layout generation method, library establishment method, device, equipment and medium, so that the layout of the standard cell can better meet the applicable requirements.

[0005] In a first aspect, the present application provides a method for generating a standard cell layout, comprising: obtaining a hardware description language and a driving capability of a standard cell to be drawn; compiling the hardware description language based on a preset sub-logic structure library to obtain a sub-logic combination netlist file of the standard cell to be drawn; wherein the sub-logic combination netlist file is used to describe the sub-logic structures constituting the standard cell to be drawn and the combination relationship between the sub-logic structures; the sub-logic structure library includes multiple sub-logic structures, and the multiple logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting logic cells, and each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file; based on the sub-logic combination netlist file, the sub-logic structure library, and the driving capability, the layout of the standard cell to be drawn is obtained.

[0006] In the embodiment of the present application, since the sub-logic structure library includes multiple sub-logic structures, the hardware description language is compiled based on the sub-logic structure library, and the obtained sub-logic combination netlist file describes the standard unit to be drawn through the target sub-logic combination. At the same time, since the sub-logic structure library does not directly store basic logic units, but stores sub-logic structures obtained by splitting logic units, when obtaining the target sub-logic structure combination, the sub-logic structures can come from different logic units, so compared with the direct standard unit layout method, this solution can obtain more implementation methods of the layout of the standard unit to be drawn, so as to adapt to different usage requirements.

[0007] In combination with the technical solution provided in the first aspect above, in some possible implementations, the sub-logical structure library is obtained by: acquiring multiple logic units; splitting each of the logic units into an N-type sub-logical structure and a P-type sub-logical structure; wherein the N-type sub-logical structure is the N-type transistor part in the logic unit, and the P-type sub-logical structure is the P-type transistor part in the logic unit; storing the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units into the sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

[0008] In the embodiment of the present application, the sub-logic structure is obtained by splitting the logic unit into an N-type sub-logic structure and a P-type sub-logic structure, so as to facilitate the subsequent combination of at least one logic structure to obtain a sub-logic combination. In addition, the description data of each sub-logic structure includes a sub-logic structure netlist file and a sub-logic structure layout file, so as to facilitate the subsequent combination of the target sub-logic structure to obtain the layout of the standard unit to be drawn.

[0009] In combination with the technical solution provided in the first aspect above, in some possible implementations, the description data of each sub-logical structure includes at least one sub-logical structure netlist file; when the description data of the same sub-logical structure includes multiple sub-logical structure netlist files, the multiple sub-logical structure netlist files corresponding to the same sub-logical structure have different driving capabilities.

[0010] In the embodiment of the present application, since multiple sub-logic structure netlist files corresponding to the same sub-logic structure have different driving capabilities, the sub-logic structure can be applied to scenarios with different driving capability requirements, so that the present solution can generate layouts of standard cells with different driving capabilities.

[0011] In combination with the technical solution provided in the first aspect above, in some possible implementations, the same sub-logical structure netlist file corresponds to at least one sub-logical structure layout file of the corresponding sub-logical structure; wherein, when the same sub-logical structure netlist file corresponds to multiple sub-logical structure layout files, each of the sub-logical structure layout files belongs to a different standard unit layout framework.

[0012] In an embodiment of the present application, since the same sub-logical structure netlist file corresponds to multiple sub-logical structure layout files belonging to different standard unit layout frameworks, this solution can be used to generate layouts that meet different standard unit layout frameworks, thereby improving the scope of application of this solution.

[0013] In combination with the technical solution provided in the first aspect above, in some possible implementations, the description data also includes at least one of characteristic data of each sub-logical structure layout file and a circuit structure diagram.

[0014] In the embodiment of the present application, since the description data also includes the circuit structure diagram of each sub-logic structure, the standard cell library obtained by this solution can be applied to more scenarios, thereby improving the scope of application of this solution. Since the characteristic data characterizes the circuit characteristics of the entire circuit corresponding to the sub-logic structure layout file, the most suitable sub-logic structure can be screened through the characteristic data, so that the final layout can better meet the actual use requirements of the standard cell to be drawn.

[0015] In combination with the technical solution provided in the first aspect above, in some possible implementations, the method further includes: obtaining the logical level of each of the logical units; accordingly, storing the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logical units in a sub-logical structure library includes: for each of the logical units, storing the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to the logical unit in a storage area in the sub-logical structure library that matches the logical level of the logical unit.

[0016] In the embodiment of the present application, the sub-logic structures are classified by the logic levels of the logic units, so that when used, sub-logic structure combinations under different logic levels can be selected according to actual needs to obtain sub-logic combinations, thereby balancing the logic integration and electrical characteristics such as path transmission delay of the final layout.

[0017] In a second aspect, the present application provides a sub-logic structure library, comprising: multiple sub-logic structures, wherein the multiple sub-logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting logic units, and each sub-logic structure corresponds to a sub-logic structure netlist file and a sub-logic structure layout file.

[0018] In a third aspect, the present application provides a method for establishing a sub-logical structure library, comprising: obtaining multiple logic units; splitting each of the logic units into an N-type sub-logical structure and a P-type sub-logical structure; wherein the N-type sub-logical structure is the N-type transistor part in the logic unit, and the P-type sub-logical structure is the P-type transistor part in the logic unit; storing the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units into a sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

[0019] In a fourth aspect, the present application provides a standard cell layout generation device, including: a first acquisition module and a first processing module, the first acquisition module is used to obtain the hardware description language and driving capability of the standard cell to be drawn; the first processing module is used to compile the hardware description language based on a preset sub-logic structure library to obtain a sub-logic combination netlist file of the standard cell to be drawn; wherein the sub-logic combination netlist file is used to describe the sub-logic structures constituting the standard cell to be drawn and the combination relationship between the sub-logic structures; the sub-logic structure library includes multiple sub-logic structures, and the multiple sub-logic structures in the sub-logic structure library are based on the sub-logic structure included The transistor type is divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting logic units, and each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file; the first processing module is also used to obtain the layout of the standard unit to be drawn based on the sub-logic combination netlist file, the sub-logic structure library, and the driving capability.

[0020] In a fifth aspect, the present application provides a sub-logical structure library establishment device, comprising: a second acquisition module and a second processing module, the second acquisition module is used to acquire multiple logic units; the second processing module is used to split each of the logic units into an N-type sub-logical structure and a P-type sub-logical structure; wherein the N-type sub-logical structure is the N-type transistor part in the logic unit, and the P-type sub-logical structure is the P-type transistor part in the logic unit; the second processing module is also used to store the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units into a sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

[0021] In a sixth aspect, the present application provides an electronic device, comprising: a memory and a processor, the memory and the processor being connected; the memory being used to store programs; the processor being used to call the programs stored in the memory to execute the method described in the first aspect above and / or in combination with any possible implementation of the first aspect above, or to execute the method described in the third aspect above.

[0022] In a seventh aspect, the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, it executes the method described in the first aspect above and / or in combination with any possible implementation of the first aspect above, or executes the method described in the third aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a flow chart of a method for generating a standard cell layout according to an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a process for establishing a sub-logical structure library shown in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of a split logic unit shown in an embodiment of the present application;

[0027] Figure 4 A sub-logical structure table shown in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of a sub-logical structure library shown in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of a sub-logical structure layout file fusion shown in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of an association relationship between a sub-logic structure library and a standard cell library shown in an embodiment of the present application;

[0031] Figure 8 A schematic diagram of generating a standard cell library based on a sub-logic structure library according to an embodiment of the present application;

[0032] Fig. 9 A structural block diagram of a standard cell layout generation device shown in an embodiment of the present application;

[0033] Fig.10 A structural block diagram of a sub-logical structure library establishment device shown in an embodiment of the present application;

[0034] Fig.11 A structural block diagram of an electronic device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0036] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it is not necessary to further define and explain it in the subsequent drawings. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0037] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0038] See also Figure 1 , Figure 1This is a flow chart of a method for generating a standard cell layout according to an embodiment of the present application. Figure 1 Describe the steps it involves.

[0039] S110: Obtain the hardware description language and driving capability of the standard unit to be drawn.

[0040] The driving capability includes various parameters of transistors constituting the voltage circuit, such as the size and threshold voltage of the transistors.

[0041] The hardware description language and driver capability of the standard unit to be drawn can be pre-acquired and stored in a local storage medium, and can be directly called when needed. Alternatively, the hardware description language and driver capability of the standard unit to be drawn can also be obtained from a third-party device in real time when needed.

[0042] The specific implementation methods and principles of the driving capabilities and hardware description language are well known to those skilled in the art and will not be described in detail here for the sake of brief description.

[0043] S120: Compiling the hardware description language based on the preset sub-logic structure library to obtain a sub-logic combinational netlist file of the standard unit to be drawn.

[0044] Among them, the sub-logic combination netlist file is used to describe the sub-logic structures that constitute the standard unit to be drawn and the combination relationship between the sub-logic structures (hereinafter referred to as the sub-logic structures that constitute the standard unit to be drawn are the target sub-logic structure combination); the sub-logic structure library includes a sub-logic structure library including multiple sub-logic structures, and the multiple sub-logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic.

[0045] Each sub-logic included in the N-type transistor sub-logic structure library includes only N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library includes only P-type transistors, and the sub-logic structure is obtained by splitting the logic unit. Each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file.

[0046] The sub-logic structure refers to a structure separated from a logic unit, and the combination relationship between the sub-logic structures is the way in which the sub-logic structures are combined to obtain the standard unit to be drawn.

[0047] Since the sub-logic structure library includes multiple sub-logic structures, the hardware description language is compiled based on the sub-logic structure library, and the obtained sub-logic combinational netlist file can be implemented through the sub-logic structure library.

[0048] The method for compiling the hardware description language may be any existing method for compiling the hardware description language, as long as the input library used for the compilation is a sub-logical structure library.

[0049] In one implementation manner, the description data of each sub-logical structure includes at least one sub-logical structure netlist file.

[0050] Optionally, the description data of each sub-logical structure includes a plurality of sub-logical structure netlist files, wherein the plurality of sub-logical structure netlist files corresponding to the same sub-logical structure have different driving capabilities.

[0051] Since multiple sub-logic structure netlist files corresponding to the same sub-logic structure have different driving capabilities, the sub-logic structure can be applied to scenarios with different driving capability requirements, so that the present solution can generate layouts of standard cells with different driving capabilities.

[0052] The driving capability includes various parameters of transistors constituting the voltage circuit, such as the size and threshold voltage of the transistors.

[0053] In one implementation manner, a same sub-logical structure netlist file corresponds to at least one sub-logical structure layout file of the corresponding sub-logical structure.

[0054] Optionally, when a same sub-logic structure netlist file corresponds to a plurality of sub-logic structure layout files, each sub-logic structure layout file belongs to a different standard cell layout framework.

[0055] The standard cell layout frame may include a standard cell height and a height multiple. Different standard cell layout frames may have different standard cell heights and / or height multiples.

[0056] The multiple sub-logic structure layout files corresponding to the same sub-logic structure netlist file in different quasi-unit layout frameworks can be drawn manually, or can be automatically generated according to the circuit structure netlist file based on the layout automatic placement and routing tool.

[0057] Since the same sub-logic structure netlist file corresponds to multiple sub-logic structure layout files belonging to different standard unit layout frameworks, this solution can be used to generate layouts that meet different standard unit layout frameworks, thereby improving the scope of application of this solution.

[0058] In one implementation, the description data also includes at least one of characteristic data of each sub-logic structure layout file and a circuit structure diagram.

[0059] Since the description data also includes the circuit structure diagram of each sub-logic structure, the standard cell library obtained by this solution can be applied to more scenarios, thereby improving the scope of application of this solution. Since the feature data represents the circuit characteristics of the entire circuit corresponding to the layout file, the most suitable sub-logic structure can be screened through the feature data, so that the final layout can better meet the actual use requirements of the standard cell to be drawn.

[0060] The characteristic data of each layout file can be obtained according to each layout file. The specific method of obtaining the characteristic data corresponding to the layout according to the layout is well known to those skilled in the art, and will not be repeated here for the sake of brief description.

[0061] Optionally, the characteristic data may include: layout area occupancy, number of virtual gates, parasitic resistance of each node in the sub-circuit, parasitic capacitance, delay time corresponding to the gate-level node to the sub-circuit port, flip time corresponding to the gate-level node to the sub-circuit port, dynamic power consumption corresponding to the gate-level node to the sub-circuit port, and static power consumption corresponding to the gate-level node state.

[0062] The circuit structure diagram is a circuit diagram corresponding to the sub-logic structure and composed of symbols of electronic components such as transistors.

[0063] The sub-logical structure library can be obtained from a third party, or the sub-logical structure library can be based on Figure 2 The steps shown are obtained.

[0064] like Figure 2 As shown, Figure 2 A method for constructing a sub-logical structure library is shown. Figure 2 Describe the steps it involves.

[0065] S210: Acquire multiple logical units.

[0066] The logic unit is a circuit that can implement one-order or multi-order logic calculations. The logic calculation is AND calculation, OR calculation, NOT calculation, AND NOT calculation, OR NOT calculation, XOR calculation, XNOR calculation, etc., and is not limited to the calculation types exemplified here.

[0067] S220: Split each logic unit into an N-type sub-logic structure and a P-type sub-logic structure.

[0068] Among them, the N-type sub-logic structure is the N-type transistor part in the logic unit, and the P-type sub-logic structure is the P-type transistor part in the logic unit.

[0069] When each logic unit is split into an N-type sub-logic structure and a P-type sub-logic structure, it is necessary to define the signal type (or connection mode) of each port of the N-type sub-logic structure and the P-type sub-logic structure, for example, input signal, output signal, power supply, grounding, etc., so as to facilitate the subsequent determination of the connection relationship of the combination of each sub-logic structure.

[0070] For ease of understanding, Figure 3 The logic unit shown is used as an example for explanation.

[0071] like Figure 3 As shown, the logic unit is composed of two parallel PMOS tubes and two series NMOS tubes. Therefore, it is split into a P-type sub-logic structure composed of two parallel PMOS tubes ( Figure 3 The two PMOS tubes framed by the dotted line) and the N-type sub-logic structure composed of two series-connected NMOS tubes ( Figure 3 Two NMOS tubes framed by dotted lines).

[0072] In addition, the sources of the two PMOS tubes in the P-type sub-logic structure are used to connect to the power supply ( Figure 3 The drains of the two PMOS tubes are used to output the output signal ( Figure 3 The gates of the two PMOS tubes are used to receive two input signals for logic operations ( Figure 3 B1, B2 shown).

[0073] The drain of the first NMOS tube in the N-type sub-logic structure is used to output the output signal ( Figure 3 F), the source of the first NMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is used for grounding ( Figure 3 The gates of the two NMOS transistors are used to receive two input signals for logic operations ( Figure 3 B1, B2 shown).

[0074] The examples given here are only for ease of understanding and should not be regarded as limitations on this application.

[0075] S230: storing the N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each logical unit into a sub-logical structure library to obtain a sub-logical structure library.

[0076] The description data includes a sub-logic structure netlist file and a sub-logic structure layout file.

[0077] Optionally, the N-type sub-logical structures and the P-type sub-logical structures may be classified and stored in the sub-logical structure library.

[0078] Optionally, the description data of each sub-logical structure may be obtained from a third party. Alternatively, the description data of each sub-logical structure may also be obtained based on the sub-logical structure.

[0079] The method of obtaining description data based on the sub-logic structure may be to first generate sub-logic structure netlist files of different driving capabilities based on the sub-logic structure. Then, for each sub-logic structure netlist file, manually draw the sub-logic structure layout file of the sub-logic structure netlist file under each standard unit layout framework; or, it may be to generate sub-logic structure layout files under different standard unit layout frameworks according to the sub-logic structure netlist file through a layout automatic placement and routing tool.

[0080] Optionally, if the sub-logic structure library also includes a parasitic parameter file corresponding to each sub-logic structure layout file, the corresponding parasitic parameter file can be obtained according to the sub-logic structure layout file. The specific method and principle of obtaining the parasitic parameter file according to the layout file are well known to those skilled in the art, and will not be repeated here for the sake of brief description.

[0081] Optionally, after obtaining the sub-logic structure layout file of the sub-logic structure netlist file under each standard cell layout framework, each sub-logic structure layout file may be functionally verified to determine whether the sub-logic structure layout file can be used normally.

[0082] Optionally, after obtaining the sub-logic structure layout file of the sub-logic structure netlist file under each standard unit layout framework, each sub-logic structure layout file can also be optimized, and the sub-logic structure layout file is iterated according to the set optimization requirements until the final sub-logic structure layout file meets the set optimization requirements.

[0083] The type of optimization requirement may be one or more of the aforementioned characteristic data, and the specific type of optimization requirement is not limited here.

[0084] The specific method of optimizing the layout file is well known to those skilled in the art and will not be described in detail here for the sake of brevity.

[0085] In one implementation, the sub-logical structures in the sub-logical structure library can also be classified and stored according to the logical levels corresponding to the sub-logical structures, wherein the logical level corresponding to the sub-logical structure is the logical level of the logical unit corresponding to the sub-logical structure.

[0086] In this implementation, the number of logical levels of each logical unit can also be obtained. Accordingly, the method of storing the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each logical unit in the sub-logical structure library can be: for each logical unit, the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to the logical unit are stored in the storage area in the sub-logical structure library that matches the number of logical levels of the logical unit.

[0087] The logic level number of a logic unit is the number of logic units included in the logic unit. The specific calculation method of the logic level number is well known to those skilled in the art and will not be repeated here for the sake of brief description.

[0088] For ease of understanding, a plurality of logic units including logic unit 1, logic unit 2, and logic unit 3 are taken as an example. Among them, logic unit 1 is used to calculate the AND operation of signal A and signal B. Logic unit 2 is used to calculate the AND operation of signal A and signal B, and then calculate the sum operation of the result of the AND operation and signal C. Logic unit 3 calculates the AND operation of signal A and signal B, and then calculates the sum operation of the result of the AND operation and signal C, and finally calculates the XOR operation of the result of the sum operation and signal D. Therefore, the logic level of logic unit 1 is 1, the logic level of logic unit 2 is 2, and the logic level of logic unit 3 is 3.

[0089] After splitting logic unit 1 into N-type sub-logic structure 1 and P-type sub-logic structure 1, splitting logic unit 2 into N-type sub-logic structure 2 and P-type sub-logic structure 2, and splitting logic unit 3 into N-type sub-logic structure 3 and P-type sub-logic structure 3, N-type sub-logic structure 1 is stored in a storage area corresponding to a first-order logic level in the N-type sub-logic structure library, N-type sub-logic structure 2 is stored in a storage area corresponding to a second-order logic level in the N-type sub-logic structure library, and N-type sub-logic structure 3 is stored in a storage area corresponding to a third-order logic level in the N-type sub-logic structure library.

[0090] Similarly, the P-type sub-logic structure 1 is stored in the storage area corresponding to the first-order logic level in the P-type sub-logic structure library, the P-type sub-logic structure 2 is stored in the storage area corresponding to the second-order logic level in the P-type sub-logic structure library, and the P-type sub-logic structure 3 is stored in the storage area corresponding to the third-order logic level in the P-type sub-logic structure library.

[0091] The examples given here are only for ease of understanding and should not be construed as limiting the present application.

[0092] In order to facilitate understanding of the specific way in which the sub-logical structures in the above-mentioned sub-logical structure library are classified and stored according to the logical levels corresponding to the sub-logical structures, please refer to Figure 4 .

[0093] like Figure 4 As shown, the sub-logic structures in the sub-logic structure library are classified according to the number of logic levels corresponding to the sub-logic structures and also according to the transistor types included.

[0094] Figure 4 The sub-logic structure library shown includes the first-order logic INV (also known as NOT gate), ND2 (NAND gate), NR2 (NOR gate), NR3 (NOR gate), and the second-order logic An AN2into an OR2, An OR2 into an AN2, Two-AN2 into an OR2, Two-OR2 into an AN2.

[0095] Figure 4 Each sub-logic structure shown is obtained by splitting up the logic units.

[0096] Figure 4 The sub-logic structure shown is only for ease of understanding. The actual implementation method and logic level of the sub-logic structure are not limited to Figure 4 By way of example.

[0097] To understand the specific implementation of the above sub-logic structure library, please refer to Figure 4 .

[0098] like Figure 5 As shown, the sub-logic structure library includes multiple sub-logic structures, each of which corresponds to a sub-logic structure hardware description language. Each sub-logic structure hardware description language corresponds to a sub-logic structure netlist file (or circuit structure) with multiple different driving capabilities. Each circuit structure corresponds to a sub-logic structure layout file under a different standard cell layout framework. Each sub-logic structure layout file corresponds to feature data.

[0099] S130: Based on the sub-logic combinational netlist file, the sub-logic structure library, and the driving capability, a layout of the standard cell to be drawn is obtained.

[0100] After obtaining a sub-logic combination netlist file according to the hardware description language of the standard cell to be drawn, the target sub-logic structure combination can be obtained from the sub-logic combination netlist file.

[0101] In the first implementation mode, each sub-logic structure includes multiple sub-logic structure layout files, and the multiple sub-logic structure layout files are generated according to the sub-logic structure netlist files of the sub-logic structure, and N sub-logic structure layout files corresponding to N standard cell layout frameworks are generated for each sub-logic structure netlist file, where N is a positive integer. Based on the sub-logic combination netlist file, the sub-logic structure library, and the driving capability, the specific method for obtaining the layout of the standard cell to be drawn can be: first, the target sub-logic structure layout files of each sub-logic structure possessed by the target sub-logic structure combination are obtained from the sub-logic structure library; the target sub-logic structure layout file is the sub-logic structure layout file corresponding to the target sub-logic structure netlist file matching the driving capability of the standard cell to be drawn. Then, according to the connection relationship between the sub-logic structures specified in the sub-logic structure netlist file of the target sub-logic structure combination, the target sub-logic structure layout files of each sub-logic structure are spliced ​​and merged into the layout of the standard cell to be drawn. Among them, each target sub-logic structure layout file that is spliced ​​and merged is a layout file corresponding to the same standard unit layout framework. Therefore, the layout file of the standard unit to be drawn under N standard unit layout frameworks is finally spliced.

[0102] The standard cell layout frame may include a standard cell height and a height multiple. Different standard cell layout frames may have different standard cell heights and / or height multiples.

[0103] For ease of understanding, N=2, and the target sub-logic structure combination includes sub-logic structure 1, sub-logic structure 2, and sub-logic structure 3. First, obtain the sub-logic structure layout file 1 (the layout file corresponding to sub-logic structure 1), sub-logic structure layout file 2 (the layout file corresponding to sub-logic structure 2), and sub-logic structure layout file 3 (the layout file corresponding to sub-logic structure 3) corresponding to the driving capability of the standard cell to be drawn from the sub-logic structure library. Then, according to the connection relationship of sub-logic structure 1, sub-logic structure 2, and sub-logic structure 3 defined in the sub-logic combination netlist file, the sub-logic structure layout file 1, the sub-logic structure layout file 2, and the sub-logic structure layout file 3 are spliced ​​and merged to obtain the layout of the standard cell to be drawn.

[0104] In one implementation, the target sub-logic structure layout files of each sub-logic structure are spliced ​​and merged into the layout of the standard unit to be drawn by directly splicing the target sub-logic structure layout files of each sub-logic structure according to the connection method to obtain the layout of the standard unit to be drawn.

[0105] Alternatively, the target sub-logic structure layout files of each sub-logic structure may be spliced ​​and merged into the layout of the standard unit to be drawn by treating the target sub-logic structure layout files of some sub-logic structures as a whole and then replacing one or more transistors in the target sub-logic structure layout files of another sub-logic structure.

[0106] In order to facilitate understanding of the specific implementation method of treating the target sub-logic structure layout file of a part of the sub-logic structure as a whole and then replacing one or more transistors in the target sub-logic structure layout file of another part of the sub-logic structure, Figure 6 This is explained with an example.

[0107] like Figure 6 As shown, the layout of and(A, B) (that is, two MOS tubes connected in series) is merged with the layout of or(C, D) (that is, two MOS tubes connected in parallel) to realize the circuit of (A&B)or C.

[0108] Merge and(A, B) and or(C, D), that is, replace D in or(C, D) with and(A, B). In the circuit, it is reflected by replacing the MOS tube for receiving the D signal in the two parallel MOS tubes with two series MOS tubes, thus obtaining the fused circuit.

[0109] When performing layout fusion, the layout of and(A, B) is first regarded as a whole, and then the layout part corresponding to transistor D in or(C, D) is replaced by it to obtain the layout of (A&B)or C.

[0110] Since the transistor has corresponding drain and source positions in the layout, and the layout of and(A, B) is regarded as a whole, it also has a drain and a source. Therefore, the connection method of the drain of the and(A, B) layout is the same as the connection method of the drain of the transistor receiving the D signal. Similarly, the connection method of the source of the and(A, B) layout is the same as the connection method of the source of the transistor receiving the D signal. Therefore, the layout of the transistor receiving the D signal in or(C, D) is replaced by the layout of and(A, B) to obtain the layout of (A&B)or C.

[0111] The examples given here are only for ease of understanding and should not be construed as limiting the present application.

[0112] In one implementation manner, N is a constant greater than or equal to 2; then the method for obtaining the target sub-logic structure layout files of each sub-logic structure of the target sub-logic structure combination from the sub-logic structure library is: obtaining all sub-logic structure layout files of each sub-logic structure of the target sub-logic structure combination under N standard cell layout frameworks from the sub-logic structure library.

[0113] Accordingly, according to the connection relationship between sub-logic structures specified in the sub-logic structure netlist file of the target sub-logic structure combination, the target sub-logic structure layout files of each sub-logic structure are spliced ​​and merged into the layout of the standard cell to be drawn: for each standard cell layout framework, the sub-logic structure layout files of each sub-logic structure included in the target sub-logic combination under the standard cell layout framework are spliced ​​and merged according to the connection relationship between sub-logic structures specified in the target sub-logic structure combination netlist file, and the layout of the standard cell to be drawn under the standard cell layout framework is obtained. That is, N layouts of the standard cell to be drawn under N standard cell layout frameworks are finally obtained.

[0114] In one implementation, after obtaining N layouts of the standard cell to be drawn, it is also possible to calculate the characteristic data of each layout in the N layouts based on the characteristic data of each of the target sub-logical structure layout files constituting the layout, and store each layout in the N layouts of the standard cell to be drawn and the characteristic data corresponding to each layout in a preset standard cell library.

[0115] The characteristic data of the layout can be calculated through the characteristic data of the target sub-logic structure layout file, thereby reducing the difficulty of calculating the characteristic data of the standard unit to be drawn. At the same time, each layout and the characteristic data corresponding to each layout are stored in the preset standard cell library, which can facilitate the subsequent direct call of the layout and characteristic data of the standard unit to be drawn, improving the user experience.

[0116] For ease of understanding, take N=2, and the target sub-logical structure combination includes sub-logical structure 1, sub-logical structure 2, and sub-logical structure 3 as an example.

[0117] First, obtain the sub-logic structure layout file 11 of the sub-logic structure 1 in the first standard cell layout framework, and the sub-logic structure layout file 12 of the sub-logic structure 1 in the second standard cell layout framework. Also obtain the sub-logic structure layout file 21 of the sub-logic structure 2 in the first standard cell layout framework, and the sub-logic structure layout file 22 of the sub-logic structure 2 in the second standard cell layout framework. Obtain the sub-logic structure layout file 31 of the sub-logic structure 3 in the first standard cell layout framework, and the sub-logic structure layout file 32 of the sub-logic structure 3 in the second standard cell layout framework.

[0118] Then the sub-logic structure Fig.11 , sub-logic structure layout 21, and sub-logic structure layout 31 are spliced ​​and merged according to the connection relationship between the sub-logic structures specified in the target sub-logic structure combination netlist file to obtain the layout of the standard cell to be drawn under the first standard cell layout framework.

[0119] And the sub-logic structure layout 12, the sub-logic structure layout 22, and the sub-logic structure layout 32 are spliced ​​and merged according to the connection relationship between the sub-logic structures specified in the target sub-logic structure combination netlist file to obtain the layout of the standard cell to be drawn under the second standard cell layout framework. Thus, the layout of the standard cell to be drawn under the two standard cell layout frameworks is obtained. The examples here are only for ease of understanding and should not be used as a limitation to this application.

[0120] In one implementation manner, after obtaining N layouts of the standard cell to be drawn, one layout may be selected from the N layouts as the final layout of the standard cell to be drawn.

[0121] Optionally, a layout may be randomly selected from the N layouts of the standard cell to be drawn as the final layout of the standard cell to be drawn.

[0122] Alternatively, based on the characteristic data of each of the N layouts, a target layout whose characteristic data best meets the requirements of the standard cell to be drawn can be selected from the N layouts as the final layout of the standard cell to be drawn. The characteristic data represents the circuit characteristics of the entire circuit corresponding to the layout.

[0123] The characteristic data of each of the N layouts of the standard cell to be drawn can be obtained according to the layout of the standard cell to be drawn, or can be calculated by the characteristic data corresponding to each of all the target sub-logical structure layout files corresponding to each layout. The characteristic data corresponding to the target sub-logical structure layout file is obtained in advance according to the target sub-logical structure layout file.

[0124] Among them, the specific method of obtaining the characteristic data corresponding to the layout according to the layout, and the specific method of calculating the characteristic data of the complete circuit according to the characteristic data of multiple sub-circuits constituting the complete circuit are already well known to those skilled in the art and will not be repeated here for the sake of brief description.

[0125] Optionally, the characteristic data may include: layout area occupancy, number of virtual gates, parasitic resistance of each node in the sub-logic structure, parasitic capacitance, delay time corresponding to the gate-level node to the sub-logic structure port, flip time corresponding to the gate-level node to the sub-logic structure port, dynamic power consumption corresponding to the gate-level node to the sub-logic structure port, and static power consumption corresponding to the gate-level node state.

[0126] Correspondingly, when a target layout whose characteristic data best meets the requirements of the standard cell to be drawn is selected from N layouts as the final layout of the standard cell to be drawn, the characteristic data may be one or more of the above, which is not limited here.

[0127] In the second implementation mode, each sub-logic structure includes multiple sub-logic structure layout files, and the multiple sub-logic structure layout files are generated according to the sub-logic structure netlist files of the sub-logic structure, and N sub-logic structure layout files corresponding to N standard cell layout frameworks are generated for each sub-logic structure netlist file, where N is a positive integer. In this case, based on the sub-logic combination netlist file, the sub-logic structure library, and the driving capability, the specific method for obtaining the layout of the standard cell to be drawn can be: first, for each standard cell layout framework, according to the characteristic data of each sub-logic structure possessed by the target sub-logic structure combination and the framework parameters of the standard cell layout framework, the characteristic data of the target sub-logic structure combination under the standard cell layout framework is determined; the characteristic data of the sub-logic structure represents the circuit characteristics of the sub-logic structure; the characteristic data of the target sub-logic structure combination represents the circuit characteristics of the target sub-logic structure combination as a whole. Then, from the characteristic data of the target sub-logic structure combination under the N standard cell layout frameworks, the target characteristic data whose characteristic data best meets the requirements of the standard cell to be drawn is selected. Finally, the target sub-logic structure layout files corresponding to the target standard cell layout frame in each sub-logic structure are spliced ​​and merged according to the connection relationship between the sub-logic structures specified in the sub-logic structure combination netlist file to obtain the layout of the standard cell to be drawn. Among them, the target standard cell layout frame is the standard cell layout frame corresponding to the target feature data.

[0128] For ease of understanding, N=2, and the target sub-logical structure combination includes sub-logical structure 1, sub-logical structure 2, and sub-logical structure 3. In the first standard cell layout framework, sub-logical structure 1 corresponds to sub-logical structure layout file 11, sub-logical structure 2 corresponds to sub-logical structure layout file 21, and sub-logical structure 3 corresponds to sub-logical structure layout file 31. In the second standard cell layout framework, sub-logical structure 1 corresponds to sub-logical structure layout file 12, sub-logical structure 2 corresponds to sub-logical structure layout file 22, and sub-logical structure 3 corresponds to sub-logical structure layout file 32.

[0129] The characteristic data of the standard cell to be drawn in the first standard cell layout framework are calculated based on the characteristic data corresponding to the sub-logical structure layout file 11, the sub-logical structure layout file 21, and the sub-logical structure layout file 31. Similarly, the characteristic data of the standard cell to be drawn in the second standard cell layout framework are calculated based on the characteristic data corresponding to the sub-logical structure layout file 12, the sub-logical structure layout file 22, and the sub-logical structure layout file 32.

[0130] If the characteristic data of the standard cell to be drawn under the first standard cell layout framework is more consistent with the target characteristic data required by the standard cell to be drawn than the characteristic data of the standard cell to be drawn under the second standard cell layout framework, the first standard cell layout framework is determined as the target standard cell layout framework, and therefore, the sub-logic structure layout file 11, the sub-logic structure layout file 21, and the sub-logic structure layout file 31 are spliced ​​and merged according to the connection relationship between the sub-logic structures specified in the target sub-logic structure combination netlist file to obtain the layout of the standard cell to be drawn.

[0131] If the characteristic data of the standard cell to be drawn under the second standard cell layout framework is more consistent with the target characteristic data required by the standard cell to be drawn than the characteristic data of the standard cell to be drawn under the first standard cell layout framework, the second standard cell layout framework is determined as the target standard cell layout framework, and therefore, the sub-logic structure layout file 12, the sub-logic structure layout file 22, and the sub-logic structure layout file 32 are spliced ​​and merged according to the connection relationship between the sub-logic structures specified in the target sub-logic structure combination netlist file to obtain the layout of the standard cell to be drawn.

[0132] The examples given here are only for ease of understanding and should not be construed as limiting the present application.

[0133] To understand the relationship between the sub-logic structure library and the standard cell library, refer to Figure 7 .

[0134] like Figure 7 As shown, the hardware description language of the standard cell to be drawn determines the combination relationship of the sub-logic structure (including the circuit structure diagram of the sub-logic structure and the sub-logic structure layout file) required by itself. Then, the circuit structure diagram and layout of each standard cell to be drawn can be obtained by combining the circuit structure of the sub-logic structure and the sub-logic structure layout file. Among them, each sub-logic structure in the sub-logic structure library can include a P-type sub-logic structure and an N-type sub-logic structure.

[0135] After obtaining the circuit structure diagram and layout of the standard cell, the standard cell library can be obtained according to the circuit structure diagram of the standard cell, the sub-logic structure layout file, and the hardware description language.

[0136] The method of generating a standard cell library based on a sub-logic structure library can be expressed as follows: Figure 8 As shown. The sub-logic structure constituting the standard cell is determined through the hardware description language and driving capability of the standard cell. And according to the requirements of the characteristic data of the standard cell, the target standard cell layout framework is determined. Among them, the characteristic data of the layout obtained by combining the sub-logic structure layout files corresponding to each sub-logic structure under the target standard cell layout framework meets the requirements of the standard cell for the characteristic data.

[0137] After determining the requirements of the characteristic data of the target standard cell, the layout of the standard cell can be obtained based on the sub-logic structure layout file of each sub-logic structure corresponding to the standard cell under the layout framework of the target standard cell. And the circuit structure diagram of the standard cell can be obtained based on the circuit structure diagram of each sub-logic structure corresponding to the standard cell.

[0138] Based on the same technical concept, the present application also provides a sub-logical structure library, which includes multiple sub-logical structures.

[0139] The multiple logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting the logic units, and each sub-logic structure corresponds to a sub-logic structure netlist file and a sub-logic structure layout file.

[0140] The specific implementation of the sub-logical structure library has been clearly described in the previous text, and will not be repeated here for the sake of brief description.

[0141] Based on the same technical concept, the present application also provides a standard cell layout generation device, such as Fig. 9 As shown, the standard cell layout generation device 100 includes a first acquisition module 110 and a first processing module 120 .

[0142] The first acquisition module 110 is used to acquire the hardware description language and driving capability of the standard cell to be drawn.

[0143] The first processing module 120 is used to compile the hardware description language based on a preset sub-logic structure library to obtain a sub-logic combination netlist file of the standard unit to be drawn; wherein the sub-logic combination netlist file is used to describe the sub-logic structures constituting the standard unit to be drawn and the combination relationship between the sub-logic structures; the sub-logic structure library includes multiple sub-logic structures, and the multiple logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting logic units, and each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file.

[0144] The first processing module 120 is further configured to obtain a layout of the standard cell to be drawn based on the sub-logic combinational netlist file, the sub-logic structure library, and the driving capability.

[0145] The first processing module 120 is further used to obtain multiple logic units; split each of the logic units into an N-type sub-logic structure and a P-type sub-logic structure; wherein the N-type sub-logic structure is the N-type transistor part in the logic unit, and the P-type sub-logic structure is the P-type transistor part in the logic unit; store the description data of the N-type sub-logic structure and the N-type sub-logic structure, the P-type sub-logic structure and the description data of the P-type sub-logic structure corresponding to each of the logic units into a sub-logic structure library to obtain the sub-logic structure library; wherein the description data includes a sub-logic structure netlist file and a sub-logic structure layout file.

[0146] In one implementation manner, the description data of each sub-logical structure includes at least one sub-logical structure netlist file; when the description data of the same sub-logical structure includes multiple sub-logical structure netlist files, the multiple sub-logical structure netlist files corresponding to the same sub-logical structure have different driving capabilities.

[0147] In one implementation manner, the same sub-logical structure netlist file corresponds to at least one sub-logical structure layout file of the corresponding sub-logical structure; wherein, when the same sub-logical structure netlist file corresponds to multiple sub-logical structure layout files, each of the sub-logical structure layout files belongs to a different standard unit layout framework.

[0148] In one implementation manner, the description data also includes at least one of characteristic data of each sub-logical structure layout file and a circuit structure diagram.

[0149] The first processing module 120 is further used to obtain the logical level of each of the logical units; for each of the logical units, the N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to the logical unit are stored in a storage area in the sub-logical structure library that matches the logical level of the logical unit.

[0150] The standard cell layout generation device 100 provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned standard cell layout generation method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned standard cell layout generation method embodiment.

[0151] Based on the same technical concept, the present application also provides a sub-logical structure library establishment device, such as Fig.10As shown, the sub-logical structure library establishing device 200 includes a second acquisition module 210 and a second processing module 220 .

[0152] The second acquisition module 210 is used to acquire multiple logical units.

[0153] The second processing module 220 is used to split each of the logic units into an N-type sub-logic structure and a P-type sub-logic structure; wherein the N-type sub-logic structure is the N-type transistor part in the logic unit, and the P-type sub-logic structure is the P-type transistor part in the logic unit.

[0154] The second processing module 220 is further used to store the N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units into the sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

[0155] The sub-logical structure library establishment device 200 provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned sub-logical structure library establishment method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned sub-logical structure library establishment method embodiment.

[0156] See also Fig.11 , which is an electronic device 300 provided in an embodiment of the present application. The electronic device 300 includes: a processor 310 and a memory 320.

[0157] The memory 320 and the processor 310 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The memory 320 is used to store computer programs, such as Fig. 9 The software function module shown in FIG. 1 , namely, the standard cell layout generation device 100; or, Fig.10 The software function module shown is the sub-logical structure library establishment device 200. The standard cell layout generation device 100 or the sub-logical structure library establishment device 200 includes at least one software function module that can be stored in the memory 320 in the form of software or firmware or fixed in the operating system (OS) of the electronic device 300.

[0158] The processor 310 is used to execute executable modules stored in the memory 320 , such as software function modules or computer programs included in the standard cell layout generation device 100 . At this time, the processor 310 is used to obtain the hardware description language and driving capability of the standard cell to be drawn; compile the hardware description language based on the preset sub-logic structure library to obtain the sub-logic combination netlist file of the standard cell to be drawn; wherein the sub-logic combination netlist file is used to describe the target sub-logic structure combination corresponding to the standard cell to be drawn, the sub-logic structure library includes multiple sub-logic structures, and the multiple logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting the logic cells, and each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file; based on the sub-logic combination netlist file, the sub-logic structure library, and the driving capability, the layout of the standard cell to be drawn is obtained.

[0159] The processor 310 is used to execute the executable modules stored in the memory 320, such as the software function modules or computer programs included in the sub-logical structure library establishment device 200. At this time, the processor 310 is used to obtain multiple logic units; split each of the logic units into an N-type sub-logical structure and a P-type sub-logical structure; wherein the N-type sub-logical structure is the N-type transistor part in the logic unit, and the P-type sub-logical structure is the P-type transistor part in the logic unit; store the description data of the N-type sub-logical structure and the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units into the sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

[0160] Among them, the memory 320 can be, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0161] The processor 310 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc.; it may also be a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor or the processor 310 may also be any conventional processor, etc.

[0162] The electronic device 300 mentioned above includes but is not limited to a personal computer, a server, etc.

[0163] The embodiment of the present application also provides a computer-readable storage medium (hereinafter referred to as storage medium), on which a computer program is stored, and when the computer program is run by a computer such as the above-mentioned electronic device 300, the standard cell layout generation method or sub-logic structure library establishment method shown above is executed. The computer-readable storage medium includes: a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and other media that can store program codes.

[0164] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating a standard cell layout, characterized in that: include: Obtain the hardware description language and driver capability of the standard unit to be drawn; The hardware description language is compiled based on a preset sub-logic structure library to obtain a sub-logic combination netlist file of the standard unit to be drawn; wherein the sub-logic combination netlist file is used to describe the sub-logic structures constituting the standard unit to be drawn and the combination relationship between the sub-logic structures; the sub-logic structure library includes multiple sub-logic structures, and the multiple logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting the logic units, and each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file; Based on the sub-logic combinational netlist file, the sub-logic structure library, and the driving capability, a layout of the standard cell to be drawn is obtained.

2. The method according to claim 1, characterized in that The sub-logical structure library is obtained by: Get multiple logical units; Splitting each of the logic units into an N-type sub-logic structure and a P-type sub-logic structure; wherein the N-type sub-logic structure is the N-type transistor part in the logic unit, and the P-type sub-logic structure is the P-type transistor part in the logic unit; The N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units are stored in a sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

3. The method according to claim 2, characterized in that The description data of each sub-logical structure has at least one sub-logical structure netlist file; When there are multiple sub-logical structure netlist files in the description data of the same sub-logical structure, the multiple sub-logical structure netlist files corresponding to the same sub-logical structure have different driving capabilities.

4. The method according to claim 3, characterized in that The same sub-logical structure netlist file corresponds to at least one sub-logical structure layout file of the corresponding sub-logical structure; wherein, when the same sub-logical structure netlist file corresponds to multiple sub-logical structure layout files, each of the sub-logical structure layout files belongs to a different standard unit layout framework.

5. The method according to claim 2, characterized in that: The description data also includes at least one of characteristic data of each sub-logical structure layout file and a circuit structure diagram.

6. The method according to any one of claims 2 to 5, characterized in that: The method further comprises: Obtaining the number of logic levels of each of the logic units; Accordingly, storing the N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logical units into the sub-logical structure library includes: For each of the logical units, the N-type sub-logical structure and description data of the N-type sub-logical structure, the P-type sub-logical structure and description data of the P-type sub-logical structure corresponding to the logical unit are stored in a storage area in the sub-logical structure library that matches the logical level of the logical unit.

7. A sub-logical structure library, characterized in that: include: A plurality of sub-logic structures, wherein the plurality of logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting logic units, and each sub-logic structure corresponds to a sub-logic structure netlist file and a sub-logic structure layout file.

8. A method for establishing a sub-logical structure library, characterized in that: include: Get multiple logical units; Splitting each of the logic units into an N-type sub-logic structure and a P-type sub-logic structure; wherein the N-type sub-logic structure is the N-type transistor part in the logic unit, and the P-type sub-logic structure is the P-type transistor part in the logic unit; The N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units are stored in a sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

9. A standard cell layout generation device, characterized in that: include: A first acquisition module is used to acquire the hardware description language and driving capability of the standard unit to be drawn; The first processing module is used to compile the hardware description language based on a preset sub-logic structure library to obtain a sub-logic combination netlist file of the standard unit to be drawn; wherein the sub-logic combination netlist file is used to describe the sub-logic structures constituting the standard unit to be drawn and the combination relationship between the sub-logic structures; the sub-logic structure library includes multiple sub-logic structures, and the multiple logic structures in the sub-logic structure library are divided into an N-type transistor sub-logic structure library and a P-type transistor sub-logic structure library according to the transistor type included in the sub-logic; wherein each sub-logic included in the N-type transistor sub-logic structure library only includes N-type transistors, and each sub-logic included in the P-type transistor sub-logic structure library only includes P-type transistors, and the sub-logic structures are obtained by splitting logic units, and each sub-logic structure corresponds to description data, and the description data includes a sub-logic structure netlist file and a sub-logic structure layout file; The first processing module is further used to obtain the layout of the standard cell to be drawn based on the sub-logic combinational netlist file, the sub-logic structure library, and the driving capability.

10. A sub-logical structure library building device, characterized in that: include: A second acquisition module is used to acquire multiple logical units; A second processing module is used to split each of the logic units into an N-type sub-logic structure and a P-type sub-logic structure; wherein the N-type sub-logic structure is an N-type transistor part in the logic unit, and the P-type sub-logic structure is a P-type transistor part in the logic unit; The second processing module is further used to store the N-type sub-logical structure and the description data of the N-type sub-logical structure, the P-type sub-logical structure and the description data of the P-type sub-logical structure corresponding to each of the logic units into the sub-logical structure library to obtain the sub-logical structure library; wherein the description data includes a sub-logical structure netlist file and a sub-logical structure layout file.

11. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are connected; The memory is used to store programs; The processor is used to call the program stored in the memory to execute the method according to any one of claims 1 to 6, or to execute the method according to claim 8.

12. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is run by a computer, the method according to any one of claims 1 to 6 is executed, or the method according to claim 8 is executed.

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