Layout and wiring method, device and equipment and readable storage medium

Abstract

The invention discloses a layout and wiring method, device and equipment and a readable storage medium, and electronic equipment determines at least one visual reward according to a wiring result of (N-1) th wiring operation, and feeds back the at least one visual reward to a layout algorithm to adjust the layout algorithm. And then, executing the Nth layout according to the adjusted layout algorithm to obtain a layout result of the Nth layout. By adopting the scheme, the electronic equipment determines at least one intuitive reward according to the wiring result of the last wiring operation, adjusts the layout algorithm based on the at least one wiring reward, and performs the layout by using the adjusted layout algorithm, so that the layout algorithm considers all wiring constraints in the wiring requirements, and the layout efficiency is improved. The purpose of improving the quality and speed of automatic layout and wiring is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of printed circuit boards, and in particular to a layout and wiring method, device, equipment, and readable storage medium. Background Art

[0002] Printed circuit board (PCB) is an important electronic component and a carrier of electronic components. PCB design is usually called layout design or PCB Layout. PCB layout and PCB routing are two important parts of PCB design.

[0003] PCB layout refers to arranging all components according to the principles of functional structure, modularization, and smooth layout and routing. PCB routing refers to connecting components through wires to achieve specific functions. With the continuous application of classic machine learning algorithms in various industries, as well as the emergence of a variety of efficient deep learning architectures and their continuous application in the field of industrial production, a variety of automatic layout algorithms and automatic routing algorithms have emerged in the industry. Since the layout of components is a pre-operation of routing, the PCB layout algorithm is often used for automatic layout operations in the PCB design process. Then, based on the layout results, the PCB automatic routing algorithm is used for routing operations.

[0004] In the above layout and routing methods, the routing process can only be performed based on the layout results. For the PCB automatic routing algorithm, the layout result is likely not the optimal solution, resulting in the need for manual adjustment of the layout result before automatic routing, poor consistency and slow speed. Summary of the invention

[0005] The embodiments of the present application provide a layout and routing method, apparatus, device and readable storage medium, which feed back the intuitive reward of routing to the layout algorithm so that the layout algorithm takes all routing constraints in the routing requirements into consideration, thereby achieving the purpose of improving the quality and speed of automatic layout and routing.

[0006] In a first aspect, an embodiment of the present application provides a layout and routing method, comprising:

[0007] Determine at least one intuitive reward according to the wiring result of the N-1th wiring operation, where the intuitive reward is used to indicate the degree of completion of the corresponding wiring indicator, where N is ≥ 2 and is an integer;

[0008] adjusting a layout algorithm based on the at least one intuitive reward;

[0009] The Nth layout is performed according to the adjusted layout algorithm to obtain a layout result of the Nth layout.

[0010] In a second aspect, an embodiment of the present application provides a layout and routing device, including:

[0011] A determination module, used to determine at least one intuitive reward according to the wiring result of the N-1th wiring operation, wherein the intuitive reward is used to indicate the completion degree of the corresponding wiring indicator, where N≥2 and is an integer;

[0012] an adjustment module for adjusting a layout algorithm according to the at least one intuitive reward;

[0013] The processing module is used to perform the Nth layout according to the adjusted layout algorithm to obtain the layout result of the Nth layout.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the electronic device implements the method described in the first aspect or various possible implementation methods of the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed by a processor, they are used to implement the method described in the first aspect or various possible implementation methods of the first aspect.

[0016] In a fifth aspect, an embodiment of the present application provides a computer program product comprising a computing program, and when the computer program is executed by a processor, the method described in the first aspect or various possible implementation methods of the first aspect is implemented.

[0017] The layout and routing method, apparatus, device, and readable storage medium provided in the embodiments of the present application, the electronic device determines at least one intuitive reward based on the wiring result of the N-1th wiring operation, and feeds back at least one intuitive reward to the layout algorithm to adjust the layout algorithm. Afterwards, the Nth layout is performed according to the adjusted layout algorithm to obtain the layout result of the Nth layout. With this scheme, the electronic device determines at least one intuitive reward based on the wiring result of the previous wiring operation, adjusts the layout algorithm based on at least one wiring reward, and uses the adjusted layout algorithm to perform this layout, so that the layout algorithm takes all wiring constraints in the wiring requirements into consideration, thereby achieving the purpose of improving the quality and speed of automatic layout and routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a flow chart of a layout and routing method provided in an embodiment of the present application;

[0020] Figure 2 It is a process schematic diagram of the layout and routing method provided in an embodiment of the present application;

[0021] Figure 3 It is a flow chart of determining the overall connectivity reward in the layout and routing method provided in an embodiment of the present application;

[0022] Figure 4 It is a schematic diagram of the process of determining the overall line length reward in the layout and routing method provided in an embodiment of the present application;

[0023] Figure 5 It is a schematic diagram of pin connection in the layout and wiring method provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of a layout and wiring device provided in an embodiment of the present application;

[0025] Figure 7 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] Printed circuit board (PCB) is one of the important components of the electronics industry. Layout and routing are two key steps in PCB design. At present, in the PCB design industry, most layout and routing work is done manually by PCB layout engineers. With the continuous application of classic machine learning algorithms in various industries, the emergence of a variety of efficient deep learning architectures and their continuous implementation in the field of industrial production, the industry has proposed a variety of PCB automatic layout algorithm solutions.

[0027] Automatic algorithm solutions mainly include automatic layout algorithms and automatic routing algorithms. Engineers have tried and explored methods such as heuristic algorithms, dynamic programming, depth-first search, and Monte Carlo simulation. On the basis of these classic mathematical methods, in order to make the results produced by the algorithm closer to the manual results of PCB layout engineers, it is necessary to give the algorithm the ability to continuously accumulate layout experience during the layout process and the ability to continuously accumulate routing experience during the routing process. At present, automatic layout and automatic routing methods based on deep learning have gradually made certain progress, mainly using generative adversarial networks, graph neural networks, and reinforcement learning methods.

[0028] During the PCB design process, the layout of components is a pre-operation for routing. Under this premise, the operation process of most PCB automatic layout and routing algorithms is: first use the layout algorithm to perform automatic layout operations, and then use the routing algorithm to perform routing operations based on the layout results. However, since routing constraints are difficult to fully quantify during the layout process, in most cases, the layout process does not take all possibilities of routing into consideration, which results in the layout results not being the optimal solution for the routing algorithm, resulting in the results of the automatic layout algorithm still needing manual adjustment for automatic routing, which in turn leads to a lack of coherence in the optimization solution and engineering application process of the PCB automatic layout and routing algorithm model, and hinders the development of automatic layout and routing algorithms.

[0029] Based on this, the embodiments of the present application provide a layout and routing method, apparatus, device and readable storage medium, which determines at least one intuitive reward based on the routing result of the last routing operation, adjusts the layout algorithm based on at least one routing reward, and uses the adjusted layout algorithm to perform this layout, so that the layout algorithm takes all routing constraints in the routing requirements into consideration, thereby achieving the purpose of improving the quality and speed of automatic layout and routing.

[0030] The execution subject of the embodiment of the present application is an electronic device, on which the layout algorithm and the routing algorithm are deployed. The electronic device is, for example, a server, a tablet computer, a personal computer, a laptop computer, a desktop computer, etc., and the embodiment of the present application is not limited thereto.

[0031] Figure 1 : is a flow chart of the layout and wiring method provided by an embodiment of the present application. The execution subject of this embodiment is the above-mentioned electronic device, and this embodiment includes:

[0032] 101. Determine at least one intuitive reward according to a wiring result of an N-1th wiring operation, where the intuitive reward is used to indicate a degree of completion of a corresponding wiring indicator, where N≥2 and is an integer.

[0033] In the embodiment of the present application, PCB layout and wiring is a continuously iterative process, such as 500 iterations, 1000 iterations, etc. After each layout using the PCB layout algorithm, wiring is performed based on the layout result to obtain a wiring result. Afterwards, the electronic device determines at least one intuitive reward based on the wiring result, and the intuitive reward is used to indicate the degree of completion of the wiring indicator. For example, if the wiring indicator includes loop connectivity, the intuitive reward is used to indicate the degree of completion of the loop connectivity. For another example, if the wiring indicator includes line length, the intuitive reward is used to indicate the degree of completion of the line length indicator.

[0034] 102. Adjust a layout algorithm according to the at least one intuitive reward.

[0035] Each time after determining at least one intuitive reward according to the wiring result, the electronic device feeds back the at least one intuitive reward to the layout algorithm, so that the layout algorithm learns how to better meet multiple wiring constraints during the layout process, thereby adjusting the layout algorithm.

[0036] 103. Perform the Nth layout according to the adjusted layout algorithm to obtain a layout result of the Nth layout.

[0037] In the embodiment of the present application, two adjacent layouts are respectively represented as the N-1th layout and the Nth layout. The electronic device obtains at least one intuitive reward based on the N-1th wiring result, adjusts the layout algorithm based on the at least one intuitive reward, and performs the Nth layout using the adjusted layout algorithm. Afterwards, a wiring operation is performed according to the layout result of the Nth layout to obtain the wiring result of the Nth wiring.

[0038] Based on the above, it can be seen that in the embodiment of the present application, each iteration round needs to determine the layout results, routing results, intuitive rewards and return to the layout algorithm in turn. Therefore, the time requirements for the layout and routing algorithms are relatively high. For smaller-scale layout and routing, small-scale dynamic programming, shortest path and other search algorithms with smaller feasible solution spaces are used; for large-scale layout and routing tasks, offline reinforcement learning, heuristic model algorithms and other methods need to be used.

[0039] In the layout and routing method provided in the embodiment of the present application, the electronic device determines at least one intuitive reward based on the wiring result of the N-1th wiring operation, and feeds back at least one intuitive reward to the layout algorithm to adjust the layout algorithm. Afterwards, the Nth layout is performed according to the adjusted layout algorithm to obtain the layout result of the Nth layout. With this scheme, the electronic device determines at least one intuitive reward based on the wiring result of the previous wiring operation, adjusts the layout algorithm based on at least one wiring reward, and uses the adjusted layout algorithm to perform this layout, so that the layout algorithm takes all the wiring constraints in the wiring requirements into consideration, thereby achieving the purpose of improving the quality and speed of automatic layout and routing.

[0040] Optionally, in the above embodiment, in the process of adjusting the layout algorithm according to the at least one intuitive reward, the electronic device first generates a reward array according to the at least one intuitive reward, and then adjusts the layout algorithm according to the reward array.

[0041] Exemplarily, the electronic device determines multiple loops based on the layout results, and for each loop, the electronic device determines multiple intuitive rewards, such as connectivity rewards, line length rewards, via rewards, etc. Then, an overall connectivity reward is determined based on the connectivity rewards of each loop; an overall line length reward is determined based on the line length rewards of each loop... Finally, the electronic device generates a reward array based on the overall connectivity reward, the overall line length reward, etc., and feeds the reward data back to the layout algorithm, thereby adjusting the layout algorithm.

[0042] In this way, the electronic device feeds back the routing reward to the layout algorithm in the form of an array, which can prevent the layout algorithm from focusing too much on certain routing performance indicators and ignoring other performance indicators. For example, it can prevent the layout algorithm from focusing mainly on connectivity integrity, resulting in the line length not meeting the requirements and the line length reward being very poor; or it can prevent the layout algorithm from focusing mainly on line length, resulting in a short line length but poor connectivity.

[0043] By adopting this solution, the electronic device can feed back the routing reward to the layout algorithm in the form of an array, thereby preventing the layout algorithm from focusing too much on certain routing performance indicators and thus ignoring other performance indicators, thereby achieving the purpose of improving the quality of automatic layout and routing.

[0044] Optionally, in the above embodiment, after the electronic device performs the Nth layout according to the adjusted layout algorithm to obtain the layout result of the Nth layout, it also performs wiring according to the layout result of the Nth layout to obtain the wiring result of the Nth wiring operation. Afterwards, the electronic device compares the N-1th wiring result with the Nth wiring result to determine whether the Nth wiring result converges. When the electronic device determines that the Nth wiring result converges, it determines that the layout and wiring are completed; if the Nth wiring result does not converge, the electronic device continues to determine at least one intuitive reward according to the Nth wiring result, and then continues to adjust the layout algorithm.

[0045] Exemplarily, each time after obtaining a wiring result, the electronic device compares the current wiring result with the previous wiring result. When the similarity between the two is higher than a preset similarity, the electronic device considers that the current wiring result has converged, stops iterating, and outputs the layout and wiring results. If the similarity between the current wiring result and the previous wiring result is low, lower than the preset similarity, the electronic device considers that the current wiring result has not converged, and continues to iterate the layout and wiring until the wiring result converges.

[0046] By adopting this solution, the electronic device determines whether the wiring result is converged each time after obtaining the wiring result, so as to obtain the converged wiring result in a timely and accurate manner.

[0047] In order to realize the joint solution process of PCB automatic layout and wiring, it is necessary to consider the impact on wiring during the iterative process of layout generation. In view of the problem that wiring constraints are difficult to quantify during the layout process, in the embodiment of the present application, starting directly from the wiring results, for each loop, the satisfaction of various wiring indicators in the wiring task is analyzed, and the overall wiring rewards of various wiring indicators are obtained, and a reward array is generated and fed back to the layout algorithm. For each loop, the wiring indicators include but are not limited to wiring connectivity, line length, number of vias and some special preset indicators; correspondingly, the wiring rewards include wiring connectivity rewards, line length rewards, via rewards, target rewards, etc. The electronic device analyzes the completion of each indicator, and designs a calculation method to calculate the independent completion of each indicator, and then obtains the intuitive reward of each indicator. The intuitive reward reflects the completion of the wiring result into an intuitive array, which facilitates the layout algorithm to consider all wiring constraints in the wiring requirements.

[0048] Figure 2 Schematic diagram of the process of the layout and routing method provided in the embodiment of the present application, comprising the following steps:

[0049] 201. Perform a layout operation using a layout algorithm to obtain a layout result.

[0050] 202. Perform routing based on the layout result to obtain a routing result.

[0051] 203. Determine at least one intuitive reward based on the wiring result.

[0052] When the at least one intuitive reward includes an overall connectivity reward, an overall line length reward, an overall via reward, or a preset reward, this step includes the following sub-steps:

[0053] 2031. Determine the overall connectivity reward based on the wiring results.

[0054] 2032. Determine the overall line length reward based on the wiring results.

[0055] 2033. Determine the overall via reward based on the routing results.

[0056] 2034. Determine a preset reward based on the wiring result.

[0057] 204. Generate a reward array according to at least one intuitive reward, and feed the reward array back to the layout algorithm.

[0058] according to Figure 2It can be seen that: the embodiment of the present application designs a variety of intuitive wiring reward calculation schemes for different aspects of PCB wiring requirements, and merges the results into a reward array, which can intuitively reflect the connectivity, integrity, line length, wiring interference, number of vias, etc. of all loops of the PCB automatic wiring results.

[0059] Next, Figure 2 The overall connectivity bonus, overall wire length bonus, overall via bonus, or preset bonus in the are explained in detail.

[0060] First, the overall connectivity bonus.

[0061] The electronic device can determine multiple loops based on the wiring results of the N-1th wiring operation. For each loop, the electronic device determines the wiring connectivity reward of the loop. Afterwards, the electronic device determines the overall connectivity reward based on the wiring connectivity rewards of each loop. Among them, the wiring connectivity reward of the loop reflects the connectivity integrity of the loop in the PCB wiring results. The overall connectivity reward reflects the connectivity integrity of all loops.

[0062] The concept of a loop is as follows: There are multiple components on a PCB, and pins with the same function on different components are connected by wires to form a loop. The wire refers to the copper-plated wire on the PCB. For example, there are components A, B, C, and D on the PCB, which have pins 1, 2, 3, and 4 respectively. The four pins have the same function, and the four pins are connected by wires to form a loop. The same function means: for example, the four pins are all VCC pins; for another example, the four pins are all ground pins.

[0063] For any loop, when the electronic device determines the wiring connectivity bonus for the loop, it is mainly calculated based on the number of all pins that need to be connected in the loop and the number of connected pins. Continuing with the above example, when pin 1, pin 2, pin 3, and pin 4 are connected to each other, the number of connected pins is 4. When calculating the number of connected pins, duplicate removal is required. For example, pin 1 is connected to pin 2, pin 2 is connected to pin 3, and pin 3 is connected to pin 4, and the number of connected pins is 4. For another example, pin 1, pin 2, and pin 3 are all connected to pin 4, and the number of connected pins is 4.

[0064] With this solution, the electronic device determines the wiring connectivity bonus based on the number of pins connected to each circuit and the number of pins that need to be connected. Then, the overall connectivity bonus is determined based on the wiring connectivity bonus of each circuit, achieving the purpose of accurately and efficiently calculating the overall connectivity bonus.

[0065] Optionally, in the above embodiment, when the electronic device determines the overall connectivity reward, it also assigns weights to different loops according to the Euclidean distances between different loop pins. Figure 3 , Figure 3 : is a flow chart of determining the overall connectivity reward in the layout and routing method provided in an embodiment of the present application, and this embodiment includes:

[0066] 301. Determine the Euclidean distance of each loop and the sum of the Euclidean distances of each loop in the wiring result of the N-1th wiring operation.

[0067] In the embodiment of the present application, the greater the Euclidean distance between the loop pins, the more components the loop needs to bypass. Therefore, the greater the Euclidean distance of the loop, the greater the weight ω of the loop.

[0068] 302. For each loop, determine a weight of the loop according to the Euclidean distance of the loop and the sum.

[0069] In the embodiment of the present application, the greater the Euclidean distance between the loop pins, the more components the loop needs to bypass. Therefore, the greater the Euclidean distance of the loop, the greater the weight ω of the loop.

[0070] The weight ω of loop i i The calculation process is as follows:

[0071]

[0072] In formula (1), ED i represents the Euclidean distance of loop i, and N represents the total number of loops in the routing task.

[0073] 303. For each loop, determine a wiring connectivity bonus for the corresponding loop according to the weight of the loop, the number of connected pins, and the number of pins that need to be connected.

[0074] Wiring connectivity bonus for loop i ConnectR i Calculated by the following formula (2):

[0075] ConnectR i =w i ×Rvalue×connect_pins / all_pins Formula (2)

[0076] In formula (2), Rvalue is the maximum reward value for loop connectivity, that is, the maximum wiring connectivity reward, which is a known parameter. connect_pins represents the number of connected pins in loop i, and all_pins represents the number of all pins that need to be connected in loop i.

[0077] 304. Determine the overall connectivity reward according to the wiring connectivity rewards of each loop.

[0078] The electronic device sums the wiring connectivity rewards of all loops to obtain the overall connectivity reward SUM_ConnectR. Without considering other wiring constraints, it can be considered that the larger the overall connectivity reward SUM_ConnectR, the higher the performance of the layout result and the wiring algorithm. The overall connectivity reward SUM_ConnectR can be determined by the following formula (3).

[0079]

[0080] With this solution, when the electronic device determines the wiring connectivity reward of a loop, different weights are assigned to the loop according to the Euclidean distances between different loop pins, ensuring that the wiring connectivity reward of the loop can accurately reflect the wiring differences of different layout results.

[0081] Secondly, overall line length rewards.

[0082] For each loop, the wire length reward of the loop reflects the degree of consumption of the wiring length by the layout result. For example, in the process of solving the routing result using the shortest path method, the pin position and direction in the layout result have a great influence on the wire length of the loop. Therefore, in the process of solving the layout and routing joint solution, it is very important to solve the wire length reward and return it to the layout algorithm.

[0083] In the embodiment of the present application, the Euclidean distance and power function of the loop pins are mainly used to calculate the line length reward. For example, please refer to Figure 4 . Figure 4 : is a schematic diagram of the process of determining the overall line length reward in the layout and routing method provided in an embodiment of the present application. This embodiment includes:

[0084] 401. The electronic device determines a first length and a second length of each loop in a wiring result of the N-1th wiring operation.

[0085] When the wiring indicator includes line length and the intuitive reward includes an overall line length reward, the electronic device determines the first length and the second length of each loop in the wiring result of the N-1th wiring operation, the first length is used to indicate the sum of the Euclidean distances of the connected point pairs in the loop, and the second length is used to indicate the sum of the line lengths of all connecting lines in the loop.

[0086] Figure 5 This is a schematic diagram of pin connections in the layout and wiring method provided in the embodiment of the present application. Figure 5, there are at least components A, B, C, and D on the PCB, which have pins 1, 2, 3, and 4 respectively, and the four pins have the same function. The four pins are connected by wires to form a loop, which is referred to as loop i below. The electronic device calculates the Euclidean distance Connect_ED of the connected point pairs in loop i according to the minimum spanning tree, that is, the first length. The first length is the sum of the lengths of the thick black solid line segments connecting the pins of all components in the figure.

[0087] Based on the wiring result of the N-1th wiring algorithm, the electronic device determines the sum of the lengths of all connecting lines in loop i, All_Length, that is, the second length. The second length is the sum of the lengths of the dashed line segments in the figure.

[0088] 402. The electronic device determines a line length reward for the corresponding loop according to the first length and the second length of each loop.

[0089] For example, the line length reward LengthR of loop i i The calculation is mainly based on the power function, so that the line length reward LengthR i The maximum reward value Rvalue for approaching loop connectivity. Line length reward LengthR i It can be calculated by the following formula (4):

[0090] Length i =w i ×Rvalue×[1.001^(Connect_ED i -All_Length i )-1] Formula (4)

[0091] Among them, Connect_ED i Represents the Euclidean distance of the connected point pairs in loop i, that is, the first is the length, All_Length i It represents the sum of the lengths of all the connecting lines in loop i, i.e., the second length. According to formula (4), it can be obtained that: Line length reward LengthR i Always less than or equal to 0, and only when the Euclidean distance between the points in the loop i is equal to the length of all connecting lines, that is, when the first length is equal to the second length, the line length bonus LengthR i When the first length is not equal to the second length, the line length reward LengthR i is a negative value. The reason why LengthR i It is always a negative value because of “-1” in formula (4).

[0092] When the line length reward LengthR that returns a negative value is not consideredi When , there is no need for "-1" in formula (4). At this time, the reward LengthR of loop i i The maximum value of w i ×Rvalue.

[0093] 403. Determine the overall line length reward based on the line length reward of each loop.

[0094] The electronic device can use the following formula (5) to determine the overall line length reward LengthR.

[0095]

[0096] In this way, when “-1” is not needed in formula (4), the line length bonus LengthR of loop i is guaranteed i The maximum value of w i ×Rvalue. That is to say, there is a perfect ideal wiring result with an overall wire length reward LengthR of Rvalue. In other cases, the overall wire length reward LengthR is less than Rvalue.

[0097] With this solution, the electronic device determines the line length reward of the loop based on the sum of the Euclidean distances of the connected point pairs in each loop and the sum of the line lengths of all connecting lines in the loop, and then determines the overall line length reward, thereby achieving the purpose of accurately and efficiently determining the overall line length reward.

[0098] Again, overall via bonus.

[0099] For each loop, the via reward reflects the number of unnecessary vias in the loop. The overall via reward reflects the number of unnecessary vias in all loops. Punching one more unnecessary via in each loop increases the complexity and manufacturing difficulty of the entire PCB routing loop. Therefore, in the process of joint layout and routing solution, unnecessary vias should be pursued as much as possible. Therefore, it is necessary to calculate the via reward for unnecessary vias.

[0100] When the routing indicator includes the number of vias and the intuitive reward includes the overall via reward, the electronic device determines the number of unnecessary vias in each loop in the routing result of the N-1th routing operation. Then, the electronic device determines the via reward of the corresponding loop according to the number of unnecessary vias in each loop. Finally, the electronic device determines the overall via reward according to the via reward of each loop. Wherein, the via reward viaR of loop i is i It can be determined by the following formula (6):

[0101] via R i =viavalue×num_via Formula (6)

[0102] In formula (6), num_via represents the number of non-essential vias in loop i. Non-essential vias refer to non-required holes in the loop, such as chip heat dissipation holes, GND loop ground wire holes, etc. These holes are not included in the calculation of the number of non-essential vias. viavalue represents a known parameter.

[0103] After the electronic device determines the via reward of each loop, the overall via reward is determined based on the via rewards of each loop. The overall via reward viaR is determined according to the following formula (7):

[0104]

[0105] With this solution, the electronic device determines the via reward of the loop according to the number of unnecessary vias in each loop, and then determines the overall via reward, thereby achieving the purpose of accurately and efficiently determining the overall via reward.

[0106] Finally, preset rewards.

[0107] During the PCB design process, some circuits have certain special requirements, such as anti-interference and enhanced heat dissipation. In order to make the layout and routing algorithms meet the special requirements of some circuits, it is necessary to calculate the preset rewards of the preset indicators. Such as the anti-interference reward of the anti-interference indicator, the heat dissipation reward of the heat dissipation indicator, etc. During the determination process, the electronic device determines the target circuit from the routing results of the N-1th routing operation, that is, the circuit that requires the preset indicators. After that, for each target circuit, the electronic device determines the target reward of the target circuit, and determines the preset reward based on the target reward of each target circuit.

[0108] For example, there are 10 loops in total, of which 5 loops require anti-interference. The electronic device determines the 5 required loops from the 10 loops, thereby obtaining 5 target loops. For each target loop, the electronic device determines the anti-interference reward, thereby obtaining 5 anti-interference rewards. Afterwards, the electronic device sums the 5 anti-interference rewards, etc., thereby determining the overall anti-interference reward, that is, the above-mentioned preset reward.

[0109] With this solution, the electronic device takes into account the special needs of some circuits when determining the intuitive reward, and feeds back the preset rewards corresponding to the special needs to the layout algorithm, so that the layout algorithm can learn the special needs and achieve the purpose of improving the layout and wiring quality.

[0110] The following are device embodiments of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0111] Figure 6A schematic diagram of a layout and routing device provided in an embodiment of the present application. The layout and routing device 600 includes: a determination module 61 , an adjustment module 62 and a processing module 63 .

[0112] A determination module 61, configured to determine at least one intuitive reward according to the wiring result of the N-1th wiring operation, wherein the intuitive reward is used to indicate the completion degree of the corresponding wiring indicator, where N≥2 and is an integer;

[0113] An adjustment module 62, for adjusting the layout algorithm according to the at least one intuitive reward;

[0114] The processing module 63 is used to perform the Nth layout according to the adjusted layout algorithm to obtain the layout result of the Nth layout.

[0115] In a feasible implementation, the determination module 61 is used to determine the number of connected pins in each loop and the number of all connected pins in the wiring result of the N-1th wiring operation when the wiring indicator includes connectivity integrity and the intuitive reward includes an overall connectivity reward; determine the wiring connectivity reward of the corresponding loop according to the number of connected pins and the number of pins that need to be connected in each loop; and determine the overall connectivity reward according to the wiring connectivity reward of each loop.

[0116] In a feasible implementation, the determination module 61 determines the wiring connectivity reward of the corresponding loop according to the number of connected pins and the number of pins that need to be connected of each loop, and is used to determine the Euclidean distance of each loop and the sum of the Euclidean distances of each loop in the wiring result of the N-1th wiring operation; for each loop, the weight of the loop is determined according to the Euclidean distance of the loop and the sum; for each loop, the wiring connectivity reward of the corresponding loop is determined according to the weight of the loop, the number of connected pins and the number of pins that need to be connected.

[0117] In a feasible implementation, the determination module 61 is used to determine the first length and the second length of each loop in the wiring result of the N-1th wiring operation when the wiring indicator includes the line length and the intuitive reward includes the overall line length reward, the first length being used to indicate the sum of the Euclidean distances of the connected point pairs in the loop, and the second length being used to indicate the sum of the line lengths of all connecting lines in the loop; determine the line length reward of the corresponding loop based on the first length and the second length of each loop; and determine the overall line length reward based on the line length reward of each loop.

[0118] In a feasible implementation, the determination module 61 is used to determine the number of non-essential vias in each loop in the wiring result of the N-1th wiring operation when the wiring indicator includes the number of vias and the intuitive reward includes the overall via reward; determine the via reward of the corresponding loop based on the number of non-essential vias in each loop; and determine the overall via reward based on the via reward of each loop.

[0119] In a feasible implementation, the determination module 61 is used to determine a target loop from the wiring results of the N-1th wiring operation when the wiring indicator includes a preset indicator and the intuitive reward includes a preset reward; the target loop is a loop that requires the preset indicator; for each target loop, determine the target reward of the target loop; and determine the preset reward based on the target reward of each target loop.

[0120] In a feasible implementation, the adjustment module 62 is used to generate a reward array according to the at least one intuitive reward; and adjust the layout algorithm according to the reward array.

[0121] In a feasible implementation, after the processing module 63 performs the Nth layout according to the adjusted layout algorithm to obtain the layout result of the Nth layout, it is also used to route according to the layout result of the Nth layout to obtain the wiring result of the Nth wiring operation; compare the N-1th wiring result with the Nth wiring result to determine whether the Nth wiring result converges; when the Nth wiring result converges, it is determined that the layout and routing are completed.

[0122] The layout and wiring device provided in the embodiment of the present application can execute the actions of the electronic device in the above embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0123] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Figure 7 The electronic device 700 described in the embodiment of the present application includes: at least one processor 71, at least one communication bus 72, a user interface 73, at least one network interface 74 and a memory 75.

[0124] The communication bus 72 is used to realize the connection and communication between these components.

[0125] The user interface 73 may include a display screen (Display) and a camera (Camera), and the optional user interface 73 may also include a standard wired interface and a wireless interface.

[0126] The network interface 74 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0127] Among them, the processor 71 may include one or more processing cores. The processor 71 uses various interfaces and lines to connect various parts of the entire electronic device 70, and executes various functions and processes data of the electronic device 70 by running or executing instructions, programs, code sets or instruction sets stored in the memory 75, and calling data stored in the memory 75. Optionally, the processor 71 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 71 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 71, and it can be implemented separately through a chip.

[0128] Among them, the memory 75 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 75 includes a non-transitory computer-readable storage medium. The memory 75 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 75 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 75 may also be optionally at least one storage device located away from the aforementioned processor 71. As Figure 7 As shown, the memory 75 as a computer storage medium may include an operating system, a network communication module, a user interface module, and an operating application of the electronic device.

[0129] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0130] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0131] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0132] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0133] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0134] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0135] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0136] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0137] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A layout and routing method, characterized in that: include: Determine at least one intuitive reward according to the wiring result of the N-1th wiring operation, where the intuitive reward is used to indicate the degree of completion of the corresponding wiring indicator, where N is ≥ 2 and is an integer; adjusting a layout algorithm based on the at least one intuitive reward; The Nth layout is performed according to the adjusted layout algorithm to obtain a layout result of the Nth layout.

2. The method according to claim 1, characterized in that The determining of at least one intuitive reward according to the wiring result of the N-1th wiring operation comprises: When the wiring indicator includes connectivity integrity and the intuitive reward includes an overall connectivity reward, determining the number of connected pins in each loop and the number of all connected pins in the wiring result of the N-1th wiring operation; Determine the wiring connectivity bonus for the corresponding circuit based on the number of connected pins and the number of pins that need to be connected for each circuit; The overall connectivity reward is determined according to the wiring connectivity rewards of each loop.

3. The method according to claim 2, characterized in that The step of determining the wiring connectivity bonus of the corresponding circuit according to the number of connected pins of each circuit and the number of pins to be connected includes: Determine the Euclidean distance of each loop and the sum of the Euclidean distances of each loop in the wiring result of the N-1th wiring operation; For each loop, determining a weight of the loop according to the Euclidean distance of the loop and the sum; For each loop, a wiring connectivity reward of the corresponding loop is determined according to the weight of the loop, the number of connected pins, and the number of pins that need to be connected.

4. The method according to claim 1, characterized in that: The determining of at least one intuitive reward according to the wiring result of the N-1th wiring operation comprises: When the wiring indicator includes line length and the intuitive reward includes an overall line length reward, determining a first length and a second length of each loop in the wiring result of the N-1th wiring operation, wherein the first length is used to indicate the sum of the Euclidean distances of the connected point pairs in the loop, and the second length is used to indicate the sum of the lengths of all connected lines in the loop; Determine the line length bonus of the corresponding loop according to the first length and the second length of each loop; The overall line length reward is determined based on the line length reward of each loop.

5. The method according to claim 1, characterized in that: The determining of at least one intuitive reward according to the wiring result of the N-1th wiring operation comprises: When the routing indicator includes the number of vias and the intuitive reward includes the overall via reward, determining the number of unnecessary vias in each loop in the routing result of the N-1th routing operation; Determine the via reward for the corresponding circuit based on the number of unnecessary vias in each circuit; The overall via reward is determined based on the via rewards of each loop.

6. The method according to claim 1, characterized in that The determining of at least one intuitive reward according to the wiring result of the N-1th wiring operation comprises: When the wiring index includes a preset index and the intuitive reward includes a preset reward, a target loop is determined from the wiring result of the N-1th wiring operation, and the target loop is a loop that requires the preset index; For each target loop, determining a target reward for the target loop; The preset reward is determined according to the target reward of each target circuit.

7. The method according to any one of claims 1 to 6, characterized in that: The adjusting the layout algorithm according to the at least one intuitive reward comprises: generating a reward array based on the at least one intuitive reward; The layout algorithm is adjusted according to the reward array.

8. The method according to any one of claims 1 to 6, characterized in that: After performing the Nth layout according to the adjusted layout algorithm to obtain the layout result of the Nth layout, the method further includes: Routing according to the layout result of the Nth layout to obtain a wiring result of the Nth wiring operation; Comparing the N-1th wiring result with the Nth wiring result to determine whether the Nth wiring result converges; When the Nth routing result converges, it is determined that the placement and routing is completed.

9. A layout and routing device, characterized in that: include: A determination module, used to determine at least one intuitive reward according to the wiring result of the N-1th wiring operation, wherein the intuitive reward is used to indicate the completion degree of the corresponding wiring indicator, where N≥2 and is an integer; an adjustment module for adjusting a layout algorithm according to the at least one intuitive reward; The processing module is used to perform the Nth layout according to the adjusted layout algorithm to obtain the layout result of the Nth layout.

10. An electronic device comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the electronic device implements the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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