Image processing method and device, equipment, storage medium and program product

Abstract

The invention provides an image processing method and device, equipment, a storage medium and a program product. The method is applied to a multi-core GPU. The image processing method comprises the following steps: dividing a plurality of cores of the multi-core GPU into at least two groups, wherein each group comprises at least one core; image rendering instructions of a plurality of picture frames are respectively transmitted to each group of cores of the multi-core GPU; wherein one picture frame corresponds to one group of image rendering instructions; at least two groups of cores of the multi-core GPU are used for respectively processing at least two groups of image rendering instructions in parallel. Through the method, the GPU utilization rate can be improved, and the rendering performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of image processing technology, and in particular to an image processing method, device, equipment, storage medium and program product. Background Art

[0002] GPU (Graphics Processing Unit), also known as display chip, is a microprocessor that performs image and graphics related operations on devices with display functions. GPU renders image or video information to display complex images on the display interface.

[0003] GPU can adopt multi-core architecture, which enables GPU to efficiently process a large number of graphics computing tasks in parallel. That is, by distributing different tasks of each frame of image to different cores for separate processing, the processing speed is improved. However, the execution rates of different rendering tasks are different, resulting in low utilization of each core and insufficient rendering performance. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide an image processing method, apparatus, device, storage medium and program product to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In one aspect, an embodiment of the present disclosure provides an image processing method, which is applied to a multi-core GPU; the image processing method comprises:

[0007] Dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core;

[0008] The image rendering instructions of multiple picture frames are transmitted to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to a group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

[0009] In some embodiments, dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core, comprises:

[0010] Configuring at least two hardware queues of the multi-core GPU; the hardware queues are used to temporarily store the image rendering instructions;

[0011] The plurality of cores are divided into at least two groups corresponding to the hardware queues, each group including at least one core.

[0012] In some embodiments, the image rendering instructions of the plurality of picture frames are transmitted to each group of the cores of the multi-core GPU respectively, including:

[0013] The image rendering instructions are transmitted to each group of the cores in sequence according to the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to different groups of the cores.

[0014] In some embodiments, the multi-core GPU includes two groups of cores; transmitting the image rendering instructions to each group of cores in sequence according to the order of the picture frames includes:

[0015] In the order of the picture frames, the image rendering instructions corresponding to the odd-numbered picture frames are transmitted to the first group of cores of the multi-core GPU, and the image rendering instructions corresponding to the even-numbered picture frames are transmitted to the second group of cores of the multi-core GPU.

[0016] In some embodiments, the image rendering instructions of the plurality of picture frames are transmitted to each group of the cores of the multi-core GPU respectively, including:

[0017] The image rendering instruction corresponding to the next picture frame to be processed is transmitted to any group of idle cores in the multi-core GPU.

[0018] In some embodiments, the method further comprises:

[0019] Instruct the multi-core GPU to send the cached data to be displayed to the display device frame by frame in sequence according to the order of the picture frames, wherein the data to be displayed is the data obtained by each group of image rendering instructions processed by the multi-core GPU.

[0020] On the other hand, the embodiment of the present disclosure further provides a GPU device, including: a multi-core GPU and a driving device;

[0021] The drive device is configured as follows:

[0022] Dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core;

[0023] The image rendering instructions of multiple picture frames are transmitted to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to a group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

[0024] On the other hand, an embodiment of the present disclosure further provides an image processing device, comprising a memory, a processor, and a computer program stored in the memory; when the processor executes the computer program, any one of the above-mentioned image processing methods is implemented.

[0025] On the other hand, an embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-mentioned image processing methods is implemented.

[0026] On the other hand, an embodiment of the present disclosure further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above-mentioned image processing methods is implemented.

[0027] In the technical solution provided by the present disclosure, the cores of a multi-core GPU are grouped and the cores of different groups are used to process the image rendering instructions of different picture frames respectively. In this way, the image rendering instructions of different picture frames can be processed in parallel, thereby reducing the difference between the utilization rates of each core caused by the different rendering rates of different image rendering instructions of the same picture frame, thereby effectively improving the utilization rate of each core of the GPU and improving the overall rendering performance of the GPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A flowchart of an image processing method provided by an embodiment of the present disclosure;

[0029] Figure 2 A schematic diagram of the principle of the image processing method provided by the embodiment of the present disclosure;

[0030] Figure 3 A structural block diagram of a GPU device provided in an embodiment of the present disclosure;

[0031] Figure 4 This is a structural block diagram of an image processing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] GPU rendering generally processes multiple frames of rendering sequentially on a single GPU graphics card, that is, each GPU only renders a certain frame at a time point. This method is suitable for most desktop and mobile applications and games.

[0036] Specifically, the GPU rendering process mainly includes:

[0037] Render the first frame: perform initialization processing, clear the target to be rendered, set the rendering state, send rendering instructions, and finally present the rendering results;

[0038] Next, loop to process the next frame.

[0039] The multi-core GPU architecture has the characteristics of efficiently processing a large number of graphics computing tasks in parallel. Generally, the rendering task of each frame can be sent to all cores of the GPU for execution at the same time, and different cores can be used to process different instructions for the same frame. When all cores have completed the rendering task, the rendering task is completed and the GPU receives the rendering task of the next frame.

[0040] For complex image processing scenarios such as games, there are many image rendering instructions for one frame, which may be sent to the GPU for rendering multiple times, and each rendering task cannot be evenly distributed to each core. However, in this case, it is still necessary to wait for all cores to complete the execution of all image rendering instructions and the rendering task of one frame before continuing to render the next frame. This imbalance in scheduling will cause a lot of isolated resource waste and prevent the GPU's rendering performance from increasing exponentially with the increase in the number of cores.

[0041] Therefore, the embodiment of the present disclosure groups the multiple cores of the GPU and optimizes the task scheduling of the GPU by means of alternating frame rendering, thereby achieving the purpose of improving performance.

[0042] like Figure 1 As shown, an embodiment of the present disclosure provides an image processing method, which is applied to a multi-core GPU. The image processing method includes:

[0043] Step S101, dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core;

[0044] Step S102, transmitting the image rendering instructions of multiple picture frames to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to a group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

[0045] When the GPU is rendering an image, it will receive rendering instructions corresponding to each frame in turn. The same frame may require one or more image rendering instructions, which are provided to the GPU core for processing in turn. When the GPU core has executed all the image rendering instructions for a frame, the rendering of the frame is completed and the frame can be displayed on the display.

[0046] Here, a picture frame refers to a frame of a picture displayed by a display screen when it is refreshed once. An image rendering instruction may be any instruction that needs to be executed by the GPU to render a picture frame.

[0047] It is understandable that if multiple cores process different image rendering instructions for a frame respectively, then the rendering tasks performed by each core are different, resulting in different processing speeds. If multiple cores are used to render the same frame, some cores will require a shorter processing time, while other cores will require a longer processing time. Each time a frame is rendered, it is necessary to wait for all cores to process all image rendering instructions for the frame, so the time required is the time required by the slowest core to process. The core with the fastest processing speed will be idle for a long time, resulting in reduced utilization.

[0048] Therefore, in the disclosed embodiment, multiple cores in a multi-core GPU can be grouped by a GPU driver, and each group of cores processes image rendering instructions for different picture frames respectively. In this way, multiple groups of cores can be processed in parallel, effectively reducing the waiting time.

[0049] Here, the GPU driver is a software driver that allows the operating system and the GPU hardware to communicate. Its main functions are: translating instructions, that is, converting high-level instructions issued by the operating system and applications into low-level instructions that the GPU can understand; optimizing the execution order and method of instructions to improve the performance and efficiency of the GPU; handling hardware errors and exceptions to ensure stable operation of the system; and providing support for hardware features and APIs, and ensuring that the GPU is compatible with different operating systems and applications. In the embodiments of the present disclosure, the GPU driver can be used to implement the above method.

[0050] In addition, it should be noted that when displaying, the pictures are displayed in sequence according to the order of the picture frames. Since each group of cores can render multiple frames synchronously, it is possible that the order in which the picture frames are rendered is different from the order in which they are displayed. Therefore, when actually displaying, the picture frames that are rendered first and in the later order can be made to wait for the picture frames that are rendered first to be completed and displayed before being displayed in the next refresh cycle. Specifically, in some embodiments, the method further includes:

[0051] Instruct the multi-core GPU to send the cached data to be displayed to the display device frame by frame in sequence according to the order of the picture frames, wherein the data to be displayed is the data obtained by each group of image rendering instructions processed by the multi-core GPU.

[0052] Each group of GPUs processes according to the received image rendering instructions. The order in which the processing is completed may be different from the order of the image frames. Therefore, each group of GPU cores can temporarily store the rendered images in the cache. Then, the GPU driver can instruct the GPU core to provide the cached data to the display device for display in sequence according to the order of the image frames. In this way, abnormal display order caused by synchronous rendering can be prevented.

[0053] For the above grouping operation, a GPU core can be divided into two groups, and receive the image rendering instructions of two picture frames. Specifically, the receiving can be started at the same time, or the instructions of the two picture frames can be received successively, or the image rendering instructions of one picture frame can be received in sequence before the image rendering instructions of the next picture frame are received. The two groups of cores process the instructions of the two picture frames respectively, and the two groups of cores process in parallel, so that the processing time periods for the image rendering instructions of the two picture frames can have a partially or completely overlapping time period.

[0054] It should be noted that a set of image rendering instructions for a picture frame may include one or more, and the number may be greater than the number of a set of cores. If the number of a set of image rendering instructions is greater than the number of a set of cores, then a set of cores may include some cores that process multiple image rendering instructions, and some cores that only process one image rendering instruction.

[0055] In actual applications, each instruction can be assigned to a group of cores for processing in sequence, and the remaining unprocessed image rendering instructions can wait for the core in the group of cores that has completed the last processing. For example, an idle core in a group of cores is detected, and when an idle core is detected, the unprocessed image rendering instructions are transferred to the idle core for processing. In this way, the utilization rate of the core can be effectively improved, so that image rendering instructions with fast processing speed are more likely to be assigned to the same core for processing, that is, some cores process multiple simple image rendering instructions, and some cores only process one complex image rendering instruction.

[0056] In addition, it is also possible that the number of a group of image rendering instructions is less than or equal to the number of a group of cores. If the number of a group of image rendering instructions is equal to the number of a group of cores, the group of image rendering instructions can be distributed to each core for processing; if the number of a group of image rendering instructions is less than the number of a group of cores, there are still idle cores when processing a group of image rendering instructions. Of course, in order to maximize the use of cores, when grouping, it can be considered to make the number of cores in each group less than or equal to the number of a group of image rendering instructions as much as possible.

[0057] In some embodiments, in the above step S101, the dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core, includes:

[0058] Configuring at least two hardware queues of the multi-core GPU; the hardware queues are used to temporarily store the image rendering instructions;

[0059] The multiple cores are divided into at least two groups corresponding to the hardware queues, each group including at least one core. The hardware queue of the GPU refers to a workflow queue used to manage and schedule execution tasks in the GPU hardware. The hardware queue is responsible for storing and blocking commands and tasks to be executed in the GPU architecture so that the GPU can process these tasks efficiently. In the embodiment of the present disclosure, the hardware queue of the GPU can be configured through a driver, and at least two hardware queues of the GPU can be configured using a driver. These hardware queues can respectively schedule different workflows, that is, respectively schedule different image rendering instructions.

[0060] In addition, the embodiment of the present disclosure also divides the multiple cores into at least two groups through a driver program, so that each hardware queue corresponds to a group of GPU cores.

[0061] like Figure 2 As shown, taking an 8-core GPU as an example, the 8 cores are divided into two groups (group 0 and group 1) corresponding to hardware queue 0 and hardware queue 1 respectively, wherein group 0 includes cores 0 to core 3, and group 1 includes cores 4 to core 7.

[0062] Each group of image rendering instructions for frame 0 to frame 5 is transmitted alternately and sequentially to the above-mentioned hardware queue. In this way, through the image rendering instructions, each group of cores can execute each image rendering instruction provided by the corresponding hardware queue in sequence.

[0063] In actual applications, the number of core groups and the number of cores in each group can be set according to the needs, and there is no restriction here. In addition, the number of hardware queues can be consistent with the number of core groups, and each group corresponds to a hardware queue. In the above example, each hardware queue can receive image rendering instructions in a fixed order of odd and even frames, such as Figure 2As shown, hardware queue 0 is used to receive image rendering instructions for even frames, namely frame 0, frame 2, frame 4, etc.; hardware queue 1 is used to receive image rendering instructions for odd frames, namely frame 1, frame 3, frame 5, etc.

[0064] In some other embodiments, the GPU cores may be grouped into other numbers, for example, 3 groups, corresponding to hardware queue 0, hardware queue 1, and hardware queue 2. Each hardware queue may receive image rendering instructions for each picture frame in sequence.

[0065] In this way, by grouping the hardware queue, the image rendering instructions corresponding to each frame can be transmitted to the corresponding core group in sequence through the hardware queue, so that the cores of each group can perform parallel processing.

[0066] In some embodiments, the image rendering instructions of the plurality of picture frames are transmitted to each group of the cores of the multi-core GPU respectively, including:

[0067] Each group of the image rendering instructions is transmitted to each group of the cores in sequence according to the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to different groups of the cores.

[0068] Here, the order of picture frames is the order in which the pictures are played. The processor (such as CPU) issues image rendering instructions in the order of picture frames. After the driver receives the image rendering instructions in order, it can transmit them to the GPU hardware queue in sequence, and then provide them to the GPU core for processing by the GPU core. Here, the driver can provide each group of image rendering instructions to each hardware queue in the order of multiple core groupings, or provide different groups of image rendering instructions to different hardware queues in a random order. In addition, since the image rendering instructions of two adjacent picture frames are provided to different groups of cores, each group of cores can be rendered alternately, avoiding the situation where two adjacent frames need to be queued for processing, thereby effectively improving processing efficiency.

[0069] In practical applications, multiple groups of cores may be numbered, and the image rendering instructions for each frame may be received in sequence according to the order of the numbers and the order of the frames.

[0070] For example, the GPU cores are divided into 4 groups, namely group 0, group 1, group 2 and group 3. Then group 0 processes frame 0, frame 4, frame 8, etc., group 1 processes frame 1, frame 5, frame 9, etc., group 2 processes frame 2, frame 6, frame 10, etc., group 3 processes frame 3, frame 7, frame 11, etc. Each group can process in parallel. For example, the above 4 groups of cores process image rendering instructions for frames 0 to 3 respectively. These 4 frames can be rendered at the same time or one after another.

[0071] It is understandable that although multiple sets of cores can process multiple frames in parallel, they still need to be displayed in the order of frames. For example, if frames 0 to 3 are rendered at the same time, they will be displayed in the order of frames 0 to 3. However, if the previous frame has not been rendered and the next frame has been rendered, it is necessary to wait until the previous frame is rendered and displayed before displaying the next frame.

[0072] In this way, the image rendering instructions corresponding to each picture frame can be provided to different groups in sequence, without the need for additional processing operations, which can effectively improve processing efficiency.

[0073] In some embodiments, the grouping of GPU cores can be set according to actual needs, and at least two grouping modes are provided, which are switched according to different scenarios or applications, or according to user settings. Exemplarily, "Grouping Mode" and "Normal Mode (No Grouping)" are provided for user selection. When the user selects "Grouping Mode", a fixed grouping mode is adopted, for example, multi-core GPUs are divided into two groups. Specifically, for an 8-core GPU, the 0th to 3rd cores are divided into the first group, and the 4th to 7th cores are divided into the second group. When the user selects "Normal Mode", normal display is performed without grouping.

[0074] Exemplarily, multiple grouping methods may be provided, each with a different number of groups or a different number of cores in each group, etc. The specific grouping method may be designed according to the number of GPU cores and applicable scenarios, and the embodiments of the present disclosure do not limit this.

[0075] In some embodiments, the multi-core GPU includes two groups of cores; transmitting each group of the image rendering instructions to each group of the cores in sequence according to the order of the picture frames includes: transmitting the image rendering instructions corresponding to the odd-numbered picture frames to the first group of cores of the multi-core GPU, and transmitting the image rendering instructions corresponding to the even-numbered picture frames to the second group of cores of the multi-core GPU in sequence.

[0076] Here, the case where the GPU cores are divided into two groups is provided, and then they can be provided to different groups in sequence according to the odd and even order of the picture frames. For example, the first group of cores processes the image rendering instructions of the odd frames (i.e., the odd-numbered picture frames mentioned above); the second group of cores processes the image rendering instructions of the even frames (i.e., the even-numbered picture frames mentioned above). In other embodiments, the first group of cores can process the image rendering instructions of the even frames, and the second group of cores processes the image rendering instructions of the odd frames.

[0077] The first group of cores and the second group of cores in the embodiment of the present disclosure are only used to distinguish the two groups of cores and are not used to limit the order in which the two cores are grouped.

[0078] In this way, alternating rendering through the cores of two groups can effectively improve the processing efficiency, and the grouping structure is simple and easy to implement.

[0079] In some embodiments, the image rendering instructions of the plurality of picture frames are transmitted to each group of the cores of the multi-core GPU respectively, including:

[0080] The image rendering instruction corresponding to the next picture frame to be processed is transmitted to any group of idle cores in the multi-core GPU.

[0081] Considering that the image rendering instructions for different frames may be different, the processing speed of each instruction in different core groups is also different. For example, the first group of cores takes t1 time to process the first frame, and the second group of cores takes t2 time to process the second frame. The t2 time may be less than t1 time. In other words, the second group of cores may complete the current rendering task before the first group of cores. If they are allocated in sequence, it may be necessary to wait for the first group of cores to finish processing before the two groups of cores can receive the image rendering instructions for the next two frames in turn. This may cause the cores of the second group to be idle for a period of time.

[0082] Therefore, another implementation of group processing is provided here, that is, after a group of cores finish executing a group of image rendering instructions, they receive the next group of image rendering instructions. That is to say, in the above example, the second group of cores first processes a group of image rendering instructions for the second screen frame, and then can receive a group of image rendering instructions for the third screen frame. The first group of cores continues to process the image rendering instructions for the first screen frame, and after the first group of processing is completed, it receives a group of image rendering instructions for the next frame (the fourth screen frame).

[0083] Take the example of three groups of cores (group 0, group 1, group 2). After initialization, the driver will provide the image rendering instructions corresponding to the 0th, 1st, and 2nd frames to the above-mentioned groups 0, 1, and 2 for processing. Assuming that group 1 is processed first and enters the idle state, the driver will provide the image rendering instructions corresponding to the next frame (the 3rd frame) to group 1. At this time, group 0, group 1, and group 2 process the 0th, 3rd, and 2nd frames respectively. Next, the 0th frame is processed, group 0 enters the idle state, and the driver provides the image rendering instructions corresponding to the next frame (the 4th frame) to group 0...

[0084] In this way, the driver can allocate image rendering instructions in sequence instead of in the order of core group numbers, but can provide each group of image rendering instructions to any core in an idle group. Alternatively, the driver can respond to any group of cores entering an idle state after executing image rendering instructions, and then provide the next group of image rendering instructions to be processed to the idle cores in that group, thereby further improving the overall processing efficiency and reducing the probability of core idleness. Since the rendered data obtained after each group of cores completes processing will be temporarily stored in the cache, and further displayed in the order of picture frames based on the driver's instructions, the processing order of image rendering instructions will not affect the display order.

[0085] Based on the same inventive concept, the embodiment of the present disclosure also provides a GUP device, such as Figure 3 As shown, the GPU device 300 includes: a multi-core GPU 301 and a driving device 302;

[0086] The driving device 302 is configured as follows:

[0087] Dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core;

[0088] The image rendering instructions of multiple picture frames are transmitted to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to a group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

[0089] In some embodiments, the driving device is specifically configured as:

[0090] At least two hardware queues of the multi-core GPU are configured; the hardware queues are used to temporarily store the image rendering instructions; the multiple cores are divided into at least two groups corresponding to the hardware queues, each group including at least one core.

[0091] In some embodiments, the driving device is specifically configured as:

[0092] Each group of the image rendering instructions is transmitted to each group of the cores in sequence according to the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to different groups of the cores.

[0093] In some embodiments, the multi-core GPU includes two groups of cores; the driving device is further configured to:

[0094] In the order of the picture frames, the image rendering instructions corresponding to the odd-numbered picture frames are transmitted to the first group of cores of the multi-core GPU, and the image rendering instructions corresponding to the even-numbered picture frames are transmitted to the second group of cores of the multi-core GPU.

[0095] In some embodiments, the driving device is specifically configured as:

[0096] The image rendering instruction corresponding to the next picture frame to be processed is transmitted to any group of idle cores in the multi-core GPU.

[0097] In some embodiments, the GPU device further includes a cache unit, and the driving device is further configured to:

[0098] Instruct the multi-core GPU to send the cached data to be displayed to the display device frame by frame in sequence according to the order of the picture frames, wherein the data to be displayed is the data obtained by each group of image rendering instructions processed by the multi-core GPU.

[0099] Based on the same inventive concept, the embodiment of the present disclosure also provides an image display device 400, such as Figure 4 As shown, the image display device 400 includes: a processor 401 and a memory 402, wherein the memory 402 stores a computer program 4021 that can be run on the processor 401, and when the processor 401 executes the computer program 4021, the image processing method in any of the above embodiments can be implemented.

[0100] In some embodiments, the memory 402 stores a computer program 4021 that can be run on the processor. The memory 402 is configured to store instructions and applications executable by the processor 401. It can also cache data to be processed or processed by the processor 401 and each module in the image display device 400 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0101] In some embodiments, the processor 401 implements the steps of any of the above-mentioned task processing methods when executing the program. The processor 401 generally controls the overall operation of the image display device 400.

[0102] Based on the same inventive concept, an embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-mentioned image processing methods is implemented.

[0103] Based on the same inventive concept, an embodiment of the present disclosure further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above-mentioned image processing methods is implemented.

[0104] In some specific examples, the processor may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understandable that the electronic device that implements the functions of the processor may also be other, and the embodiments of the present disclosure are not specifically limited.

[0105] In some specific examples, the above-mentioned computer storage medium / memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM) and the like; it can also be various terminals including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.

[0106] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0107] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0108] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An image processing method, characterized in that: Applied to a multi-core image processor GPU; the image processing method comprises: Dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core; The image rendering instructions of multiple picture frames are transmitted to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to a group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

2. The image processing method according to claim 1, characterized in that: The method of dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core, comprises: Configuring at least two hardware queues of the multi-core GPU; the hardware queues are used to temporarily store the image rendering instructions; The plurality of cores are divided into at least two groups corresponding to the hardware queues, each group including at least one core.

3. The image processing method according to claim 1, characterized in that: The step of transmitting the image rendering instructions of the plurality of picture frames to the cores of each group of the multi-core GPU respectively includes: Each group of the image rendering instructions is transmitted to each group of the cores in sequence according to the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to different groups of the cores.

4. The image processing method according to claim 3, characterized in that: The multi-core GPU includes two groups of cores; the image rendering instructions of each group are transmitted to each group of cores in sequence according to the order of picture frames, including: According to the order of the picture frames, the image rendering instructions corresponding to the odd-numbered picture frames are transmitted to the first group of cores of the multi-core GPU, and the image rendering instructions corresponding to the even-numbered picture frames are transmitted to the second group of cores of the multi-core GPU.

5. The image processing method according to claim 1, characterized in that: The step of transmitting the image rendering instructions of the plurality of picture frames to the cores of each group of the multi-core GPU respectively includes: The image rendering instruction corresponding to the next picture frame to be processed is transmitted to any group of idle cores in the multi-core GPU.

6. The image processing method according to any one of claims 1 to 5, characterized in that: The method further comprises: Instruct the multi-core GPU to send the cached data to be displayed to the display device frame by frame in sequence according to the order of the picture frames, wherein the data to be displayed is the data obtained by each group of image rendering instructions processed by the multi-core GPU.

7. A GUP device, characterized in that: Including: multi-core GPU and driver; The drive device is configured as follows: Dividing the multiple cores of the multi-core GPU into at least two groups, each group including at least one core; The image rendering instructions of multiple picture frames are transmitted to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to a group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

8. An image processing device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory; when the processor executes the computer program, the image processing method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the image processing method according to any one of claims 1 to 7 is implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the image processing method according to any one of claims 1 to 7 is implemented.

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