Memory device and operating method thereof, memory system

Abstract

This disclosure provides a memory device including a memory array and peripheral circuitry. The memory array includes multiple memory cell strings, each memory cell string including adjacent first and second memory groups. Both the first and second memory groups include multiple memory cells. The first memory group is in a programming state, and at least some memory cells in the second memory group are in an erasing state. The first memory group includes a first sub-memory group and a second sub-memory group, with the second sub-memory group located between the first and second sub-memory groups. The peripheral circuitry is configured to: apply a first on-state voltage to word lines coupled to the first memory group during a first pre-charge phase; and apply a first voltage to word lines coupled to memory cells of the second sub-memory group and a second voltage to word lines coupled to memory cells of the first sub-memory group during a second pre-charge phase following the first pre-charge phase; the first voltage is less than the second voltage and both are less than the first on-state voltage.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a memory device and its operation method, and a memory system. Background Technology

[0002] With technological advancements, the semiconductor industry is constantly seeking new production methods to enable each memory die in a memory device to have a greater number of memory cells. Among these, 3D NAND memory devices, due to their advantages such as high storage density and low cost, have become a cutting-edge and highly promising three-dimensional memory technology.

[0003] However, there are still many problems to be solved in memory devices in related technologies.

[0004] Public content

[0005] According to a first aspect of the present disclosure, a memory device is provided, the memory device comprising: a memory array and peripheral circuitry coupled to the memory array; the memory array comprising a plurality of memory cell strings, each memory cell string comprising an adjacent first memory group and a second memory group; both the first memory group and the second memory group comprising a plurality of memory cells, the first memory group being in a programming state, and at least a portion of the memory cells in the second memory group being in an erasing state; the first memory group comprising a first sub-memory group and a second sub-memory group, the second sub-memory group being located between the first sub-memory group and the second memory group;

[0006] The peripheral circuit is configured as follows:

[0007] During the first pre-charge phase, a first on-state voltage is applied to the word lines coupled to the first memory group;

[0008] In the second pre-charge phase following the first pre-charge phase, a first voltage is applied to the word lines coupled to the memory cells of the second sub-memory group, and a second voltage is applied to the word lines coupled to the memory cells of the first sub-memory group; the first voltage is less than the second voltage and both are less than the first turn-on voltage.

[0009] In the above scheme, the memory array further includes a first conductive line; the end of the first memory group away from the second memory group is connected to the first conductive line; the peripheral circuit is configured as follows:

[0010] A first pre-charge voltage is applied to the first conductive line during the first pre-charge phase and the second pre-charge phase.

[0011] In the above scheme, some memory cells in the second memory group are in a programmed state, and the memory cells in the programmed state in the second memory group are far away from the first memory group, while the memory cells in the erased state in the second memory group are close to the first memory group; the peripheral circuit is configured as follows:

[0012] During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells of the second memory group are all connected to the ground voltage.

[0013] In the above scheme, some memory cells in the second memory group are in a programmed state, and the memory cells in the programmed state in the second memory group are close to the first memory group; the peripheral circuit is configured as follows:

[0014] During the first pre-charge phase, a second on-state voltage is applied to the word lines coupled to the memory cells of the second memory group that are in the programming state;

[0015] During the second pre-charge phase, a third voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group, and a fourth voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group; the fourth voltage is less than the third voltage, the third voltage is less than or equal to the first voltage, and both the third voltage and the fourth voltage are less than the second turn-on voltage.

[0016] In the above scheme, the peripheral circuit is configured as follows:

[0017] During the first precharge phase and the second precharge phase, the word lines coupled to the memory cells in the erase state in the second memory group are connected to the ground voltage.

[0018] In the above scheme, the peripheral circuit is configured as follows:

[0019] In the third precharge phase following the second precharge phase, the word lines coupled to the memory cells in the first memory group and the second memory group are all connected to the ground voltage.

[0020] In the above scheme, the peripheral circuit is configured as follows:

[0021] In the programming voltage application phase following the third pre-charge phase, a programming voltage is applied to the word line coupled to the selected memory cell in the erased state of the second memory group.

[0022] In the above scheme, the memory array further includes a second conductive line, and each memory cell string further includes a third memory group; the third memory group includes multiple memory cells, and each memory cell is in a programmed state; the second memory group is located between the first memory group and the third memory group; the end of the third memory group away from the second memory group is connected to the second conductive line.

[0023] In the above scheme, the memory array includes:

[0024] A first stacking structure is provided, wherein a first channel structure is provided through the first stacking structure; the first stacking structure includes a plurality of first memory groups arranged side by side along a direction perpendicular to the stacking direction;

[0025] A second stacking structure is located on the first stacking structure; the second stacking structure is provided with a second channel structure that penetrates the second stacking structure and is connected to the first channel structure; the second stacking structure includes a plurality of second memory groups arranged side by side along a direction perpendicular to the stacking direction;

[0026] A third stacking structure is located on the second stacking structure; the third stacking structure is provided with a third channel structure that penetrates the third stacking structure and is connected to the second channel structure; the third stacking structure includes a plurality of the third memory groups arranged side by side along a direction perpendicular to the stacking direction.

[0027] In the above scheme, the peripheral circuit is configured as follows:

[0028] During the first pre-charge phase and the second pre-charge phase, the word lines and second conductive lines coupled to the memory cells in the third memory group are all connected to the ground voltage.

[0029] In the above scheme, the third storage group includes a third sub-storage group and a fourth sub-storage group, and the third sub-storage group is located between the fourth sub-storage group and the second storage group; the peripheral circuit is configured as follows:

[0030] During the first pre-charge phase, a second pre-charge voltage is applied to the second conductive line, and a third on-voltage is applied to the word line coupled to the third memory group.

[0031] During the second pre-charge phase, the second pre-charge voltage is applied to the second conductive line, and a fifth voltage is applied to the word line coupled to the memory cell of the third sub-memory group, and a sixth voltage is applied to the word line coupled to the memory cell of the fourth sub-memory group; the fifth voltage is less than the sixth voltage and both are less than the third turn-on voltage.

[0032] In the above scheme, the memory array further includes a first selection transistor and a second selection transistor; the first selection transistor is located between the first conductive line and the first memory group, and is connected to both the first conductive line and the first memory group; the second selection transistor is located between the second conductive line and the third memory group, and is connected to both the second conductive line and the third memory group; the peripheral circuit is configured as follows:

[0033] During the first pre-charge phase and the second pre-charge phase, a third pre-charge voltage is applied to the first selector and a fourth pre-charge voltage is applied to the second selector.

[0034] According to a second aspect of the present disclosure, a memory system is provided, including a memory controller and a memory device as described in any of the above embodiments; the memory controller is coupled to the memory device and configured to control the memory device.

[0035] According to a third aspect of the present disclosure, a method for operating a memory device is provided, the method comprising:

[0036] During the first pre-charge phase, a first on-state voltage is applied to the word line coupled to the first memory group of the memory cell string in the programming state;

[0037] In the second precharge phase following the first precharge phase, a first voltage is applied to the word lines of the second sub-storage group located between the first sub-storage group and the second storage group where at least some of the storage cells are in an erased state, and a second voltage is applied to the word lines of the first sub-storage group in the first storage group; the first voltage is less than the second voltage and both are less than the first turn-on voltage.

[0038] The above scheme further includes the following operating method:

[0039] During the first precharge phase and the second precharge phase, a first precharge voltage is applied to a first conductive line connected to the end of the first memory group that is away from the second memory group.

[0040] The above scheme further includes the following operating method:

[0041] During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells of the second memory group in which some memory cells are in the programming state are all connected to the ground voltage; the memory cells in the programming state in the second memory group are far away from the first memory group, and the memory cells in the erasure state in the second memory group are close to the first memory group.

[0042] The above scheme further includes the following operating method:

[0043] During the first pre-charge phase, a second on-state voltage is applied to the word lines coupled to the memory cells in the second memory group that are in the programming state; the memory cells in the second memory group that are in the programming state are close to the first memory group;

[0044] During the second pre-charge phase, a third voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group, and a fourth voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group; the fourth voltage is less than the third voltage, the third voltage is less than or equal to the first voltage, and both the third voltage and the fourth voltage are less than the second turn-on voltage.

[0045] The above scheme further includes the following operating method:

[0046] During the first precharge phase and the second precharge phase, the word lines coupled to the memory cells in the erase state in the second memory group are connected to the ground voltage.

[0047] The above scheme further includes the following operating method:

[0048] In the third precharge phase following the second precharge phase, the word lines coupled to the memory cells in the first memory group and the second memory group are all connected to the ground voltage.

[0049] The above scheme further includes the following operating method:

[0050] In the programming voltage application phase following the third pre-charge phase, a programming voltage is applied to the word line coupled to the selected memory cell in the erased state of the second memory group.

[0051] The above scheme further includes the following operating method:

[0052] During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells in the third memory group in the programming state of the memory cell string, as well as the second conductive lines connected to the end of the third memory group away from the second memory group, are all connected to the ground voltage; the second memory group is located between the first memory group and the third memory group.

[0053] The above scheme further includes the following operating method:

[0054] During the first pre-charge phase, a second pre-charge voltage is applied to the second conductive line connected to the end of the third memory group of the memory cell string that is away from the second memory group, and a third on-state voltage is applied to the word line coupled to the third memory group; the second memory group is located between the first memory group and the third memory group.

[0055] During the second pre-charge phase, the second pre-charge voltage is applied to the second conductive line, and a fifth voltage is applied to the word line of the storage cell of the third sub-storage group located between the fourth sub-storage group and the second storage group. A sixth voltage is applied to the word line of the storage cell of the fourth sub-storage group of the third storage group. The fifth voltage is less than the sixth voltage and both are less than the third turn-on voltage.

[0056] The above scheme further includes the following operating method:

[0057] During the first pre-charge phase and the second pre-charge phase, a third pre-charge voltage is applied to a first select transistor located between the first conductive line and the first memory group, which is connected to both the first conductive line and the first memory group, and a fourth pre-charge voltage is applied to a second select transistor located between the second conductive line and the third memory group, which is connected to both the second conductive line and the third memory group.

[0058] In this embodiment, firstly, by applying a first on-state voltage to the word lines coupled to the first memory group during a first pre-charge phase, the first memory group maintains the first on-state voltage, thereby conducting the channel to pre-charge the memory cell string and clear residual electrons in the channel below the word line coupled to the memory cell in the erased state in the second memory group; secondly, during a second pre-charge phase, a first voltage is applied to the word lines coupled to the memory cells of the second sub-memory group close to the second memory group, and a second voltage greater than the first voltage is applied to the word lines coupled to the memory cells of the first sub-memory group far from the second memory group, thereby constructing a stepped potential on the word lines coupled to the memory cells of the first memory group, which reduces the backflow of electrons into the channel corresponding to the second memory group and reduces the decoupling residual electrons in the channel corresponding to the second memory group, thereby effectively improving the pre-charge effect and reducing programming interference. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0060] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0061] Figure 2bThis is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0062] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0063] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0064] Figure 4 This is a schematic cross-sectional view of a memory array including a string of memory cells according to an embodiment of the present disclosure;

[0065] Figure 5 This is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present disclosure;

[0066] Figure 6 This is a schematic diagram of the framework structure of a memory system according to an embodiment of the present disclosure;

[0067] Figure 7 A schematic diagram of a storage cell string provided in an embodiment of this disclosure. Figure 1 ;

[0068] Figure 8 A voltage waveform variation diagram provided in this embodiment of the present disclosure Figure 1 ;

[0069] Figure 9 This is a schematic diagram illustrating the implementation flow of an operation method for a memory device according to an embodiment of the present disclosure;

[0070] Figure 10 This is a schematic diagram of the structure of a storage cell string provided in an embodiment of the present disclosure;

[0071] Figure 11 A second schematic diagram of voltage waveform variation provided in an embodiment of this disclosure;

[0072] Figure 12 A schematic diagram of a storage cell string structure provided in this embodiment of the present disclosure is shown in Figure 3.

[0073] Figure 13 A schematic diagram of voltage waveform variation provided in this embodiment of the present disclosure is shown in Figure 3.

[0074] Figure 14 A schematic diagram of a storage cell string provided in an embodiment of this disclosure. Figure 4 ;

[0075] Figure 15 A voltage waveform variation diagram provided in this embodiment of the present disclosure Figure 4 ;

[0076] Figure 16a A schematic diagram of channel potential change provided in an embodiment of this disclosure;

[0077] Figure 16b This is a schematic diagram illustrating an electron migration process provided in an embodiment of the present disclosure;

[0078] Figure 17 A schematic diagram of a storage cell string provided in an embodiment of this disclosure. Figure 5 ;

[0079] Figure 18 A voltage waveform variation diagram provided in this embodiment of the present disclosure Figure 5 ;

[0080] Figure 19 A schematic diagram of a storage cell string provided in an embodiment of this disclosure. Figure 6 ;

[0081] Figure 20 A voltage waveform variation diagram provided in this embodiment of the present disclosure Figure 6 ;

[0082] Figure 21 A voltage waveform variation diagram provided in this embodiment of the present disclosure Figure 7 ;

[0083] Figure 22 A voltage waveform variation diagram provided in this embodiment of the present disclosure Figure 8 ;

[0084] Figure 23 This is a schematic diagram of a stacked structure provided in an embodiment of the present disclosure. Detailed Implementation

[0085] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0086] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0087] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0088] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0089] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0090] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0091] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0092] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host device 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host device 108 may be a processor (e.g., a central processing unit) or a system-on-a-chip (e.g., an application processor) of an electronic device. The host device 108 may be configured to send data to or receive data from the memory device 104.

[0093] According to some embodiments, memory controller 106 is coupled to memory device 104 and host device 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host device 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, universal serial bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0094] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable function, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host device 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCHS), Advanced Technology Attached Protocol (ATIP), Serial Advanced Technology Attached Protocol (STP), Parallel Advanced Technology Attached Protocol (PATP), Minicomputer Small Interface Protocol (MSIP), Enhanced Small Disk Interface (MSDI), Integrated Drive Electronic Devices Protocol (IDEMP), firmware protocols, etc.

[0095] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash memory card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host device (e.g., Figure 1 The host device 108 in the memory card connector 204 is coupled to it. In such a way... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include interfaces for connecting the SSD 206 to host devices (e.g., Figure 1 The SSD connector 208 is coupled to the host device 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0096] Figure 3a An exemplary schematic diagram of a three-dimensional NAND flash memory array is provided, such as... Figure 3aAs shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Every four rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The storage block shown contains 6 storage slices. In practical applications, the number of storage slices in a storage block is not limited to this. A storage cell in a storage slice coupled to a word line can be associated with a storage page (a physical page).

[0097] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0098] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 306 are NAND memory cells, provided in the form of an array of memory cell strings 308, each memory cell string 308 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0099] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0100] like Figure 3b As shown, each memory cell string 308 may include a bottom selected transistor (BST) 310 at its source end and a top selected transistor (TST) 312 at its drain end. BST 310 and TST 312 may be configured to activate the selected memory cell string 308 during read and program operations. In some embodiments, the sources of memory cell strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory cell strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory cell string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory cell string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TST312) or a deselection voltage (e.g., 0V) to the corresponding TST312 via one or more TSL (Top selected line) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BST310) or a deselection voltage (e.g., 0V) to the corresponding BST310 via one or more BSL (Bottom Selected line) 315.

[0101] like Figure 3bAs shown, the memory cell string 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory cell strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0102] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including a string of memory cells 308, according to some aspects of this disclosure, is shown. Figure 4 As shown, the memory cell string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory cell string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412. The number of memory cells included in the memory array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0103] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0104] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0105] In some embodiments, the memory cell string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0106] Return to reference Figure 3b Peripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, BSL 315, and TSL 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSL 315, and TSL 313, and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0107] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more memory cell strings 308 by applying a bit line voltage generated from voltage generator 510.

[0108] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSL 315 and TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0109] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host device (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host device. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0110] Figure 6 A block diagram of a memory system 601 is shown. The memory system 601 includes a memory controller 602 and a memory device 603. The memory controller 602 controls the memory device 603 to perform read and write operations. Here, the memory controller 602 and the memory device 603 can be coupled in any suitable manner. The memory controller 602 includes a control unit (CPU) 608, a cache 609, an error correction unit 606, a host I / F 605, a memory I / F 607, a wear leveling unit 611, and a garbage collection unit 612. In this embodiment, the memory device 603 can be a non-volatile semiconductor memory for storing data, such as a NAND flash memory. The memory system 601 is connected to a host 604. The host I / F 605 outputs commands and valid data (write data) received from the host 604 to the internal bus 610, and sends valid data read from the memory device 603 (read data) and responses from the control unit 608 back to the host 604.

[0111] The memory I / F 607 controls the processes of writing data to and reading data from the memory device 603 based on instructions from the control unit 608. The control unit 608 controls the memory system 601 as a whole; the control unit 608 may be, for example, a central processing unit (CPU) or a microprocessor (MPU). The control unit 608 performs control based on commands received from the host 604 via the host I / F 605. For example, the control unit 608 instructs the memory I / F 607 to write data to the memory device 603 based on a command from the host 604. Furthermore, the control unit 608 instructs the memory I / F 607 to read data from the memory device 603 based on a command from the host 604.

[0112] The buffer 609 temporarily stores the data received from the host 604 before storing it in the memory device 603, and temporarily stores the data read from the memory device 603 before sending it to the host 604.

[0113] Error correction unit 606 is a data encoding and decoding unit. Due to the bit error rate in flash memory storage, error checking and correction (ECC) protection should be added to the original data during data writing operations to ensure data integrity. This is an encoding process. Similarly, when reading data, decoding is required for error detection and correction. If the number of erroneous bits exceeds the ECC error correction capability, the data will be uploaded to the host in an "uncorrectable" form. The ECC encoding and decoding process here is performed by error correction unit 606.

[0114] Due to the demand for high-capacity, low-cost storage media, 3D NAND memory devices are continuously increasing the number of stacked layers to improve storage density. In some embodiments, 3D NAND memory devices use memory blocks as the smallest unit for erase operations. Larger memory block capacities undoubtedly increase the system burden of data management and affect product performance; therefore, it is necessary to consider dividing the memory block into multiple stacked structures, i.e., multiple decks, each of which performs separate encoding, erasing, and read operations. Each memory block in a 3D NAND memory device includes multiple arrayed strings of memory cells, and each string of memory cells includes multiple memory cells connected in series. In these multiple strings of memory cells, memory cells located on the same layer are connected to the same word line. When programming a selected memory cell, a programming voltage needs to be applied to the selected word line coupled to the selected memory cell to cause electrons in the channel of the selected memory cell to tunnel to the floating gate. However, this programming voltage can also cause electron tunneling in unselected memory cells connected to the selected word line, affecting subsequent programming or data reading of those unselected memory cells. In other words, when programming a selected memory cell, the unselected memory cells connected to the selected word line will be subject to programming interference. To reduce programming interference, a pre-charge voltage can be applied to the memory cell string corresponding to the unselected memory cell connected to the selected word line before applying the programming voltage to the selected word line, thereby reducing the number of electrons in the channel of the unselected memory cell. Thus, when programming the selected memory cell, the probability of electron tunneling in the unselected memory cell can be effectively reduced, thereby suppressing programming interference.

[0115] In some embodiments, the memory block is divided into three or more stacked structures for independent operation. When the stacked structures on both sides are already programmed, there is no discharge path for the channel electrons during the pre-charge stage when programming the middle stacked structure. Therefore, it is necessary to develop a new pre-charge strategy to enhance the raised potential during the programming process and reduce programming crosstalk.

[0116] In some embodiments, such as Figure 7 As shown, the memory cell string includes a first memory group, a second memory group, and a third memory group. The second memory group is located between the first and third memory groups. The end of the third memory group furthest from the second memory group can be connected to a bit line, and the end of the first memory group furthest from the second memory group can be connected to a common source line. With the memory cells in the first and second memory groups already programmed, when programming the memory cells in the second memory group in reverse programming order (top to bottom), the voltage applied is as follows: Figure 8 As shown, in the pre-charge stage, a first pre-charge voltage (Vpre1) is applied to the common source line, and a third pre-charge voltage (Vpre3) is applied to the lower select transistor. In the first pre-charge stage (stage 1), a first turn-on voltage (Vpass1) is applied to the word lines coupled to the memory cells of the first memory group. In the second pre-charge stage (stage 2), all word lines coupled to the memory cells of the first memory group are connected to ground, causing the corresponding channel of the first memory group to be turned on in the first pre-charge stage, thereby releasing the residual electrons in the corresponding channel of the second memory group. However, in the second pre-charge stage, since all word lines coupled to the memory cells of the first memory group are connected to ground, the channel potential of the channel below the word lines coupled to the memory cells of the first memory group decreases. A potential difference is formed between the channel below the word lines coupled to the memory cells of the first memory group and the channel below the word lines coupled to the second memory group. This causes the electrons induced by the gate voltage and decoupled from the word line channel of the memory cells coupled to the first memory group to flow back to the corresponding channel of the second memory group, thus affecting the programming pre-charge effect.

[0117] Improving programming pre-charge effectiveness and reducing programming interference have become pressing issues. Based on one or more of these issues, this disclosure provides an operation method for a memory device, such as… Figure 9 As shown, the method includes:

[0118] Step S1001: In the first pre-charge phase, a first on-state voltage is applied to the word line coupled to the first memory group of the memory cell string in the programming state;

[0119] Step S1002: In the second pre-charge stage after the first pre-charge stage, a first voltage is applied to the word lines of the second sub-storage group located between the first sub-storage group and the second storage group where at least some storage cells are in the erase state, and a second voltage is applied to the word lines of the first sub-storage group in the first storage group; the first voltage is less than the second voltage and both are less than the first turn-on voltage.

[0120] In this embodiment of the present disclosure, in a first aspect, by applying a first on-state voltage to the word lines coupled to the first memory group during the first pre-charge phase, the first memory group maintains the first on-state voltage, thereby making the channel on-state and clearing residual electrons in the channel below the word line coupled to the memory cell in the erase state of the second memory group; in a second aspect, during the second pre-charge phase, a first voltage is applied to the word lines coupled to the memory cells of the second sub-memory group that are close to the second memory group, and a second voltage greater than the first voltage is applied to the word lines coupled to the memory cells of the first sub-memory group that are far from the second memory group, thereby constructing a stepped potential on the word lines coupled to the memory cells of the first memory group, thereby reducing the backflow of electrons into the channel corresponding to the second memory group, and reducing the decoupling residual electrons in the channel corresponding to the second memory group, thereby effectively improving the pre-charge effect and reducing programming interference.

[0121] In some specific examples, the memory device includes a memory array and peripheral circuitry coupled to the memory array; the memory array includes a plurality of memory cell strings, each memory cell string including an adjacent first memory group and a second memory group; both the first memory group and the second memory group include a plurality of memory cells, the first memory group is in a programmed state, and at least some of the memory cells in the second memory group are in an erased state; the first memory group includes a first sub-memory group and a second sub-memory group, and the second sub-memory group is located between the first sub-memory group and the second memory group.

[0122] In this embodiment of the present disclosure, the first storage group may be located below the second storage group and coupled to the lower select transistor; the first storage group may also be located above the second storage group and coupled to the upper select transistor.

[0123] In some embodiments, the operating method further includes:

[0124] During the first precharge phase and the second precharge phase, a first precharge voltage is applied to a first conductive line connected to the end of the first memory group that is away from the second memory group.

[0125] In some specific examples, the operation method further includes: applying a first pre-charge voltage to the first conductive line in a third pre-charge phase following the second pre-charge phase.

[0126] In some specific examples, the first pre-charge voltage is greater than or equal to 0V. For example, the first pre-charge voltage applied to the first conductor can be the ground voltage or a voltage greater than the ground voltage.

[0127] In this embodiment of the present disclosure, the actuator that applies corresponding voltages to the word line, the first conductive line, the second conductive line, the upper select transistor, and the lower select transistor can be a voltage generator of the peripheral circuit.

[0128] The first conductive line here can be either a common source line or a bit line. When the first memory bank is below the second memory bank, the first conductive line is a common source line. When the first memory bank is above the second memory bank, the first conductive line is a bit line.

[0129] Figure 10 This is a schematic diagram of the structure of a storage cell string provided in an embodiment of the present disclosure; Figure 11 Provided for embodiments of this disclosure Figure 10 The voltage waveform diagram under the structure of a memory cell string is shown below. The following will combine... Figure 10 as well as Figure 11 The method provided in the above embodiment will be described by way of example, with the first storage group located below the second storage group and the first storage group coupled to the lower select transistor.

[0130] like Figure 10 As shown, the first storage group is located below the second storage group. The first storage group includes a first sub-storage group and a second sub-storage group, with the second sub-storage group located between the first sub-storage group and the second storage group. Furthermore, storage cells in the second storage group that are in the programming state are farther from the first storage group, while storage cells in the second storage group that are in the erasure state are closer to the first storage group. Figure 10 In the structure of the storage cell string shown, the first storage group is connected to the first conductive line, which is a common source line.

[0131] Here, the memory cells in the second memory group that are in the programming state are far away from the first memory group. This can be understood as the programming order of the second memory group being reverse programming, that is, programming from top to bottom.

[0132] like Figure 11 As shown, in the first pre-charge stage (stage 1), the second pre-charge stage (stage 2), and the third pre-charge stage (stage 3), a first pre-charge voltage (Vpre1) is applied to the common source line, and a third pre-charge voltage (Vpre3) is applied to the lower select transistor to perform pre-charging from the common source line terminal. Here, in the pre-charge stage, the voltage applied to the common source line is represented by a dashed line and a solid line: Vpre1 ​​can be the ground voltage or a voltage greater than the ground voltage.

[0133] like Figure 11As shown, in the first pre-charge phase, a first on-state voltage (Vpass1) is applied to the word lines (word lines to the first sub-memory group) coupled to the memory cells of the first sub-memory group and the word lines (word lines to the second sub-memory group) coupled to the memory cells of the second sub-memory group. In the second pre-charge phase, a first voltage (Vss) is applied to the word lines coupled to the memory cells of the second sub-memory group, and a second voltage (V1) is applied to the word lines coupled to the memory cells of the first sub-memory group, where V1 is greater than Vss. In some specific examples, the first voltage may also be a voltage greater than Vss but less than V1.

[0134] Here, the voltage difference between the second voltage and the first voltage should not be too large to prevent hot carrier injection during the pre-charging stage, which could cause programming crosstalk.

[0135] It should be noted that, in this embodiment, the peripheral circuit is configured to perform programming operations on the memory cells in the memory cell string, including multiple programming cycles. Each programming cycle may include a programming phase and a verification phase. For multiple programming cycles, the programming voltage applied to the selected word line may be incremental, and the verification voltage applied to the selected word line may be different. Each programming phase includes a pre-charge phase and a programming voltage application phase. Figure 11 The voltage curves during programming and verification operations on the memory cell string are shown in the example above, which only take the programming phase of one programming cycle and the verification phase of the previous programming cycle as examples.

[0136] In some specific examples, during the verification phase prior to the programming phase, the word lines coupled to selected memory cells in the second memory group can be verified. Figure 11 A verification voltage (Vverify) is applied to the selected word line (second memory group) in the second memory group, and the word lines coupled to the unselected memory cells in the second memory group are also verified. Figure 11 Apply a pass voltage (Vpass) to the unselected word line (second memory group).

[0137] In some embodiments, such as Figure 11 As shown, the operation method further includes:

[0138] In the first precharge stage (stage 1) and the second precharge stage (stage 2), the word lines coupled to the memory cells of the second memory group in which some memory cells are in the programming state are all connected to the ground voltage (Vss); the memory cells in the programming state in the second memory group are far away from the first memory group, and the memory cells in the erasure state in the second memory group are close to the first memory group.

[0139] Understandably, when pre-charging is performed from the first conductive line end, electrons in the channel corresponding to the second memory group are released from one end of the first conductive line. The channel corresponding to the memory cell in the programming state in the second memory group does not need to be turned on. Therefore, the word lines coupled to the memory cells in the second memory group can all be connected to the ground voltage.

[0140] In some embodiments, such as Figure 11 As shown, the operation method further includes:

[0141] In the third precharge stage (stage 3) following the second precharge stage (stage 2), the word lines coupled to the memory cells in the first memory group and the second memory group are all connected to the ground voltage (Vss).

[0142] In some embodiments, such as Figure 11 As shown, the operation method further includes:

[0143] During the programming voltage application phase following the third pre-charge stage (stage 3), the word lines coupled to the selected memory cells in the erased state of the second memory group are... Figure 11 The selected word line (second memory group) applies a programming voltage (Vprogram).

[0144] In some specific examples, the memory array also includes a second conductive line, which can be connected to the end of the second memory bank furthest from the first memory bank. This second conductive line can be a common source line or a bit line. For example, when the first conductive line is a bit line, the second conductive line is a common source line; when both the first and common source lines are present, the second conductive line is a bit line. Figure 10 as well as Figure 11 In the example shown, the second conductive line is a bit line.

[0145] In some specific examples, such as Figure 11 As shown, the method further includes, during the pre-charging phase, connecting the bit lines of the memory cells in series and the upper select transistor to the ground voltage.

[0146] In this embodiment of the disclosure, such as Figure 12 The first memory group shown can be located above the second memory group. The first conductive line is a bit line, and the second conductive line is a common source line. Memory cells in the second memory group that are in the programming state are farther from the first memory group, while memory cells in the second memory group that are in the erasure state are closer to the first memory group. That is, when programming the memory cells of the second memory group, the programming order is forward programming, i.e., programming is performed from bottom to top.

[0147] Figure 13 In order to be in Figure 12The voltage waveform diagram in the case of a string of storage cells. Figure 13 The scheme shown is related to Figure 11 The voltage application to the first and second memory banks is similar in the illustrated scheme and will not be repeated here. Figure 13 As shown, during the pre-charging phase, a first pre-charging voltage (Vpre1) is applied to the bit line, a third pre-charging voltage (Vpre3) is applied to the upper select transistor, and the lower select transistor and the common source line are connected to the ground voltage.

[0148] Here, applying a third pre-charge voltage to the upper select transistor can be understood as applying the third pre-charge voltage to both the upper select transistor connected in series with the selected memory cells and the upper select transistor connected in series with the unselected memory cells. Applying the third pre-charge voltage to the upper select transistor will turn it on, and applying a fourth pre-charge voltage to the lower select transistor will turn it on. Similarly, applying the fourth pre-charge voltage to both the upper and lower select transistors will also turn them on.

[0149] In some embodiments, the storage cell string further includes a third storage group, which includes a plurality of storage cells and is in a programmed state, and a second storage group is located between the first storage group and the third storage group.

[0150] In this embodiment of the disclosure, the third storage group can be as follows: Figure 14 As shown, it is located above the second storage group; in other embodiments, the third storage group may also be as follows: Figure 17 As shown, it is located below the second storage group. The following will combine... Figures 14 to 18 Further explanation is needed.

[0151] like Figure 14 As shown, the first storage group is located below the second storage group, and the third storage group is located above the second storage group. Storage cells in the second storage group that are in the programming state are closer to the third storage group, while those in the erasure state are closer to the first storage group. In other words, the programming order for the second storage group is reverse programming, i.e., programming from top to bottom. The third storage group includes a third sub-storage group and a fourth sub-storage group, with the third sub-storage group located between the fourth sub-storage group and the second storage group.

[0152] exist Figure 14 In the embodiment shown, the end of the third memory group furthest from the second memory group can be connected to the upper select transistor, which is connected to the second conductive line (bit line). The end of the first memory group furthest from the second memory group can be connected to the lower select transistor, which is connected to the first conductive line (common source line).

[0153] Figure 15 In order to be in Figure 14 The voltage waveform diagram for the case of the memory cell string is shown. Figure 15 As shown, in the case of pre-charging from the common source line terminal, the operation method further includes: during the pre-charging phase, the word lines coupled to the memory cells of the third memory bank ( Figure 15 A ground voltage is applied to the word lines (third sub-memory group and fourth sub-memory group). During the verification phase, an on-state voltage (Vpass) is applied to the word lines coupled to the memory cells of the third memory group. Other voltage application conditions are the same as those in the verification phase. Figure 11 Similar to those in the text, I will not elaborate further.

[0154] In some embodiments, such as Figure 15 As shown, the operation method further includes:

[0155] In the first precharge stage (stage 1) and the second precharge stage (stage 2), the word lines that couple the memory cells in the third memory group in the programming state of the memory cell string are... Figure 15 The word line (third sub-memory group and word line (fourth sub-memory group)) and the second conductive line (bit line) connected to the end of the third memory group away from the second memory group are all connected to the ground voltage; the second memory group is located between the first memory group and the third memory group.

[0156] In some specific examples, the method further includes connecting the upper selection tube to ground voltage during the pre-charging phase.

[0157] It is understood that in the above embodiments, the storage cell string is precharged at one end, that is, precharged only from one end of the first conductive line.

[0158] The following will combine Figure 16a , Figure 16b right Figure 14 , Figure 15 The changes in channel potential are explained in detail in the illustrated embodiment.

[0159] like Figure 16a As shown, before channel pre-charging, the word lines coupled to the erased memory cells in the second memory bank ( Figure 16a The word line (WL) below the channel is coupled to the programmed memory cell. Figure 16aTo decouple the PGMed WL (programmed memory) to a negative voltage, pre-charging is required to raise the potential. In the first pre-charging stage, a first pre-charging voltage is applied to the ACS (Acoustic Switching Array), and a first conduction voltage is applied to the word lines coupled to the memory cells of the first memory group. This opens all channels corresponding to the first memory group, making the channel below the word line coupled to the erased memory cell in the second memory group conduct with the ACS. The ground voltage applied by the ACS is directly transferred to the channel corresponding to the erased memory cell in the second memory group, raising the channel potential to 0V. This releases residual electrons in the channel of the second memory group, achieving the pre-charging function. In the second pre-charging stage, if... Figure 8 The illustrated scheme, without constructing a stepped potential, means that if all word lines coupled to the memory cells of the first memory group are connected to ground during the second pre-charge stage, the channel potential of the channel below the word lines coupled to the memory cells of the first memory group decreases. This creates a potential difference between the channel below the word lines coupled to the memory cells of the first memory group and the channel below the word lines coupled to the word lines of the second memory group. This causes the gate voltage induction and decoupling electrons from the word line channel coupled to the memory cells of the first memory group to flow back to the corresponding channel of the second memory group, affecting the programming pre-charge effect. In this embodiment, if... Figure 15 The scheme shown involves constructing a stepped potential during the second pre-charge stage. Specifically, the word lines of the memory cells in the first memory group that are coupled to the memory cells in the second memory group are first connected to ground. The other word lines of the memory cells in the first memory group are kept at a certain bias, and a voltage greater than the ground voltage is applied to construct the stepped potential. Figure 16b as well as Figure 16a As shown, electrons in the channel migrate towards higher potentials to remove residual electrons from the channel below the word lines where ground voltage is applied in the word lines coupled to the memory cells of the first memory group. This reduces electron backflow into the corresponding channel of the second memory group. Furthermore, in the second pre-charge phase, the word lines coupled to the memory cells in the erase state in the second memory group are connected to ground voltage. The voltage applied to the word lines coupled to the first sub-memory group of the first memory group is greater than the ground voltage, resulting in a larger step potential, causing electrons to primarily flow into the channel corresponding to the first memory group. In the third pre-charge phase, all word lines coupled to the memory cells of the first memory group are connected to ground voltage, allowing the channels that were grounded in the second pre-charge phase to also function as turn-off channels, hindering electron backflow.

[0160] like Figure 17As shown, the first storage group is located above the second storage group, and the third storage group is located below the second storage group. Storage cells in the second storage group that are in the programming state are closer to the third storage group, while storage cells in the erase state are closer to the first storage group. This means that the programming order for the second storage group is forward programming, i.e., programming from bottom to top. The third storage group includes a third sub-storage group and a fourth sub-storage group, with the third sub-storage group located between the fourth sub-storage group and the second storage group.

[0161] exist Figure 17 In the embodiment shown, the end of the third memory group that is furthest from the second memory group can be connected to the lower select transistor, which is connected to the first conductive line (common source line). The end of the first memory group that is furthest from the second memory group can be connected to the upper select transistor, which is connected to the second conductive line (bit line).

[0162] Figure 18 In order to be in Figure 17 The voltage waveform diagram for the case of the memory cell string is shown. Figure 18 As shown, in the case of pre-charging from the bit line end, the operation method further includes: during the pre-charging phase, the word lines coupled to the memory cells of the third memory bank ( Figure 18 A ground voltage is applied to the word lines (third sub-memory group and fourth sub-memory group). During the verification phase, an on-state voltage (Vpass) is applied to the word lines coupled to the memory cells of the third memory group. Other voltage application conditions are the same as those in the verification phase. Figure 13 Similar to those in the text, I will not elaborate further.

[0163] like Figure 19 As shown, when the first storage group is above the second storage group and the third storage group is below the second storage group, the programming order of the second storage group can be illustrated in the diagram. Figure 17 The difference can be specifically: the memory cells in the second memory group that are in the programming state are closer to the first memory group, and the memory cells in the second memory group that are in the erasure state are closer to the third memory group. In other words, the programming order for the second memory group is reverse programming, i.e., programming from top to bottom. Figure 19 In the case of the memory cell string shown, precharging can also be performed from the bit line end. Figure 20 for Figure 19 The voltage waveform diagram is shown in the case of the memory cell string.

[0164] In some embodiments, such as Figure 20 As shown, the operation method further includes:

[0165] During the first pre-charge stage (stage 1), a second on-state voltage (Vpass 2) is applied to the word line coupled to the memory cell in the second memory group that is in the programming state; the memory cell in the second memory group that is in the programming state is close to the first memory group;

[0166] In the second pre-charge stage (stage 2), word lines () in the memory cells of the second memory group that are in the programming state and are coupled to the memory cells of the first memory group are ( Figure 20 A third voltage (V2) is applied to the word lines of the second memory group whose memory cells are in the programming state and which are far from the selected word line, and the word lines of the second memory group whose memory cells are in the programming state and which are far from the selected word line are applied to the word lines of the first memory group. Figure 20 A fourth voltage (Vss) is applied to the word line of the second memory group in the programming state (the word line closest to the selected word line); the fourth voltage is less than the third voltage, the third voltage is less than or equal to the first voltage, and both the third voltage and the fourth voltage are less than the second turn-on voltage.

[0167] In some embodiments, such as Figure 20 As shown, the operation method further includes:

[0168] During the first precharge stage (stage 1) and the second precharge stage (stage 2), the word lines coupled to the memory cells in the erase state in the second memory group are connected to the ground voltage.

[0169] The word lines coupled to the memory cells in the erase state in the second memory group here include Figure 20 The second memory group shown is in the erase state, with memory cells coupled to unselected word lines and selected word lines – second memory group.

[0170] In the above embodiment, in the second pre-charge stage (stage 2), a first voltage is applied to the word line coupled to the memory cell of the second sub-memory group, and a second voltage is applied to the word line coupled to the memory cell of the first sub-memory group, wherein the second voltage is greater than the first voltage, the first voltage is greater than or equal to the third voltage, and the third voltage is greater than the fourth voltage.

[0171] It is understood that in the above embodiments, pre-charging is performed from the bit line end. In the first pre-charging stage (stage 1), a second conduction voltage is applied to the word lines coupled to the memory cells in the programming state of the second memory group, so that the channels corresponding to the memory cells in the programming state of the second memory group are turned on, and the electrons in the channels corresponding to the memory cells in the erasure state of the second memory group can be drawn away through the bit line end. In the second pre-charging stage (stage 2), a third voltage is applied to the word lines coupled to the memory cells in the programming state of the second memory group that are close to the memory cells in the first memory group, and a fourth voltage smaller than the third voltage is applied to the word lines coupled to the memory cells in the programming state of the second memory group that are far from the first memory group. A stepped potential is constructed between the word lines coupled to the programmed memory cells in the second memory group and the word lines coupled to the memory cells in the first memory group to prevent the backflow of electrons.

[0172] In some of the above embodiments, single-ended pre-charging is shown, i.e., pre-charging is performed from the bit line end or the common source line end. In other embodiments, double-ended pre-charging can also be performed on the memory cell string, i.e., pre-charging is performed simultaneously from the bit line end and the common source line end. The following describes... Figure 21 , Figure 22 Further explanation is needed. Figure 21 for Figure 14 The voltage waveform diagram corresponding to the case of a string of storage cells; Figure 22 for Figure 17 The voltage waveform diagram corresponding to the case of a string of storage cells.

[0173] In some embodiments, such as Figure 21 as well as Figure 22 As shown, the operation method further includes:

[0174] In the first precharge stage (stage 1), a second precharge voltage is applied to the second conductive line connected to the end of the third memory group of the memory cell string away from the second memory group, and a third conduction voltage is applied to the word line coupled to the third memory group; the second memory group is located between the first memory group and the third memory group.

[0175] In the second pre-charge stage (stage 2), the second pre-charge voltage is applied to the second conductive line, and a fifth voltage is applied to the word line of the storage cell of the third sub-storage group located between the fourth sub-storage group and the second storage group. A sixth voltage is applied to the word line of the storage cell of the fourth sub-storage group of the third storage group. The fifth voltage is less than the sixth voltage and both are less than the third turn-on voltage.

[0176] In some embodiments, the operating method further includes:

[0177] In the first pre-charge stage (stage 1) and the second pre-charge stage (stage 2), a third pre-charge voltage is applied to a first select transistor located between the first conductive line and the first memory group, which is connected to both the first conductive line and the first memory group, and a fourth pre-charge voltage is applied to a second select transistor located between the second conductive line and the third memory group, which is connected to both the second conductive line and the third memory group.

[0178] like Figure 21 As shown, after the verification is completed, in the first pre-charge stage (stage 1), the word lines coupled to the memory cells of the second memory group are connected to the ground voltage, and a first turn-on voltage (Vpass1) is applied to the word lines coupled to the memory cells of the first memory group, so that the corresponding channel of the first memory group is turned on. A third turn-on voltage (Vpass3) is applied to the word lines coupled to the memory cells of the third memory group, so that the corresponding channel of the third memory group is turned on, thereby clearing the residual electrons in the channel below the word line coupled to the memory cells in the erase state in the second memory group. In the second pre-charge stage (stage 2), the word lines coupled to the memory cells of the first and third memory groups are both reduced. Some of the electrons accumulated in the channels below these cells will flow back to the corresponding channels of the second memory group, lowering the potential. Therefore, in the second pre-charge stage (stage 2), a stepped potential is constructed: specifically, the word lines of the memory cells in the first memory group that are close to the memory cells of the second memory group are connected to ground (Vss), and a second voltage (V1) is applied to the word lines of the memory cells in the first memory group that are far from the memory cells of the second memory group, where V1 is greater than Vss; similarly, the word lines of the memory cells in the third memory group that are close to the memory cells of the second memory group are connected to ground (Vss), and a sixth voltage (V3) is applied to the word lines of the memory cells in the third memory group that are far from the memory cells of the second memory group, where V3 is greater than Vss. This reduces the electron backflow into the corresponding channels of the second memory group and reduces the residual electrons from the decoupling between the channels of the first and third memory groups.

[0179] Figure 21 The first conductive line is the common source line, and the second conductive line is the potential line; Figure 22 The first conductive line is the bit line, and the second conductive line is the common source line. Figure 22 The voltage applied in and Figure 21 The voltage applied in the middle is similar, so I will not go into details.

[0180] It is understandable that in the above embodiments, the double-ended pre-charging and the construction of a stepped potential at both ends enable more sufficient extraction and accumulation of electrons, thereby improving the boost potential during non-selective string programming.

[0181] The solutions provided in the above embodiments can be applied to both single-stack structures and multi-stack structures, and this disclosure does not specifically limit them. When the memory device includes a stacked structure, the stacked structure includes multiple strings of memory cells arranged side-by-side in a direction perpendicular to the stacking direction. The following will exemplarily combine... Figure 23 The case of a memory device comprising three stacked structures arranged in a stacked configuration will be further explained.

[0182] In some embodiments, such as Figure 23 As shown, the memory array includes:

[0183] A first stacking structure is provided, wherein a first channel structure is provided through the first stacking structure; the first stacking structure includes a plurality of first memory groups arranged side by side along a direction perpendicular to the stacking direction;

[0184] A second stacking structure is located on the first stacking structure; the second stacking structure is provided with a second channel structure that penetrates the second stacking structure and is connected to the first channel structure; the second stacking structure includes a plurality of second memory groups arranged side by side along a direction perpendicular to the stacking direction;

[0185] A third stacking structure is located on the second stacking structure; the third stacking structure is provided with a third channel structure that penetrates the third stacking structure and is connected to the second channel structure; the third stacking structure includes a plurality of the third memory groups arranged side by side along a direction perpendicular to the stacking direction.

[0186] It is understood that the memory array provided in the embodiments of this disclosure may include multiple stacked structures arranged in a stacked manner, and different memory groups may be located in different stacked structures.

[0187] The above embodiments provide a pre-charge scheme for programming intermediate stack structures when the memory device is stacked in multiple stacked structures with memory blocks as the smallest unit of the erase operation, and each stack structure corresponding to each memory block is independently programmed, erased and read, providing an implementable strategy for realizing independent operation of multiple stack structures.

[0188] In this embodiment, firstly, by performing a pre-charging stage on the middle second stacked structure before the programming voltage application stage, a voltage is applied to the word lines of the two programmed stacked structures to open the channel and clear the electrons accumulated in the channel. Secondly, by reducing the electrons in the word lines of the two programmed stacked structures at different timings, the channel potential is controlled to construct a stepped potential to extract electrons attracted below the word lines of the two programmed stacked structures and decouple electrons, preventing electrons from flowing back into the channel in the middle stacked structure and improving the channel pre-charging effect. The solution provided by this embodiment can better clear the electrons accumulated in the channel, increase the rise potential of the non-selective memory cell string, and reduce programming crosstalk.

[0189] Based on the above-described operation method of the memory device, this disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the operation method described in any of the above embodiments.

[0190] Here, implementing all or part of the processes in the methods of the above embodiments can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive, etc.; the storage medium can also include combinations of the above types of memory.

[0191] Based on the above-described operation method of the memory device, this disclosure also provides a memory device, including: a memory array and peripheral circuitry coupled to the memory array; the memory array includes a plurality of memory cell strings, each memory cell string including an adjacent first memory group and a second memory group; both the first memory group and the second memory group include a plurality of memory cells, the first memory group is in a programming state, and at least some memory cells in the second memory group are in an erasing state; the first memory group includes a first sub-memory group and a second sub-memory group, and the second sub-memory group is located between the first sub-memory group and the second memory group;

[0192] The peripheral circuit is configured as follows:

[0193] During the first pre-charge phase, a first on-state voltage is applied to the word lines coupled to the first memory group;

[0194] In the second pre-charge phase following the first pre-charge phase, a first voltage is applied to the word lines coupled to the memory cells of the second sub-memory group, and a second voltage is applied to the word lines coupled to the memory cells of the first sub-memory group; the first voltage is less than the second voltage and both are less than the first turn-on voltage.

[0195] In some embodiments, the memory array further includes a first conductive line; one end of the first memory group remote from the second memory group is connected to the first conductive line; the peripheral circuitry is configured to:

[0196] A first pre-charge voltage is applied to the first conductive line during the first pre-charge phase and the second pre-charge phase.

[0197] In some embodiments, some memory cells in the second memory group are in a programmed state, and the memory cells in the programmed state in the second memory group are far from the first memory group, while the memory cells in the erased state in the second memory group are close to the first memory group; the peripheral circuit is configured as follows:

[0198] During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells of the second memory group are all connected to the ground voltage.

[0199] In some embodiments, some memory cells in the second memory group are in a programmed state, and the programmed memory cells in the second memory group are located close to the first memory group; the peripheral circuitry is configured as follows:

[0200] During the first pre-charge phase, a second on-state voltage is applied to the word lines coupled to the memory cells of the second memory group that are in the programming state;

[0201] During the second pre-charge phase, a third voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group, and a fourth voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group; the fourth voltage is less than the third voltage, the third voltage is less than or equal to the first voltage, and both the third voltage and the fourth voltage are less than the second turn-on voltage.

[0202] In some embodiments, the peripheral circuit is configured as follows:

[0203] During the first precharge phase and the second precharge phase, the word lines coupled to the memory cells in the erase state in the second memory group are connected to the ground voltage.

[0204] In some embodiments, the peripheral circuit is configured as follows:

[0205] In the third precharge phase following the second precharge phase, the word lines coupled to the memory cells in the first memory group and the second memory group are all connected to the ground voltage.

[0206] In some embodiments, the peripheral circuit is configured as follows:

[0207] In the programming voltage application phase following the third pre-charge phase, a programming voltage is applied to the word line coupled to the selected memory cell in the erased state of the second memory group.

[0208] In some embodiments, the memory array further includes a second conductive line, and each memory cell string further includes a third memory group; the third memory group includes a plurality of memory cells, and each memory cell is in a programmed state; the second memory group is located between the first memory group and the third memory group; the end of the third memory group away from the second memory group is connected to the second conductive line.

[0209] In some embodiments, the memory array includes:

[0210] A first stacking structure is provided, wherein a first channel structure is provided through the first stacking structure; the first stacking structure includes a plurality of first memory groups arranged side by side along a direction perpendicular to the stacking direction;

[0211] A second stacking structure is located on the first stacking structure; the second stacking structure is provided with a second channel structure that penetrates the second stacking structure and is connected to the first channel structure; the second stacking structure includes a plurality of second memory groups arranged side by side along a direction perpendicular to the stacking direction;

[0212] A third stacking structure is located on the second stacking structure; the third stacking structure is provided with a third channel structure that penetrates the third stacking structure and is connected to the second channel structure; the third stacking structure includes a plurality of the third memory groups arranged side by side along a direction perpendicular to the stacking direction.

[0213] In some embodiments, the peripheral circuit is configured as follows:

[0214] During the first pre-charge phase and the second pre-charge phase, the word lines and second conductive lines coupled to the memory cells in the third memory group are all connected to the ground voltage.

[0215] In some embodiments, the third storage group includes a third sub-storage group and a fourth sub-storage group, the third sub-storage group being located between the fourth sub-storage group and the second storage group; the peripheral circuitry is configured to:

[0216] During the first pre-charge phase, a second pre-charge voltage is applied to the second conductive line, and a third on-voltage is applied to the word line coupled to the third memory group.

[0217] During the second pre-charge phase, the second pre-charge voltage is applied to the second conductive line, and a fifth voltage is applied to the word line coupled to the memory cell of the third sub-memory group, and a sixth voltage is applied to the word line coupled to the memory cell of the fourth sub-memory group; the fifth voltage is less than the sixth voltage and both are less than the third turn-on voltage.

[0218] In some embodiments, the memory array further includes a first select transistor and a second select transistor; the first select transistor is located between the first conductive line and the first memory group, and is connected to both the first conductive line and the first memory group; the second select transistor is located between the second conductive line and the third memory group, and is connected to both the second conductive line and the third memory group; the peripheral circuitry is configured as follows:

[0219] During the first pre-charge phase and the second pre-charge phase, a third pre-charge voltage is applied to the first selector and a fourth pre-charge voltage is applied to the second selector.

[0220] In some specific examples, the memory device includes a three-dimensional NAND-type memory.

[0221] Other details regarding the memory device have been described in detail in the section on the operation of the memory device, and will not be repeated here for the sake of brevity.

[0222] Based on the above-described operating method of the memory device, this disclosure also provides a memory system, including a memory controller and a memory device as described in any of the above embodiments; the memory controller is coupled to the memory device and configured to control the memory device.

[0223] In some specific examples, the memory system includes, but is not limited to, general-purpose flash storage, solid-state drives, and memory cards.

[0224] Here, the specific structure and composition of the memory system can be referred to the aforementioned section. Figure 1 , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4 , Figure 5 , Figure 6 The detailed introduction of the memory system is provided here, and other details regarding the memory system are similar to those in the aforementioned memory system operation method. For the sake of brevity, they will not be repeated here.

[0225] Based on the memory system described above, this disclosure also provides an electronic device, including a memory system as described in any of the above embodiments, and a host coupled to the memory system.

[0226] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0227] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0228] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, characterized in that, include: Memory array and peripheral circuitry coupled to said memory array; The memory array includes multiple memory cell strings, each memory cell string including an adjacent first memory group and a second memory group; both the first memory group and the second memory group include multiple memory cells, the first memory group is in a programmed state, and at least some memory cells in the second memory group are in an erased state; the first memory group includes a first sub-memory group and a second sub-memory group, and the second sub-memory group is located between the first sub-memory group and the second memory group. The peripheral circuit is configured as follows: During the first pre-charge phase, a first on-state voltage is applied to the word lines coupled to the first memory group; In the second pre-charge phase following the first pre-charge phase, a first voltage is applied to the word lines coupled to the memory cells of the second sub-memory group, and a second voltage is applied to the word lines coupled to the memory cells of the first sub-memory group; the first voltage is less than the second voltage and both are less than the first turn-on voltage.

2. The memory device according to claim 1, characterized in that, The memory array further includes a first conductive line; the end of the first memory group away from the second memory group is connected to the first conductive line; the peripheral circuitry is configured as follows: A first pre-charge voltage is applied to the first conductive line during the first pre-charge phase and the second pre-charge phase.

3. The memory device according to claim 2, characterized in that, In the second storage group, some storage cells are in a programmed state, and the storage cells in the programmed state are far from the first storage group, while the storage cells in the erased state are close to the first storage group; the peripheral circuit is configured as follows: During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells of the second memory group are all connected to the ground voltage.

4. The memory device according to claim 2, characterized in that, In the second memory group, some memory cells are in a programmed state, and the programmed memory cells in the second memory group are located close to the first memory group; the peripheral circuit is configured as follows: During the first pre-charge phase, a second on-state voltage is applied to the word lines coupled to the memory cells of the second memory group that are in the programming state; During the second pre-charge phase, a third voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group, and a fourth voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group; the fourth voltage is less than the third voltage, the third voltage is less than or equal to the first voltage, and both the third voltage and the fourth voltage are less than the second turn-on voltage.

5. The memory device according to claim 4, characterized in that, The peripheral circuit is configured as follows: During the first precharge phase and the second precharge phase, the word lines coupled to the memory cells in the erase state in the second memory group are connected to the ground voltage.

6. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: In the third precharge phase following the second precharge phase, the word lines coupled to the memory cells in the first memory group and the second memory group are all connected to the ground voltage.

7. The memory device according to claim 6, characterized in that, The peripheral circuit is configured as follows: In the programming voltage application phase following the third pre-charge phase, a programming voltage is applied to the word line coupled to the selected memory cell in the erased state of the second memory group.

8. The memory device according to claim 2, characterized in that, The memory array further includes a second conductive line, and each memory cell string further includes a third memory group; the third memory group includes multiple memory cells, and each memory cell is in a programmed state; the second memory group is located between the first memory group and the third memory group; the end of the third memory group away from the second memory group is connected to the second conductive line.

9. The memory device according to claim 8, characterized in that, The memory array includes: A first stacking structure is provided, wherein a first channel structure is provided through the first stacking structure; the first stacking structure includes a plurality of first memory groups arranged side by side along a direction perpendicular to the stacking direction; A second stacking structure is located on the first stacking structure; the second stacking structure is provided with a second channel structure that penetrates the second stacking structure and is connected to the first channel structure; the second stacking structure includes a plurality of second memory groups arranged side by side along a direction perpendicular to the stacking direction; A third stacking structure is located on the second stacking structure; the third stacking structure is provided with a third channel structure that penetrates the third stacking structure and is connected to the second channel structure; the third stacking structure includes a plurality of the third memory groups arranged side by side along a direction perpendicular to the stacking direction.

10. The memory device according to claim 8, characterized in that, The peripheral circuit is configured as follows: During the first pre-charge phase and the second pre-charge phase, the word lines and second conductive lines coupled to the memory cells in the third memory group are all connected to the ground voltage.

11. The memory device according to claim 8, characterized in that, The third storage group includes a third sub-storage group and a fourth sub-storage group, the third sub-storage group being located between the fourth sub-storage group and the second storage group; the peripheral circuitry is configured as follows: During the first pre-charge phase, a second pre-charge voltage is applied to the second conductive line, and a third on-voltage is applied to the word line coupled to the third memory group. During the second pre-charge phase, the second pre-charge voltage is applied to the second conductive line, and a fifth voltage is applied to the word line coupled to the memory cell of the third sub-memory group, and a sixth voltage is applied to the word line coupled to the memory cell of the fourth sub-memory group; the fifth voltage is less than the sixth voltage and both are less than the third turn-on voltage.

12. The memory device according to claim 11, characterized in that, The memory array further includes a first selection transistor and a second selection transistor; the first selection transistor is located between the first conductive line and the first memory group, and is connected to both the first conductive line and the first memory group; the second selection transistor is located between the second conductive line and the third memory group, and is connected to both the second conductive line and the third memory group; the peripheral circuit is configured as follows: During the first pre-charge phase and the second pre-charge phase, a third pre-charge voltage is applied to the first selector and a fourth pre-charge voltage is applied to the second selector.

13. A memory system, characterized in that, It includes a memory controller and a memory device as described in any one of claims 1-12; the memory controller is coupled to the memory device and configured to control the memory device.

14. A method of operating a memory device, characterized in that, The operation method includes: During the first pre-charge phase, a first on-state voltage is applied to the word line coupled to the first memory group of the memory cell string in the programming state; In the second precharge phase following the first precharge phase, a first voltage is applied to the word lines of the second sub-storage group located between the first sub-storage group and the second storage group where at least some of the storage cells are in an erased state, and a second voltage is applied to the word lines of the first sub-storage group in the first storage group; the first voltage is less than the second voltage and both are less than the first turn-on voltage.

15. The operating method according to claim 14, characterized in that, The operation method further includes: During the first precharge phase and the second precharge phase, a first precharge voltage is applied to a first conductive line connected to the end of the first memory group that is away from the second memory group.

16. The operating method according to claim 15, characterized in that, The operation method further includes: During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells of the second memory group in which some memory cells are in the programming state are all connected to the ground voltage; the memory cells in the programming state in the second memory group are far away from the first memory group, and the memory cells in the erasure state in the second memory group are close to the first memory group.

17. The operating method according to claim 15, characterized in that, The operation method further includes: During the first pre-charge phase, a second on-state voltage is applied to the word lines coupled to the memory cells in the second memory group that are in the programming state; the memory cells in the second memory group that are in the programming state are close to the first memory group; During the second pre-charge phase, a third voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group, and a fourth voltage is applied to the word lines of the memory cells in the second memory group that are in the programming state and are coupled to the memory cells of the first memory group; the fourth voltage is less than the third voltage, the third voltage is less than or equal to the first voltage, and both the third voltage and the fourth voltage are less than the second turn-on voltage.

18. The operating method according to claim 17, characterized in that, The operation method further includes: During the first precharge phase and the second precharge phase, the word lines coupled to the memory cells in the erase state in the second memory group are connected to the ground voltage.

19. The operating method according to claim 14, characterized in that, The operation method further includes: In the third precharge phase following the second precharge phase, the word lines coupled to the memory cells in the first memory group and the second memory group are all connected to the ground voltage.

20. The operating method according to claim 19, characterized in that, The operation method further includes: In the programming voltage application phase following the third pre-charge phase, a programming voltage is applied to the word line coupled to the selected memory cell in the erased state of the second memory group.

21. The operating method according to claim 15, characterized in that, The operation method further includes: During the first pre-charge phase and the second pre-charge phase, the word lines coupled to the memory cells in the third memory group in the programming state of the memory cell string, as well as the second conductive lines connected to the end of the third memory group away from the second memory group, are all connected to the ground voltage; the second memory group is located between the first memory group and the third memory group.

22. The operating method according to claim 15, characterized in that, The operation method further includes: During the first pre-charge phase, a second pre-charge voltage is applied to the second conductive line connected to the end of the third memory group of the memory cell string that is away from the second memory group, and a third on-state voltage is applied to the word line coupled to the third memory group; the second memory group is located between the first memory group and the third memory group. During the second pre-charge phase, the second pre-charge voltage is applied to the second conductive line, and a fifth voltage is applied to the word line of the storage cell of the third sub-storage group located between the fourth sub-storage group and the second storage group. A sixth voltage is applied to the word line of the storage cell of the fourth sub-storage group of the third storage group. The fifth voltage is less than the sixth voltage and both are less than the third turn-on voltage.

23. The operating method according to claim 22, characterized in that, The operation method further includes: During the first pre-charge phase and the second pre-charge phase, a third pre-charge voltage is applied to a first select transistor located between the first conductive line and the first memory group, which is connected to both the first conductive line and the first memory group, and a fourth pre-charge voltage is applied to a second select transistor located between the second conductive line and the third memory group, which is connected to both the second conductive line and the third memory group.

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