Semiconductor memory device

Abstract

A semiconductor memory device includes a first chip and a second chip. The first chip comprises a first unit array piece and a second unit array piece adjacent to the first unit array piece. The second chip forms a stacked structure with the first chip, and includes a first sub-word line driver configured to generate a first driving signal applied to the first word line from one side of each of the first cell array sheet and the second cell array sheet, and a second sub-word line driver configured to generate a second driving signal applied to the second word line from the other side of each of the first cell array sheet and the second cell array sheet. The second sub-word line driver is configured to generate a second driving signal applied to the second word line from the other side of each of the first cell array sheet and the second cell array sheet opposite to the one side.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0153818 filed in the Korean Intellectual Property Office on November 8, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments of the present disclosure described herein relate to a semiconductor memory device. Background Art

[0003] Semiconductor memory devices are used to store data. Semiconductor memory devices are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices in which the stored data is lost when the power is cut off. Among volatile memory devices, dynamic random access memory (DRAM) is used in various fields such as mobile systems, servers, graphic devices, etc.

[0004] When writing data to or reading data from a memory cell, DRAM basically performs a word line level operation. Multiple memory cells are connected to one word line, and as the number of connected memory cells increases, the word line load also increases. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor memory device for improving performance thereof by properly arranging sub word line drivers using a cell-on-periphery (CoP) structure.

[0006] According to an embodiment, a semiconductor memory device includes a first chip and a second chip. The first chip includes a first cell array sheet and a second cell array sheet adjacent to the first cell array sheet, and each of the first cell array sheet and the second cell array sheet includes a first word line and a second word line. The second chip forms a stacked structure with the first chip and includes a first sub-word line driver and a second sub-word line driver, the first sub-word line driver is configured to generate a first drive signal applied to the first word line from one side of each of the first cell array sheet and the second cell array sheet, and the second sub-word line driver is configured to generate a second drive signal applied to the second word line from another side of each of the first cell array sheet and the second cell array sheet opposite to the one side.

[0007] According to an embodiment, a semiconductor memory device includes: a plurality of cell array chips implemented in a first chip, each cell array chip including a plurality of word lines; and a plurality of sub-word line drivers implemented in a second chip having a stacked structure with the first chip and arranged to correspond to the plurality of cell array chips, respectively. The plurality of sub-word line drivers generate drive signals applied to the plurality of word lines of the plurality of cell array chips. A first drive signal in the drive signal is applied to the even word lines among the plurality of word lines from one side of the corresponding cell array chip, and a second drive signal in the drive signal is applied to the odd word lines among the plurality of word lines from the other side of the corresponding cell array chip opposite to the one side.

[0008] According to an embodiment, a semiconductor memory device having a cell-on-periphery (CoP) structure includes a first chip and a second chip, the first chip includes a plurality of cell array sheets, each cell array sheet includes a plurality of word lines, and the second chip includes a plurality of sub-word line drivers respectively arranged under the plurality of cell array sheets. The plurality of sub-word line drivers are configured to generate drive signals. The plurality of word lines include even word lines and odd word lines, a first drive signal in the drive signal is applied to the even word lines from one side of the corresponding cell array sheet, and a second drive signal in the drive signal is applied to the odd word lines from the other side of the corresponding cell array sheet opposite to the one side. The plurality of sub-word line drivers include a first sub-word line driver and a second sub-word line driver corresponding to two adjacent cell array sheets, the first sub-word line driver and the second sub-word line driver being configured to respectively generate a first drive signal applied to the even word lines of the two adjacent cell array sheets and a second drive signal applied to the odd word lines of the two adjacent cell array sheets. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2A is a diagram showing the layout of a semiconductor memory device.

[0012] Figure 2B is a diagram showing a layout of a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 3A is a schematic plan view showing a part of a semiconductor memory device.

[0014] Figure 3B is with Figure 3A The cross-sectional view corresponding to the plan view.

[0015] Figure 4A is a schematic plan view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 4B is according to an example embodiment and Figure 4A The cross-sectional view corresponding to the plan view.

[0017] Figure 5 is a schematic cross-sectional view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 6 is a block diagram showing a configuration of a semiconductor memory system according to an embodiment of the present disclosure.

[0019] Figure 7 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Figure 8 is a diagram showing a configuration of a unit array sheet according to an embodiment of the present disclosure.

[0021] Fig. 9A is a diagram showing a layout of a cell array sheet according to an embodiment of the present disclosure.

[0022] Fig. 9B is a diagram showing a method according to an example embodiment Fig. 9A A perspective view of a cell array sheet.

[0023] Fig. 9C shows an example embodiment according to the Fig. 9A A cross-sectional view taken along line X1-X1' and line Y1-Y1'.

[0024] Fig.9D is a diagram showing a layout of a cell array sheet according to an embodiment of the present disclosure.

[0025] Fig.9E is a diagram showing a method according to an example embodiment Fig.9D A perspective view of a cell array sheet.

[0026] Fig. 10A is a schematic plan view showing a portion of a semiconductor memory device according to an embodiment of the present disclosure.

[0027] Fig. 10B is according to an example embodiment and Fig. 10A The cross-sectional view corresponding to the plan view. DETAILED DESCRIPTION

[0028] In some aspects, based on the increased integration of memory cells, the number of memory cells connected to a word line may increase, and the word line driver processing the word line may be affected by the increased load. In some embodiments, the word line load can be shared by using multiple sub-word line drivers distributed in the memory cell array.

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure.

[0030] Terms such as “first”, “second”, etc. used herein may be used to refer to various components regardless of their order and / or priority, and to distinguish relevant components from other components, but not to limit these components.

[0031] Hereinafter, a first wafer on which a memory cell is disposed may be referred to as a first chip. In addition, a second wafer on which various circuits for driving the memory cell are disposed may be referred to as a second chip.

[0032] Figure 1 is a block diagram showing a configuration of a semiconductor memory device 1000 according to an embodiment of the present disclosure.

[0033] refer to Figure 1 , the semiconductor memory device 1000 may include a first chip 100 and a second chip 200. The first chip 100 and the second chip 200 may have a stack structure. For example, the first chip 100 and the second chip 200 may have a cell-on-periphery (CoP) structure.

[0034] The CoP structure may be a structure in which a first wafer including a memory cell and a second wafer including a core circuit and a peripheral circuit are separately manufactured and then the first wafer is stacked on the second wafer and bonded to the second wafer. In this specification, the first wafer on which the memory cell is disposed and the second wafer on which the core circuit and the peripheral circuit are disposed may be referred to as a first chip and a second chip, respectively.

[0035] In an embodiment, the first chip 100 and the second chip 200 having the CoP structure may be electrically connected to each other by bonding a first bonding metal 10 formed at the bottom of the first chip 100 and a second bonding metal 20 formed at the top of the second chip 200. Alternatively, in some embodiments, the first chip 100 and the second chip 200 having the CoP structure may be electrically connected to each other by a through-substrate via (e.g., through-silicon via (TSV)) method.

[0036] The first chip 100 may include a memory cell array. The memory cell array may include a plurality of memory cells formed at intersections of word lines and bit lines. The memory cell array may be divided into a plurality of cell array sheets. The memory cell array may be divided into regions that each sub-word line driver is responsible for. The regions of the memory cell array divided from each other may be cell array sheets, respectively.

[0037] According to an embodiment, the first chip 100 may include a first cell array sheet 110-1 and a second cell array sheet 110-2 adjacent to the first cell array sheet 110-1. Each of the first cell array sheet 110-1 and the second cell array sheet 110-2 may include a first word line 111 to which a driving signal is applied from one side of the corresponding cell array sheet, and a second word line 112 to which a driving signal is applied from the other side of the corresponding cell array sheet opposite to the one side.

[0038] In an embodiment, the one side and the other side may be a left side and a right side, respectively. Alternatively, in some embodiments, the one side and the other side may be an upper side and a lower side, respectively. In addition, in an embodiment, the first word line 111 and the second word line 112 may be an even word line and an odd word line, respectively, but are not limited thereto.

[0039] exist Figure 1 , only one first word line 111 and one second word line 112 are shown on each of the cell array sheets 110-1 and 110-2. However, this is only for convenience of explanation, and each of the cell array sheets 110-1 and 110-2 may include a plurality of first word lines 111 and a plurality of second word lines 112.

[0040] The second chip 200 may include various circuits for driving the memory cell array of the first chip 100. For example, the second chip 200 may include various core circuits, such as a bit line sense amplifier, a sub-word line driver, a row decoder (or an X decoder), a column decoder (or a Y decoder), etc. In addition, the second chip 200 may include various peripheral circuits, such as a control logic circuit for decoding commands, an address register, a delay locked loop (DLL), a data I / O buffer, a power supply circuit, etc.

[0041] According to an embodiment, the second chip 200 may include a plurality of sub-word line drivers corresponding to the plurality of cell array sheets, respectively. According to an embodiment, the plurality of sub-word line drivers may be respectively disposed under the corresponding cell array sheets.

[0042] For example, refer to Figure 1, the second chip 200 may include a first sub-word line driver 210-1 corresponding to the first cell array sheet 110-1, and a second sub-word line driver 210-2 corresponding to the second cell array sheet 110-2. The first sub-word line driver 210-1 and the second sub-word line driver 210-2 may be located below the first cell array sheet 110-1 and the second cell array sheet 110-2, respectively. In an embodiment, the first sub-word line driver 210-1 may be disposed in a portion of an area 201-1 of the second chip 200 that overlaps with an area of ​​the first chip 100 in which the first cell array sheet 110-1 is formed. In addition, the second sub-word line driver 210-2 may be disposed in a portion of an area 201-2 of the second chip 200 that overlaps with an area of ​​the first chip 100 in which the second cell array sheet 110-2 is formed.

[0043] According to an embodiment of the present disclosure, the first sub-word line driver 210-1 may generate a driving signal applied to the first word line 111 of the first cell array cell 110-1 and the second cell array cell 110-2. In addition, the second sub-word line driver 210-2 may generate a driving signal applied to the second word line 112 of the first cell array cell 110-1 and the second cell array cell 110-2.

[0044] In this case, for example, the driving signal generated by the first sub-word line driver 210-1 can be transmitted to the first chip 100 through the first bonding metal 10 and the second bonding metal 20, and can be transmitted to the opposite sides of the first cell array sheet 110-1 (for example, one side of the first cell array sheet 110-1 and the other side opposite to the one side) through the lower metal layer 30 of the first chip 100. In an embodiment, the lower metal layer 30 can be formed below the first cell array sheet 110-1 and the second cell array sheet 110-2. The driving signal transmitted to the opposite sides of the first cell array sheet 110-1 can be applied to the first word lines 111 of the first cell array sheet 110-1 and the second cell array sheet 110-2 through the vias 40.

[0045] Likewise, the driving signal generated by the second sub-word line driver 210-2 can be transmitted to the first chip 100 through the first bonding metal 10 and the second bonding metal 20, and can be transmitted to the opposite sides of the second cell array sheet 110-2 (e.g., one side of the second cell array sheet 110-2 and the other side opposite to the one side) through the lower metal layer 30 of the first chip 100. The driving signal transmitted to the opposite sides of the second cell array sheet 110-2 can be applied to the second word lines 112 of the first cell array sheet 110-1 and the second cell array sheet 110-2 through the vias 40.

[0046] According to the above-described embodiments of the present disclosure, the sub-word line drivers can be appropriately arranged using the CoP structure. In this case, the gross die gain can be ensured, and the word line load difference between the sub-word line drivers can be eliminated. Accordingly, the performance of the semiconductor memory device 1000 can be improved.

[0047] In the following, reference will be made to Figure 2A and Figure 2B Describe the layout of semiconductor memory devices.

[0048] Figure 2A 5 is a diagram showing a layout of a semiconductor memory device. In the semiconductor memory device, a memory cell array, a core circuit, and a peripheral circuit may be implemented in one chip 50.

[0049] refer to Figure 2A , a cell core including a cell array sheet having a certain size, a sub-word line driver SWD, a bit line sense amplifier BLSA, and a connection region Conj may be disposed in a first region 51 of the chip 50. The cell core may be arranged in a matrix form in the chip 50. For example, an enlarged view of an area 60 of the chip 50 is shown below the arrow. Specifically, in a first direction, a plurality of sub-word line drivers SWD may be disposed between a plurality of cell array sheets, and in a second direction, a plurality of bit line sense amplifiers BLSA may be disposed between the cell array sheets. The connection region Conj may be disposed between a plurality of sub-word line drivers SWD in the second direction and between a plurality of bit line sense amplifiers BLSA in the first direction.

[0050] The row decoder may be disposed in the second region 52 of the chip 50, and the column decoder may be disposed in the third region 53 of the chip 50. In addition, various peripheral circuits (e.g., control logic circuits, address registers, DLLs, data I / O buffers, power supply circuits, etc.) may be disposed in the fourth region 54.

[0051] Figure 2B is a diagram showing a layout of a semiconductor memory device according to an embodiment of the present disclosure. Figure 2B , the semiconductor memory device 1000 may have a CoP structure in which a first chip 100 in which a memory cell is implemented and a second chip 200 in which a core circuit and a peripheral circuit are implemented are bonded to each other.

[0052] The first chip 100 may include a plurality of unit array sheets 110. Figure 2A Compared with the first region 51 of the cell core, each cell array sheet 110 of the first chip 100 may not have the sub word line driver SWD, the bit line sense amplifier BLSA, and the connection region Conj around the cell array sheet 110 .

[0053] In this case, the sub word line driver SWD, the bit line sense amplifier BLSA, and the connection region Conj for driving each cell array sheet 110 may be disposed in the first region 201 of the second chip 200. Figure 2B As shown, the bit line sense amplifier BLSA and the sub word line driver SWD 210 for driving the cell array sheet 110 may be disposed in a first region 201 of the second chip 200 corresponding to the corresponding cell array sheet 110. Specifically, according to an embodiment of the present disclosure, the sub word line driver 210 corresponding to the relevant cell array sheet 110 may be disposed in a portion of the first region 201 of the second chip 200 overlapping with a region in which the corresponding cell array sheet 110 is formed.

[0054] According to an embodiment of the present disclosure, a row decoder may be disposed in the second region 26 of the second chip 200, and a column decoder may be disposed in the third region 27 of the second chip 200. In addition, various peripheral circuits (e.g., a control logic circuit, an address register, a DLL, a data I / O buffer, a power supply circuit, etc.) may be disposed in the fourth region 28 of the second chip 200.

[0055] exist Figure 2B In Figure 2A The cell array sheet, the core circuit, and the peripheral circuit are shown in the same form as in FIG. However, this is only an example for comparison with the layout of the semiconductor memory device, and the layout of the semiconductor memory device 1000 according to the embodiment of the present disclosure is not limited to Figure 2B For example, when Figure 2A The first chip 100 of the semiconductor memory device 1000 may have a space in which the sub-word line driver SWD, the bit line sense amplifier BLSA, the row decoder, and the column decoder do not exist when compared with the chip 50 of the semiconductor memory device 1000. Accordingly, a layout different from the layout shown in the figure may be adopted, for example, the size of the cell array sheet is increased by utilizing the corresponding space.

[0056] Figure 3A and Figure 3B 1 is a diagram for explaining the configuration and operation of the semiconductor memory device 50A. Figure 3A is a schematic plan view showing a portion of a semiconductor memory device 50A, and Figure 3B is with Figure 3A The cross-sectional view corresponding to the plan view.

[0057] Also refer to Figure 3A and Figure 3BIn the semiconductor memory device 50A, the sub word line drivers 55 and 56 are located on the same plane as the cell array chip 57. That is, in the semiconductor memory device 50A, the cell array chip 57 and the sub word line drivers 55 and 56 are implemented together on one wafer (or chip). In addition, in the semiconductor memory device 50A, each of the sub word line drivers 55 and 56 is provided between the cell array chips 57 to appropriately distribute the word line load and improve the area efficiency.

[0058] The sub-word line driver 56 arranged in the central area of ​​the cell array has an even / odd dual-arm word line structure. Here, the even / odd dual-arm word line structure refers to a structure in which the sub-word line driver 56 is responsible for the even word lines or odd word lines of two adjacent cell array slices. Meanwhile, the sub-word line driver 55 arranged in the edge area of ​​the cell array is only responsible for the even word lines or odd word lines of one cell array slice.

[0059] In this case, the sub-word line driver 56 arranged in the center area and the sub-word line driver 55 arranged in the edge area are different from each other in the number of word lines that the sub-word line driver is responsible for (that is, the number of memory cells that the sub-word line driver is responsible for), and therefore there is a difference in word line load. The difference in word line load may cause a difference in driving time between memory cells connected to word lines having the same row address.

[0060] In order to eliminate the aforementioned driving time difference, the driving performance of the sub-word line drivers 55 and 56 can be adjusted as a whole by reducing the size of the sub-word line driver 55 disposed in the edge region where the word line load is relatively small. However, this increases the complexity of the design and reduces the overall driving performance of the sub-word line driver, thereby limiting the performance improvement of the semiconductor memory device.

[0061] Figure 4A and Figure 4B 2 is a diagram for explaining the configuration and operation of a semiconductor memory device according to an embodiment of the present disclosure. Figure 4A is a schematic plan view showing a portion of a semiconductor memory device 1000A according to an embodiment of the present disclosure, and Figure 4B is according to an example embodiment and Figure 4A The semiconductor memory device 1000A may be Figure 1 and Figure 2B However, the present disclosure is not limited thereto.

[0062] refer to Figure 4A and Figure 4B, the semiconductor memory device 1000A may include a first cell array cell 110-1, a second cell array cell 110-2, a third cell array cell 110-3, and a fourth cell array cell 110-4. In addition, the semiconductor memory device 1000A may include a first sub-word line driver 210-1 disposed under the first cell array cell 110-1, a second sub-word line driver 210-2 disposed under the second cell array cell 110-2, a third sub-word line driver 210-3 disposed under the third cell array cell 110-3, and a fourth sub-word line driver 210-4 disposed under the fourth cell array cell 110-4.

[0063] The first to fourth cell array sheets 110-1, 110-2, 110-3, and 110-4 may be included in the first chip 100, and the first to fourth sub word line drivers 210-1, 210-2, 210-3, and 210-4 may be included in the second chip 200. The first chip 100 and the second chip 200 may have a CoP structure in which the first chip 100 is stacked on the second chip 200. According to an embodiment, the first chip 100 and the second chip 200 may be electrically connected to each other by bonding a first bonding metal 10 formed at a bottom of the first chip 100 with a second bonding metal 20 formed at a top of the second chip 200.

[0064] Each of the first cell array sheet 110-1 to the fourth cell array sheet 110-4 may include a first word line 111 to which a driving signal is applied from one side of the corresponding cell array sheet, and a second word line 112 to which a driving signal is applied from the other side of the corresponding cell array sheet opposite to the one side. The first word line 111 and the second word line 112 may be alternately arranged on the corresponding cell array sheet. In an embodiment, the first word line 111 may be an even word line, and the second word line 112 may be an odd word line. However, the present disclosure is not limited thereto.

[0065] The first to fourth sub-word line drivers 210-1, 210-2, 210-3, and 210-4 may generate driving signals applied to the first to fourth cell array sheets 110-1, 110-2, 110-3, and 110-4. The first to fourth sub-word line drivers 210-1, 210-2, 210-3, and 210-4 may include, for example, even sub-word line drivers 210-1 and 210-3 generating driving signals applied to even word lines 111, and odd sub-word line drivers 210-2 and 210-4 generating driving signals applied to odd word lines 112.

[0066] According to an embodiment of the present disclosure, among a plurality of sub-word line drivers, two sub-word line drivers corresponding to two adjacent cell array sheets may respectively generate driving signals applied to even word lines of the two adjacent cell array sheets, and driving signals applied to odd word lines of the two adjacent cell array sheets. In an embodiment, some sub-word line drivers (e.g., even sub-word line drivers 210-1 and 210-3) may generate driving signals applied to even word lines of a plurality of cell array sheets in response to a first row address, and other sub-word line drivers (e.g., odd sub-word line drivers 210-2 and 210-4) may generate driving signals applied to odd word lines of a plurality of cell array sheets in response to a second row address.

[0067] For example, the first sub-word line driver 210-1 and the second sub-word line driver 210-2 corresponding to the first cell array cell 110-1 and the second cell array cell 110-2 adjacent to each other may generate a driving signal applied to the even word line 111 of the first cell array cell 110-1 and the second cell array cell 110-2, and a driving signal applied to the odd word line 112 of the first cell array cell 110-1 and the second cell array cell 110-2, respectively. In addition, the third sub-word line driver 210-3 and the fourth sub-word line driver 210-4 corresponding to the third cell array cell 110-3 and the fourth cell array cell 110-4 adjacent to each other may generate a driving signal applied to the even word line 111 of the third cell array cell 110-3 and the fourth cell array cell 110-4, and a driving signal applied to the odd word line 112 of the third cell array cell 110-3 and the fourth cell array cell 110-4, respectively.

[0068] The driving signals generated by the first to fourth sub word line drivers 210 - 1 , 210 - 2 , 210 - 3 , and 210 - 4 may be transferred to the first chip 100 through the first bonding metal 10 and the second bonding metal 20 , and then may be applied to word lines to which the driving signals must be applied.

[0069] Specifically, the driving signal generated from the first sub-word line driver 210-1 may be transmitted to the first chip 100 through the first bonding metal 10 and the second bonding metal 20. The driving signal transmitted to the first chip 100 may be transmitted to both sides of the first cell array sheet 110-1 through the lower metal layer 30 of the first chip 100. The driving signal transmitted to both sides of the first cell array sheet 110-1 may be applied to the even word lines 111 of the first cell array sheet 110-1 and the second cell array sheet 110-2 through the vias 40 formed on both sides of the first cell array sheet 110-1.

[0070] The driving signal generated from the second sub word line driver 210-2 may be transmitted to the first chip 100 through the first bonding metal 10 and the second bonding metal 20. The driving signal transmitted to the first chip 100 may be transmitted to both sides of the second cell array sheet 110-2 through the lower metal layer 30 of the first chip 100. The driving signal transmitted to both sides of the second cell array sheet 110-2 may be applied to the odd word lines 112 of the first cell array sheet 110-1 and the second cell array sheet 110-2 through vias 40 formed on both sides of the second cell array sheet 110-2.

[0071] Similar to the above, driving signals generated from the third and fourth sub word line drivers 210 - 3 and 210 - 4 may be applied to even and odd word lines 111 and 112 of the third and fourth cell array sheets 110 - 3 and 110 - 4 , respectively.

[0072] According to the above-mentioned embodiment of the present disclosure, since the sub-word line drivers 210-1, 210-2, 210-3 and 210-4 are respectively located under the corresponding cell array slices, Figure 3A and Figure 3B Unlike the semiconductor memory device 50A of FIG. 1 , the output of the sub-word line driver can be connected to both sides of the cell array sheet. In this case, no additional sub-word line driver is required in the edge area, and thus the total die gain can be obtained. The performance of the semiconductor memory device 1000A can be improved by using the additional space ensured in various ways. For example, the performance of the semiconductor memory device 1000A can be improved by increasing the size of the sub-word line driver or the bit line sense amplifier, or by adding a power supply circuit for the core circuit. According to an embodiment of the present disclosure, the sub-word line drivers 210-1, 210-2, 210-3, and 210-4 can have the same drive strength.

[0073] In addition, according to the above-mentioned embodiments of the present disclosure, Figure 3A and Figure 3BUnlike the semiconductor memory device 50A of the present invention, a drive signal can be applied to the even word line of each cell array sheet from one side (e.g., the left side) of the corresponding cell array sheet, and a drive signal can be applied to the odd word line of each cell array sheet from the other side (e.g., the right side) of the corresponding cell array sheet opposite to the one side. For example, in all cell array sheets, the even word lines or the odd word lines can be respectively configured in the same direction. In this case, each of the sub-word line drivers 210-1, 210-2, 210-3, and 210-4 can be connected to two cell array sheets, and thus the difference in word line load between the sub-word line drivers can be eliminated. For example, all sub-word line drivers can have the same word line load. Therefore, the semiconductor memory device 1000A can have a lower design complexity than the semiconductor memory device 50A, and the overall driving performance of the sub-word line drivers 210-1, 210-2, 210-3, and 210-4 can be enhanced.

[0074] exist Figure 4A and Figure 4B , for ease of description, four cell array chips 110-1, 110-2, 110-3, and 110-4, and four sub-word line drivers 210-1, 210-2, 210-3, and 210-4 for driving the four cell array chips 110-1, 110-2, 110-3, and 110-4 are shown. However, the number of cell array chips and sub-word line drivers included in the semiconductor memory device 1000A is not limited thereto.

[0075] Figure 5 1 is a schematic cross-sectional view showing a portion of a semiconductor memory device 1000B according to an embodiment of the present disclosure. The semiconductor memory device 1000B may be Figure 1 , Figure 2B , Figure 4A and Figure 4B However, the present disclosure is not limited thereto.

[0076] refer to Figure 5, the semiconductor memory device 1000B may include a first chip 100 and a second chip 200. The first chip 100 and the second chip 200 may have a CoP structure in which the first chip 100 is stacked on the second chip 200. According to an embodiment, the first chip 100 and the second chip 200 may be electrically connected to each other by bonding a first bonding metal 10 formed at the bottom of the first chip 100 with a second bonding metal 20 formed at the top of the second chip 200. The materials of the first bonding metal 10 and the second bonding metal 20 may include copper (Cu) or be formed of copper (Cu). In this case, the bonding method of the first chip 100 and the second chip 200 may be referred to as a Cu-Cu bonding method. However, the present disclosure is not limited thereto, and in some embodiments, the first bonding metal 10 and the second bonding metal 20 may include other metal materials such as aluminum (Al) or tungsten (W), or be formed of other metal materials such as aluminum (Al) or tungsten (W).

[0077] The first chip 100 may include a plurality of cell array sheets. For example, the first chip 100 may include a first cell array sheet 110-1 and a second cell array sheet 110-2 adjacent to the first cell array sheet 110-1. Each of the cell array sheets 110-1 and 110-2 may include a plurality of memory cells formed at the intersection of a plurality of word lines WL and a plurality of bit lines BL. According to an embodiment, each memory cell may be a DRAM memory cell including a vertical channel transistor 33 and a capacitor 34, but is not limited thereto. As described above, each of the cell array sheets 110-1 and 110-2 may include a first word line 111 to which a drive signal is applied from one side of the corresponding cell array sheet, and a second word line 112 to which a drive signal is applied from the other side of the corresponding cell array sheet opposite to the one side. However, due to Figure 5 1 is a cross-sectional view, and thus only one word line WL included in each of the first cell array cell 110 - 1 and the second cell array cell 110 - 2 is shown.

[0078] According to an embodiment of the present disclosure, the first chip 100 may include a metal layer 30 formed under the cell array sheets 110-1 and 110-2, and metal layers 31 and 32 formed on opposite sides of the first cell array sheet 110-1. The driving signal transmitted to the first chip 100 through the first bonding metal 10 and the second bonding metal 20 may be transmitted to the vias 40 formed on opposite sides of the first cell array sheet 110-1 through at least one metal layer among the plurality of metal layers 30, 31, and 32. Although Figure 5An example is shown in which the driving signal is transmitted to the via 40 through the lowest metal layer 30 among the plurality of metal layers 30, 31, and 32, but the present disclosure is not limited thereto. In some embodiments, the driving signal may be transmitted to the via 40 through at least one of the other metal layers 31 and 32. In addition, the layer used as the signal transmission path for the word line WL or the layer used as the signal transmission path for the bit line BL is not limited thereto. Figure 5 The layers shown in , and in some embodiments, other layers may be used.

[0079] The plurality of metal layers 30 , 31 , and 32 may include metal layers formed of various materials (eg, aluminum layer, copper layer, tungsten layer, etc.) In an embodiment, a driving signal may be transmitted to the via 40 through the tungsten layer 30 . However, the present disclosure is not limited thereto.

[0080] The driving signals transmitted to the via holes 40 formed on opposite sides of the first cell array sheet 110 - 1 may be applied to the word lines WL of the first cell array sheet 110 - 1 and the second cell array sheet 110 - 2 .

[0081] The second chip 200 may include a plurality of sub-word line drivers respectively disposed under the plurality of cell array sheets. According to an embodiment, among the plurality of sub-word line drivers, two sub-word line drivers corresponding to two adjacent cell array sheets may respectively generate a driving signal applied to the even word lines of the two adjacent cell array sheets, and a driving signal applied to the odd word lines of the two adjacent cell array sheets. In an embodiment, unlike the memory cells of the first chip 100, the plurality of sub-word line drivers may be implemented to include horizontal channel transistors, but are not limited thereto.

[0082] refer to Figure 5 The second chip 200 may include a sub word line driver 210-1 disposed under the first cell array sheet 110-1. The sub word line driver 210-1 may generate a driving signal applied to the even word lines or odd word lines of the first cell array sheet 110-1 and the second cell array sheet 110-2.

[0083] The driving signal generated by the sub word line driver 210 - 1 may be transferred to the second bonding metal 20 through a plurality of metal layers 71 , 72 , 73 , 74 , and 75 formed over the sub word line driver 210 - 1 and vias 70 penetrating the metal layers 72 , 73 , and 74 .

[0084] Figure 6 1 is a block diagram showing a configuration of a semiconductor memory system 10000 according to an embodiment of the present disclosure. Figure 6 , the semiconductor memory system 10000 may include a memory controller 2000 and a semiconductor memory device 1000C. The semiconductor memory device 1000C may be Figure 1 , Figure 2B , Figure 4A , Figure 4B and Figure 5 However, the present disclosure is not limited thereto.

[0085] The memory controller 2000 may control the semiconductor memory device 1000C. For example, the memory controller 2000 may control the semiconductor memory device 1000C in response to a request of a processor supporting various applications (e.g., server applications, personal computer (PC) applications, mobile applications, etc.). For example, the memory controller 2000 may be included in a host including a processor, and may control the semiconductor memory device 1000C in response to a request of the processor.

[0086] The memory controller 2000 may send a clock signal CK, a command CMD, and / or an address ADDR to the semiconductor memory device 1000C to control the semiconductor memory device 1000C. In addition, the memory controller 2000 may send a data signal DQ to the semiconductor memory device 1000C, or may receive the data signal DQ from the semiconductor memory device 1000C. The memory controller 2000 may receive a data strobe signal DQS from the semiconductor memory device 1000C when reading the data signal DQ from the semiconductor memory device 1000C. The memory controller 2000 may send a data strobe signal DQS to the semiconductor memory device 1000C when writing the data signal DQ to the semiconductor memory device 1000C.

[0087] The semiconductor memory device 1000C may receive data from the memory controller 2000 and may store the received data. The semiconductor memory device 1000C may read the stored data in response to a request from the memory controller 2000 and may transmit the data to the memory controller 2000.

[0088] In an embodiment, the semiconductor memory device 1000C may be a semiconductor memory device including a volatile memory cell. For example, the semiconductor memory device 1000C may include various DRAM devices, such as double data rate synchronous dynamic random access memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4XSDRAM, LPDDR5 SDRAM, graphic double data rate synchronous graphic random access memory (GDDR SGRAM), GDDR2SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, etc.

[0089] In an embodiment, the semiconductor memory device 1000C may be a memory device (eg, high bandwidth memory (HBM), HBM2, HBM3, etc.) in which DRAM dies or DRAM chips are stacked.

[0090] In an embodiment, the semiconductor memory device 1000C may be a memory module, such as a dual in-line memory module (DIMM). For example, the semiconductor memory device 1000C may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). However, these are illustrative, and the semiconductor memory device 1000C may be other memory modules, such as a single in-line memory module (SIMM).

[0091] In an embodiment, the semiconductor memory device 1000C may include an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, an MRAM device, or the like.

[0092] The semiconductor memory device 1000C may include a memory cell array 100C and a core / peripheral circuit 200C. The memory cell array 100C may be implemented in the above-mentioned first chip 100 , and the core / peripheral circuit 200C may be implemented in the above-mentioned second chip 200 .

[0093] The memory cell array 100C may include a plurality of memory banks Bank 1 to Bank n (n is a natural number greater than 1), each of which may include a memory cell for storing data. For ease of description, it is assumed that each memory bank includes a DRAM cell. However, this is illustrative, and each of the plurality of memory banks Bank 1 to Bank n may be implemented to include a volatile memory cell other than a DRAM cell. In addition, each of the plurality of memory banks Bank 1 to Bank n may be implemented to include memory cells of the same type as each other, or may be implemented to include at least one different type of memory cell.

[0094] According to an embodiment, each of the plurality of memory banks Bank 1 to Bank n may include a plurality of cell array tiles. The cell array tiles may refer to memory cell regions divided from each other based on sub word line drivers.

[0095] The core / peripheral circuit 200C may include various circuits for driving the memory cell array 100C. For example, the core / peripheral circuit 200C may include various core circuits, such as a bit line sense amplifier, a sub-word line driver, a row decoder (or an X decoder), a column decoder (or a Y decoder), etc. In addition, the core / peripheral circuit 200C may include various peripheral circuits, such as a control logic circuit for decoding commands, an address register, a delay locked loop (DLL), a data I / O buffer, a power supply circuit, etc.

[0096] Figure 7 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present disclosure. The semiconductor memory device 1000D may be Figure 1 , Figure 2B , Figure 4A , Figure 4B , Figure 5 and Figure 6 However, the present disclosure is not limited thereto.

[0097] refer to Figure 6 and Figure 7 , the semiconductor memory device 1000D may include a control logic circuit 410, an address register 420, a bank control circuit 430, a refresh control circuit 500, a row address multiplexer (RA MUX) 440, a column address (CA) latch 450, a row decoder 460, a column decoder 470, a memory cell array 100C, a sense amplifier unit 485, an I / O gating circuit 490, an error correction code (ECC) engine 550, and a data I / O buffer 520. In addition, although not shown in the figure, the semiconductor memory device 1000D may include a plurality of sub word line drivers.

[0098] According to an embodiment, the memory cell array 100C may be implemented in the above-mentioned first chip 100. In addition, the remaining circuits 410, 420, 430, 440, 450, 460, 470, 485, 490, 500, 520 and 550 and a plurality of sub-word line drivers (not shown) may be implemented in the above-mentioned second chip 200. In an embodiment, while referring to Figure 2B , a plurality of sub word line drivers (not shown) and a sense amplifier unit 485 may be disposed in the first region 201 of the second chip 200. A row decoder 460 may be disposed in the second region 26 of the second chip 200, and a column decoder 470 may be disposed in the third region 27 of the second chip 200. A control logic circuit 410, an address register 420, a bank control circuit 430, a refresh control circuit 500, a row address multiplexer 440, a column address latch 450, an I / O gating circuit 490, an ECC engine 550, and a data I / O buffer 520 may be disposed in the fourth region 28 of the second chip 200. However, embodiments are not limited thereto.

[0099] The memory cell array 100C may include a plurality of memory cell arrays 100C_1 to 100C_n. Each of the plurality of memory cell arrays 100C_1 to 100C_n may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at the intersection of a corresponding word line and a corresponding bit line. Each of the plurality of memory cell arrays 100C_1 to 100C_n may include a plurality of cell array sheets. Here, n is a natural number greater than 1.

[0100] The row decoder 460 may include a plurality of sub-row decoders 460_1 to 460_n. Each of the plurality of sub-row decoders 460_1 to 460_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 100C_1 to 100C_n.

[0101] The sense amplifier unit 485 may include a plurality of sense amplifiers 485_1 to 485_n. Each of the plurality of sense amplifiers 485_1 to 485_n may be connected to a corresponding bank array among the plurality of bank arrays 100C_1 to 100C_n.

[0102] The column decoder 470 may include a plurality of sub-column decoders 470_1 to 470_n. Each of the plurality of sub-column decoders 470_1 to 470_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 100C_1 to 100C_n through a corresponding sense amplifier.

[0103] A plurality of bank arrays 100C_1 to 100C_n, a plurality of sense amplifiers 485_1 to 485_n, a plurality of sub-column decoders 470_1 to 470_n, and a plurality of sub-row decoders 460_1 to 460_n may constitute a plurality of banks. For example, a first bank array 100C_1, a first sense amplifier 485_1, a first sub-column decoder 470_1, and a first sub-row decoder 460_1 may constitute a first bank.

[0104] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 2000. The address register 420 may provide the received bank address BANK_ADDR to the bank control circuit 430, may provide the received row address ROW_ADDR to the row address multiplexer 440, and may provide the received column address COL_ADDR to the column address latch 450.

[0105] The memory control circuit 430 may generate a memory control signal in response to the memory address BANK_ADDR. For example, in response to the memory control signal, a row decoder corresponding to the memory address BANK_ADDR among the plurality of sub-row decoders 460_1 to 460_n may be activated. In response to the memory control signal, a column decoder corresponding to the memory address BANK_ADDR among the plurality of sub-column decoders 470_1 to 470_n may be activated.

[0106] The row address multiplexer 440 may receive a row address ROW_ADDR from the address register 420 and may receive a refresh row address REF_ADDR from the refresh control circuit 500. The row address multiplexer 440 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 may be applied to a plurality of sub-row decoders 460_1 to 460_n.

[0107] The refresh control circuit 500 may sequentially increase or decrease the refresh row address REF_ADDR in response to the refresh signal from the control logic circuit 410 .

[0108] Among the plurality of sub row decoders 460_1 to 460_n, a row decoder selected by the bank control circuit 430 may activate a word line corresponding to a row address RA output from the row address multiplexer 440. For example, the selected row decoder may apply a driving signal to a word line corresponding to the row address RA.

[0109] According to an embodiment, a driving signal may be applied to a main word line corresponding to a row address. The driving signal applied to the main word line may be applied to the above Figure 1 , Figure 2B , Figure 4A , Figure 4B and Figure 5 One of the sub word line drivers described in is used to drive a word line corresponding to a row address. Therefore, a word line corresponding to the relevant row address can be activated by the sub word line driver.

[0110] The column address latch 450 may receive the column address COL_ADDR from the address register 420 and may temporarily store the received column address COL_ADDR. In addition, for example, in a burst mode, the column address latch 450 may gradually increase the received column address COL_ADDR. The column address latch 450 may apply the temporarily stored or gradually increased column address COL_ADDR' to a plurality of sub-column decoders 470_1 to 470_n.

[0111] Among the plurality of sub-column decoders 470_1 to 470 — n, a column decoder activated by the bank control circuit 430 may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through an I / O gating circuit 490 .

[0112] The I / O gating circuit 490 may include a circuit for gating I / O data. In addition, the I / O gating circuit 490 may include a data latch for storing code words CW output from the plurality of memory bank arrays 100C_1 to 100C_n, and a write driver for writing data to the plurality of memory bank arrays 100C_1 to 100C_n.

[0113] In an embodiment, during a read operation, a codeword CW read out from a selected memory bank array among the plurality of memory bank arrays 100C_1 to 100C_n may be read out by a sense amplifier corresponding to the selected memory bank array, and may be stored in a data latch of the I / O strobe circuit 490. The codeword CW stored in the data latch may be ECC decoded by the ECC engine 550, and may be provided as data DTA to the data I / O buffer 520. The data I / O buffer 520 may generate a data signal DQ based on the data DTA, and may provide the data signal DQ together with the strobe signal DQS to the memory controller 2000.

[0114] In an embodiment, during a write operation, data DTA to be written to a selected memory bank array among the plurality of memory bank arrays 100C_1 to 100C_n may be received as a data signal DQ by the data I / O buffer 520. The data I / O buffer 520 may convert the data signal DQ into data DTA, and may provide the data DTA to the ECC engine 550. The ECC engine 550 may generate a parity bit (or parity data) based on the data DTA, and may provide a codeword CW including the data DTA and the parity bit to the I / O strobe circuit 490. The I / O strobe circuit 490 may write the codeword CW to the selected memory bank array.

[0115] In a write operation, the data I / O buffer 520 may convert the data signal DQ into data DTA and may provide the data DTA to the ECC engine 550. In a read operation, the data I / O buffer 520 may convert the data DTA provided from the ECC engine 550 into the data signal DQ.

[0116] In a write operation, the ECC engine 550 may perform ECC encoding on the data DTA. In a read operation, the ECC engine 550 may perform ECC decoding on the codeword CW.

[0117] The control logic circuit 410 may control the operation of the semiconductor memory device 1000D. For example, the control logic circuit 410 may generate a control signal so that the semiconductor memory device 1000D performs a write operation, a read operation, and a refresh operation. The control logic circuit 410 may include a command decoder 411 that decodes a command CMD received from the memory controller 2000, and a mode register set MRS 412 that is used to set an operation mode of the semiconductor memory device 1000D.

[0118] The command decoder 411 may decode the command CMD, and may generate internal command signals, such as an internal activation signal IACT, an internal precharge signal IPRE, an internal read signal IRD, an internal write signal IWR, etc. In addition, the command decoder 411 may decode a chip selection signal and a command / address signal, and may generate a control signal corresponding to the command CMD.

[0119] Figure 8 is a diagram showing the configuration of a cell array sheet 110 according to an embodiment of the present disclosure. Figure 8 The cell array sheet 110 may include a plurality of word lines WL0 to WLm, a plurality of bit lines BL0 to BLn, and a plurality of memory cells MC disposed at intersections of the word lines WL0 to WLm and the bit lines BL0 to BLn. Here, m is a natural number greater than 1.

[0120] According to an embodiment, each memory cell MC may be a DRAM cell. For example, each memory cell MC may include a cell transistor connected to a word line and a bit line, and a cell capacitor connected to the cell transistor. According to an embodiment of the present disclosure, the cell transistor may be a vertical channel transistor.

[0121] Since the vertical channel transistor has a structure different from that of the horizontal channel transistor, the vertical channel transistor and the horizontal channel transistor can be implemented using different wafers. According to an embodiment of the present disclosure, each memory cell can be implemented using a vertical transistor. In addition, a core circuit or a peripheral circuit can be implemented using a horizontal transistor. According to an embodiment, a memory cell can be implemented in a first chip 100 including a vertical channel transistor, and a core circuit or a peripheral circuit can be implemented in a second chip 200 including a horizontal channel transistor. Accordingly, a semiconductor memory device 1000 having a CoP structure can be implemented by joining the first chip 100 and the second chip 200.

[0122] In the following, reference will be made to 9A to 9E Embodiments of a cell array sheet including vertical channel transistors are described in more detail. Fig. 9A is a diagram showing a layout of a cell array sheet 110A according to an embodiment of the present disclosure. Fig. 9B is a diagram showing a method according to an example embodiment Fig. 9A 110A is a perspective view of a cell array sheet 110A. Fig. 9C shows an example embodiment according to the Fig. 9A A cross-sectional view taken along line X1-X1' and line Y1-Y1'.

[0123] refer to 9A to 9C , the cell array sheet 110A may include a substrate 610, a plurality of first conductive lines 620, a channel layer 630, a gate electrode 640, a gate insulating layer 650, and a capacitor structure 680. The cell array sheet 110A may include a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer 630 extends from the substrate 610 in a vertical direction.

[0124] The lower insulating layer 612 may be disposed on the substrate 610, and the plurality of first conductive lines 620 on the lower insulating layer 612 may be spaced apart from each other in the first direction (X direction) and may extend in the second direction (Y direction). A plurality of first insulating patterns 622 may be disposed on the lower insulating layer 612 to fill the spaces between the plurality of first conductive lines 620. The plurality of first insulating patterns 622 may extend in the second direction (Y direction), and the upper surfaces of the plurality of first insulating patterns 622 may be disposed at the same height as the upper surfaces of the plurality of first conductive lines 620. The plurality of first conductive lines 620 may be used as bit lines of the cell array sheet 110A.

[0125] In some embodiments, the plurality of first wires 620 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first wires 620 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. The plurality of first wires 620 may include a single layer or multiple layers of the aforementioned materials. In some embodiments, the plurality of first wires 620 may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0126] The channel layer 630 may be arranged in a matrix form on the plurality of first conductive lines 620 to be spaced apart from each other in a first direction (X direction) and a second direction (Y direction). The channel layer 630 may have a first width in the first direction (X direction) and a first height in the third direction (Z direction). The first height may be greater than the first width. For example, the first height may be about two to ten times the first width, but is not limited thereto. The bottom of the channel layer 630 may be used as a first source / drain region (not shown), the upper portion of the channel layer 630 may be used as a second source / drain region, and the portion of the channel layer 630 between the first source / drain region and the second source / drain region may be used as a channel region (not shown).

[0127] In some embodiments, the channel layer 630 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zny Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O or a combination thereof. The channel layer 630 may include a single layer or a multilayer oxide semiconductor. In some embodiments, the band gap energy of the channel layer 630 may be greater than the band gap energy of silicon. For example, the channel layer 630 may have a band gap energy of about 1.5 eV to about 5.6 eV. For example, when the channel layer 630 has a band gap energy of about 2.0 eV to about 4.0 eV, the channel layer 630 may have optimal channel performance. For example, the channel layer 630 may be polycrystalline or amorphous, but is not limited thereto. In some embodiments, the channel layer 630 may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0128] The gate electrode 640 may extend in a first direction (X direction) on opposite side walls of the channel layer 630. The gate electrode 640 may include a first sub-gate electrode 640P1 facing the first side wall of the channel layer 630 and a second sub-gate electrode 640P2 facing the second side wall of the channel layer 630, the second side wall being away from the first side wall of the channel layer 630. Since one channel layer 630 is disposed between the first sub-gate electrode 640P1 and the second sub-gate electrode 640P2, the unit array sheet 110A may have a dual-gate transistor structure. However, the embodiments of the present disclosure are not limited thereto. The second sub-gate electrode 640P2 may be omitted, and only the first sub-gate electrode 640P1 facing the first side wall of the channel layer 630 may be formed to realize a single-gate transistor structure.

[0129] The gate electrode 640 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrode 640 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0130] The gate insulating layer 650 may surround the sidewall of the channel layer 630 and may be interposed between the channel layer 630 and the gate electrode 640. Fig. 9AAs shown, all sidewalls of the channel layer 630 may be surrounded by the gate insulating layer 650, and a portion of the sidewalls of the gate electrode 640 may be in contact with the gate insulating layer 650. In other embodiments, the gate insulating layer 650 may extend in the extension direction of the gate electrode 640 (i.e., the first direction (X direction)), and only two sidewalls of the channel layer 630 facing the gate electrode 640 may be in contact with the gate insulating layer 650.

[0131] In some embodiments, the gate insulating layer 650 may be formed of a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high-k dielectric film may be made of a metal oxide or a metal oxynitride. For example, the high-k dielectric film that can be used as the gate insulating layer 650 may be made of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 or a combination thereof, but not limited thereto.

[0132] The plurality of second insulating patterns 632 may extend in the second direction (Y direction) on the plurality of first insulating patterns 622, and the channel layer 630 may be disposed between two adjacent second insulating patterns 632 among the plurality of second insulating patterns 632. In addition, between the two adjacent second insulating patterns 632, the first buried layer 634 and the second buried layer 636 may be disposed in the space between the two adjacent channel layers 630. The first buried layer 634 may be disposed at the bottom of the space between the two adjacent channel layers 630, and the second buried layer 636 may be formed on the first buried layer 634 to fill the remaining space between the two adjacent channel layers 630. The upper surface of the second buried layer 636 may be disposed at the same height as the upper surface of the channel layer 630, and the second buried layer 636 may cover the upper surface of the gate electrode 640. Alternatively, the plurality of second insulating patterns 632 may be formed as a material layer continuous with the plurality of first insulating patterns 622, or the second buried layer 636 may be formed as a material layer continuous with the first buried layer 634.

[0133] The capacitor contact 660 may be disposed on the channel layer 630. The capacitor contact 660 may be disposed to overlap vertically with the channel layer 630, and may be arranged in a matrix form, wherein the capacitor contacts 660 are spaced apart from each other in a first direction (X direction) and a second direction (Y direction). The capacitor contact 660 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. An upper insulating layer 662 may be disposed on the plurality of second insulating patterns 632 and the second buried layer 636 to surround the sidewalls of the capacitor contact 660.

[0134] An etch stop layer 670 may be disposed on the upper insulating layer 662, and a capacitor structure 680 may be disposed on the etch stop layer 670. The capacitor structure 680 may include a lower electrode 682, a capacitor dielectric layer 684, and an upper electrode 686.

[0135] The lower electrode 682 may penetrate the etch stop layer 670 and may be electrically connected to the upper surface of the capacitor contact 660. The lower electrode 682 may be formed in a columnar type extending in the third direction (Z direction), but is not limited thereto. In some embodiments, the lower electrode 682 may be arranged to vertically overlap the capacitor contact 660 and may be arranged in a matrix form, wherein the lower electrodes 682 are spaced apart from each other in the first direction (X direction) and the second direction (Y direction). Alternatively, a land pad (not shown) may be additionally provided between the capacitor contact 660 and the lower electrode 682, and the lower electrode 682 may be arranged in a hexagonal shape.

[0136] Fig.9D is a diagram showing a layout of a unit array sheet 110B according to an embodiment of the present disclosure, and Fig.9E is a diagram showing a method according to an example embodiment Fig.9D 110B is a perspective view of a unit array sheet 110B.

[0137] refer to Fig.9D and Fig.9E , the cell array sheet 110B may include a substrate 610A, a plurality of first conductive lines 620A, a channel structure 630A, a contact gate electrode 640A, a plurality of second conductive lines 642A, and a capacitor structure 680. The cell array sheet 110B may include a vertical channel transistor.

[0138] A plurality of active regions AC may be defined on the substrate 610A by the first device isolation film 612A and the second device isolation film 614A. The channel structures 630A may be respectively disposed in the active regions AC. Each channel structure 630A may include a first active pillar 630A1 and a second active pillar 630A2 extending in a vertical direction, and a connecting portion 630L connected to the bottom of the first active pillar 630A1 and the bottom of the second active pillar 630A2. The first source / drain region SD1 may be disposed in the connecting portion 630L, and the second source / drain region SD2 may be disposed at the top of the first active pillar 630A1 and the second active pillar 630A2. Each of the first active pillar 630A1 and the second active pillar 630A2 may constitute an independent unit memory cell.

[0139] A plurality of first conductive lines 620A may extend in a direction intersecting with a plurality of active regions AC (e.g., in the second direction (Y direction)). One first conductive line 620A among the plurality of first conductive lines 620A may be disposed on a connection portion 630L between a first active pillar 630A1 and a second active pillar 630A2. The one first conductive line 620A may be disposed on a first source / drain region SD1. Another first conductive line 620A adjacent to the one first conductive line 620A may be disposed between two channel structures 630A. One first conductive line 620A among the plurality of first conductive lines 620A may be used as a common bit line included in two unit memory cells composed of a first active pillar 630A1 and a second active pillar 630A2 disposed on opposite sides of the one first conductive line 620A.

[0140] A contact gate electrode 640A may be disposed between two channel structures 630A adjacent to each other along the second direction (Y direction). For example, the contact gate electrode 640A may be disposed between a first active pillar 630A1 included in one channel structure 630A and a second active pillar 630A2 included in another channel structure 630A, and may be shared by the first active pillar 630A1 and the second active pillar 630A2 disposed on opposite sides of the contact gate electrode 640A. A gate insulating layer 650A may be disposed between the contact gate electrode 640A and the first active pillar 630A1, and between the contact gate electrode 640A and the second active pillar 630A2. A plurality of second conductive wires 642A may extend in the first direction (X direction) on the upper surface of the contact gate electrode 640A. A plurality of second conductive wires 642A may be used as word lines of the cell array sheet 110B.

[0141] The capacitor contact 660A may be disposed on the channel structure 630A. The capacitor contact 660A may be disposed on the second source / drain region SD2, and the capacitor structure 680 may be disposed on the capacitor contact 660A.

[0142] At the same time, despite 9A to 9E Although not shown in the figure, according to an embodiment of the present disclosure, a plurality of metal layers may be formed under the cell array sheets 110A and 110B.

[0143] Fig. 10A is a schematic plan view showing a portion of a semiconductor memory device 3000 according to an embodiment of the present disclosure, and Fig. 10B is according to an example embodiment and Fig. 10A The cross-sectional view corresponding to the plan view.

[0144] Also refer to Fig. 10A and Fig. 10B , the semiconductor memory device 3000 may include first to fourth cell array sheets 710-1, 710-2, 710-3, and 710-4. In addition, as shown in the figure, the semiconductor memory device 3000 may include first to fifth sub-word line drivers 810-1, 810-2, 810-3, 810-4, and 810-5 disposed below the first to fourth cell array sheets 710-1, 710-2, 710-3, and 710-4.

[0145] The first to fourth cell array sheets 710-1, 710-2, 710-3, and 710-4 may be included in the above-mentioned first chip 100, and the first to fifth sub word line drivers 810-1, 810-2, 810-3, 810-4, and 810-5 may be included in the above-mentioned second chip 200. The first chip 100 and the second chip 200 may have a CoP structure in which the first chip 100 is stacked on the second chip 200. According to an embodiment, the first chip 100 and the second chip 200 may be electrically connected to each other by bonding a first bonding metal 10 formed at the bottom of the first chip 100 with a second bonding metal 20 formed at the top of the second chip 200.

[0146] Each of the first to fourth cell array sheets 710 - 1 , 710 - 2 , 710 - 3 , and 710 - 4 may include an even word line 711 and an odd word line 712 of the corresponding cell array sheet.

[0147] The first to fifth sub-word line drivers 810-1, 810-2, 810-3, 810-4, and 810-5 may generate driving signals applied to the first to fourth cell array pieces 710-1, 710-2, 710-3, and 710-4. The first to fifth sub-word line drivers 810-1, 810-2, 810-3, 810-4, and 810-5 may include, for example, sub-word line drivers 810-1 and 810-5 each responsible for one cell array piece, and sub-word line drivers 810-2, 810-3, and 810-4 each responsible for two adjacent cell array pieces.

[0148] The driving signals generated from the first to fifth sub-word line drivers 810-1, 810-2, 810-3, 810-4, and 810-5 may be transmitted to the first chip 100 through the first bonding metal 10 and the second bonding metal 20. Each driving signal transmitted to the first chip 100 may be transmitted to one of the opposite sides of the corresponding cell array sheet 710-1, 710-2, 710-3, or 710-4 through the lower metal layer 30 of the first chip 100. As shown in the figure, the driving signals transmitted to the cell array sheets 710-1, 710-2, 710-3, and 710-4 may be applied to the word lines 711 and 712 of the first to fourth cell array sheets 710-1, 710-2, 710-3, and 710-4 through the vias 40A.

[0149] In an embodiment, each lower metal layer 30 connected between a corresponding first bonding metal 10 and a corresponding via 40A may have similar patterns to each other to reduce word line load differences.

[0150] In this case, the semiconductor memory device 3000 is similar to the semiconductor memory device 3000 described above. Figure 3A and Figure 3B The semiconductor memory device 50A described is different in that sub word line drivers 810 - 1 , 810 - 2 , 810 - 3 , 810 - 4 , and 810 - 5 are disposed below the cell array sheets 710 - 1 , 710 - 2 , 710 - 3 , and 710 - 4 .

[0151] Although it has been described that the first chip 100 and the second chip 200 forming the CoP structure are electrically connected to each other by bonding, the embodiment is not limited thereto. According to an embodiment of the present disclosure, the first chip 100 and the second chip 200 may be electrically connected to each other by a through silicon via (TSV) method.

[0152] In this case, for example, the driving signal generated by the first sub-word line driver 210-1 or 810-1 of the second chip 200 described above may be transmitted to the first chip 100 through one of a plurality of TSVs formed between the first chip 100 and the second chip 200, and may be applied to the first word line 111 or 711 of the first cell array sheet 110-1 or 710-1 and the second cell array sheet 110-2 or 710-2. In addition, the driving signal generated by the second sub-word line driver 210-2 or 810-2 may be transmitted to the first chip 100 through another TSV formed between the first chip 100 and the second chip 200, and may be applied to the second word line 112 or 712 of the first cell array sheet 110-1 or 710-1 and the second cell array sheet 110-2 or 710-2.

[0153] Although it has been described that two chips (i.e., the first chip 100 and the second chip 200) form a CoP structure, the embodiment is not limited thereto. In an example embodiment, three or more chips may be stacked to implement a semiconductor memory device having a CoP structure. In particular, according to an embodiment of the present disclosure, at least one chip in which a memory cell array is implemented and at least one chip in which a core / peripheral circuit is implemented may be stacked to implement a semiconductor memory device having a CoP structure.

[0154] According to the various embodiments of the present disclosure described above, the sub word line driver may be appropriately arranged, and thus, the characteristics of the semiconductor memory device may be improved.

[0155] According to various embodiments of the present disclosure described above, the performance of a semiconductor memory device may be improved by properly arranging sub word line drivers.

[0156] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: A first chip includes a first cell array sheet and a second cell array sheet adjacent to the first cell array sheet, wherein each of the first cell array sheet and the second cell array sheet includes a first word line and a second word line; as well as A second chip forms a stacked structure with the first chip, and the second chip includes: a first sub word line driver configured to generate a first driving signal applied to the first word line from one side of each of the first cell array sheet and the second cell array sheet, and The second sub word line driver is configured to generate a second driving signal applied to the second word line from another side of each of the first cell array sheet and the second cell array sheet opposite to the one side.

2. The semiconductor memory device according to claim 1, wherein: The second chip is disposed below the first chip, and The first sub-word line driver and the second sub-word line driver are respectively located under the first cell array sheet and the second cell array sheet.

3. The semiconductor memory device according to claim 2, wherein: The first sub word line driver is provided in a portion of a region of the second chip configured to overlap a region where the first cell array sheet is formed, and The second sub-word line driver is disposed in a portion of a region of the second chip that is configured to overlap a region where the second cell array sheet is formed.

4. The semiconductor memory device according to claim 2, wherein: The first chip and the second chip are electrically connected to each other by bonding a first bonding metal formed at a bottom of the first chip with a second bonding metal formed at a top of the second chip, and The first driving signal and the second driving signal are transmitted to the first chip through the first bonding metal and the second bonding metal.

5. The semiconductor memory device according to claim 4, wherein: The material of the first bonding metal and the second bonding metal includes copper.

6. The semiconductor memory device according to claim 1, wherein The first driving signal is applied to the first word lines of the first cell array sheet and the second cell array sheet through via holes formed on the one side and the other side of the first cell array sheet, and The second driving signal is applied to the second word lines of the first cell array cell and the second cell array cell through via holes formed on the one side and the other side of the second cell array cell.

7. The semiconductor memory device according to claim 6, wherein: The first chip further includes a plurality of metal layers formed below the first cell array sheet and the second cell array sheet, and The first driving signal and the second driving signal are transmitted to the via holes formed on the one side and the other side of the first unit array sheet and the second unit array sheet through one metal layer among the plurality of metal layers.

8. The semiconductor memory device according to claim 7, wherein: The plurality of metal layers include a copper layer and a tungsten layer, and The first driving signal and the second driving signal are transmitted through the tungsten layer to the via holes formed on the one side and the other side of the first cell array sheet and the second cell array sheet.

9. The semiconductor memory device according to claim 1, wherein: Each of the first cell array sheet and the second cell array sheet includes a plurality of memory cells, the plurality of memory cells being arranged in a region where the first word line and the second word line intersect a plurality of bit lines, and Wherein, each of the plurality of memory cells comprises a vertical channel transistor.

10. The semiconductor memory device according to claim 9, wherein: Each of the first sub word line driver and the second sub word line driver includes one or more horizontal channel transistors.

11. The semiconductor memory device according to claim 1, wherein: The first word lines and the second word lines are alternately arranged in each of the first cell array sheet and the second cell array sheet.

12. The semiconductor memory device according to claim 1, wherein: The first chip includes a plurality of unit array sheets in which the first unit array sheet and the second unit array sheet are repeated, wherein the second chip includes a plurality of sub-word line drivers in which the first sub-word line driver and the second sub-word line driver are repeated, and The plurality of sub-word line drivers have the same driving strength.

13. The semiconductor memory device according to claim 12, wherein: The plurality of sub word line drivers have the same word line load.

14. A semiconductor memory device comprising: A plurality of cell array chips are implemented in the first chip, each cell array chip including a plurality of word lines; as well as a plurality of sub-word line drivers, which are implemented in a second chip forming a stacked structure with the first chip and are arranged to correspond to the plurality of cell array chips respectively, wherein the plurality of sub-word line drivers are configured to generate driving signals applied to the plurality of word lines of the plurality of cell array sheets, The first driving signal in the driving signals is applied to the even word lines among the plurality of word lines from one side of the corresponding cell array sheet, and The second driving signal among the driving signals is applied to odd word lines among the plurality of word lines from the other side of the corresponding unit array sheet opposite to the one side.

15. The semiconductor memory device according to claim 14, wherein: The second chip is disposed below the first chip, and Wherein, the plurality of sub-word line drivers are respectively located under the plurality of cell array sheets.

16. The semiconductor memory device according to claim 14, wherein: The plurality of sub-word line drivers include: a first sub word line driver configured to generate the first driving signal applied to the even word line, and The second sub word line driver is configured to generate the second driving signal applied to the odd word line.

17. The semiconductor memory device according to claim 16, wherein: The plurality of unit array sheets include a first unit array sheet and a second unit array sheet adjacent to each other, and The first sub-word line driver and the second sub-word line driver are respectively arranged under the first cell array sheet and the second cell array sheet.

18. The semiconductor memory device according to claim 17, wherein: Each of the plurality of cell array sheets includes the even word line and the odd word line, wherein the first driving signal is transmitted to the one side and the other side of the first unit array sheet, and The second driving signal is transmitted to the one side and the other side of the second unit array sheet.

19. The semiconductor memory device according to claim 18, wherein: The plurality of unit array sheets further include a third unit array sheet adjacent to the second unit array sheet and a fourth unit array sheet adjacent to the third unit array sheet, The plurality of sub-word line drivers further include a third sub-word line driver configured to generate a third drive signal applied to the even word lines of the third cell array sheet and the fourth cell array sheet, and a fourth sub-word line driver configured to generate a fourth drive signal applied to the odd word lines of the third cell array sheet and the fourth cell array sheet, The third sub-word line driver and the fourth sub-word line driver are respectively arranged under the third cell array sheet and the fourth cell array sheet, The third driving signal is transmitted to two opposite sides of the third unit array sheet. The fourth driving signal is transmitted to two opposite sides of the fourth unit array sheet, and Among them, the first sub-word line driver and the third sub-word line driver are configured to generate the first drive signal and the third drive signal in response to a first row address, and the second sub-word line driver and the fourth sub-word line driver are configured to generate the second drive signal and the fourth drive signal in response to a second row address.

20. A semiconductor memory device having a peripheral upper cell CoP structure, the semiconductor memory device comprising: A first chip includes a plurality of cell array chips, each of which includes a plurality of word lines; as well as The second chip includes a plurality of sub-word line drivers respectively arranged under the plurality of cell array chips, wherein the plurality of sub-word line drivers are configured to generate driving signals, The plurality of word lines include even word lines and odd word lines, a first drive signal among the drive signals is applied to the even word lines from one side of the corresponding cell array sheet, a second drive signal among the drive signals is applied to the odd word lines from another side of the corresponding cell array sheet opposite to the one side, and Among them, the multiple sub-word line drivers include a first sub-word line driver and a second sub-word line driver corresponding to two adjacent cell array pieces, and the first sub-word line driver and the second sub-word line driver are configured to respectively generate the first drive signal applied to the even word lines of the two adjacent cell array pieces and the second drive signal applied to the odd word lines of the two adjacent cell array pieces.

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