Macro construction method and device for back-end compatible capacitance-free DRAM storage circuit

Abstract

The invention relates to a post-channel compatible non-capacitance DRAM (Dynamic Random Access Memory) storage circuit macro construction method and device, and the method comprises the steps: constructing a multi-layer non-capacitance DRAM storage circuit macro according to a full-post-channel compatible channel material meeting a preset preparation requirement; constructing a peripheral circuit based on a back-end compatible vertical complementary field effect transistor; and according to each layer of capacitance-free DRAM storage circuit macro and the corresponding peripheral circuit, constructing multiple layers of complete back-channel compatible capacitance-free DRAM storage circuit macro, and based on the interlayer via holes, stacking the multiple layers of complete back-channel compatible capacitance-free DRAM storage circuit macro on the target silicon-based circuit so as to obtain a monolithic three-dimensional integrated full back-channel compatible capacitance-free DRAM storage circuit macro. Therefore, the problems that the overall storage holding time is short, refreshing is frequent, power consumption is high and practical application is not facilitated due to high electric leakage of a silicon transistor in a capacitance-free DRAM storage circuit macro based on a silicon-based chip manufacturing process at present, and the occupied area of a storage peripheral circuit in the whole circuit macro is large are solved.

Description

Technical Field

[0001] The present application relates to the technical field of capacitor-less DRAM storage devices, and in particular to a method and device for constructing a back-end compatible capacitor-less DRAM storage circuit macro. Background Art

[0002] Traditional dynamic random access memory (DRAM) technology uses one transistor and one capacitor (1Transistor 1Capacitor, 1T1C) to store one bit of information. The transistor switch is used to control the reading and writing of information, while the capacitor is used to store information. Currently, as the device continues to shrink, it poses increasing challenges to the process and reliability.

[0003] 2T0C DRAM is composed of two transistors, and does not require additional capacitors to store information. The charge is stored on the gate capacitance of the read transistor. However, the charge retention time of traditional silicon-based 2T0C DRAM is always low because the turn-off current of the write transistor is relatively high and the gate capacitance of the read transistor is relatively small compared to traditional capacitors. This has become the biggest factor limiting its application.

[0004] The 2T0C DRAM memory cell made of oxide semiconductors represented by IGZO makes it possible to achieve effective storage under small-size conditions. Compared with traditional silicon-based devices, thin-film transistors made based on such oxide semiconductors have extremely low leakage. Therefore, the retention time of small-size 2T0C devices will increase by an order of magnitude compared to silicon devices, meeting the requirements for data caching.

[0005] CMOS (Complementary Metal Oxide Semiconductor) technology builds a low-static power and high-efficiency circuit system by integrating NMOS and PMOS transistors on the same silicon wafer. Designs based on planar CMOS technology are currently widely used in a variety of scenarios and are the core of various processors, application-specific integrated circuits, and memory peripheral circuits.

[0006] However, with the continuous evolution of integrated circuit technology, the size of transistors continues to shrink, and the distance between the source and the drain becomes shorter and shorter, resulting in various non-ideal effects such as the short channel effect. The gate of the transistor's ability to control the current continues to weaken, leakage increases, and power consumption increases. However, the planar NMOS and PMOS still need to continue to shrink in size to ensure the increase in integrated circuit density and the improvement of the overall chip computing power. To this end, people have developed many solutions for high-density integration of transistors, such as FinFET and GAAFET. However, in the manufacturing process of traditional silicon-based semiconductor transistors, the type and distribution of doped atoms need to be used to achieve the desired electronic properties. However, due to the diffusion of doped atoms at a certain temperature, planar CMOS needs to isolate PMOS and NMOS in space, resulting in a waste of chip area.

[0007] In response to the above problems, the emergence of vertical complementary field effect transistors (CFETs) provides a new solution. CFET stacks P-type and N-type field effect transistors in the vertical direction so that the two share a gate electrode as a signal input, while the drain is connected as a signal output, and the two sources are grounded and powered respectively. This design allows the size of NFET and PFET to be adjusted according to performance requirements, and the channels of NFET and PFET can use different semiconductor materials to achieve mobility matching, thereby increasing the drive current. In addition, the vertical stacking structure helps to reduce device size and improve chip integration.

[0008] In addition to the most important storage unit 2T0C DRAM, the capacitor-free DRAM storage circuit macro also needs to design circuit modules for storage address selection, row and column signal driving, sensitive amplification, data write-back, data buffering, data pre-charging, etc., in order to realize the functions of a complete storage circuit macro. These circuit modules occupy part of the area of ​​the storage circuit macro.

[0009] Among them, the storage address selection module is mainly implemented by row and column decoders, using smaller address information to select the corresponding storage unit in a larger array for operation. The row and column signal driving circuit is mainly dominated by the inverter structure, and its main purpose is to enhance the corresponding signal and ensure that each storage unit receives the signal correctly. Since the stored data will leak over time, it is necessary to set up a data write-back module to connect the read-out interface of the sensitive amplifier and write it back to the storage unit to ensure that the stored data is correct and complete. This operation is also called refresh. In addition, supplementary modules such as buffering and pre-charging are also required to ensure the effective writing and reading of stored data.

[0010] It is worth noting that for the capacitor-free DRAM storage circuit macro, it has separate write and read circuits. Unlike the traditional 1T1C DRAM, it uses a transistor to open the write data to the capacitor, and then opens the same transistor to read the data from the capacitor to the bit line, so that the charge on the bit line changes, which is reflected as a change in voltage. Capacitor-free DRAM (2T0C) stores data on the gate dielectric of the read transistor by opening the write transistor; when reading, the charge stored on the gate capacitor is read out in the form of current by adjusting the voltage on both sides of the source and drain of the read transistor. Therefore, for the storage circuit macro of capacitor-free DRAM, the sensitive amplifier needs to use a current-type sensitive amplifier, which is different from the voltage-type sensitive amplifier of the traditional 1T1C DRAM.

[0011] Capacitor-free DRAM memory macros consist of only two transistors and do not require additional capacitor processes, so in theory, the process manufacturing can be compatible with the logic process, but its disadvantages are also obvious:

[0012] 1. Due to the high leakage of silicon transistors, the macro storage retention time of this circuit is short;

[0013] 2. Because the retention time is short, data needs to be refreshed and written back multiple times, resulting in higher power consumption of the overall storage circuit macro.

[0014] The preparation of traditional silicon-based integrated circuit semiconductor processes requires many process steps. For traditional silicon-based processes, after completing the preparation of a layer of transistors, it is difficult to prepare a second layer of devices on top of it, otherwise it will have a huge impact on the overall performance of the chip. Therefore, existing traditional silicon-based semiconductor integrated circuits are basically based on planes, with long data paths, and more speed and power consumption are lost in the data paths. Therefore, if a new layer of transistors needs to be integrated on an existing traditional silicon integrated circuit, the temperature of these transistor processes is crucial. At this stage, channel materials such as oxide semiconductors (IGZO, ITO, IWO, TeOx) and carbon nanotubes have the characteristics of low preparation temperatures and can be used for further transistor preparation above silicon transistors without damaging the silicon transistors in the previous process.

[0015] The monolithic three-dimensional integration technology refers to the technology of integrating multiple layers of transistors in the same chip by vertical stacking. The main advantages of this technology are two: first, it can be compatible with the back-end process steps in terms of temperature. The semiconductor process is divided into the front-end and the back-end. The front-end generally refers to the preparation of silicon transistors, which has a higher temperature; and the back-end refers to the process steps with lower temperatures after the transistors are made, such as metal interconnection. Nowadays, the process temperatures of some new storage and computing devices and new materials are compatible with the back-end, so they can be stacked vertically on a single chip. The second advantage is that it greatly reduces the chip area. Because the vertical stacking of devices and arrays is adopted, the data path between layers is shorter, which can greatly improve the data transmission bandwidth, improve the chip speed and integration. Of course, it should be noted here that, unlike the millimeter-diameter through-silicon via (TSV) process in the "three-dimensional integration technology" at the packaging level, the monolithic three-dimensional integration process does not require multi-layer silicon wafers to be punched and interconnected, but uses inter-layer vias (ILV) of hundreds of nanometers, that is, the interconnection between insulating layers such as oxide layers is used in a set of process flows, rather than the interconnection between silicon. This technology achieves high-bandwidth interconnection of multiple functional layers of devices on a single silicon wafer, which can improve the efficiency of data exchange.

[0016] In summary, the current capacitor-free DRAM storage circuit macro based on silicon-based chip manufacturing process has a short overall storage retention time, frequent refresh, and high power consumption due to the high leakage of silicon transistors, which is not conducive to its practical application. In addition, the storage peripheral circuit occupies a large area in the entire circuit macro, which needs to be solved urgently. Summary of the invention

[0017] The present application provides a method and device for constructing a back-end compatible capacitor-free DRAM storage circuit macro to solve the problems that the current capacitor-free DRAM storage circuit macro based on silicon-based chip manufacturing process has a short overall storage retention time, frequent refresh, and high power consumption due to the high leakage of silicon transistors, which is not conducive to its practical application, and the storage peripheral circuit occupies a large area in the entire circuit macro.

[0018] The first aspect of the present application provides a method for constructing a back-end compatible capacitor-free DRAM storage circuit macro, comprising the following steps: determining a fully back-end compatible channel material that meets preset preparation requirements, and using the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro; based on preset back-end compatible vertical complementary field effect transistors, constructing a peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro; constructing a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, and based on inter-layer vias, allowing the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro to perform a multi-layer stacking operation on a target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0019] Optionally, in one embodiment of the present application, determining a fully back-end compatible channel material that meets preset preparation requirements and constructing a multi-layer capacitor-free DRAM storage circuit macro using the fully back-end compatible channel material includes: determining an N-type channel material and a P-type channel material in the fully back-end compatible channel material based on preset leakage, mobility and preparation temperature requirements of the oxide semiconductor; preparing the N-type channel material and the P-type channel material according to a preset deposition method, and constructing the multi-layer capacitor-free DRAM storage circuit macro using the N-type channel material and the P-type channel material.

[0020] Optionally, in one embodiment of the present application, the peripheral circuit corresponding to each layer of capacitor-less DRAM storage circuit macro in the multi-layer capacitor-less DRAM storage circuit macro is constructed based on the preset back-end compatible vertical complementary field effect transistor, including: determining the storage circuit area of ​​each layer of capacitor-less DRAM storage circuit macro, and determining the circuit area of ​​the peripheral circuit corresponding to each layer of capacitor-less DRAM storage circuit macro according to the storage circuit area; constructing the circuit topology structure of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field effect transistor; constructing the peripheral circuit corresponding to each layer of capacitor-less DRAM storage circuit macro according to the circuit area and the circuit topology structure of the peripheral circuit, wherein the peripheral circuit includes at least one of a storage address selection circuit, a row and column signal driving circuit, a sensitive amplifier circuit, a data write-back circuit, a data buffer circuit and a data pre-charging circuit.

[0021] Optionally, in one embodiment of the present application, based on the inter-layer vias, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro, including: based on the inter-layer vias corresponding to the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain the monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0022] The second aspect of the present application provides a back-end compatible capacitor-free DRAM storage circuit macro construction device, including: a first construction module, used to determine a fully back-end compatible channel material that meets preset preparation requirements, and use the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro; a second construction module, used to construct a peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro based on preset back-end compatible vertical complementary field effect transistors; a stacking module, used to construct a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, and based on inter-layer vias, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0023] Optionally, in one embodiment of the present application, the first building module includes: a first determination unit, used to determine the N-type channel material and the P-type channel material in the fully back-end compatible channel material based on the preset leakage, mobility and preparation temperature requirements of the oxide semiconductor; a first establishment unit, used to prepare the N-type channel material and the P-type channel material according to a preset deposition method, and construct the multi-layer capacitor-free DRAM storage circuit macro through the N-type channel material and the P-type channel material.

[0024] Optionally, in one embodiment of the present application, the second building module includes: a second determination unit, used to determine the storage circuit area of ​​each layer of the capacitor-less DRAM storage circuit macro, and determine the circuit area of ​​the peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro based on the storage circuit area; a second establishment unit, used to construct the circuit topology structure of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field effect transistor; a third establishment unit, used to construct the peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro based on the circuit area of ​​the peripheral circuit and the circuit topology structure, wherein the peripheral circuit includes at least one of a storage address selection circuit, a row and column signal driving circuit, a sensitive amplifier circuit, a data write-back circuit, a data buffer circuit and a data pre-charge circuit.

[0025] Optionally, in one embodiment of the present application, the stacking module includes: a three-dimensional integrated unit, which is used to stack the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macros on the target silicon-based circuit based on the inter-layer vias corresponding to the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macros to obtain the monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0026] The third aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the back-end compatible capacitor-less DRAM storage circuit macro construction method as described in the above embodiment.

[0027] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, which, when executed by a processor, implements the above-mentioned back-end compatible capacitor-free DRAM storage circuit macro construction method.

[0028] The fifth aspect of the present application provides a computer program product, including a computer program, which is executed to implement the above-mentioned back-end compatible capacitor-free DRAM storage circuit macro construction method.

[0029] Therefore, the embodiments of the present application have the following beneficial effects:

[0030] The embodiments of the present application can be implemented by determining a fully back-end compatible channel material that meets the preset preparation requirements, and using the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro; based on the preset back-end compatible vertical complementary field effect transistor, the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro is constructed; according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is constructed, and based on the inter-layer via, a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro. The capacitor-free DRAM storage circuit macro of the present application has the characteristics of long retention time, low refresh frequency, low power consumption, and can be stacked in multiple layers to prepare high-density storage; in addition, the peripheral circuit of the present application adopts the vertical complementary field effect transistor CFET process, so that the area of ​​the peripheral circuit can be further compressed, making the storage circuit macro more compact, which is conducive to the high-density integration of future storage. This solves the problems of the current capacitor-free DRAM storage circuit macro based on the silicon-based chip manufacturing process, such as the high leakage current of silicon transistors, resulting in a short overall storage retention time, frequent refreshes, and high power consumption, which is not conducive to its practical application, and the storage peripheral circuit occupies a large area in the entire circuit macro.

[0031] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0033] Figure 1 A flowchart of a method for constructing a back-end compatible capacitor-free DRAM storage circuit macro according to an embodiment of the present application;

[0034] Figure 2 A macro schematic diagram of a capacitor-free DRAM storage circuit provided for one embodiment of the present application;

[0035] Figure 3 A schematic diagram of a multi-layer stackable back-end capacitor-free DRAM storage circuit macro provided for one embodiment of the present application;

[0036] Figure 4 A schematic diagram comparing a planar CMOS and a vertical CFET of a back-end device provided in one embodiment of the present application;

[0037] Figure 5A schematic diagram of macro area optimization of an overall capacitor-free DRAM storage circuit provided for one embodiment of the present application;

[0038] Figure 6 A schematic diagram of a NOT, NAND, or NOT circuit topology structure based on vertical complementary field effect transistors provided in one embodiment of the present application;

[0039] Figure 7 An exemplary diagram of a back-end compatible capacitor-free DRAM storage circuit macro construction device according to an embodiment of the present application;

[0040] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0041] Among them, 10 is a back-end compatible capacitor-free DRAM storage circuit macro construction device; 100 is a first construction module, 200 is a second construction module, 300 is a stacking module; 801 is a memory, 802 is a processor, and 803 is a communication interface. DETAILED DESCRIPTION

[0042] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0043] The following describes the back-end compatible capacitor-free DRAM storage circuit macro construction method and device of the embodiment of the present application with reference to the accompanying drawings. In view of the problems mentioned in the above background technology, the present application provides a back-end compatible capacitor-free DRAM storage circuit macro construction method, in which a multi-layer capacitor-free DRAM storage circuit macro is constructed by determining a fully back-end compatible channel material that meets the preset preparation requirements, and using the fully back-end compatible channel material; based on the preset back-end compatible vertical complementary field effect transistor, the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro is constructed; according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is constructed, and based on the inter-layer vias, a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro. The capacitor-free DRAM storage circuit macro of the present application has the characteristics of long retention time, low refresh frequency, low power consumption, and can be stacked in multiple layers to prepare high-density storage; in addition, the peripheral circuit of the present application adopts the vertical complementary field effect transistor CFET process, so that the area of ​​the peripheral circuit can be further compressed, making the storage circuit macro more compact, which is conducive to the high-density integration of future storage. Thus, the current capacitor-free DRAM storage circuit macro based on silicon-based chip manufacturing process solves the problems that the overall storage retention time is short, the refresh is frequent, the power consumption is high, which is not conducive to its practical application, and the storage peripheral circuit occupies a large area in the entire circuit macro due to the high leakage of silicon transistors.

[0044] Specifically, Figure 1 A flowchart of a method for constructing a back-end compatible capacitor-less DRAM storage circuit macro provided in an embodiment of the present application.

[0045] like Figure 1 As shown, the back-end compatible capacitor-free DRAM storage circuit macro construction method includes the following steps:

[0046] In step S101, a fully back-end compatible channel material that meets preset manufacturing requirements is determined, and a multi-layer capacitor-free DRAM storage circuit macro is constructed using the fully back-end compatible channel material.

[0047] The embodiments of the present application can first determine the fully back-end compatible channel material that meets the preset preparation requirements (such as low leakage, large-scale uniform preparation, high mobility, etc.), and then use the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro.

[0048] Optionally, in one embodiment of the present application, a fully back-end compatible channel material that meets preset preparation requirements is determined, and a multi-layer capacitor-free DRAM storage circuit macro is constructed using the fully back-end compatible channel material, including: determining N-type channel materials and P-type channel materials in the fully back-end compatible channel material based on preset leakage, mobility and preparation temperature requirements of the oxide semiconductor; preparing N-type channel materials and P-type channel materials according to a preset deposition method, and constructing a multi-layer capacitor-free DRAM storage circuit macro using the N-type channel material and the P-type channel material.

[0049] It should be noted that the main feature of the capacitor-free DRAM storage circuit macro in the embodiment of the present application is that the entire capacitor-free DRAM storage circuit macro is made of all post-compatible materials. Among them, as a capacitor-free DRAM write transistor, it is necessary to meet the low leakage requirement, so that the retention time can be effectively delayed; the write tube and the read tube are preferably both high in mobility to ensure the write and read speeds.

[0050] In the actual implementation process, the embodiment of the present application can be used for storage cells, with N transistors as write transistors and P transistors as read transistors. The requirements for N-type channel materials are low leakage, large-scale uniform preparation, and high mobility; the requirements for P-type channel materials are large-scale uniform preparation and good mobility; and both N-type and P-type channel materials need to have a low preparation temperature, generally at least below 500 degrees, which is roughly close to the process temperature of the back-end interconnection process, and is a "back-end process compatible" material.

[0051] For N-type transistors, the embodiments of the present application may use oxide semiconductor materials such as IGZO, which are characterized by leakage several orders of magnitude lower than silicon-based transistors and lower preparation temperature; for P-type transistors, P-type oxides such as TeOx are used. Both of the above-mentioned two oxide semiconductor-based channel materials can be prepared at low temperature and on a large scale, and can be prepared by deposition methods such as atomic layer deposition ALD and physical vapor deposition PVD.

[0052] It should be noted that those skilled in the art should understand that for capacitor-free DRAM, the write tube requires low leakage. Currently, N-type back-end channel materials show relatively low leakage characteristics. N-type channel materials can use any low leakage, back-end fabricable, and uniform material, such as IWO, ITO and other oxide semiconductor materials in addition to IGZO; and P-type channel materials can use any back-end fabricable, large-scale fabricable, and uniform material, such as SnO and other P-type oxide semiconductor materials, P-type two-dimensional materials, P-type carbon nanotubes, etc. in addition to TeOx. However, if the later P-type back-end channel material shows low leakage characteristics, the write tube can be replaced with a P-type channel material, and the additional requirement for the P-type channel material is low leakage.

[0053] Therefore, the storage circuit macro prepared based on the above materials can effectively realize multi-layer stacking on the silicon-based circuit without excessively affecting the performance of the silicon-based circuit underneath.

[0054] In step S102, based on the preset back-end compatible vertical complementary field effect transistor, a peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro in the multi-layer capacitor-less DRAM storage circuit macro is constructed.

[0055] Furthermore, the embodiments of the present application also need to utilize back-end compatible vertical complementary field effect transistors to construct peripheral circuits corresponding to each layer of capacitor-free DRAM storage circuit macros.

[0056] Optionally, in one embodiment of the present application, based on preset back-end compatible vertical complementary field effect transistors, a peripheral circuit corresponding to each layer of capacitor-less DRAM storage circuit macro in a multi-layer capacitor-less DRAM storage circuit macro is constructed, including: determining the storage circuit area of ​​each layer of capacitor-less DRAM storage circuit macro, and determining the circuit area of ​​the peripheral circuit corresponding to each layer of capacitor-less DRAM storage circuit macro according to the storage circuit area; constructing a circuit topology structure of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field effect transistors; constructing a peripheral circuit corresponding to each layer of capacitor-less DRAM storage circuit macro according to the circuit area and circuit topology structure of the peripheral circuit, wherein the peripheral circuit includes at least one of a storage address selection circuit, a row and column signal driving circuit, a sensitive amplifier circuit, a data write-back circuit, a data buffer circuit, and a data pre-charging circuit.

[0057] It should be noted that the peripheral circuit design of the specific back-end compatible capacitor-less DRAM storage circuit macro in the embodiment of the present application is relatively close to the capacitor-less DRAM storage circuit macro based on silicon-based CMOS.

[0058] Specifically, the peripheral circuits in the embodiments of the present application mainly include circuit modules such as storage address selection, row and column signal driving, sensitive amplification, data write back, data buffering, and data pre-charging. Figure 2 As shown. Among them, the storage address selection module is mainly implemented by row and column decoders, and uses smaller address information to select the corresponding storage unit in a larger array for operation; the row and column signal driving circuit is mainly dominated by the inverter structure, and the main purpose is to enhance the corresponding signal to ensure that each storage unit receives the signal correctly; the sensitive amplifier needs to use a current-type sensitive amplifier; because the stored data will leak over time, it is necessary to set a data write-back module to connect the read interface of the sensitive amplifier and write it back to the storage unit to ensure that the stored data is correct and complete. This operation can also be called refresh. In addition, the embodiments of the present application also require supplementary modules such as buffering and pre-charging during the actual execution process to ensure the effective writing and reading of stored data.

[0059] It should be noted that Figure 3 A schematic diagram of a multi-layer stackable back-end capacitor-free DRAM storage circuit macro, in which both the storage array and the peripheral circuit must be prepared using a back-end compatible process.

[0060] As an achievable method, the embodiment of the present application can use a back-end compatible vertical complementary field effect transistor CFET to implement the design part of the peripheral circuit of the capacitor-free DRAM storage circuit macro, such as Figure 4 As shown in the figure, compared with the traditional CMOS process design, it can complete the preparation of N-type transistors and P-type transistors within the unit area of ​​one transistor. The peripheral circuit occupies a certain area in the capacitor-free DRAM storage circuit macro, and its area ratio depends on the size of the storage array; although the area of ​​the storage peripheral circuit will increase with the area of ​​the storage array, its growth rate is not as fast as the array area. When the storage array reaches 8Mbit, the peripheral circuit is about 30% of the overall storage circuit macro area. Therefore, vertical complementary field effect transistors can reduce the area of ​​the peripheral circuit by nearly half, as shown in Figure 1. Figure 5 As shown, it is beneficial to the area optimization of the overall storage circuit macro.

[0061] It can be understood that, unlike the traditional planar CMOS circuit design, in the embodiments of the present application, when vertical complementary field effect transistors are used for circuit design, their vertical complementary characteristics can also be applied to design corresponding NOT gates, NAND gates, and NOR gate circuit topologies, which saves area while also saving a certain amount of wiring. Figure 6 The NOT, NAND, and NOR circuit topologies based on vertical complementary field-effect transistors are demonstrated. Figure 6 As shown in the figure, it shows its unique construction method. Therefore, based on the designed logic gates, peripheral circuit modules with multiple functions can be further constructed.

[0062] To summarize, the peripheral circuit portion of the circuit macro in the embodiment of the present application is prepared by a vertical complementary field effect transistor process. Compared with the silicon-based capacitor-free DRAM storage circuit macro that uses a low-leakage oxide semiconductor as a write tube, the embodiment of the present application has the characteristics of long retention time, low refresh frequency, low power consumption, and can be stacked in multiple layers to prepare high-density storage; and the peripheral circuit adopts a vertical complementary field effect transistor CFET process, which can further compress the area of ​​the peripheral circuit, making the storage circuit macro more compact, which is conducive to high-density integration of future storage.

[0063] In step S103, multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros are constructed according to each layer of capacitor-free DRAM storage circuit macros and the corresponding peripheral circuits, and based on inter-layer vias, multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros are stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0064] Afterwards, the embodiment of the present application can construct multiple layers of complete back-end compatible capacitor-less DRAM storage circuit macros through each layer of capacitor-less DRAM storage circuit macros and the corresponding peripheral circuits, and stack multiple layers of complete back-end compatible capacitor-less DRAM storage circuit macros on the target silicon-based circuit through inter-layer vias, thereby obtaining a monolithic three-dimensionally integrated fully back-end compatible capacitor-less DRAM storage circuit macro.

[0065] Optionally, in one embodiment of the present application, based on interlayer vias, multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros are stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro, including: based on interlayer vias corresponding to the multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros, multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros are stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0066] It is understandable that at present, there are some problems with the capacitor-free DRAM storage circuit macro based on the silicon-based chip manufacturing process. The main problem is that the leakage of silicon transistors is relatively high, resulting in a short overall storage retention time, requiring frequent refreshes, and high power consumption. It is not suitable for practical applications, and the storage circuit macro based on silicon cannot achieve multi-layer stacking in the back-end.

[0067] Therefore, the embodiment of the present application utilizes the inter-layer vias corresponding to the multiple layers of complete back-end compatible capacitor-less DRAM storage circuit macros to stack multiple layers of complete back-end compatible capacitor-less DRAM storage circuit macros on the target silicon-based circuit, thereby obtaining a monolithic three-dimensionally integrated fully back-end compatible capacitor-less DRAM storage circuit macro.

[0068] It should be noted that the embodiments of the present application mainly use 2T0C capacitor-less DRAM as the basis for demonstration. In addition, capacitor-less DRAM also exists in the forms of 2T0C, 3T0C, 4T0C, etc. Although their cell structures and operation programming schemes are somewhat different from the embodiments of the present application, the CFET-prepared capacitor-less DRAM storage peripheral circuit and the fully back-end integrated capacitor-less DRAM storage circuit of the embodiments of the present application can be well applied to different capacitor-less DRAM storage cell structures.

[0069] According to the back-end compatible capacitor-free DRAM storage circuit macro construction method proposed in the embodiment of the present application, by determining the fully back-end compatible channel material that meets the preset preparation requirements, and using the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro; based on the preset back-end compatible vertical complementary field effect transistor, the corresponding peripheral circuit of each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro is constructed; according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is constructed, and based on the inter-layer via, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro. The capacitor-free DRAM storage circuit macro of the present application has the characteristics of long retention time, low refresh frequency, low power consumption, and can be stacked in multiple layers to prepare high-density storage; in addition, the peripheral circuit of the present application adopts the vertical complementary field effect transistor CFET process, so that the area of ​​the peripheral circuit can be further compressed, making the storage circuit macro more compact, which is conducive to the high-density integration of future storage.

[0070] Secondly, a back-end compatible capacitor-less DRAM storage circuit macro construction device proposed according to an embodiment of the present application is described with reference to the accompanying drawings.

[0071] Figure 7 It is a block diagram of a back-end compatible capacitor-less DRAM storage circuit macro construction device according to an embodiment of the present application.

[0072] like Figure 7 As shown, the back-end compatible capacitor-free DRAM storage circuit macro construction device 10 includes: a first construction module 100 , a second construction module 200 and a stacking module 300 .

[0073] Among them, the first construction module 100 is used to determine a fully back-end compatible channel material that meets preset preparation requirements, and use the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro.

[0074] The second construction module 200 is used to construct a peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro in the multi-layer capacitor-less DRAM storage circuit macro based on a preset back-end compatible vertical complementary field effect transistor.

[0075] The stacking module 300 is used to construct multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros according to each layer of capacitor-free DRAM storage circuit macros and corresponding peripheral circuits, and based on inter-layer vias, multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros are stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0076] Optionally, in one embodiment of the present application, the first building module 100 includes: a first determining unit and a first establishing unit.

[0077] Among them, the first determination unit is used to determine the N-type channel material and the P-type channel material in the full back-end compatible channel material based on the preset leakage, mobility and preparation temperature requirements of the oxide semiconductor.

[0078] The first establishing unit is used to prepare the N-type channel material and the P-type channel material according to a preset deposition method, and construct the multi-layer capacitor-free DRAM storage circuit macro by using the N-type channel material and the P-type channel material.

[0079] Optionally, in one embodiment of the present application, the second building module 200 includes: a second determining unit, a second establishing unit and a third establishing unit.

[0080] The second determining unit is used to determine the storage circuit area of ​​each layer of the capacitor-less DRAM storage circuit macro, and determine the circuit area of ​​the peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro according to the storage circuit area.

[0081] The second establishing unit is used to construct a circuit topology structure of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field effect transistor.

[0082] The third establishing unit is used to construct the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro according to the circuit area of ​​the peripheral circuit and the circuit topology structure, wherein the peripheral circuit includes at least one of a storage address selection circuit, a row and column signal driving circuit, a sensitive amplifier circuit, a data write back circuit, a data buffer circuit and a data precharge circuit.

[0083] Optionally, in one embodiment of the present application, the stacking module 300 includes: a three-dimensional integrated unit for stacking the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macros on the target silicon-based circuit based on the inter-layer vias corresponding to the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macros to obtain the monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

[0084] It should be noted that the above explanation of the embodiment of the back-end compatible capacitor-less DRAM storage circuit macro construction method is also applicable to the back-end compatible capacitor-less DRAM storage circuit macro construction device of this embodiment, and will not be repeated here.

[0085] According to the back-end compatible capacitor-free DRAM storage circuit macro construction device proposed in the embodiment of the present application, it includes a first construction module for determining a fully back-end compatible channel material that meets the preset preparation requirements, and using the fully back-end compatible channel material to construct a multi-layer capacitor-free DRAM storage circuit macro; a second construction module for constructing the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro based on the preset back-end compatible vertical complementary field effect transistor; a stacking module for constructing a multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, and based on the inter-layer via, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro. The capacitor-free DRAM storage circuit macro of the present application has the characteristics of long retention time, low refresh frequency, low power consumption, and can be prepared by multi-layer stacking for high-density storage; in addition, the peripheral circuit of the present application adopts the vertical complementary field effect transistor CFET process, so that the area of ​​the peripheral circuit can be further compressed, making the storage circuit macro more compact, which is conducive to the high-density integration of future storage.

[0086] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0087] A memory 801 , a processor 802 , and a computer program stored in the memory 801 and executable on the processor 802 .

[0088] When the processor 802 executes the program, the back-end compatible capacitor-less DRAM storage circuit macro construction method provided in the above embodiment is implemented.

[0089] Furthermore, the electronic device further comprises:

[0090] The communication interface 803 is used for communication between the memory 801 and the processor 802 .

[0091] The memory 801 is used to store computer programs that can be executed on the processor 802 .

[0092] The memory 801 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0093] If the memory 801, the processor 802 and the communication interface 803 are implemented independently, the communication interface 803, the memory 801 and the processor 802 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0094] Optionally, in a specific implementation, if the memory 801, the processor 802 and the communication interface 803 are integrated on a chip, the memory 801, the processor 802 and the communication interface 803 can communicate with each other through an internal interface.

[0095] The processor 802 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0096] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned back-end compatible capacitor-free DRAM storage circuit macro construction method.

[0097] The embodiment of the present application also provides a computer program product, including a computer program, which, when executed, is used to implement the above-mentioned back-end compatible capacitor-free DRAM storage circuit macro construction method.

[0098] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0099] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0100] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0101] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.

[0102] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0103] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0104] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0105] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for constructing a back-end compatible capacitor-free DRAM storage circuit macro, characterized in that: The following steps are involved: Determine a fully back-end compatible channel material that meets preset fabrication requirements, and construct a multi-layer capacitor-free DRAM storage circuit macro using the fully back-end compatible channel material; Based on the preset back-end compatible vertical complementary field effect transistor, constructing the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro; A multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is constructed according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, and based on the inter-layer vias, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

2. The method according to claim 1, characterized in that The step of determining a fully back-end compatible channel material that meets preset preparation requirements and constructing a multi-layer capacitor-free DRAM storage circuit macro using the fully back-end compatible channel material includes: Based on the preset leakage, mobility and preparation temperature requirements of the oxide semiconductor, determining the N-type channel material and the P-type channel material in the full back-end compatible channel material; The N-type channel material and the P-type channel material are prepared according to a preset deposition method, and the multi-layer capacitor-free DRAM storage circuit macro is constructed by using the N-type channel material and the P-type channel material.

3. The method according to claim 2, characterized in that The method of constructing a peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro based on the preset back-end compatible vertical complementary field effect transistor includes: Determine the storage circuit area of ​​each layer of the capacitor-free DRAM storage circuit macro, and determine the circuit area of ​​the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro according to the storage circuit area; Based on the vertical complementary characteristics of the back-end compatible vertical complementary field effect transistor, constructing a circuit topology structure of the peripheral circuit; The peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro is constructed according to the circuit area of ​​the peripheral circuit and the circuit topology structure, wherein the peripheral circuit includes at least one of a storage address selection circuit, a row and column signal driving circuit, a sensitive amplifier circuit, a data write-back circuit, a data buffer circuit and a data pre-charging circuit.

4. The method according to claim 3, characterized in that The method is based on interlayer vias, so that the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated full back-end compatible capacitor-free DRAM storage circuit macro, including: Based on the interlayer vias corresponding to the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro, the multi-layer complete back-end compatible capacitor-free DRAM storage circuit macro is stacked on the target silicon-based circuit to obtain the monolithic three-dimensional integrated full back-end compatible capacitor-free DRAM storage circuit macro.

5. A back-end compatible capacitor-free DRAM storage circuit macro construction device, characterized in that: include: A first construction module is used to determine a fully back-end compatible channel material that meets preset preparation requirements, and to construct a multi-layer capacitor-free DRAM storage circuit macro using the fully back-end compatible channel material; A second construction module is used to construct a peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro in the multi-layer capacitor-free DRAM storage circuit macro based on a preset back-end compatible vertical complementary field effect transistor; The stacking module is used to construct multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros according to each layer of the capacitor-free DRAM storage circuit macro and the corresponding peripheral circuit, and based on the inter-layer vias, the multiple layers of complete back-end compatible capacitor-free DRAM storage circuit macros are stacked on the target silicon-based circuit to obtain a monolithic three-dimensional integrated fully back-end compatible capacitor-free DRAM storage circuit macro.

6. The device according to claim 5, characterized in that The first building block comprises: A first determining unit, configured to determine an N-type channel material and a P-type channel material in the full back-end compatible channel material based on a preset leakage property, mobility and preparation temperature requirement of the oxide semiconductor; The first establishing unit is used to prepare the N-type channel material and the P-type channel material according to a preset deposition method, and construct the multi-layer capacitor-free DRAM storage circuit macro by using the N-type channel material and the P-type channel material.

7. The device according to claim 6, characterized in that The second building block comprises: a second determining unit, configured to determine a storage circuit area of ​​each layer of the capacitor-less DRAM storage circuit macro, and determine a circuit area of ​​a peripheral circuit corresponding to each layer of the capacitor-less DRAM storage circuit macro according to the storage circuit area; A second establishing unit, configured to construct a circuit topology structure of the peripheral circuit based on the vertical complementary characteristics of the back-end compatible vertical complementary field effect transistor; The third establishing unit is used to construct the peripheral circuit corresponding to each layer of the capacitor-free DRAM storage circuit macro according to the circuit area of ​​the peripheral circuit and the circuit topology structure, wherein the peripheral circuit includes at least one of a storage address selection circuit, a row and column signal driving circuit, a sensitive amplifier circuit, a data write back circuit, a data buffer circuit and a data precharge circuit.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method for constructing a back-end compatible capacitor-free DRAM storage circuit macro as described in any one of claims 1 to 4.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the back-end compatible capacitor-free DRAM storage circuit macro construction method as described in any one of claims 1 to 4.

10. A computer program product, comprising a computer program, characterized in that The computer program is executed to implement the back-end compatible capacitor-less DRAM storage circuit macro construction method as described in any one of claims 1 to 4.

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