Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. The method of manufacturing a semiconductor device includes: a step of forming a sealing body; and a step of irradiating a laser beam to a region of the sealing body covering a portion of each of the plurality of leads. Each of a plurality of leads of the lead frame LF includes a first portion having a first upper surface and a first lower surface opposite the first upper surface, and a second portion having a thickness smaller than a thickness of the first portion. The second portion has a second upper surface and a second lower surface opposite the second upper surface. In the step of irradiating the laser light, the second lower surface is exposed from the sealing body by selectively irradiating a region with the laser light.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-190650 filed on November 8, 2023 including specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present embodiment relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-191240;

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2014-007287;

[0007] [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2014-187308;

[0008] Patent Documents 1 and 2 disclose semiconductor devices provided with a stepped surface (recess) on the lower surface of a lead. In addition, Patent Document 3 discloses a method of irradiating laser light as a step of removing a diallyl maleate (dam) resin embedded in a groove portion on the upper surface of a lead in a method of manufacturing a semiconductor device. Summary of the invention

[0009] As one aspect of a semiconductor device, there is a package in which leads serving as external terminals are exposed from the lower surface of a sealing body. As such a package, for example, there are a QFN (quad flat leadless package) type and a DFN (double flat leadless package) type. When mounting a package in which leads are exposed from the lower surface of a sealing body onto a mounting substrate, the package is mounted by attaching a bonding material (such as solder) to the exposed surface of the leads. In addition, from the perspective of improving the visibility of solder in inspection after the package is mounted, as shown in the above-mentioned patent documents 1 and 2, there is a method of forming a solder fillet at the tip of the lead by forming a stepped portion at the tip of the lead.

[0010] However, when the distance between two leads becomes narrower due to, for example, the miniaturization of semiconductor devices, there is a concern that a short circuit may occur between two adjacent leads via solder. Specifically, as shown in Patent Document 2, for example, when each lead is cut using a cutting blade as a rotating blade, a metal burr extending in the array direction of a plurality of leads (multiple leads) may be formed on the side surface of the seal, that is, on the surface processed by the cutting blade (particularly, the part located between the two leads). Moreover, when the metal burr is formed, during the installation step of the package, the solder may be wicked along the metal burr, thereby possibly causing a short circuit between the two leads.

[0011] Therefore, in order to improve the reliability of semiconductor devices, a technology capable of preventing short circuits between adjacent leads is required.

[0012] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0013] A method for manufacturing a semiconductor device according to an embodiment includes: (a) preparing a lead frame, the lead frame including: a die pad, the die pad having a first upper surface and a first lower surface opposite to the first upper surface, and a plurality of leads spaced apart from the die pad, wherein each of the plurality of leads has a second upper surface facing the same direction as the first upper surface and a second lower surface opposite to the second upper surface; (b) mounting a semiconductor chip on the first upper surface of the die pad, wherein the semiconductor chip has a plurality of electrodes; (c) electrically connecting the plurality of electrodes of the semiconductor chip to the plurality of leads via a plurality of conductive members, respectively; (d) in a state where a tape material is in contact with the first lower surface of the die pad and the second lower surface of each of the plurality of leads, sealing a portion of the die pad, a first portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip with a resin made of an insulating material, and forming a sealing body, the sealing body having a third upper surface facing the same direction as the first upper surface and a third upper surface opposite to the third upper surface lower surface; (e) removing the tape material and irradiating an area of ​​the seal with a laser, wherein the area covers a second portion of each of the plurality of leads; (f) after (e), forming a metal film on the second lower surface of each of the plurality of leads and on the second portion of each of the plurality of leads, wherein each of the plurality of leads of the lead frame prepared in (a) comprises: a first portion having a second upper surface and a second lower surface; and a second portion, the second portion being located further away from the die pad than the first portion and having a thickness less than that of the first portion, wherein the plurality of leads of the lead frame prepared in (a) are arranged in a first direction, wherein the second portion comprises: a second upper surface; and a fourth lower surface opposite to the second upper surface, wherein a length from the second upper surface to the fourth lower surface is less than a length from the second upper surface to the second lower surface, and wherein in (e), the fourth lower surface of the second portion of each of the plurality of leads is exposed from the seal by selectively irradiating an area of ​​the seal.

[0014] According to another embodiment, a semiconductor device includes: a die pad having a first upper surface and a first lower surface opposite to the first upper surface; a plurality of leads spaced apart from the die pad, wherein each of the plurality of leads has a second upper surface facing the same direction as the first upper surface and a second lower surface opposite to the second upper surface; a semiconductor chip mounted on the first upper surface of the die pad, wherein the semiconductor chip has: a plurality of electrodes; a plurality of conductive members, wherein the plurality of conductive members electrically connect the plurality of electrodes of the semiconductor chip with the plurality of leads; and a sealing body, wherein the sealing body seals a portion of the die pad, a first portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip, so that the first lower surface of the die pad and the second lower surface of each of the plurality of leads are exposed from a third lower surface, wherein the sealing body has a third upper surface facing the same direction as the first upper surface and a third lower surface opposite to the third upper surface, wherein the plurality of leads Each lead of the present invention comprises: a first part, the first part having a second upper surface and a second lower surface; and a second part, the second part being located farther away from the die pad than the first part and having a thickness smaller than that of the first part, wherein the plurality of leads are arranged in a first direction, wherein the second part comprises: a second upper surface; and a fourth lower surface opposite to the second upper surface, wherein a length from the second upper surface to the fourth lower surface is less than a length from the second upper surface to the second lower surface, wherein the plurality of leads arranged in the first direction comprise two leads adjacent to each other, wherein a portion of a sealing body made of an insulating material is inserted between a second portion of one of the two leads and a second portion of the other of the two leads, and wherein, in a thickness direction of the sealing body, a length from a third upper surface of the portion of the sealing body to a third lower surface of the portion of the sealing body is greater than a length from the third upper surface of the sealing body to a fourth lower surface of the second portion of each of the plurality of leads.

[0015] According to the above-described embodiments, the performance of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a top surface view of a semiconductor device according to an embodiment.

[0017] Figure 2 yes Figure 1 0 is a bottom surface view of the semiconductor device shown in .

[0018] Figure 3 is along Figure 1 Cross-sectional view along line AA.

[0019] Figure 4 It shows Figure 1 0 is a perspective view of the internal structure of a semiconductor device without a sealing body shown in FIG.

[0020] Figure 5 is along Figure 2 An enlarged cross-sectional view of line BB.

[0021] Figure 6 It shows Figure 3 The illustrated cross-sectional view is a state in which the semiconductor device is mounted on the mounting surface of the mounting substrate via a bonding material.

[0022] Figure 7 It shows Figures 1 to 5 A flowchart of an example of a manufacturing process of a semiconductor device is shown in FIG.

[0023] Figure 8 is Figure 7 FIG. 2 is a plan view of a lead frame prepared in the lead frame preparation steps shown.

[0024] Fig. 9 is formed Figure 8 An enlarged plan view of two of the multiple devices in the portion shown.

[0025] Fig.10 is along Fig. 9 An enlarged cross-sectional view of line CC.

[0026] Fig.11 is along Fig. 9 An enlarged cross-sectional view of line DD.

[0027] Fig.12 It shows that Figure 7 A plan view of a sealed body formed in the sealing step is shown.

[0028] Fig.13 is along Fig.12 An enlarged cross-sectional view along line EE shows a state where the lead frame is placed in the cavity of the molded die.

[0029] Fig.14 The sealing body covering the end portion of the lead is shown in FIG. Figure 7 An enlarged cross-sectional view showing a state of being irradiated with laser light in the laser irradiation step is shown.

[0030] Fig.15 It shows that Figure 7 An enlarged plan view showing an example of a scanning direction of a position where laser light is irradiated in the laser irradiation step is shown.

[0031] Fig.16 The seal body is shown in FIG. Figure 7 An enlarged plan view of the example after the laser irradiation step shown in is removed.

[0032] Fig.17 is along Fig.16 An enlarged cross-sectional view of line FF.

[0033] Fig.18 is along Fig.16 An enlarged cross-sectional view of line GG.

[0034] Fig.19 It is shown that Fig.14 Enlarged cross-sectional view of the corresponding inspection example.

[0035] Fig. 20 It is shown that Fig.15 Corresponding enlarged plan view of the inspection example.

[0036] Fig.21 It is schematically shown Figure 7 An explanatory diagram of an example of a metal film forming step shown in .

[0037] Fig. 22 It shows that Fig.17 An enlarged cross-sectional view of a state in which a metal film is formed on the leads shown in FIG.

[0038] Fig.23 It shows Figure 7 An enlarged cross-sectional view of the cutting step shown in FIG.

[0039] Fig.24 It shows that the Figure 7 An enlarged side surface view of one side of a semiconductor device after the dicing step is shown in FIG.

[0040] Fig.25 It is shown that Fig.14 An enlarged cross-sectional view of a corresponding modified example.

[0041] Fig.26 It is shown that Fig.15 An enlarged plan view of a corresponding modified example.

[0042] Fig. 27 It is shown that Fig.14 A corresponding enlarged cross-sectional view of another modified example.

[0043] Fig.28 It is shown that Fig.15 A corresponding enlarged plan view of another modified example. DETAILED DESCRIPTION

[0044] (Description of the format and basic terms and usage in this application)

[0045] In the present application, for convenience, the description of the embodiment is divided into multiple parts as needed, but unless otherwise explicitly stated, regardless of the order of description, these parts are not independent and separated from each other, and are parts of a single example, one of which can be a detailed part of another part or a part or all of a modified example. In addition, in principle, the description of similar parts is omitted. In addition, each component in the embodiment is not required, unless otherwise explicitly stated, theoretically limited to the figure mark, and obviously not from the context.

[0046] Likewise, in the description of the embodiments, etc., regarding materials, composition, etc., unless it is explicitly stated otherwise and it is clear from the context, saying "X consists of A" does not exclude elements other than A. For example, for a component, it means "X includes A as a main component". For example, a reference to a "silicon member" is not limited to pure silicon, but also includes a member containing SiGe (germanium-silicon) alloy or other multi-component alloys with silicon as a main component and other additives. In addition, a reference to gold plating, Cu layer, nickel plating, etc., unless otherwise specified, includes not only pure materials but also members with gold, Cu, nickel, etc. as main components.

[0047] Furthermore, when a specific value or quantity is referred to, it may be greater or less than the specific value, unless otherwise expressly stated, theoretically limited to the reference numeral and not obviously so from the context.

[0048] In the drawings of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and in principle, the description thereof will not be repeated.

[0049] Furthermore, in the drawings, hatching or the like may be omitted even if the cross section becomes complicated or it is clearly distinguished from the gap. In this regard, even if the hole is closed in the plane, the outline of the background may be omitted when the outline of the background is obvious from the description or the like. Furthermore, hatching or dot patterns may be applied not only to the cross section but also to indicate that the area is not a gap or to define the boundary of the area.

[0050] The technology described in the following embodiments is applicable to semiconductor devices of various package types in which leads are exposed on the lower side of the sealing body. In this embodiment, as an example, an embodiment applied to a QFN type semiconductor device is discussed, in which a plurality of leads as external terminals are exposed from the sealing body on the bottom side (mounting surface).

[0051] <Semiconductor devices>

[0052] Figure 1 is a plan view of the semiconductor device of this embodiment, Figure 2 yes Figure 1A bottom view of the semiconductor device shown in FIG. Figure 3 is along Figure 1 In addition, Figure 4 It shows that Figure 1 A perspective view of the internal structure of a semiconductor device with a sealing body removed is shown. Figure 5 is along Figure 2 An enlarged cross-sectional view of line BB in FIG.

[0053] Figures 1 to 5 Describes the X direction (ref. Figure 1 , Figure 2 , Figure 3 and Figure 4 ), Y direction (reference Figure 1 , Figure 2 , Figure 4 and Figure 5 ) or Z direction (reference Figure 3 and Figure 5 ). The Y direction is the side that intersects the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is orthogonal to both the X direction and the Y direction. In other words, the Z direction is the normal direction of the XY plane, and the XY plane includes the X direction and the Y direction. In the following description, "thickness" mainly refers to the length in the Z direction. In addition, in the following description, "plan view" mainly refers to the view of the XY plane.

[0054] The semiconductor device PKG1 of the present embodiment includes a die pad (chip mounting portion, bump) DP (refer to Figure 3 and Figure 4 ) and semiconductor chip CP (reference Figure 3 and Figure 4 ), the semiconductor chip CP is mounted on the die pad DP via the die bonding material DB. In addition, the semiconductor device PKG1 has a plurality of leads (terminals, external terminals) LD arranged around the semiconductor chip CP (die pad DP), and a plurality of wires (conductive members) BW (reference Figure 3 and Figure 4 ), a plurality of wires BW respectively connect the semiconductor chip CP (reference Figure 3 and Figure 4 ) is electrically connected to a plurality of leads LD. In addition, the die pad DP is connected to a plurality of suspension leads TL (reference Figure 4 ). In addition, the semiconductor device PKG1 includes a sealing body (resin body) MR that seals the semiconductor chip CP, the plurality of wires BW, and the plurality of leads LD.

[0055] Figure 1The plane shape of the sealing body (resin body) MR shown is composed of a quadrilateral, and in the present embodiment, it is a square, for example. The sealing body MR has an upper surface MRt, a lower surface (back surface, mounting surface) MRb (reference Figure 2 ), and a side surface (sealing body side surface) MRs located between the upper surface MRt and the lower surface MRb. Figure 3 In the example shown, the side surface MRs intersects each of the upper surface MRt and the lower surface MRb. Figure 3 In the illustrated example, the side surface MRs is orthogonal to each of the upper surface MRt and the lower surface MRb.

[0056] In addition, if Figure 2 As shown, in the semiconductor device PKG1, a plurality of leads LD are arranged along each side (side surface MRsr) of the sealing body MR. The plurality of leads LD are each made of a metal material, and in the present embodiment, they are made of, for example, copper (Cu) or a copper alloy.

[0057] In addition, if Figure 2 As shown, a plurality of leads LD are exposed from the sealing body MR at their lower surfaces MRb, wherein a portion (lower surface LDb) of each lead LD is exposed from the sealing body MR. In addition, a metal film SD is formed on the portion of the lead LD exposed from the sealing body MR, and the lower surface LDb is covered with the metal film SD. The metal film SD is a plated film formed by, for example, an electroplating method, made of, for example, a solder material, and functions as a bonding material when bonding the lead LD to a terminal on the mounting board side, which will be described later.

[0058] The metal film SD (solder material) of the present embodiment is made of a so-called lead-free solder, which does not substantially contain lead (Pb) and is, for example, made of only tin (Sn), tin-bismuth (Sn-Bi) or tin-copper-silver (Sn-Cu-Ag). Here, the lead-free solder refers to a solder containing less than 0.1wt% of lead (Pb), and the content is defined as a standard guided by RoHS (Restriction of Hazardous Substances). Hereinafter, in the present embodiment, unless otherwise specifically stated, the term "solder material" or "solder component" refers to lead-free solder.

[0059] like Figure 2 As shown, each of the plurality of leads LD has a portion (portion, wire bonding portion) LDm and a portion (portion, end portion, stepped portion) LDe, the portion LDe being located farther from the die pad DP than the portion LDm.

[0060] like Figure 3As shown, the portion LDm includes an upper surface LDt and a lower surface LDb, and the lower surface LDb is opposite to the upper surface LDt. The upper surface LDt of the portion LDm is connected to the wire BW. The portion LDe has an upper surface LDt and a lower surface (stepped surface) LDb2, and the lower surface (stepped surface) LDb2 is opposite to the upper surface LDt. The length from the upper surface LDt to the lower surface LDb2 is less than the length from the upper surface LDt to the lower surface LDb. The thickness of the portion LDe is less than the thickness of the portion LDm.

[0061] Although the details will be described later, providing a portion LDe (which is a stepped portion) for each of the plurality of leads LD at the peripheral portion of the lower surface (mounting surface) of the semiconductor device PKG1 improves visibility during inspection after mounting. Figure 5 As shown, in the case of this embodiment, a portion (part) MRW of the sealing body MR made of an insulating material is interposed between portions LDe of adjacent leads LD. Figure 4 As shown, the plurality of leads LD arranged along the Y direction include two leads LD adjacent to each other. Figure 5 In the two adjacent leads LD shown, a portion MRW of the sealing body MR made of an insulating material is inserted between the portion LDe of one lead and the portion LDe of the other lead. In the thickness direction (Z direction) of the sealing body MR, the length from the upper surface MRt to the lower surface MRb of the portion (portion) MRW of the sealing body MR is greater than the length from the upper surface MRt of the sealing body MR to the lower surface LDb2 of the portion (portion) LDe of each of the multiple leads LD, as shown in FIG. Figure 5 Taking the plane including the lower surface LDb2 as a reference plane, the portion MRW protrudes from the reference plane so that the length from the upper surface MRt to the lower surface MRb of the portion MRW is greater than the length from the upper surface MRt of the sealing body MR to the lower surface LDb2 of the portion LDe of the lead LD.

[0062] In the case where the partial MRW is inserted between each portion LDe of two adjacent leads LD, the direction of the wetting and spreading of the solder bonded to the lead LD is adjusted by the partial MRW (specifically, the portion protruding from the reference surface including the lower surface LDb2 of the partial MRW). As a result, even if the space between the adjacent leads LD is reduced compared to when the partial MRW does not exist, a short circuit between the leads can be prevented.

[0063] The portion LDm includes: a side surface (lead side surface) LDs, the side surface LDs faces the side surface DPs of the die pad DP; and a side surface (lead side surface) LDs2, the side surface LDs2 is opposite to the side surface (lead side surface) LDs3. The side surface LDs is continuous with the upper surface LDt and the lower surface LDb. The side surface LDs2 is continuous with the lower surface LDb2 and the lower surface LDb.

[0064] The portion LDe has a side surface (lead side surface) LDs located at the farthest position from the portion LDm. Among the plurality of lead side surfaces of each of the plurality of leads LD, the side surface LDs is farthest from the die pad DP. The side surface LDs is continuous with the upper surface LDt and the lower surface LDb2. Although the details will be described later, the semiconductor device PKG1 is manufactured by a so-called MAP type manufacturing method. In a MAP type semiconductor device, during the separation step described, the lead LD is cut together with the sealing body MR. Therefore, as Figure 3 As shown, the side surface LDs is positioned on an extension of the side surface MRs of the sealing body MR. In other words, the side surface MRs and the side surface LDs are arranged in the same plane with each other. Further restated, in the Z direction, the position of the side surface LDs coincides with the position of the side surface MRs. Such a state is called "the side surface LDs is flush with the side surface MRs".

[0065] like Figure 2 As shown, the lower surface DPb of the die pad (chip mounting portion, convex piece) DP is exposed from the sealing body MR at the lower surface MRb of the sealing body MR. That is, the semiconductor device PKG1 is a die pad exposure type (convex piece exposure type) semiconductor device. In addition, the die pad DP is made of a metal material having a higher thermal conductivity than the sealing body MR, and in the present embodiment, it is made of, for example, copper (Cu) or a copper alloy. Therefore, compared with a semiconductor device in which the die pad DP is not exposed, the die pad exposure type semiconductor device is able to improve the heat dissipation of the package by exposing a metal member (die pad DP) (such as copper (Cu)) having a higher thermal conductivity than the sealing body MR. In addition, in Figure 2 and Figure 3 In the example shown, a metal film SD is formed on the lower surface DPb of the die pad DP and covers the lower surface of the substrate, and the metal film SD functions as a bonding material during mounting. The metal film SD is, for example, a plated film (solder film) formed by electroplating as described above.

[0066] like Figure 2 and Figure 4 As shown in FIG. 1 , the upper surface (chip mounting surface) DPt of the die pad DP has a planar shape consisting of quadrilaterals. In the present embodiment, for example, it is a square. Figure 4In the example shown, the outer dimensions of the semiconductor chip CP (the planar dimensions of the back surface CPb) are smaller than the outer dimensions (planar dimensions) of the die pad DP. Therefore, by mounting the semiconductor chip CP on the die pad DP having an area larger than its outer dimensions and exposing the lower surface DPb of the die pad DP from the sealing body MR, heat dissipation can be improved.

[0067] In addition, if Figure 3 and Figure 4 As shown, the semiconductor chip CP is mounted on the die pad DP. The semiconductor chip CP is mounted in the center (including the center area) of the die pad DP. Figure 3 As shown, the semiconductor chip CP is mounted on the die pad DP with the aid of a die bonding material (adhesive) DB, wherein the back surface CPb of the semiconductor chip CP faces the upper surface DPt of the die pad DP. In other words, the semiconductor chip CP is mounted by a so-called face-up mounting method, which involves facing the opposite surface (back surface CPb) of the surface (main surface) CPt forming the plurality of pads PD to the chip mounting surface (upper surface DPt). In the present embodiment, the die bonding material DB used is an adhesive for die bonding the semiconductor chip CP, the adhesive comprising, for example, metal particles made of silver (Ag) in an epoxy-based thermosetting resin.

[0068] like Figure 4 As shown in FIG. 1 , the plane shape of the semiconductor chip CP mounted on the die pad DP is rectangular. In the present embodiment, it is, for example, square. Figure 3 As shown, the semiconductor chip CP has a surface (main surface, upper surface) CPt, a back surface (main surface, lower surface) CPb opposite to the surface CPt, and a side surface CPs located between the surface CPt and the back surface CPb.

[0069] like Figure 3 and Figure 4 As shown, a plurality of pads (bonding pads) PD are formed on the surface CPt of the semiconductor chip CP, and in the present embodiment, a plurality of pads PD are formed along each edge of the surface CPt. Although not shown, a plurality of semiconductor elements (circuit elements) are formed in the main surface of the semiconductor chip CP (specifically, in a semiconductor element formation region provided on the upper surface of the substrate (semiconductor substrate) of the semiconductor chip CP). In addition, the plurality of pads PD are electrically connected to these semiconductor elements by means of wiring (not shown) formed in a wiring layer located inside the semiconductor chip CP (specifically, between the surface CPt and the semiconductor element formation region not shown).

[0070] The semiconductor chip CP (specifically, the substrate of the semiconductor chip CP) is made of, for example, silicon (Si). In addition, an insulating film covering the substrate and wiring of the semiconductor chip CP is formed on the surface CPt, and the surface of each of the plurality of pads PD is exposed in an opening formed in the insulating film. In addition, the pad PD is made of metal, and in the present embodiment, it is made of, for example, aluminum (Al) or an alloy layer mainly composed of aluminum (Al).

[0071] In addition, if Figure 4 As shown, a plurality of leads LD made of, for example, the same copper (Cu) as the die pad DP is arranged around the semiconductor chip CP (in other words, around the die pad DP). Each of the plurality of leads LD is arranged to be spaced apart from the die pad DP. In addition, each of the plurality of leads LD is arranged to be spaced apart from each other.

[0072] A plurality of pads (bonding pads) PD formed on the surface CPt of the semiconductor chip CP are electrically connected to a plurality of leads LD via a plurality of wires (conductive members) BW, respectively. The wire BW is made of, for example, gold (Au) or copper (Cu), wherein a portion (for example, one end) of the wire BW is bonded to the pad PD, and the other portion (for example, the other end) is bonded to a bonding area on the upper surface LDt of the lead LD. Although not shown in the figure, a plating film is generated on the surface of the bonding area of ​​the lead LD. The plating film is made of, for example, silver (Ag) or gold (Au). By forming a plating film made of silver (Ag) or gold (Au) on the surface of the bonding area (wire bonding area) of the lead LD (inner lead portion), the bonding strength with the wire BW made of gold (Au) can be improved.

[0073] like Figure 4 As shown, a plurality of suspension leads TL are connected (linked) to the die pad DP. Each of the plurality of suspension leads TL is connected to a corner of the die pad DP at one end, and the corner forms a quadrilateral in a plan view. In addition, each of the plurality of suspension leads TL extends toward a corner of the sealing body MR at the other end. By extending the suspension lead TL toward the corner of the sealing body MR, the suspension lead TL can be arranged without interfering with the arrangement of the plurality of leads LD arranged along each side (each main side) of the sealing body MR, thereby increasing the number of leads LD, that is, the number of terminals of the semiconductor device PKG1. In addition, the suspension lead TL is subjected to a half-etching process from the lower surface side, and the lower surface side is sealed by the sealing body MR. This allows the suspension lead TL and the sealing body MR to be firmly fixed, preventing the suspension lead TL from falling off the sealing body MR.

[0074] <State after mounting semiconductor device>

[0075] Next, we will describe the use of Figures 1 to 4 A state in which a semiconductor device is mounted on a mounting board is described. Figure 6 It shows Figure 3 Shown is a cross-sectional view of a state in which a semiconductor device is mounted on a mounting surface of a mounting board via a bonding material. Figure 6 The mounting board structure shown includes a mounting board MB and a semiconductor device PKG1 mounted on the mounting board MB.

[0076] The mounting board (motherboard, wiring board) MB has an upper surface (mounting surface) MBt, which is an electronic component mounting surface and is used Figures 1 to 4 The semiconductor device PKG1 described is mounted on the upper surface MBt. On the upper surface MBt, a plurality of lands (terminals) LND are arranged, which are terminals on the side of the mounting board. Figure 6 In the example shown, the mounting board MB includes a plurality of convex surfaces (lead connection terminals) LNDa, and convex surfaces (die pad connection terminals) LNDb. The upper surface MBt is covered with an insulating film (solder resist film) SR1, but the insulating film SR1 has openings formed at positions overlapping the plurality of convex surfaces LND, and at these openings, the plurality of convex surfaces LND are exposed from the insulating film SR1.

[0077] The bonding material SD1 is arranged (applied) on each of the plurality of convex surfaces LND. The bonding material SD1 is made of, for example, a solder material and is Figure 3 The metal film SD shown is formed into an integrated metal member.

[0078] In the step of electrically connecting the semiconductor device PKG1 and the mounting substrate MB via the solder material SD1 made of solder, a reflow process is performed after heating to a melting point of the solder or above and then cooling. Figure 3 ) is integrated with the solder material SD1. Through this reflow process, the solder material SD1 is bonded to the lead LD and the convex surface LNDa (or the die pad DP and the convex surface LNDb), and the semiconductor device PKG1 and the mounting substrate MB are electrically connected via the solder material SD1.

[0079] At this time, when the solder material SD1 is heated, the solder material SD1 wets and spreads over the entire exposed surface of the convex surface LND. In addition, the solder material SD1 wets and spreads over the entire lower surface DPb (which is the exposed surface of the die pad DP). In addition, the solder material SD1 wets and spreads over the exposed surface of the lead LD, the exposed surface including the lower surface LDb and the stepped portion between the lower surface LDb and the lower surface LDb2, the stepped portion being Fig.10 is shown as a stepped portion ST. On the other hand, Figure 3 As shown, since no metal film SD is formed on the side surface LDs, Figure 6 The solder material SD1 shown is difficult to wet and spread on the side surface LDs.

[0080] Next, after the semiconductor device PKG1 is mounted on the mounting substrate MB, the mounting state of the mounted semiconductor device PKG1 is visually inspected. In this step, the connection portion between the semiconductor device PKG1 and the mounting substrate MB (i.e., the bonding state by the solder material SD1) is inspected. For example, in this step, the connection portion (i.e., the bonding state by the solder material SD1) from the upper surface side of the semiconductor device PKG1 is inspected. Figure 6 The upper surface MRt side of the sealing body MR shown) or visually performed using image processing.

[0081] In the case of the present embodiment, each of the plurality of leads LD is provided with a stepped portion (portion LDe) at its periphery. In this case, the distance (height difference) from the lower surface LDb2 of the portion LDe to the convex surface LNDa is greater than the distance (height difference) from the lower surface LDb of the portion LDm to the convex surface LNDa. Therefore, a solder fillet that is easy to visually inspect from above (in other words, easy to perform pass / fail judgment) is formed at the periphery of the solder material SD1.

[0082] Therefore, in the case of this embodiment, since each of the multiple leads LD has a portion LDe at the periphery of the semiconductor device PKG1, the electrical connection state between the multiple leads LD and the multiple convex surfaces LNDa can be easily confirmed during the appearance inspection after installation on the mounting substrate MB.

[0083] More details on the structure of the portion LDe of the lead LD will be described later.

[0084] <Method of Manufacturing Semiconductor Device>

[0085] Next, we will explain the manufacturing Figures 1 to 4 A method for a semiconductor device is shown. Figure 7 yes Figures 1 to 5 FIG. 1 is a flow chart showing an example of a manufacturing process of a semiconductor device. Figure 7 In the example shown, the manufacturing method of the semiconductor device of the present embodiment includes a lead frame preparing step, a semiconductor chip mounting step, a wire bonding step, a sealing step, a laser irradiation step, a metal film forming step (plating step), and a separation step.

[0086] <Lead frame preparation step>

[0087] First, in Figure 7 In the lead frame preparation steps shown, Figures 8 to 9The lead frame LF shown is prepared. Figure 8 is Figure 7 FIG. 2 is a plan view of a lead frame prepared in the lead frame preparation steps shown. Fig. 9 yes Figure 8 An enlarged plan view of two device forming portions among the plurality of device forming portions shown in FIG. Fig.10 is along Fig. 9 Magnified cross-section of midline CC. Fig.11 is along Fig. 9 This is an enlarged cross-sectional view taken along line DD. Fig. 9 It is a plan view, but the extent of the portion where the plate thickness is reduced is clearly indicated by hatching the thin-walled portion LFhf.

[0088] like Figure 8 As shown, the lead frame LF prepared in this process includes a plurality of device forming sections (device forming sections) LFd connected to the frame section (frame section) LFf. In addition, the lead frame LF includes a cutting section (cutting section) LFc provided between the device forming sections LFd adjacent to each other among the plurality of device forming sections LFd.

[0089] The lead frame LF is made of, for example, copper (Cu) or a copper alloy. Each of the plurality of device forming sections LFd is connected to the frame section LFf. The frame section LFf serves as a support section that supports each member formed in the device forming section LFd until Figure 7 The individualization process shown in .

[0090] Each of the plurality of device formation sections LFd corresponds to Figure 1 A semiconductor device PKG1 is shown. Each of the plurality of device forming sections LFd has a die pad DP and a plurality of leads LD, and the plurality of leads LD are spaced apart from the die pad DP. The lead frame LF is a so-called multi-unit substrate in which a plurality of device forming sections LFd are arranged in a matrix. Therefore, by using the lead frame LF equipped with a plurality of device forming sections LFd, a plurality of semiconductor devices PKG1 (refer to Figure 1 ), thereby improving manufacturing efficiency.

[0091] In addition, the cutting segment LFc is Figure 7 The planned cutting area cut by the cutting blade during the individualization process is shown. The plurality of cutting sections LFc include a plurality of cutting sections LFcX extending in the X direction and a plurality of cutting sections LFcY extending in the Y direction.

[0092] like Fig. 9As shown, the cutting portion LFc is formed to surround the device forming section LFd. In addition, the connecting rod LFtb is arranged in the cutting portion LFc to surround the device forming section LFd. Figure 8 The plurality of leads LD shown and the frame section (frame body) LFf are integrally formed.

[0093] In distinguishing Fig. 9 In the case of two device formation sections LFd shown, they can be divided into a device formation section LFd1 and a device formation section LFd2. Fig. 9 The illustrated embodiment can be expressed as follows: that is, the lead frame LF has: a device forming section LFd1; a device forming section LFd2, which is close to the device forming section LFd1 in the X direction; and a cutting section LFcY, which is arranged between the device forming section LFd1 and the device forming section LFd2 and extends in the Y direction.

[0094] In addition, in the lead frame LF part, it is pre-processed so that the thickness of the board becomes thinner. In other words, as Fig. 9 As shown by the hatched lines in FIG. 1 , the lead frame LF has a thin section (half-etched section) LFhf that is thinner than other regions. Figures 9 to 11 In the example shown, the thin section LFhf is formed by a half-etching process that etches halfway in the thickness direction from the bottom surface LDb side of the lead LD. Specifically, the connecting bar LFtb and the portion of the lead LD adjacent to the connecting bar LFtb ( Fig.10 The thickness of the portion LDe shown in FIG. 1 is greater than that of the other portions ( Fig.10 The thickness of the portion LDm) shown in FIG. 1 is thin.

[0095] like Fig.10 As shown, the portion of the connecting bar LFtb and the lead LD located in the cutting section LFc between the adjacent device forming sections LFd is formed as a thin section LFhf. In other words, the portion of the connecting bar LFtb and the lead LD removes a portion of the bottom side of the lead frame, making it thinner than the other portion of the lead LD. In addition, the portion of the connecting bar LFtb and the lead LD (designated as LDe) removes a portion of the metal in advance to form a stepped section ST.

[0096] As a modified example of the present embodiment, in the lead frame manufacturing process, the stepped sections are not formed, and the method involves Figure 7 The laser irradiation step shown removes metal from the leads LD to form Figure 3 and Figure 5 The part LDe shown.

[0097] In the case of the present embodiment, the stepped section ST (in other words, the portion LDe of the lead LD) is Fig.10 Therefore, when the stepped section ST is preformed, only the Figure 7 The resin in the stepped section ST is removed during the laser irradiation step shown. Therefore, the irradiation time of the laser can be shortened in the laser irradiation step.

[0098] Furthermore, in the lead frame manufacturing process, if the cutting section LFc is formed into the thin section LFhf in advance, Figure 7 The amount of metal to be cut during the separation step shown can be reduced. Therefore, it is possible to reduce metal burrs generated during the cutting process and improve the reliability of the semiconductor device.

[0099] In addition, if Fig.11 As shown, the suspension lead TL is formed into a thin section LFhf. By manufacturing the suspension lead TL into a thin section LFhf, the bottom side of the suspension lead TL can be Figure 7 The die pad DP is sealed during the sealing process shown, thereby preventing the die pad DP from falling off from the sealing body.

[0100] like Figure 6 As explained, in order to form a solder fillet that is easily visible during external inspection, Fig.10 The depth D1 of the stepped section ST shown is preferably deeper. Fig.10 In the case shown, the depth D1 of the stepped section ST is half the thickness T1 of the portion LDm of the lead LD. In other words, the thickness T2 of the portion LDe of the lead LD is half the thickness T1 of the portion LDm. The thickness T2 of the portion LDe of the lead LD can be made thinner within a certain range, thereby allowing each of the multiple leads LD to maintain the strength required from the lead preparation process to the separation step. Therefore, the depth D1 of the stepped section ST is preferably at least half the thickness T1 of the portion LDm of the lead LD. In addition, the thickness T2 of the portion LDe of the lead LD is preferably half or less of the thickness T1 of the portion LDm. For example, the thickness T1 of the portion LDm of the lead LD is between 150μm and 200μm. On the other hand, the depth D1 of the stepped section ST is preferably about 75μm to 100μm.

[0101] Note that in this embodiment, although the method of forming the portion LDe by the etching process has been described, there are various modified examples for the method for forming the portion LDe (the method of removing the portion of the metal member constituting the lead frame). For example, a method using a cutting tool (such as Fig.19 The cutting blade DB1 shown is a method of forming the portion LDe by so-called half cutting.

[0102] When the portion LDe is formed by half cutting, metal burrs may appear around the LDe. However, even if the metal burrs are generated in the lead frame manufacturing process, the metal burrs are Figure 7 Therefore, as a method of forming the portion LDe in the lead frame manufacturing process, in addition to the etching process, various modification examples can be applied.

[0103] <Semiconductor chip mounting steps>

[0104] exist Figure 7 In the semiconductor chip mounting process shown in FIG. Figure 3 and Figure 4 As shown, the semiconductor chip CP is mounted on the die pad DP via the die bonding material DB. Figure 3 and Figure 4 to explain, but the semiconductor chip CP is mounted on the formation Fig. 9 The portion LFd shown is on the die pad DP of each of the multiple devices.

[0105] For example, in this process, the semiconductor chip CP is mounted in a so-called face-up mounting method in which the back surface CPb (the surface opposite to the surface CPt where the plurality of pads PD are formed) of the semiconductor chip CP faces the upper surface DPt of the die pad DP. Figure 4 As shown, the semiconductor chip CP is mounted in the center of the die pad DP so that each side of the surface CPt is arranged along each side of the die pad DP.

[0106] For example, in this process, the semiconductor chip CP is mounted via a die bonding material DB, which is an epoxy-based thermosetting resin, but the die bonding material DB is a paste material that is fluid before curing (thermosetting). In the case of using a paste material as the die bonding material DB, first, the die bonding material DB is applied to the die pad DP, and then, the back surface CPb of the semiconductor chip CP is adhered to the upper surface DPt of the die pad DP. Then, after bonding, by curing the die bonding material DB (for example, by applying a heat treatment), such as Figure 3 As shown, the semiconductor chip CP is fixed on the die pad DP via the die bonding material DB.

[0107] Furthermore, in this process, the die bonding material DB and the semiconductor chip CP are respectively placed on the die pad DP provided in each of the plurality of device forming parts LFd, and the semiconductor chip CP is mounted on each device forming section LFd.

[0108] In the present embodiment, although an embodiment using a paste material made of a thermosetting resin as the die bonding material DB has been described, various modified examples can be applied. For example, a solder material can be used as the die bonding material DB.

[0109] <Wire bonding step>

[0110] Next, in Figure 7 In the wire bonding step shown, Figure 3 and Figure 4 As shown, a plurality of pads (electrodes) PD and a plurality of leads LD of the semiconductor chip CP are electrically connected to each other via a plurality of wires (conductive members) BW.

[0111] For example, in this process, the semiconductor chip CP (reference Figure 3 ) is installed in Fig. 9 The lead frames LF on the die pads DP of the plurality of device forming sections LFd shown are placed on a heating stage (lead frame heating stage) not shown in the figure. Figure 3 and Figure 4 As shown, the pad PD and the lead LD of the semiconductor chip CP are electrically connected to each other via the wire BW. For example, in the present embodiment, the wire BW is supplied by means of a capillary not shown in the figure, and the wire BW is connected by a so-called nail head bonding method, which uses a combination of ultrasonic and thermal compression bonding. Note that various modified examples can be applied to the wire bonding method.

[0112] A portion of the lead LD (a bonding area at the tip of the inner lead section) is formed using a plating film made of silver (Ag) or gold (Au), and a portion of the wire BW is electrically connected to the lead LD via the plating film. In addition, the wire BW is made of metal, and in the present embodiment, for example, it is made of gold (Au) or copper (Cu).

[0113] Furthermore, in the present embodiment, after the portion (end portion) of the wire is connected to the pad PD of the semiconductor chip CP, the other portion of the wire BW is connected to the bonding area (the portion on the upper surface of the lead LD) on the wire LD by a so-called forward bonding method. Figure 3 That is, since the wire BW is bonded to the thick portion of the lead LDm, a sufficient load can be applied when bonding the wire BW to the lead LD, thereby improving the bonding strength.

[0114] In addition, in this process, the wire BW is bonded to the Fig. 9A plurality of leads LD are provided in each of the plurality of device formation sections LFd shown. As a result, in each device formation section LFd, the semiconductor chip CP and the plurality of leads LD are electrically connected to each other via a plurality of wires BW.

[0115] <Sealing Step>

[0116] Next, in Figure 7 In the sealing step shown, Fig.13 As shown, a sealing body MR is formed, which seals a portion of the die pad DP, a portion of each of the plurality of leads LD, the plurality of wires BW, and the semiconductor chip CP. Fig.12 Shown in Figure 7 A plan view of a sealed body formed in the sealing step is shown. Fig.13 is shown along the lead frame Fig.12 An enlarged cross-sectional view of a state in which line EE is placed in the cavity of the molding die.

[0117] In this process, Fig.13 As shown, the sealing body MR is formed so that the lower surfaces LDb of the plurality of leads LD provided in each of the plurality of device formation sections LFd and the lower surface DPb of the die pad DP are exposed.

[0118] For example, in this process, Fig.12 The sealing body MR shown is formed by a so-called transfer mold method which involves clamping the lead frame LF between the lead frame LF and the sealing body MR. Fig.13 In the molded core 50 shown, softened resin is injected into the molded core 50 and then cured. The resin is made of an insulating material.

[0119] The molded die 50 includes an upper die (mold) 51 arranged on the lead frame LF and a lower die (mold) 52 arranged under the lead frame LF. The upper die 51 includes a clamping surface (not shown) for pressing the lead frame LF and a cavity (recess) 53 formed inside the clamping surface. In addition, the lower die 52 includes a supporting surface (mold surface, pressing surface, surface) 52a, which is arranged to face the cavity 53 and support the lead frame LF. In the present embodiment, since a QFN type package is manufactured, the supporting surface 52a of the lower die 52 has no cavity formed therein.

[0120] In the sealing step, the sealing resin is pressed into the cavity 53 to seal the semiconductor chip CP (refer to Fig.13 ) and multiple wire BW (reference Fig.13 ). A portion of one lead among the plurality of leads LD (excluding the lower surface LDb) and a portion of the die pad DP (excluding the lower surface DPb) are also sealed with the sealing resin.

[0121] In addition, if Fig.13 As shown, the tape material (resin film) TP is arranged between the lead frame LF and the lower tube core 52. On the lower side (back side, mounting side) of the lead frame LF, the pressing force from the supporting surface 52a of the lower tube core 52 is applied through the tape material TP. Fig.13 As shown, the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP are likely to adhere to the tape material TP. In other words, in the sealing step of the present embodiment, the sealing body MR is formed using the tape material adhered to the lower surface DPb of the die pad DP and the lower surface LDb of each of the plurality of leads LD. By adhering the tape material TP, it is possible to prevent the sealing resin from being wrapped around the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP. In other words, the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP can be exposed.

[0122] Next, Fig.12 The sealing body MR shown is formed by thermally curing the resin supplied to the cavity 53. Specifically, after the sealing body MR is molded by the cavity 53, the portion of the thermosetting resin contained in the sealing body MR is heated until it hardens (referred to as temporary curing). Once the lead frame LF can be removed from the molded tube core due to this temporary curing, the lead frame LF is removed from the molded tube core. Then, it is transported to a heating furnace for further heat treatment (curing baking). As a result, the remaining portion of the thermosetting resin hardens, and the sealing body MR is obtained.

[0123] In the present embodiment, the sealing body MR is formed to collectively seal a plurality of device forming sections LFd. Fig.13 As shown in the figure, the sealing step includes the following steps. The sealing step includes the step of adhering a single sheet of tape material TP across the device forming sections LFd1 and LFd2. In addition, the sealing step includes the step of accommodating the two device forming sections LFd1 and LFd2 in the cavity (single cavity) 53. In addition, the sealing step includes the step of supplying resin into the cavity 53 and collectively sealing the two device forming sections LFd1 and LFd2.

[0124] It should be noted that the timing of adhering the tape material TP to the lead frame LF exists as follows. For example, in the case where an adhesive layer is provided on one surface of the tape material TP, there may be a case where the tape material TP is pre-attached before the lead frame LF is placed in the cavity 53. Alternatively, for example, there is a method in which the tape material TP is pre-placed on the support surface 52a of the lower mold 52 and the lead frame LF is placed thereon. In this case, the lead frame LF and the tape material TP are pressed and adhered to each other by the supply pressure of the sealing resin.

[0125] As shown in the present embodiment, a semiconductor package in which a sealing body MR is formed to collectively cover a plurality of device forming sections LFd arranged in an array is referred to as a MAP (multi-array package) type semiconductor device. In addition, a sealing method for collectively sealing a plurality of device forming sections LFd is referred to as a block molding method. Since the MAP type semiconductor device is capable of reducing the distance between each device forming section in the plurality of device forming sections LFd, the effective area on a single lead frame LF is increased. That is, the number of products that can be obtained from a single lead frame LF is increased. Therefore, by increasing the effective area on a single lead frame LF, the manufacturing process can be completed more efficiently. In particular, in the case of obtaining dozens of products from a single lead frame LF, the effect of improved manufacturing efficiency due to the increased effective area is significant.

[0126] Here, in this process, Fig.13 As shown, the sealing resin adheres by wrapping around the area that is not adhered to the molded tube core 50 or the tape material TP. Therefore, the sealing body MR is formed on the thin-walled part LFhf formed by the half-etching process. In other words, in this process, the thin-walled part LFhf is sealed with resin. Therefore, in order to expose the thin-walled part LFhf from the sealing body MR, the sealing resin is formed on the thin-walled part LFhf formed by the half-etching process. Figure 3 The lower surface LDb2 of the portion LDe shown in FIG. 1 needs to remove the sealing body MR covering the lower surface LDb2. Figure 7 The laser irradiation step shown is performed as a process of removing the sealing body MR covering the lower surface LDb2.

[0127] <Laser irradiation step>

[0128] exist Figure 7 In the laser irradiation step shown, Fig.13 After the tape material TP is shown, laser is irradiated on a region covering the portions of the plurality of leads LD within the sealing body MR. Fig.14 It shows that Figure 7 An enlarged cross-sectional view showing a state in which laser light is irradiated onto a sealing body covering an end portion of a lead in a laser irradiation step. Fig.15 It shows that the laser Figure 7An enlarged plan view showing an example of the scanning direction of the position to be irradiated in the laser irradiation step is shown. Fig.16 It shows that the seal has passed Figure 7 An enlarged plan view of the example after the laser irradiation step is removed is shown. Fig.17 is along Fig.16 An enlarged cross-sectional view of line FF. Fig.18 is along Fig.16 An enlarged cross-sectional view of line GG.

[0129] like Fig.14 As shown, in the laser irradiation step, the lower surface LDb2 is exposed from the sealing body MR by selectively irradiating a portion (region) of the sealing body MR covering the lower surface LDb2 of each of the plurality of leads LD with the laser light LZ.

[0130] Focused Discussion Fig.15 In the device forming section LFd1 shown, a plurality of leads LD are arranged adjacent to each other in the Y direction to be spaced apart from each other. In the sealing body MR, a portion (region) covering the lower surface LDb2 of each of the plurality of leads LD is selectively removed. Figure 5 The portion MRW described is formed between the portions LDe adjacent to each other in the Y direction (in other words, between the lower surfaces LDb2 adjacent to each other in the Y direction). In the laser irradiation step, the laser LZ (refer to Fig.14 ) is not irradiated on part of the MRW.

[0131] The phrase "selectively irradiating laser light onto B among A" means "laser light is irradiated onto at least B, and there is a portion of A that is not irradiated with laser light". Therefore, "selectively irradiating laser light onto B among A" includes a case where there is a portion of "B" that is not irradiated with laser light. Furthermore, "selectively irradiating laser light onto B among A" includes a case where a portion of "A" is irradiated with laser light.

[0132] As a method for selectively removing the portion covering the lower surface LDb2 of each of the plurality of leads LD after the sealing step, a method using laser irradiation is particularly effective. This is because the directivity of the laser LZ can be enhanced. For example, in the present embodiment, the laser LZ is an ultraviolet laser with a wavelength of 355 nm. The maximum output of the laser LZ is 20 W (100 kHz). In addition, the spot diameter of the laser LZ (the diameter of the spot irradiated in a circular shape) is about 30 μm to 35 μm.

[0133] On the other hand, the width WLDe of the lower surface LDb2 ( Fig.15That is, the irradiation area of ​​laser LZ in the laser irradiation step of this embodiment (the area of ​​the irradiation range when the irradiation position of laser LZ is fixed) is smaller than the plane area of ​​lower surface LDb2.

[0134] Therefore, in order to expose most of the lower surface LDb2, it is necessary to scan the laser LZ and sequentially remove the sealing body MR covering the lower surface LDb2. Fig.16 As schematically shown by arrows, the laser LZ (reference Fig.14 )'s irradiation position moves sequentially along the scanning trajectory LZS.

[0135] In addition, from the improvement Figure 6 From the perspective of reliability of connection between the bonding material SD1 shown in FIG. 1 and the lower surface LDb2 of the lead LD, it is necessary to reliably expose the lower surface LDb2. Therefore, in the laser irradiation step, the laser LZ (reference Fig.14 ) is irradiated not only on the sealing body MR but also on the lower surface LDb2 of the portion LDe of the lead LD.

[0136] Therefore, in the laser irradiation step, a plurality of grooves LZT extending in the Y direction are formed on the lower surface LDb2. In addition, from the viewpoint of surface flatness, the following state is achieved: that is, as Fig.17 As shown, after the laser irradiation step is completed, the lower surface LDb2 is rougher than the lower surface LDb. In other words, after the laser irradiation step is completed, the flatness of the lower surface LDb2 is lower than the flatness of the lower surface LDb.

[0137] When the sealing body MR is removed by laser irradiation, Fig.14 The portion irradiated with the laser LZ shown and the area around it are evaporated and removed. Therefore, from the perspective of preventing the portion other than the portion covered by the lower surface LDb2 of the sealing body MR from being removed, the range of the area irradiated with the laser LZ in this process does not overlap with the range of the lower surface LDb2. Fig.16 and Fig.18 As shown, it is preferred that the sealing body MR is kept at the peripheral portion of the lower surface LDb2 without being removed. In other words, after the laser irradiation step is completed, it is preferred that the portion ( Fig.16 and Fig.18 The portion LDc shown in FIG. 1 is covered with the sealing body MR. Further, it is preferable that the portion LDe of the lead LD includes the portion LDc covered with the sealing body MR.

[0138] On the other hand, Figure 7 In the metal film forming step shown in FIG. Figure 3The metal film SD is formed on the side surface LDs2 of the portion LDm of the lead LD shown in the figure, and it is necessary to expose the side surface LDs2 in this process. Fig.16 As shown, laser LZ (reference Fig.14 ) exists near the side surface LDs2, and it is preferred that the groove LZT closest to the side surface LDs2 is in contact with the side surface LDs2. This allows the side surface LDs2 to be exposed from the sealing body MR during the laser irradiation step.

[0139] The structure of the plurality of grooves LZT or the structure of the portion LDe having the portion LDc covered by the sealing body MR is a characteristic structure formed by removing the portion of the sealing body MR by the laser irradiation step after the sealing process. Figure 3 Therefore, regarding the completed semiconductor device PKG1, it is possible to determine whether there is Fig.16 and Fig.17 The groove LZT shown, or by whether there is Fig.16 and Fig.18 The section LDc shown determines whether the laser irradiation step of this embodiment has been performed.

[0140] In addition, Figure 3 In the portion LDe of the lead LD shown, the sealing body MR is not retained at the tip farthest from the die pad DP (having a Figure 3 In order to ensure that the sealing body MR is removed in this part, in the case of this embodiment, as shown in FIG. Fig.16 As shown, the sealing body MR is removed in a range wider than a predetermined area of ​​the portion LDe of the lead LD.

[0141] Specifically, in the case of the present embodiment, the lead frame LF is arranged between the connecting bar LFtb and the lead LD (particularly, the portion LDe of the lead LD), and includes a lead connection portion LFx having a lower surface LDb2. After the laser irradiation step is completed, the lower surface LFb2 of the lead connection portion LFx is partially exposed from the sealing body MR, and the other portions are sealed by the sealing body.

[0142] Although not shown in the figure, by controlling the output and irradiation time of laser irradiation, it is possible to Fig.16 and Fig.17 The unevenness of the LZT grooves shown is too small to be recognized. Fig.16 and Fig.18 In the modified example, in the laser irradiation step, there is a case where the entire lower surface LDb2 is exposed (that is, all portions of the sealing body MR covering the lower surface LDb2 are removed).

[0143] also, Fig.16 The scanning trajectory LZS shown is an example and is Fig.14 ) in the scanning direction. For example, in Fig.16 In the example shown, the plurality of grooves LZT extend in the Y direction, but as a modified example, there is a case where the plurality of grooves LZT extend in the X direction. However, scanning the laser light LZ along the side surface LDs2 tends to prevent unevenness in the exposure state of the sealing body MR from the side surface LDs2. From this point of view, Fig.16 As shown, it is preferred that the plurality of grooves LZT extend in the Y direction which is the same direction as the extending direction of the side surface LDs2.

[0144] <Example of inspection>

[0145] Furthermore, as an inspection example, the inventors of the present application have considered a method of exposing the lower surface LDb2 using a dicing blade instead of the laser irradiation step of the present embodiment. Fig.19 It is shown that Fig.14 Enlarged cross-sectional view of the corresponding inspection example. Fig. 20 It is shown that Fig.15 Corresponding enlarged plan view of the inspection example.

[0146] Fig.19 The inspection example shown is different from the manufacturing method of the semiconductor device of the present embodiment in that it includes a half-cutting step instead of Figure 7 In the half-cutting step, the stepped portion ST (reference Fig.10 ) is removed by running the cutting blade (cutting edge) along the cutting portion LFc (reference Fig. 20 ).

[0147] The cutting blade DB1 is a ring-shaped or disc-shaped cutting tool in which a plurality of abrasive particles are fixed to a cutting portion located on the circumference of a circle. By pressing the cutting portion of the cutting blade DB1 to which the plurality of abrasive particles are fixed against the workpiece, the workpiece can be cut and removed.

[0148] In the half-cutting step, the sealing body MR is processed by the cutting blade DB1 so that the lower surface LDb2 of the portion LDe of the lead LD is exposed. In addition, by running the cutting blade DB1 (refer to Fig. 20 ), the lower surfaces LDb2 of the plurality of leads LD can be exposed in sequence.

[0149] In the case of this inspection example, by rotating the dicing blade DB1 while linearly running it, continuous dicing processing can be performed on a plurality of leads LD. Therefore, there is an advantage of higher manufacturing efficiency compared to the laser irradiation step of the present embodiment.

[0150] However, according to the research of the inventors of the present application, in the method of the inspection example, when the distance between the adjacent leads LD is narrow, due to Fig. 20 The metal burr MS1 shown may cause a short circuit between adjacent leads LD.

[0151] Fig. 20 The metal burr MS1 shown is formed during the half-cutting process by Fig.19 The rotation direction of the dicing blade DB1 shown is formed by dragging the metal (for example, copper in the inspection example) constituting the lead frame LF. Fig. 20 In the example shown, the metal burr MS1 is formed from the top to the bottom of the page.

[0152] Since the metal burr MS1 itself is made of copper or copper alloy, for example, if the metal burr MS1 is oxidized by heat treatment, the wettability to solder is significantly reduced. However, in order to improve the wettability of the lead LD to solder, as Figure 7 As shown, it is necessary to form a metal film SD made of a metal having higher wettability to solder than copper (refer to Figure 3 ) of the metal film forming step.

[0153] When the metal film forming step is performed in a state where the metal burr MS1 is exposed from the sealing body MR, the metal film SD (see Figure 3 ) is also formed on the surface of the metal burr MS1. Figure 6 As shown, when the semiconductor device of the inspection example is mounted on the mounting substrate MB, the solder wets and spreads not only on the surface of the lead LD exposed from the sealing body MR but also on the metal burr MS1.

[0154] In addition, if Fig. 20 As shown, in the case of inspecting the semiconductor device of the example, the dicing process uses a dicing blade DB1 (see FIG. Fig.19 ) is performed on the portion (portion) between the portions LDe of the adjacent leads LD. Therefore, there is no Fig.15 Part of MRW shown.

[0155] In this case, the solder that has wetted and spread on the metal burr MS1 may become integrated with the solder spread on the adjacent lead LD. Therefore, the adjacent leads LD may be short-circuited by the solder.

[0156] In the case of this embodiment, if Figure 7 As shown, Fig.15 The lower surface LDb2 shown is exposed by the laser irradiation step. Therefore, no Fig. 20 Therefore, even after the metal film forming step after the laser irradiation step, the metal film SD (see Figure 3 ) are also formed on the lower surface LDb, the lower surface LDb2, and the side surface LDs2 instead of being formed between the adjacent leads LD.

[0157] also, Figure 5 and Fig.15 The illustrated portion MRW acts as an insulating material to ensure insulation between adjacent leads LD.

[0158] Therefore, according to this embodiment, even if the interval between adjacent leads LD is narrow, short circuit between adjacent leads LD can be prevented. In other words, according to this embodiment, since short circuit between adjacent leads LD can be prevented, the distance between adjacent leads LD can be reduced. That is, the planar size of the semiconductor device can be reduced.

[0159] <Metal Film Formation Step>

[0160] Next, in Figure 7 In the solder film forming step shown, after the laser irradiation step, the metal film SD is formed on Fig. 22 On the lower surface LDb and the lower surface LDb2 shown. Fig.21 It is schematically shown Figure 7 An explanatory diagram of an example of a metal film forming step shown in . Fig. 22 is a diagram showing a metal film formed on Fig.17 An enlarged cross-sectional view of the state of the lead shown.

[0161] In this process, for example, Fig.21 As shown, the lead frame LF is immersed in a plating solution 61. The plating solution 61 is, for example, a solder solution. An anode rod 62 is immersed in the plating solution 61. In the electroplating method, the anode rod 62 is used as an anode, and the metal portion of the lead frame LF is used as a cathode. Fig.21 As shown, the lead frame LF is connected to the negative electrode of the power source 63, and the anode rod 62 is connected to the positive electrode of the power source 63. When current passes in this state, a reduction reaction occurs on the cathode side, and the metal film SD (see Fig. 22 ) is formed on the surface of the metal portion exposed from the sealing body MR of the lead frame LF. This method is called an electroplating method (also called electrolytic plating).

[0162] like Fig. 22As shown, a metal film SD is formed on the lower surface LDb, the side surface LDs2, and the lower surface LDb2 of the lead LD by an electroplating method. The metal film SD is made of a metal material having higher wettability to solder than copper or a copper alloy as a base material of the lead frame LF. In the case of the present embodiment, as described above, the metal film SD is made of solder.

[0163] As mentioned above, in the case of this embodiment, Fig.10 The sealing body MR (see Fig.14 ) by irradiating laser LZ (see Fig.14 ) is removed, so Fig. 20 The metal burr MS1 shown is not formed. Therefore, in the metal film forming step, the metal film SD is not formed on the single device forming portion LFd (see Fig. 9 ) between the leads LD adjacent to each other.

[0164] As explained at the end of the lead frame manufacturing process, as a modified example of the present embodiment, when the portion LDe is formed by half-cutting, metal burrs may appear around the portion LDe. However, even if the metal burrs are generated during the lead frame manufacturing process, they will be Figure 7 Therefore, even if the portion LDe is formed by half-cutting during the lead frame manufacturing process, the metal film SD is not formed on the metal burr in the metal film forming step.

[0165] As a modified example of this embodiment, there is a metal film SD (see Fig. 22 ) is formed by an electroless plating method. In the case of the electroplating method described in this embodiment, it is necessary to pass an electric current through a member (electroplating target) on which a plated film is formed, and thus it is necessary to be performed before the cutting process described later. However, the film quality of the metal film SD is preferred when it is formed by electroplating rather than by electroless plating.

[0166] On the other hand, in the case of the electroless plating method, since it is not necessary to pass an electric current through the plating target, it is conceivable to perform the metal film forming step after the separation step described later. However, if the electroless plating is performed after the cutting process, the plated film is also formed on the surface of the metal burr MS2 (see the process described later). Fig.24 ). In this case, there is a concern that the adjacent leads LD may be short-circuited by the metal burrs MS2. Therefore, even if electroless plating is used, it is preferable to perform a metal film forming step before the cutting process.

[0167] <Separation Step>

[0168] Next, in Figure 7 In the cutting process shown, by Figure 8 The cutting section LFc shown runs Fig.23 The dicing blade DB2 shown in the figure is used to divide and cut each of the device forming parts LFd. Fig.23 The step shown is to separate the device formation part LFd1 from the device formation part LFd2. Fig.23 It shows Figure 7 An enlarged cross-sectional view of the cutting process is shown. Note that Fig.23 Corresponds to Fig.14 The enlarged cross section shown in . Fig.24 It shows that Figure 7 An enlarged side view of one side of a semiconductor device is shown after the sawing process is completed.

[0169] The cutting blade DB2 is a ring-shaped or disc-shaped cutting tool in which a plurality of abrasive particles are fixed to a cutting portion located on the circumference of a circle. By pressing the cutting portion of the cutting blade DB2 to which the plurality of abrasive particles are fixed against the workpiece, the workpiece can be cut and removed.

[0170] In the case of this embodiment, Fig.15 In the sealing body MR shown, the portion that seals the connection rod LFtb of the cut portion LFc is cut together with the connection rod LFtb. Fig.16 The lead connection portions LFx shown are cut in this process.

[0171] like Fig.23 As shown, through this process, the side surface LDs of the lead LD and the side surface MRs of the sealing body MR are formed. In the case of this embodiment, since the lead LD and the sealing body MR are processed together, such as using Figure 3 It has been explained that the side surface LDs is positioned on the extension of the side surface MRs of the sealing body MR.

[0172] However, in this process, since the processing is performed using the cutting blade DB2, as explained in the inspection example, metal burrs MS2 (refer to Fig.24 ).like Fig.24 As shown, metal burrs MS2 are formed on the side surfaces of the semiconductor device PKG1.

[0173] However, most metal burrs MS2 consist of copper or copper alloy, which is the base material of the lead frame LF (refer to Fig.23). The component of the metal film SD included in the metal burr MS2 is the smallest. In addition, in the case of this embodiment, since the separation step is performed after the metal film forming step, even if the metal burr MS2 appears, the metal film having high wettability to the solder will not be formed on the metal burr MS2.

[0174] Therefore, if the metal burr MS2 is oxidized by heat treatment, for example, the wettability of the metal burr MS2 to the solder is very low. Therefore, even if the metal burr MS2 occurs, the possibility of the adjacent leads LD being short-circuited through the metal burr MS2 is low.

[0175] Through the above process, Figures 1 to 5 The semiconductor device PKG1 shown is obtained. Thereafter, as necessary, tests such as electrical tests and appearance inspections are performed, and semiconductor devices judged to be non-defective are transported to the next process such as a packaging process of the semiconductor device.

[0176] <First Modification Example>

[0177] Next, modified examples of the above-described embodiment will be explained. Fig.25 It shows Fig.14 An enlarged cross-sectional view of a modified example of . Fig.26 It shows Fig.15 In the described embodiment, during the laser irradiation step, the laser LZ (refer to Fig.14 ) is not irradiated on the connecting rod LFtb, and it is explained that the lower surface LDb2 of the connecting rod LFtb remains covered with the sealing body MR when the laser irradiation step is completed.

[0178] On the other hand, in the case of this modification example, during the laser irradiation step, as Fig.25 As shown, the laser LZ is moved so that not only the lower surface LDb2 of the portion LDe of the lead LD but also the portion of the lower surface LDb2 of the tie bar LFtb is exposed from the sealing body MR (refer to Fig.26 ).

[0179] In the case of this modification example, laser irradiation can be collectively performed on two adjacent leads LD in the X direction. Therefore, when laser irradiation is performed on a large number of leads LD, the number of times the laser LZ is turned off can be halved. Fig.14 and Fig.15 As shown, compared with the use of laser LZ (see Fig.14 ) irradiation method, the processing efficiency of the laser irradiation step can be improved, thereby leaving the sealing body MR on the connecting rod LFtb.

[0180] However, from the viewpoint of suppressing the occurrence of metal burrs that may occur in the cutting process, it is preferable to perform the cutting while the metal member is sealed in the sealing body MR. Fig.15 As shown, it is preferred that the entire connection rod LFtb be kept sealed in the sealing body MR at the stage where the laser irradiation step is completed.

[0181] <Second Modification Example>

[0182] Next, another modified example of the above embodiment will be explained. As briefly explained in the part of the lead frame preparation process, as a modified example of the above embodiment, in the lead frame preparation process, no stepped piece is formed, and Figure 7 In the laser irradiation step shown, the metal of the lead LD is removed (reference Fig. 27 ), existence is formed Figure 3 and Figure 5 The method of the part LDe is shown. Fig. 27 It shows Fig.14 An enlarged cross-sectional view of another modified example of . Fig.28 It shows Fig.15 An enlarged plan view of another modified example of .

[0183] Fig. 27 and Fig.28 The lead frame LF2 shown with Fig.10 and Fig.11 The lead frame LF shown differs in that Figure 7 The thin portion LFhf (in other words, Fig.10 The stepped portion ST) shown is not formed.

[0184] In the case of the second modified example, it is the same as using Fig.14 and Fig.15 The embodiment explained differs in that Fig. 27 and Fig.28 In the laser irradiation step shown, Figure 3 and Figure 5 The part LDe shown is obtained by using laser LZ (ref. Fig. 27 ) is formed by irradiating a portion of the lower surface LDb of the lead LD, thereby removing the metal (copper or copper alloy) constituting the lead frame LF2.

[0185] In the case of the second modification example, the formation of Fig.10 and Fig.11 The process of thin section LFhf is shown.

[0186] However, in the laser irradiation step, when removing the metal, it is necessary to remove the sealing body MR (reference Fig.28 ) compared to laser LZ (reference Fig. 27 ) irradiation time becomes longer. Therefore, from the perspective of improving overall manufacturing efficiency, using Fig.14 and Fig.15 The explanatory method is preferred.

[0187] Regarding the manufacturing method of the semiconductor device, that is, the second modification example, when the technical concept is extracted, the technical concept can be expressed as follows.

[0188] That is, the method for manufacturing a semiconductor device according to this modified example includes: (a) preparing a lead frame, the lead frame including: a die pad, the die pad having a first upper surface and a first lower surface opposite to the first upper surface, and a plurality of leads spaced apart from the die pad, wherein each of the plurality of leads has a second upper surface facing the same direction as the first upper surface and a second lower surface opposite to the second upper surface; (b) mounting a semiconductor chip on the first upper surface of the die pad, wherein the semiconductor chip has a plurality of electrodes; (c) electrically connecting the plurality of electrodes of the semiconductor chip to the plurality of leads via a plurality of conductive members, respectively; (d) in a state where a tape material is in contact with the first lower surface of the die pad and the second lower surface of each of the plurality of leads, sealing a portion of the die pad, a first portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip with a resin made of an insulating material, and forming a sealing body, the sealing body having a third upper surface facing the same direction as the first upper surface and a third upper surface facing the third upper surface a third lower surface opposite to the lead frame; (e) after removing the tape material, irradiating a portion of the second lower surface of each of the plurality of leads with a laser; and (f) after (e), forming a metal film on the second lower surface of each of the plurality of leads and on a portion of each of the plurality of leads exposed by irradiating the laser, wherein each of the plurality of leads of the lead frame after completing the step (e) comprises: a first portion having a second upper surface and a second lower surface; and a second portion located farther away from the die pad than the first portion and having a thickness smaller than the first portion, wherein the plurality of leads prepared in (a) are arranged in a first direction, wherein the second portion comprises: a second upper surface and a fourth lower surface opposite to the second upper surface, wherein a length from the second upper surface to the fourth lower surface is less than a length from the second upper surface to the second lower surface, and wherein in step (e), the fourth lower surface is formed by selectively irradiating a portion of each of the plurality of leads with a laser.

[0189] <Other modification examples>

[0190] In addition to the above-mentioned modification examples, the described technology can also be applied to various modification examples. For example, in the described embodiments and modification examples, a QFN type semiconductor device is explained, where, as an example, a plurality of leads are arranged on each of the four sides of the semiconductor device. However, the arrangement of the plurality of leads is not limited to the QFN type. For example, it can be applied to a DFN type semiconductor device, where the plurality of leads LD are arranged only on two sides opposite to each other among the four sides of the semiconductor device.

[0191] As described above, although the present invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and it is obvious that various modifications can be made without departing from the gist of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) preparing a lead frame, the lead frame comprising: a die pad having a first upper surface and a first lower surface, the first lower surface being opposite to the first upper surface, and a plurality of leads spaced apart from the die pad, wherein each of the plurality of leads has a second upper surface and a second lower surface, the second upper surface facing in the same direction as the first upper surface, the second lower surface being opposite to the second upper surface; (b) mounting a semiconductor chip on the first upper surface of the die pad, wherein the semiconductor chip has a plurality of electrodes; (c) electrically connecting the plurality of electrodes of the semiconductor chip to the plurality of leads via a plurality of conductive members, respectively; (d) in a state where a tape material is in contact with the first lower surface of the die pad and the second lower surface of each of the plurality of leads, a portion of the die pad, a first portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip are sealed with a resin made of an insulating material, and a sealed body is formed, the sealed body having a third upper surface and a third lower surface, the third upper surface facing the same direction as the first upper surface, and the third lower surface facing the third upper surface; (e) removing the tape material and irradiating an area of ​​the seal with a laser, wherein the area covers a second portion of each of the plurality of leads; (f) after (e), forming a metal film on the second lower surface of each of the plurality of leads and on the second portion of each of the plurality of leads, Each of the plurality of leads of the lead frame prepared in (a) comprises: a first portion having the second upper surface and the second lower surface; and a second portion, the second portion being located farther from the die pad than the first portion and having a thickness smaller than a thickness of the first portion, wherein the plurality of leads of the lead frame prepared in (a) are arranged in a first direction, The second part includes: the second upper surface; and a fourth lower surface, the fourth lower surface being opposite to the second upper surface, wherein a length from the second upper surface to the fourth lower surface is less than a length from the second upper surface to the second lower surface, and Wherein in the (e), the fourth lower surface of the second portion of each of the plurality of leads is exposed from the sealing body by selectively irradiating the region of the sealing body.

2. The method according to claim 1, The lead frame prepared in (a) comprises: a first device forming portion; a second device forming portion, the second device forming portion being arranged close to the first device forming portion in a second direction, the second direction intersecting the first direction; as well as a cutting portion extending in the first direction and located between the first device forming portion and the second device forming portion, and Wherein said step (d) comprises: (d1) adhering a single sheet of the tape material across the first device forming portion and the second device forming portion; (d2) accommodating the first device forming portion and the second device forming portion in a cavity; and (d3) The resin is supplied into the cavity, and each of the first device forming portion and the second device forming portion is collectively sealed.

3. The method according to claim 2, further comprising: (g) after (f), separating the first device forming portion from the second device forming portion by running a cutting blade along the cutting portion, the cutting blade being a rotating blade, wherein each of the first device forming portion and the second device forming portion includes the die pad and the plurality of leads, and wherein the cutting portion includes a connecting bar connected to each of the plurality of leads in the first device forming portion and the plurality of leads in the second device forming portion, and the connecting bar extends in the first direction.

4. The method according to claim 1, wherein said (a) comprises: The step of forming the second portion by removing a portion of each of the plurality of leads using an etching process.

5. The method according to claim 1, wherein: In the (e), a plurality of grooves are formed on the fourth lower surface. The method of claim 1 , wherein after (e), the fourth lower surface is rougher than the second lower surface. 7 . The method according to claim 1 , wherein after (e), a portion of the fourth lower surface is covered by the sealing body. 8 . The method according to claim 1 , wherein an irradiation area of ​​the laser irradiated in the (e) is smaller than a plane area of ​​the fourth lower surface.

9. The method according to claim 1, wherein the plurality of leads arranged in the first direction include two leads, the two leads are adjacent to each other, wherein a portion of the sealing body is interposed between the second portion of one of the two leads and the second portion of the other of the two leads, the portion of the sealing body being made of the insulating material, and in, In the thickness direction of the sealing body, a length from the third upper surface of the portion of the sealing body to the third lower surface of the portion of the sealing body is greater than a length from the third upper surface of the sealing body to the fourth lower surface of the second portion of each of the plurality of leads.

10. A semiconductor device comprising: a die pad having a first upper surface and a first lower surface, the first lower surface being opposite to the first upper surface; a plurality of leads spaced apart from the die pad, wherein each of the plurality of leads has a second upper surface and a second lower surface, the second upper surface facing in the same direction as the first upper surface, the second lower surface being opposite to the second upper surface; a semiconductor chip mounted on the first upper surface of the die pad, wherein the semiconductor chip has a plurality of electrodes; a plurality of conductive members electrically connecting the plurality of electrodes of the semiconductor chip with the plurality of leads; as well as a sealing body that seals a portion of the die pad, a first portion of each of the plurality of leads, the plurality of conductive members, and the semiconductor chip so that the first lower surface of the die pad and the second lower surface of each of the plurality of leads are exposed from the third lower surface, wherein the sealing body has a third upper surface and the third lower surface, the third upper surface faces the same direction as the first upper surface, and the third lower surface is opposite to the third upper surface, Each of the plurality of leads comprises: a first portion having the second upper surface and the second lower surface; and a second portion, the second portion being located farther from the die pad than the first portion and having a thickness smaller than a thickness of the first portion, wherein the plurality of leads are arranged in a first direction, The second part includes: the second upper surface; and a fourth lower surface, the fourth lower surface being opposite to the second upper surface, wherein a length from the second upper surface to the fourth lower surface is less than a length from the second upper surface to the second lower surface, wherein the plurality of leads arranged in the first direction include two leads, the two leads are adjacent to each other, wherein a portion of the sealing body is interposed between the second portion of one of the two leads and the second portion of the other of the two leads, the portion of the sealing body being made of an insulating material, and Wherein, in the thickness direction of the sealing body, the length from the third upper surface of the portion of the sealing body to the third lower surface of the portion of the sealing body is greater than the length from the third upper surface of the sealing body to the fourth lower surface of the second portion of each lead of the plurality of leads. The semiconductor device according to claim 10 , wherein a plurality of grooves are formed on the fourth lower surface. 12 . The semiconductor device according to claim 10 , wherein the fourth lower surface is rougher than the second lower surface. 13 . The semiconductor device according to claim 10 , wherein a portion of the fourth lower surface is covered with the sealing body.

14. The semiconductor device according to claim 10, wherein each of the plurality of leads has a plurality of lead side surfaces, wherein the sealing body has a sealing body side surface intersecting each of the third upper surface and the third lower surface, and wherein a first lead side surface located at a position farthest from the die pad among the plurality of lead side surfaces and the sealing body side surface are arranged in the same plane with each other.

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