Semiconductor structure with bonding pad and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure with a bonding pad and a manufacturing method thereof. The manufacturing method of the semiconductor structure with the bonding pad comprises the following steps: providing a target layer; forming a first photoresist layer on one side of the target layer; the first photoresist layer is provided with a plurality of first through holes; forming a second photoresist layer at the central position of each first through hole of the first photoresist layer so as to form a plurality of second through holes between the first photoresist layer and the second photoresist layer; the second through hole comprises an annular hole; forming a plurality of bonding pads in the plurality of second through holes; wherein the shape of the cross section of each bonding pad in the direction parallel to the surface of the target layer comprises an annular shape. According to the invention, the problem of center depression of the bonding pad can be effectively improved, the problem of pseudo soldering is avoided, and the connection reliability of the semiconductor chip is improved, so that the process yield and the performance stability of the semiconductor chip are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure with a pad and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor technology, the internal circuit (net) of an integrated circuit (IC) needs to be led out to the outside of the integrated circuit for packaging. However, since the line width inside the integrated circuit is small and it is difficult to withstand the pressure of welding, the internal circuit (net) needs to be connected to a pad (pad) with a larger line width first, and the pad (pad) is used as a support for welding.

[0003] However, in the related art, in the manufacturing process of pads with larger lateral dimensions, the center of the pad is easily sunken due to the larger size of the electroplated opening of the pad. This will cause poor contact between the pad and the bump structure (BUMP) on the substrate during the flip chip (FC) process of the semiconductor chip, resulting in cold solder joints, reducing the connection reliability of the semiconductor chip, thereby adversely affecting the performance stability of the semiconductor chip, and in severe cases causing the semiconductor chip to fail. Summary of the invention

[0004] Based on this, the embodiment of the present application provides a semiconductor structure with a pad and a manufacturing method thereof, so as to effectively improve the problem of central depression of the pad, avoid the problem of cold soldering, and improve the connection reliability of the semiconductor chip, thereby improving the process yield and performance stability of the semiconductor chip.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a method for manufacturing a semiconductor structure with a pad. The manufacturing method includes: providing a target layer; forming a first photoresist layer on one side of the target layer; the first photoresist layer has a plurality of first through holes; forming a second photoresist layer at the center position of each of the first through holes of the first photoresist layer, so that a plurality of second through holes are formed between the first photoresist layer and the second photoresist layer; wherein the second through holes include annular holes; forming a plurality of pads in the plurality of the second through holes; wherein the cross-sectional shape of each of the pads in a direction parallel to the surface of the target layer includes an annular shape.

[0006] In some embodiments, before forming the first photoresist layer on one side of the target layer, the method for manufacturing the semiconductor structure with a pad also includes: forming a plurality of insulating structures on one side of the target layer; wherein the first photoresist layer is located on a side of the plurality of insulating structures away from the target layer, and the second photoresist layer is located on a side of the target layer between any two adjacent insulating structures; and each of the pads borders both the insulating structure and the target layer.

[0007] In some embodiments, forming a first photoresist layer on one side of the target layer includes: forming a first photoresist material layer covering each of the insulating structures and the target layer on one side of the target layer; etching the first photoresist material layer to form a plurality of the first through holes to obtain a first photoresist layer; wherein the plurality of the first through holes expose the target layer between any two adjacent insulating structures and a portion of the surface of the insulating structure.

[0008] In some embodiments, the second photoresist layer is formed at the center position of each of the first through holes in the first photoresist layer, including: forming a second photoresist material layer at least in the first through hole; etching the second photoresist material layer to remove the second photoresist material layer on the surface of the insulating structure and the second photoresist material layer on a portion of the surface of the target layer, and making the second photoresist material layer retained at the center position of the first through hole constitute the second photoresist layer; and forming a plurality of second through holes between each of the first photoresist layers and each of the second photoresist layers.

[0009] In some embodiments, after forming multiple solder pads in the multiple second through holes, the manufacturing method further includes: removing the first photoresist layer and the second photoresist layer; providing a substrate; one side of the substrate has multiple connection structures; connecting each of the solder pads to each of the connection structures one by one, so that multiple air columns are formed between each of the solder pads and each of the connection structures.

[0010] In some embodiments, the target layer is connected to the substrate using a flip chip process.

[0011] On the other hand, the present application also provides a semiconductor structure with a pad according to some embodiments; the semiconductor structure with the pad includes: a target layer and a plurality of pads; the plurality of pads are located on one side of the target layer; wherein the cross-sectional shape of each of the pads in a direction parallel to the surface of the target layer includes a ring shape, and the center of each of the pads has a third through hole; the third through hole exposes a portion of the surface of the target layer.

[0012] In some embodiments, the surfaces of each of the pads facing away from the target layer are all planes and are all in the same plane parallel to the surface of the target layer.

[0013] In some embodiments, the semiconductor structure with a pad also includes a plurality of insulating structures; the plurality of insulating structures are located on one side of the target layer; wherein each of the pads borders both the insulating structure and the target layer; and each of the third through holes exposes a portion of the surface of the target layer between any two adjacent insulating structures.

[0014] In some embodiments, the semiconductor structure with a pad also includes a substrate; one side of the substrate has a plurality of connection structures; each of the connection structures is connected to each of the pad structures in a one-to-one correspondence; wherein each of the third through holes between the pad and the connection structure constitutes a plurality of air columns.

[0015] The embodiments of the present application may or at least have the following advantages:

[0016] In an embodiment of the present application, two photoresist etching processes are performed to form a first photoresist layer and a second photoresist layer located at the center of the first through hole in the first photoresist layer, and a pad is formed in the second through hole between the first photoresist layer and the second photoresist layer, so that the cross-sectional shape of each pad in a direction parallel to the surface of the target layer is annular; in this way, the cross-sectional area of ​​the pad can be reduced while ensuring that the lateral size of the pad remains unchanged, and the electroplating process of the pad with a larger opening is converted into the electroplating process of the pad with a smaller opening. Moreover, since the pad has a hollow annular columnar structure, it is not easy for the center of the pad to be depressed, thereby effectively improving the problem of center depression in the manufacturing process of the pad with a larger lateral size, avoiding the phenomenon of cold soldering between the pad and the substrate in the subsequent flip-chip process, and improving the connection reliability of the semiconductor chip, which is beneficial to improving the process yield and performance stability of the semiconductor chip.

[0017] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic structural diagram of a semiconductor structure with a pad provided in the related art;

[0020] Figure 2A schematic flow chart of a method for manufacturing a semiconductor structure with a pad provided in some embodiments;

[0021] Figure 3 A schematic flow chart of another method for manufacturing a semiconductor structure with a pad provided in some embodiments;

[0022] Figure 4 A schematic flow chart of another method for manufacturing a semiconductor structure with a pad provided in some embodiments;

[0023] Figure 5 A schematic flow chart of another method for manufacturing a semiconductor structure with a pad provided in some embodiments;

[0024] Figure 6 A schematic diagram of a structure obtained after forming an insulating structure provided in some embodiments;

[0025] Figure 7 A schematic structural diagram of a structure obtained after forming a first photoresist layer provided in some embodiments;

[0026] Figure 8 A schematic structural diagram of a structure obtained after forming a second photoresist layer provided in some embodiments;

[0027] Fig. 9 A schematic diagram of a structure obtained after forming a pad provided in some embodiments;

[0028] Fig.10 A schematic structural diagram of a structure obtained after removing a first photoresist layer and a second photoresist layer provided in some embodiments;

[0029] Fig.11 A schematic diagram of a structure obtained by flipping a target layer onto a substrate provided in some embodiments.

[0030] Description of reference numerals:

[0031] 1-target layer, P1-first photoresist layer, H1-first through hole, P2-second photoresist layer, H2-second through hole, 2-pad, 3-insulating structure, 4-substrate, 41-connecting structure, 5-welding material layer, H3-third through hole. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0037] In the field of semiconductor technology, in the manufacturing process of pads with larger lateral dimensions, the pad center is easily sunken due to the larger size of the electroplating opening of the pad. Figure 1 The problem of the center depression of the pad will cause poor contact between the pad and the connection structure (such as the bump structure BUMP) on the substrate during the flip chip (FC) process of the semiconductor chip, resulting in a cold solder joint (such as Figure 1 ), which reduces the connection reliability of the semiconductor chip, thereby adversely affecting the performance stability of the semiconductor chip, and in severe cases may cause the semiconductor chip to fail.

[0038] Based on this, the embodiment of the present application provides a semiconductor structure with a pad and a manufacturing method thereof, so as to effectively improve the problem of central depression of the pad, avoid the problem of cold soldering, and improve the connection reliability of the semiconductor chip, thereby improving the process yield and performance stability of the semiconductor chip.

[0039] In some embodiments, see Figure 2 The method for manufacturing a semiconductor structure with a pad includes the following steps S100 to S400.

[0040] S100, providing a target layer.

[0041] S200, forming a first photoresist layer on one side of the target layer; the first photoresist layer has a plurality of first through holes.

[0042] S300, forming a second photoresist layer at the center position of each first through hole of the first photoresist layer, so as to form a plurality of second through holes between the first photoresist layer and the second photoresist layer; wherein the second through holes include annular holes.

[0043] S400, forming a plurality of pads in the plurality of second through holes; wherein the cross-sectional shape of each pad in a direction parallel to the surface of the target layer includes a ring shape.

[0044] In an embodiment of the present application, two photoresist etching processes are performed to form a first photoresist layer and a second photoresist layer located at the center of the first through hole in the first photoresist layer, and a pad is formed in the second through hole between the first photoresist layer and the second photoresist layer, so that the cross-sectional shape of each pad in a direction parallel to the surface of the target layer is annular; in this way, the cross-sectional area of ​​the pad can be reduced while ensuring that the lateral size of the pad remains unchanged, and the electroplating process of the pad with a larger opening is converted into the electroplating process of the pad with a smaller opening. Moreover, since the pad has a hollow annular columnar structure, it is not easy for the center of the pad to be depressed, thereby effectively improving the problem of center depression in the manufacturing process of the pad with a larger lateral size, avoiding the phenomenon of cold soldering between the pad and the substrate in the subsequent flip-chip process, and improving the connection reliability of the semiconductor chip, which is beneficial to improving the process yield and performance stability of the semiconductor chip.

[0045] In some embodiments, see Figure 3 Before step S200, the method for manufacturing a semiconductor structure with a pad further includes the following step S201.

[0046] S201, forming a plurality of insulating structures on one side of the target layer.

[0047] Accordingly, please continue to refer to Figure 3 , step S200 includes the following step S200': forming a first photoresist layer on a side of the plurality of insulating structures away from the target layer; the first photoresist layer has a plurality of first through holes. Step S300 includes the following step S300': forming a second photoresist layer on a side of the target layer between any two adjacent insulating structures, so that a plurality of second through holes are formed between the first photoresist layer and the second photoresist layer; wherein the second through holes include annular holes. Each pad formed in step S400 borders both the insulating structure and the target layer.

[0048] In some embodiments, step S201 includes: forming an insulating material layer on one side of the target layer; and etching the insulating material layer to form a plurality of insulating structures.

[0049] In the embodiment of the present application, insulation isolation between the pads is achieved through multiple insulation structures, which is helpful to avoid short circuit problems and thus ensure the performance stability of the semiconductor chip.

[0050] In some embodiments, see Figure 4 , step S200 includes the following steps S210~S220.

[0051] S210 , forming a first photoresist material layer on one side of the target layer to cover each insulating structure and the target layer.

[0052] S220, etching the first photoresist material layer to form a plurality of first through holes to obtain a first photoresist layer; wherein the plurality of first through holes expose a target layer between any two adjacent insulating structures and a portion of the surface of the insulating structure.

[0053] In the embodiment of the present application, each first through hole of the first photoresist layer is used to define the lateral dimension of the pad and expose the target layer between any two adjacent insulating structures so as to achieve electrical connection between the pad and the target layer.

[0054] In some embodiments, please refer to Figure 4 , step S300 includes the following steps S310~S320.

[0055] S310, forming a second photoresist material layer at least in the first through hole.

[0056] S320, etching the second photoresist material layer to remove the second photoresist material layer on the surface of the insulating structure and the second photoresist material layer on a portion of the surface of the target layer, and making the second photoresist material layer retained at the center position of the first through hole constitute a second photoresist layer; a plurality of second through holes are formed between each first photoresist layer and each second photoresist layer.

[0057] In the embodiment of the present application, a second photoresist etching process is carried out to form a second photoresist layer at the center position of the first through hole to obtain a second through hole, so that a pad with an annular columnar structure can be formed in each second through hole. Under the premise of ensuring that the lateral size of the pad remains unchanged, the cross-sectional area of ​​the pad is reduced, and the center of the pad is not prone to depression, thereby effectively improving the problem of center depression in the manufacturing process of pads with larger lateral sizes, avoiding the phenomenon of cold soldering between the pad and the substrate in the subsequent flip-chip process, and improving the connection reliability of the semiconductor chip.

[0058] In some embodiments, see Figure 5 After step S400, the method for manufacturing a semiconductor structure with a pad further includes the following steps S500 to S700.

[0059] S500, removing the first photoresist layer and the second photoresist layer.

[0060] S600, providing a substrate; one side of the substrate has a plurality of connection structures.

[0061] S700, connecting each pad to each connection structure in a one-to-one correspondence, so that a plurality of air columns are formed between each pad and each connection structure.

[0062] In some examples, the target layer is connected to the substrate using a flip chip process.

[0063] In an embodiment of the present application, after the target layer is connected to the substrate using a flip-chip process, multiple air columns are formed corresponding to the removed areas of the second photoresist layer between each pad and each connecting structure, which not only achieves a reliable connection between the target layer and the substrate, but also enables the target layer and the substrate to dissipate heat through the air columns, further improving the performance stability of the semiconductor chip.

[0064] It should be understood that although Figure 2~Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2~Figure 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0065] In order to more clearly illustrate the manufacturing method of the semiconductor structure with a pad in some of the above embodiments, the following embodiments are combined with Figure 6~Figure 11 Understand.

[0066] In some embodiments, a method for manufacturing a semiconductor structure having a pad includes the following steps S100 - S400 .

[0067] In step S100, refer to Figure 6 , providing target layer 1.

[0068] In some examples, target layer 1 includes a substrate.

[0069] For example, the substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of this application.

[0070] In step S200, refer to Figure 7 , a first photoresist layer P1 is formed on one side of the target layer 1; the first photoresist layer P1 has a plurality of first through holes H1.

[0071] In some embodiments, before step S200 , the method for manufacturing a semiconductor structure having a pad further includes the following step S201 .

[0072] In step S201, refer to Figure 6 , a plurality of insulating structures 3 are formed on one side of the target layer 1 .

[0073] In some embodiments, step S201 includes: forming an insulating material layer on one side of the target layer 1 ; and etching the insulating material layer to form a plurality of insulating structures 3 .

[0074] For example, the etching process of the insulating material layer includes but is not limited to a dry etching process; the etching process of the insulating material layer may be, for example, a photolithography process.

[0075] By way of example, the material of the insulating structure 3 includes but is not limited to polyimide.

[0076] In some examples, step S200 includes the following step S200': Figure 7, a first photoresist layer P1 is formed on a side of the plurality of insulating structures 3 away from the target layer 1 ; the first photoresist layer P1 has a plurality of first through holes H1 .

[0077] Please note that Figure 7 , a lateral dimension of the first through hole H1 in a direction parallel to the target layer 1 is greater than a distance between any two adjacent insulating structures 3 .

[0078] For example, the cross-sectional shape of the first through hole H1 in a direction parallel to the target layer 1 includes, but is not limited to, a circle, an ellipse, a square, a regular polygon, or the like.

[0079] In some embodiments, step S200 includes the following steps S210 to S220.

[0080] In step S210 , a first photoresist material layer is formed on one side of the target layer 1 to cover the insulating structures 3 and the target layer 1 .

[0081] In step S220, refer to Figure 7 , etching the first photoresist material layer to form a plurality of first through holes H1, and obtaining a first photoresist layer P1; wherein the plurality of first through holes H1 expose a portion of the surface of the target layer 1 and the insulating structure 3 between any two adjacent insulating structures 3.

[0082] For example, the etching process of the first photoresist material layer includes but is not limited to a dry etching process; the etching process of the first photoresist material layer may be, for example, a photolithography process.

[0083] In step S300, refer to Figure 8 A second photoresist layer P2 is formed at the center of each first through hole H1 of the first photoresist layer P1, so that a plurality of second through holes H2 are formed between the first photoresist layer P1 and the second photoresist layer P2; wherein the second through holes H2 include annular holes.

[0084] It should be noted that the cross-sectional shape of the second photoresist layer P2 at the center of each first through hole H1 in a direction parallel to the target layer 1 is the same as or similar to the cross-sectional shape of each first through hole H1 in a direction parallel to the target layer 1 .

[0085] For example, the shape of the second photoresist layer P2 at the center of each first through hole H1 includes, but is not limited to, a circular column, an elliptical column, a square column, a regular polygonal column, or the like.

[0086] In some examples, step S300 includes the following step S300': Figure 8A second photoresist layer P2 is formed on one side of the target layer 1 between any two adjacent insulating structures 3, so that a plurality of second through holes H2 are formed between the first photoresist layer P1 and the second photoresist layer P2; wherein the second through holes H2 include annular holes.

[0087] For example, the cross-sectional shape of the second through hole H2 in a direction parallel to the target layer 1 includes, but is not limited to, a circular ring, an elliptical ring, a square ring, a regular polygonal ring, and the like.

[0088] For example, please continue to see Figure 8 The second through hole H2 exposes a portion of the surface of the target layer 1 between any two adjacent insulating structures 3 and a portion of the surface of the insulating structure 3 .

[0089] In some embodiments, step S300 includes the following steps S310 to S320.

[0090] In step S310 , a second photoresist material layer is formed at least in the first through hole H1 .

[0091] In step S320, the second photoresist material layer is etched to remove the second photoresist material layer on the surface of the insulating structure 3 and the second photoresist material layer on a portion of the surface of the target layer 1, and the second photoresist material layer retained at the center of the first through hole H1 constitutes a second photoresist layer P2; a plurality of second through holes H2 are formed between each first photoresist layer P1 and each second photoresist layer P2.

[0092] For example, the etching process of the second photoresist material layer includes but is not limited to a dry etching process; the etching process of the second photoresist material layer may be, for example, a photolithography process.

[0093] In step S400 , a plurality of pads 2 are formed in the plurality of second through holes H2 ; wherein the cross-sectional shape of each pad 2 in a direction parallel to the surface of the target layer 1 includes a ring shape.

[0094] By way of example, the formation process of the pad 2 includes but is not limited to an electroplating process.

[0095] For example, the material of the pad 2 includes but is not limited to conductive metal; the material of the pad 2 may be copper (Cu), etc.

[0096] For example, the cross-sectional shape of each pad 2 in a direction parallel to the surface of the target layer 1 includes, but is not limited to, a circular ring, an elliptical ring, a square ring, a regular polygonal ring, and the like.

[0097] For example, the shape of each pad 2 includes but is not limited to a circular ring column, an elliptical ring column, a square ring column, a regular polygonal ring column, etc.

[0098] For example, each pad 2 formed in step S400 borders both the insulating structure 3 and the target layer 1 .

[0099] In some examples, each pad 2 is electrically connected to the target layer 1 .

[0100] In some examples, step S400 further includes: forming a pad 2 contact layer on a side of each pad 2 facing away from the target layer 1 .

[0101] In some embodiments, after step S400 , the method for manufacturing a semiconductor structure having a pad further includes the following steps S500 - S700 .

[0102] In step S500, refer to Fig.10 , remove the first photoresist layer P1 and the second photoresist layer P2.

[0103] Illustratively, the removal process of the first photoresist layer P1 and / or the second photoresist layer P2 includes, but is not limited to, a debonding process.

[0104] In step S600, refer to Fig.11 , providing a substrate 4; one side of the substrate 4 has a plurality of connection structures 41.

[0105] By way of example, the substrate 4 includes but is not limited to a printed circuit board (PCB) and the like.

[0106] By way of example, the connection structure 41 includes, but is not limited to, a bump structure (BUMP).

[0107] For example, the material of the connection structure 41 includes, but is not limited to, conductive metal; the material of the connection structure 41 may be, for example, copper (Cu) or the like.

[0108] In step S700, please continue to refer to Fig.11 , each pad 2 is connected to each connection structure 41 in a one-to-one correspondence, so that a plurality of air columns are formed between each pad 2 and each connection structure 41 .

[0109] For example, the connection method between each pad 2 and each connection structure 41 includes but is not limited to welding.

[0110] For example, please continue to see Fig.11 , each pad 2 and each connection structure 41 can be connected through the welding material layer 5.

[0111] By way of example, each pad 2 is electrically connected to each connection structure 41 .

[0112] Please refer to Fig.11In the embodiment of the present application, each pad 2 and each connection structure 41 are tightly connected through the welding material layer 5, and there is no Figure 1 The problem of cold soldering is shown.

[0113] In some embodiments, the target layer 1 is connected to the substrate 4 by using a flip chip (FC) process.

[0114] It should be explained that a plurality of air columns are formed corresponding to the removed regions of the second photoresist layer P2 between each pad 2 and each connection structure 41 .

[0115] The present application also provides a semiconductor structure with a pad according to some embodiments, and the semiconductor structure with a pad can be prepared by the manufacturing method of the semiconductor structure with a pad in some of the above embodiments. The technical advantages of the manufacturing method of the semiconductor structure with a pad are also possessed by the semiconductor structure with a pad. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0116] In some embodiments, see Fig.10 , a semiconductor structure with pads includes: a target layer 1 and a plurality of pads 2; the plurality of pads 2 are located on one side of the target layer 1; wherein the cross-sectional shape of each pad 2 in a direction parallel to the surface of the target layer 1 includes a ring, and the center of each pad 2 has a third through hole H3; the third through hole H3 exposes a portion of the surface of the target layer 1.

[0117] In some examples, target layer 1 includes a substrate.

[0118] For example, the substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of this application.

[0119] By way of example, the material includes but is not limited to conductive metal; the material of the pad 2 may be copper (Cu) or the like, for example.

[0120] For example, the cross-sectional shape of each pad 2 in a direction parallel to the surface of the target layer 1 includes, but is not limited to, a circular ring, an elliptical ring, a square ring, a regular polygonal ring, and the like.

[0121] For example, the shape of each pad 2 includes but is not limited to a circular ring column, an elliptical ring column, a square ring column, a regular polygonal ring column, etc.

[0122] By way of example, each pad 2 is electrically connected to the target layer 1 .

[0123] For example, the cross-sectional shape of the third through hole H3 in the direction parallel to the surface of the target layer 1 includes, but is not limited to, a circle, an ellipse, a square, a regular polygonal ring, and the like.

[0124] In some embodiments, please refer to Fig.10 , the surfaces of each pad 2 facing away from the target layer 1 are all planes and are all in the same plane parallel to the surface of the target layer 1.

[0125] In the embodiments of the present application, a semiconductor structure with pads is prepared by the manufacturing method of a semiconductor structure with pads in some of the aforementioned embodiments of the present application, and the surface of each pad 2 facing away from the target layer 1 is flat, that is, there is no problem of a center depression of the pad 2, thereby avoiding the cold solder joint between the pad 2 and the substrate 4 in the subsequent flip-chip process, improving the connection reliability of the semiconductor chip, and further facilitating improving the process yield and performance stability of the semiconductor chip.

[0126] In some embodiments, see Fig.10 or Fig.11 The semiconductor structure with pads also includes multiple insulating structures 3; the multiple insulating structures 3 are located on one side of the target layer 1; wherein each pad 2 borders both the insulating structure 3 and the target layer 1; each third through hole H3 exposes a portion of the surface of the target layer 1 between any two adjacent insulating structures 3.

[0127] By way of example, the material of the insulating structure 3 includes but is not limited to polyimide.

[0128] In some embodiments, see Fig.11 The semiconductor structure with the pad also includes a substrate 4; one side of the substrate 4 has a plurality of connection structures 41; each connection structure 41 is connected to each pad 2 structure in a one-to-one correspondence; wherein each third through hole H3 between the pad 2 and the connection structure 41 constitutes a plurality of air columns.

[0129] By way of example, the substrate 4 includes but is not limited to a printed circuit board (PCB) and the like.

[0130] By way of example, the connection structure 41 includes, but is not limited to, a bump structure (BUMP).

[0131] For example, the material of the connection structure 41 includes, but is not limited to, conductive metal; the material of the connection structure 41 may be, for example, copper (Cu) or the like.

[0132] It should be noted that the semiconductor structure with a pad provided in the embodiment of the present application includes a flip chip (FC) structure.

[0133] In the embodiment of the present application, after the target layer 1 is connected to the substrate 4 using a flip-chip process, a plurality of air columns are formed corresponding to the removed areas of the second photoresist layer P2 between each pad 2 and each connecting structure 41 (i.e., the third through hole H3), which not only achieves a reliable connection between the target layer 1 and the substrate 4, but also enables the target layer 1 and the substrate 4 to dissipate heat through the air columns, thereby improving the performance stability of the semiconductor chip.

[0134] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0135] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0136] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure having a pad, characterized in that: include: Provide target layer; forming a first photoresist layer on one side of the target layer; The first photoresist layer has a plurality of first through holes; forming a second photoresist layer at the center position of each of the first through holes of the first photoresist layer, so as to form a plurality of second through holes between the first photoresist layer and the second photoresist layer; wherein the second through holes include annular holes; A plurality of pads are formed in the plurality of the second through holes; wherein the cross-sectional shape of each of the pads in a direction parallel to the surface of the target layer includes a ring shape.

2. The method for manufacturing a semiconductor structure with a pad according to claim 1, characterized in that: Before forming the first photoresist layer on one side of the target layer, the method for manufacturing the semiconductor structure with a pad further includes: forming a plurality of insulating structures on one side of the target layer; The first photoresist layer is located on a side of the multiple insulating structures away from the target layer, and the second photoresist layer is located on a side of the target layer between any two adjacent insulating structures; each pad borders the insulating structure and the target layer.

3. The method for manufacturing a semiconductor structure with a pad according to claim 2, characterized in that: The step of forming a first photoresist layer on one side of the target layer comprises: forming a first photoresist material layer covering each of the insulating structures and the target layer on one side of the target layer; The first photoresist material layer is etched to form a plurality of the first through holes to obtain a first photoresist layer; wherein the plurality of the first through holes expose the target layer between any two adjacent insulating structures and a portion of the surface of the insulating structure.

4. The method for manufacturing a semiconductor structure with a pad according to claim 2, characterized in that: The forming of a second photoresist layer at the center position of each of the first through holes of the first photoresist layer comprises: forming a second photoresist material layer at least in the first through hole; The second photoresist material layer is etched to remove the second photoresist material layer on the surface of the insulating structure and the second photoresist material layer on a portion of the surface of the target layer, and the second photoresist material layer retained at the center position of the first through hole constitutes the second photoresist layer; a plurality of second through holes are formed between each of the first photoresist layers and each of the second photoresist layers.

5. The method for manufacturing a semiconductor structure with a pad according to claim 1, characterized in that: After forming a plurality of pads in the plurality of second through holes, the manufacturing method further includes: removing the first photoresist layer and the second photoresist layer; Providing a substrate; one side of the substrate has a plurality of connection structures; Each of the pads is connected to each of the connection structures in a one-to-one correspondence, so that a plurality of air columns are formed between each of the pads and each of the connection structures.

6. The method for manufacturing a semiconductor structure with a pad according to claim 5, characterized in that: The target layer is connected to the substrate by using a flip-chip process.

7. A semiconductor structure having a pad, characterized in that: include: Target layer; A plurality of pads are located on one side of the target layer; The cross-sectional shape of each of the pads in a direction parallel to the surface of the target layer includes a ring shape, and the center of each of the pads has a third through hole; the third through hole exposes a portion of the surface of the target layer.

8. The semiconductor structure with a pad according to claim 7, characterized in that: The surfaces of the pads facing away from the target layer are all planes and are all in the same plane parallel to the surface of the target layer.

9. The semiconductor structure with a pad according to claim 7, characterized in that: Also includes: a plurality of insulating structures, located on one side of the target layer; Wherein, each of the pads borders both the insulating structure and the target layer; Each of the third through holes exposes a portion of the surface of the target layer between any two adjacent insulating structures.

10. The semiconductor structure with a pad according to claim 7, characterized in that: Also includes: A substrate; one side of the substrate has a plurality of connection structures; each of the connection structures is connected to each of the pad structures in a one-to-one correspondence; Wherein, each of the third through holes between the pad and the connecting structure forms a plurality of air columns.

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