Semiconductor component and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor assembly and a forming method thereof. A plurality of processor dies may be attached to an interposer structure that includes an interposer dielectric material layer having an interposer metal interconnect structure formed therein. A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. The routing die may be attached to a plurality of processor dies. The routing die includes a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing substrate through-via structure formed therein. The backside of the routing substrate may be thinned, exposing an end face of the routing substrate through-via structure. After the backside of the routing substrate is thinned, a memory die is attached to the routing substrate. A bond pad of the memory die is electrically connected to the routing through substrate via structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor components and methods of forming the same. Background Art

[0002] As the performance levels of ASICs and memory dies continue to increase, the traditional integration scheme of application-specific integrated circuit (ASIC) dies and memory chips has encountered challenges in providing sufficient memory bandwidth. System performance and efficiency can be severely limited by insufficient memory bandwidth and relatively slow data transfer speeds. Therefore, memory bandwidth limitations have hindered the progress of high-performance computing. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a semiconductor component is provided, comprising: attaching a plurality of processor dies to an interposer structure, the interposer structure comprising an interposer dielectric material layer having an interposer metal interconnect structure formed therein; forming a dielectric matrix around the plurality of processor dies above the interposer structure; attaching a routing die to the plurality of processor dies, wherein the routing die comprises a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing substrate through-hole structure formed therein; thinning the back side of the routing substrate to expose an end face of the routing substrate through-hole structure; and after thinning the back side of the routing substrate, attaching a memory die to the routing substrate, wherein a bonding pad of the memory die is electrically connected to the routing substrate through-hole structure.

[0004] According to another aspect of an embodiment of the present application, a semiconductor component is provided, comprising: a plurality of processor dies bonded to an intermediate structure, the intermediate structure comprising an intermediate dielectric material layer having an intermediate metal interconnect structure formed therein; a dielectric substrate laterally surrounding the plurality of processor dies; a routing die bonded to the plurality of processor dies and comprising a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing substrate through-hole structure formed therein; and a memory die comprising a bonding pad electrically connected to the routing substrate through-hole structure.

[0005] According to another aspect of an embodiment of the present application, a semiconductor component is provided, comprising: an intermediate structure, comprising an intermediate dielectric material layer, in which an intermediate metal interconnect structure and a front intermediate bonding pad are formed; a plurality of processor dies, formed in a dielectric matrix and comprising a first processor bonding pad bonded to the front intermediate bonding pad; a routing die, comprising a routing dielectric material layer in which a routing metal interconnect structure and a front routing bonding pad are formed, and also comprising a routing substrate in which a routing substrate through-hole structure is formed, wherein the front routing bonding pad is bonded to a second processor bonding pad in the plurality of processor dies; and a memory chip bonded to the routing die, wherein the memory die comprises a memory die bonding pad electrically connected to the routing substrate through-hole structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure including an interposer structure after forming an interposer metal interconnect structure and a front interposer bond pad formed within an interposer dielectric material layer according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after bonding a processor die to an interposer according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a dielectric matrix according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of a routing die according to an embodiment of the present disclosure.

[0011] Figure 5 is a vertical cross-sectional view of an exemplary structure after bonding a routing die to a processor die array according to an embodiment of the present disclosure.

[0012] Figure 6 is a vertical cross-sectional view of an exemplary structure after thinning the back side of the routing die according to an embodiment of the present disclosure.

[0013] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming a backside routing dielectric layer and forming a backside routing bond pad according to an embodiment of the present disclosure.

[0014] Figure 8is a vertical cross-sectional view of an exemplary structure after attaching a memory die to a routing die according to an embodiment of the present disclosure.

[0015] Fig. 9 is a vertical cross-sectional view of an exemplary structure after removal of a carrier substrate from an interposer according to an embodiment of the present disclosure.

[0016] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming a backside interposer bonding pad according to an embodiment of the present disclosure.

[0017] Fig.11 By cutting Fig.10 A top view of a semiconductor component formed by an exemplary structure.

[0018] Fig.12 It is shown Fig.10 and Fig.11 The operation of the semiconductor component is shown in a circuit schematic.

[0019] Fig.13 The changes in the operating mechanism of a computing device including the semiconductor assembly of the present disclosure relative to previously known computing devices are schematically illustrated.

[0020] Fig.14 is a flow chart showing general processing steps for forming the semiconductor assembly of the present disclosure. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. Elements with the same reference numbers represent the same elements and are assumed to have the same material composition and the same thickness range unless otherwise expressly indicated. As used herein, an element or system that is "configured for" a function or operation or "configured to" provide or perform a function or operation refers to an element or system that is equipped with hardware and software (if applicable) to provide the function or operation described in this disclosure and as known in the art, provided that any details of such hardware or software are not explicitly described herein.

[0023] The present disclosure is directed generally to semiconductor devices, and more particularly to semiconductor components including an application specific integrated circuit (ASIC) die and a memory die, such as a high bandwidth memory (HBM) die, configured to enhance memory bandwidth. The integration of the ASIC die and the memory die is achieved through a network-on-chip (NoC) architecture that utilizes wafer-on-chip (CoWoS) technology and through silicon vias (TSVs) to enhance connectivity and performance. The integration scheme of the present disclosure uses a modular design framework that improves scalability and adaptability, optimizes data transfer and processing through its direct, high-speed data paths, and provides efficient thermal management.

[0024] The network-on-chip architecture used in various embodiments disclosed herein integrates the ASIC die with the memory die through a high-speed, low-latency data path provided within the network-on-chip routing. The physical distance between the ASIC die and the memory die can be reduced by using the network-on-chip routing, which provides high operating efficiency and robust heat resistance. The network-on-chip routing uses a through-silicon via (TSV) structure to provide an electrical connection to the memory die. The use of the TSV structure can increase memory capacity and bandwidth and allow a large number of memory dies to be integrated. Data flows routed through the network-on-chip can be dynamically managed to optimize resource utilization. The network-on-chip architecture can be embodied in a semiconductor component formed by chip-on-wafer-on-substrate (CoWoS) technology and hybrid bonding, thereby reducing storage latency and improving storage efficiency.

[0025] Through the disclosed on-chip network architecture, the storage capacity and bandwidth of the computing system can be increased. In addition, the embodiments of the present disclosure provide performance improvement, efficiency improvement and power consumption reduction for environmental sustainability, provide excellent thermal management for reliability, and provide design scalability for future advancements. The present disclosure provides a scalable, high-performance solution for enhancing the performance of high-end computing systems.

[0026] Reference Figure 1 , shows an exemplary structure including an interposer 100 formed on a carrier substrate 108. The carrier substrate 108 may be a commercially available silicon wafer. An interface material layer 109 may be formed on a top surface of the carrier substrate 108. The interface material layer 109 may include a thermally decomposable adhesive material, or any other material that may serve as a blocking material during subsequent removal of the carrier substrate 108.

[0027] The interposer structure 100 may be formed by depositing an interposer dielectric material layer 160 over the carrier substrate 108. An interposer metal interconnect structure 180 and a front interposer bonding pad 188 may be formed within the interposer dielectric material layer 160. The interposer dielectric material layer 160 may include an interlayer dielectric (ILD) material known in the art, which may include, for example, undoped silicate glass, doped silicate glass, silicon nitride, silicon carbide nitride, dielectric metal oxide, etc. In one embodiment, the interposer dielectric material layer 160 may include an inorganic dielectric material and / or may be substantially composed of an inorganic dielectric material. The interposer metal interconnect structure 180 may include a metal via structure and a metal line structure. In some embodiments, the sidewalls of the metal via structure may be tapered so that the lateral dimension (e.g., diameter) of each metal via increases as the vertical distance from the top surface of the carrier substrate 108 increases. The total number of layers of the metal line structure may be in the range of 1 to 12, but more layers may also be used. The interposer metal interconnect structure 180 may include copper, aluminum, tungsten, titanium, or other metals that provide high conductivity. Interposer metal interconnect structure 180 may be configured to provide electrical connections to multiple processor dies that are subsequently bonded thereto.

[0028] The front interposer bonding pad 188 may be formed at the topmost layer of the interposer dielectric material layer 160. The topmost dielectric material selected from the interposer dielectric material layer 160 is also referred to as an interposer bonding dielectric layer. The interposer bonding dielectric layer may include a dielectric material that can be used for dielectric-to-dielectric bonding, such as silicon oxide to silicon oxide bonding. In one embodiment, the interposer bonding dielectric layer may include undoped silicate glass or doped silicate glass.

[0029] The front interposer bonding pad 188 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. As used herein, a "metal-to-metal" bonding refers to a bonding in which two metal surfaces are directly bonded to each other without any intermediate material portion (such as a solder portion). Therefore, atomic interdiffusion of metal atoms occurs at the bonding interface, and grain growth and recrystallization of the metal material occur during the metal-to-metal bonding process. In one embodiment, the front interposer bonding pad 188 may include a copper bonding pad having a copper surface as a bonding surface.

[0030] Front interposer bond pads 188 may be arranged in a plurality of arrays, each array having a respective pitch along a repeating direction. Typically, the pattern of each array of front interposer bond pads 188 may be a mirror image pattern of a front processor bond pad pattern of a processor die that is subsequently bonded to interposer structure 100. According to one aspect of the present disclosure, front interposer bond pads 188 may be configured in a pattern for bonding to a plurality of processor dies (e.g., a two-dimensional array of processor dies).

[0031] Figure 1 The area shown corresponds to the area of ​​a single interposer 100. In general, a two-dimensional array of interposers 100 may be formed on a carrier substrate 108. It should be understood that the shown portion of the exemplary structure may be repeated in a two-dimensional array such that multiple interposers 100 are provided on a carrier substrate 108. The area of ​​each interposer 100 may correspond to the area of ​​a single reticle (which may be approximately 30 mm x 30 mm), or may extend over the area of ​​multiple reticles. The area of ​​each interposer 100 may be selected based on the total number of memory dies that are subsequently to be attached to an assembly including the interposer 110.

[0032] Reference Figure 2 , a plurality of processor dies 300 may be attached to the interposer 100. In one embodiment, the plurality of processor dies 300 may be attached to the interposer 100 by metal-to-metal bonding and dielectric-to-dielectric bonding. Alternatively, at least one of the plurality of processor dies 300 may be attached to the interposer 100 by microbump bonding (also referred to as C2 bonding or chip attach bonding), C4 (controlled collapse chip attach) bonding, or an alternative chip attach method. Each processor die 300 includes a processor die substrate 308, which may be a semiconductor substrate, such as a single crystal silicon substrate. Each processor die 300 includes a through substrate via structure 304 extending vertically through the processor die substrate 308. The through substrate via (TSV) structure 304 is electrically isolated from the processor die substrate 308 by an insulating spacer 302 (also referred to as a processor die insulating spacer). The insulating spacer 302 may have a tubular structure.

[0033] At least one processing unit 320 is included in each processor die 300. The processing unit 320 may be any one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a neural processing unit (NPU), an artificial intelligence (AI) accelerator, etc. In addition, the processor die 300 may include multiple processing units, such as in the case of a system on chip (SoIC) die. For example, the SoIC die may include a CPU, a GPU, a DSP, and / or an NPU. In addition, the processor die 300 may optionally include a cache memory, which is referred to as an L1 cache memory (i.e., a first-level cache memory), which may include a static random access memory (SRAM). Such a cache memory present in the processor die 300 is generally referred to as an embedded cache memory. An additional cache memory referred to as an L2 cache memory (i.e., a second-level cache memory) may be incorporated into one or more processor dies 300. Typically, relative to the L1 cache memory, the L2 cache memory may have a larger storage capacity and a slower access speed.

[0034] Each processor die 300 includes a collection of chip dielectric material layers 360, in which a collection of die metal interconnect structures 380 and a collection of pre-processor bonding pads 388 are formed. The die dielectric material layers 360 may include interlayer dielectric (ILD) materials known in the art. In one embodiment, the die dielectric material layers 360 may include and / or be substantially composed of inorganic dielectric materials. The die metal interconnect structures 380 may include metal via structures and metal wire structures. The total number of layers of the metal wire structure may be in the range of 2 to 16, but more layers may also be used. The die metal interconnect structures 380 may include copper, aluminum, tungsten, titanium, or other metals that provide high conductivity.

[0035] Pre-processor bonding pad 388 may be formed at the topmost layer of die dielectric material layer 360. The topmost dielectric material selected from die dielectric material layer 360 is also referred to as a processor bonding dielectric layer and may include a dielectric material that may be used for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. In one embodiment, the processor bonding dielectric layer may include undoped silicate glass or doped silicate glass. Pre-processor bonding pad 388 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, pre-processor bonding pad 388 may include a copper bonding pad having a copper surface as a bonding surface.

[0036] Each processor die 300 may include a backside die dielectric layer 312 located on the backside of the processor die substrate 308. The backside die dielectric layer 312 may include a dielectric material that can be used for dielectric-to-dielectric bonding. For example, the backside die dielectric layer 312 may include undoped silicate glass or doped silicate glass. Backside processor bonding pads 318 may be formed in the backside die dielectric layer 312 on the backside end surface of the substrate through-hole structure 304. The backside processor bonding pads 318 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, the backside processor bonding pads 318 may include copper pads having a copper surface as a bonding surface. The backside processor bonding pads 318 are located on the die substrate through-hole structure 304.

[0037] The processor die 300 may be attached to the interposer 100 by bonding the backside processor bond pads 318 to the front interposer bond pads 188 of the interposer 100. Thus, when multiple processor dies 300 are attached to the interposer 100, the through substrate via structures 304 are electrically connected to the front interposer bond pads 188. The backside processor bond pads 318 may be bonded to the front interposer bond pads 188 by metal-to-metal bonding (e.g., copper-to-copper bonding). In one embodiment, the backside die dielectric layer 312 of the processor die 300 may be bonded to a surface segment of the interposer dielectric material layer 160 by dielectric-to-dielectric bonding (e.g., silicon oxide-to-silicon oxide bonding).

[0038] As described above, the interposer metal interconnect structure 180 can be configured to provide electrical connections to multiple processor dies 300. Direct data transfer between processing units 320 of different processor dies 300 can be achieved using a subset of the interposer metal interconnect structure 180 used as a data bus. In general, in an embodiment where M processor dies 300 are bonded to the interposer structure 100, the interposer metal interconnect structure 180 can include up to M(M-1) / 2 sets of data buses that are configured to serve as signal transmission paths to and from the M processor dies 300. Thus, the processing units 320 within the M processor dies 300 can exchange data with each other using the data transfer buses within the interposer structure 100.

[0039] Reference Figure 3 The dielectric matrix 390 may be formed by depositing a dielectric material in the gaps between adjacent pairs of processor dies 300 and by removing portions of the dielectric material from above a level including the top surfaces of the plurality of processor dies 200. The remaining portions of the dielectric material filling the gaps comprise the dielectric matrix 390.

[0040] In one embodiment, the dielectric material of the dielectric matrix may include a molding compound (MC). MC may include an epoxy-containing compound that can be hardened (i.e., cured) to provide a dielectric material portion having sufficient rigidity and mechanical strength. MC may include epoxy, a hardener, silicon dioxide (as a filler material), and other additives. MC may be provided in liquid form or solid form, depending on viscosity and fluidity. Liquid MC generally provides better handling, good fluidity, fewer voids, better filling, and fewer flow marks. Solid MC generally has less curing shrinkage, better tolerance, and less die drift. A high filler content (e.g., 85 weight percent) in MC can shorten molding time, reduce mold shrinkage, and reduce mold warpage. A uniform filler particle size distribution in MC can reduce flow marks and can improve fluidity. Excess portions of the molding compound may be removed from above the horizontal plane including the top surface of the processor die 300.

[0041] MC may be cured at a curing temperature to form a dielectric matrix 390, which is a matrix made of MC. Dielectric matrix 390 may extend laterally across the entire area of ​​carrier substrate 108. A reconstructed wafer is thereby formed, which includes carrier substrate 108, a two-dimensional array of interposers 100, a collection of processor dies 300 bonded to a corresponding one of interposers 100, and dielectric matrix 390. Within each area of ​​interposer 100 in a plan view, a plurality of processor dies 300 bonded to interposer 100 may be formed within dielectric matrix 390.

[0042] Reference Figure 4 , a wafer including an array of routing die 600 may be provided. Each routing die 600 may have a Figure 1-Figure 3 The interposer 100 depicted in the top view and other plan views has the same area. Figure 4 The area shown in corresponds to the area of ​​a single routing die 600. In general, a two-dimensional array of routing dies 600 can be formed on a routing substrate 608, which can be a semiconductor substrate, such as a single crystal silicon substrate. It should be understood that instances of routing die 600 can be repeated in a two-dimensional array so that multiple routing dies 600 include corresponding portions of routing substrate 608. The area of ​​each routing die 600 can be the same as the area of ​​interposer 100 and can be selected based on the total number of memory dies that are subsequently to be attached to routing die 600.

[0043] The via cavity can be formed in the upper portion of the routing substrate 608. For example, a photoresist layer can be applied on the top surface of the routing substrate 608 and can be photolithographically patterned to form an array of discrete openings. An anisotropic etching process can be performed to transfer the pattern of discrete openings in the photoresist layer to the upper portion of the routing substrate 608. The void formed in the upper portion of the routing substrate 608 includes a through-hole cavity. The depth of the through-hole cavity can be in the range of 5 microns to 30 microns. The lateral dimensions (such as diameter) of each through-hole cavity can be in the range of 1 micron to 10 microns, but smaller or larger lateral dimensions can also be used. The photoresist layer can then be removed, for example, by ashing.

[0044] The insulating material may be conformally deposited in the peripheral region of the through-hole cavity in the routing substrate 608. The insulating material may include a silicon oxide material, such as an undoped silicate glass or a doped silicate glass. At least one conductive material may be deposited in the remaining volume of the through-hole cavity. The at least one conductive material may include, for example, a combination of a metal barrier material (such as TiN, TaN, WN and / or MoN) and a metal filling material (such as tungsten or copper). The insulating material and the excess portion of the at least one conductive material may be removed from above the horizontal plane including the top surface of the routing substrate 608 by a planarization process, which may use a chemical mechanical polishing (CMP) process and / or a groove etching process. Each remaining portion of the insulating material includes an insulating spacer, which is referred to as a routing insulating spacer 602. Each remaining portion of the at least one conductive material includes a routing substrate through-hole structure 604, which is also referred to as a routing through-substrate through-hole structure. In this processing step, the routing substrate through-hole structure 604 does not extend through the entire thickness of the routing substrate 608. However, when the back side of the routing substrate 608 is subsequently thinned, the routing through substrate via structure 604 may extend through the thinned routing substrate 608 .

[0045] A routing dielectric material layer 660 may then be deposited on the routing substrate 608. A routing metal interconnect structure 680 and a front routing bonding pad 688 may be formed within the routing dielectric material layer 660. The routing dielectric material layer 660 may include an interlayer dielectric (ILD) material known in the art, which may include, for example, undoped silicate glass, doped silicate glass, silicon nitride, silicon carbide nitride, dielectric metal oxide, etc. In one embodiment, the routing dielectric material layer 660 may include and / or may be substantially composed of an inorganic dielectric material. The routing metal interconnect structure 680 may include a metal via structure and a metal line structure. In some embodiments, the sidewalls of the metal via structure may be tapered so that the lateral dimension (e.g., diameter) of each metal via increases as the vertical distance from the top surface of the routing substrate 608 increases. The total number of layers of the metal line structure may be in the range of 2 to 16, but more layers may also be used. The routing metal interconnect structure 680 may include copper, aluminum, tungsten, titanium, or other metals that provide high conductivity.

[0046] The front routing bonding pad 688 can be formed at the topmost layer of the routing dielectric material layer 660. The topmost dielectric material selected from the routing dielectric material layer 660 is also referred to as a routing bonding dielectric layer, and can include a dielectric material that can be used for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. In one embodiment, the routing bonding dielectric layer can include undoped silicate glass or doped silicate glass. The front routing bonding pad 688 can be configured for metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, the front routing bonding pad 688 can include a copper bonding pad having a copper surface as a bonding surface.

[0047] The front routing bonding pads 688 can be arranged in a plurality of arrays, each array having a respective pitch along the repeating direction. Typically, the pattern of each array of the front routing bonding pads 688 can be a reference Figure 2 The pattern of the front processor bonding pads 388 of the processor die 300 described above may be a mirror image pattern. According to one aspect of the present disclosure, the pattern of the front routing bonding pads 688 may be located as shown in FIG. Figure 3 The exemplary structure provides a mirror image pattern of the pattern of the pre-processor bond pads 388 of the processor dies within the interposer 100 and the assembly of the plurality of processor dies 300 .

[0048] In general, the routing metal interconnect structure 680 provides a conductive path between each array of routing through-substrate via structures 604 and each array of front routing bonding pads 688. Specifically, each array of routing through-substrate via structures 604 configured to be electrically connected to a corresponding memory die in a subsequent processing step includes multiple groups of routing through-substrate via structures 604. Each array of front routing bonding pads 688 may include multiple groups of front routing bonding pads 688. Each group of front routing bonding pads 688 may be electrically connected to a corresponding group of routing through-substrate via structures 604.

[0049] In one embodiment, the front routing bond pads 688 within the routing die 600 may include an array of M front routing bond pads 688. The integer M may be the total number of processor dies 300 to be bonded to the routing die 600. The integer M may be between 2 and 2. 6 The routing substrate through via structure 604 within the routing die 600 may include an array of N routing substrate through via structures 604. The integer N may be the total number of memory dies to be subsequently bonded to the routing die 600. The integer N may be between 2 and 2 6 within the range.

[0050] In one embodiment, each array of front routing pads 688 selected from the M arrays of front routing bond pads 688 may include N groups of front routing bond pads 688. In one embodiment, each array of routing through substrate via structures 604 selected from the N arrays of routing through substrate via structures 604 may include M groups of routing through substrate via structures 604. In one embodiment, a total of M x N groups of front routing bond pads 688 may be provided, and a total of M x N groups of routing through substrate via structures 604 may be provided. In one embodiment, each group of front routing bond pads 688 selected from the M x N groups of routing through substrate via structures 604 may be electrically connected to a corresponding group of routing through substrate via structures 604 selected from the M x N groups of routing through substrate via structures 604.

[0051] In one embodiment, for each selected combination of an array of front routing bonding pads 688 and an array of routing substrate through-via structures 604, an electrical connection is provided between a set of front routing bonding pads 688 in the selected array of front routing bonding pads 688 and a set of routing substrate through-via structures 604 in the array of routing substrate through-via structures 604, which electrical connection may include a corresponding subset of the routing metal interconnect structure 680.

[0052] Reference Figure 5, a wafer including a two-dimensional array of routing die 600 can be bonded to a wafer of a bonded assembly including a two-dimensional array of interposer structures 100 and a two-dimensional array of processor die 300 by wafer-to-wafer bonding. Specifically, the front routing bond pad 688 of each routing die 600 is bonded to a first processor bond pad (e.g., front processor bond pad 388) within a plurality of processor dies 300 (bonded to the corresponding interposer structures 100). The front routing bond pad 688 is formed within a routing dielectric material layer 660 within each routing die 600. The front processor bond pads 388 of the plurality of processor dies 300 are formed within the die dielectric material layer 360 of the plurality of processor dies 300.

[0053] Each routing die 600 can be connected to a corresponding interposer 100 through a plurality of processor dies 300 that are completely located within the area of ​​the routing die 600. In one embodiment, each routing die 600 can have the same area as the corresponding underlying interposer 100. Each routing die 600 includes a routing dielectric material layer 660 having a routing metal interconnect structure 680 formed therein and a routing substrate 608 having a routing through substrate via structure 604 formed therein. Each of the plurality of processor dies 300 includes a respective set of die dielectric material layers 360 having respective die metal interconnect structures 380 formed therein and respective front processor bonding pads 388. The routing dielectric material layer 660 has a front routing bonding pad 688 formed therein.

[0054] In each region of routing die 600, front routing bond pads 688 are electrically connected to a corresponding one of front processor bond pads 388 when routing die 600 is attached to multiple processor dies 300. In one embodiment, each routing die 600 can be attached to multiple processor dies 300 by performing a hybrid bonding process that is a combination of a metal-to-metal bonding process to and from a bond pad and a dielectric-to-dielectric bonding process to a dielectric surface. In one embodiment, front routing bond pads 688 are bonded to front processor bond pads 388 by metal-to-metal bonding (e.g., copper-to-copper bonding). The surface of die dielectric material layer 360 is bonded to a surface segment of intervening dielectric material 160 by dielectric-to-dielectric bonding (e.g., silicon oxide-to-silicon oxide bonding). Alternatively, the two-dimensional array of routing die 600 can be bonded to the two-dimensional array of processor dies 300 by microbump bonding (also known as C2 bonding or chip attach bonding), C4 (controlled collapse chip attach) bonding, or an alternative chip attach method.

[0055] Reference Figure 6, the back side of the routing substrate 608 may be thinned, for example, by grinding, polishing, an anisotropic etching process, an isotropic etching process, or a combination thereof. The final step of the thinning process to thin the back side of the routing substrate 608 may include a chemical mechanical polishing step that uses the routing substrate through-via structure 604 as a stop structure. After thinning the back side of the routing substrate 608, the back side end surface of the routing substrate through-via structure 604 is exposed. A recess etching process may optionally be performed to vertically recess the physically exposed back side of the routing substrate 608.

[0056] Reference Figure 7 , a backside routing dielectric layer 612 may be deposited on the physically exposed back side of the routing substrate 608. The backside routing dielectric layer 612 may include a dielectric material that can be used for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. The thickness of the backside routing dielectric layer 612 may be in the range of 100nm to 600nm, but smaller or larger thicknesses may also be used. A pad cavity may be formed in the backside routing dielectric layer 612 above the region of the routing substrate through-hole structure 604, and the end face of the routing substrate through-hole structure 604 may be physically exposed below the pad cavity. At least one conductive material may be deposited in the pad cavity, and excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the backside routing dielectric layer 612. The at least one conductive material may include a combination of a metal barrier material (such as TiN, TaN, WN and / or MoN) and a metal fill material (such as copper). Each remaining portion of the at least one conductive material filling the pad cavity constitutes a backside routing bonding pad 618.

[0057] The backside routing bond pads 618 within the region of the interposer 100 may be arranged as an array of backside routing bond pads 618. As described above, the routing through substrate via structure 604 within the routing die 600 may include N arrays of routing through substrate via structures 604. The integer N may be the total number of memory dies that are subsequently bonded to the routing die 600. The integer N may be between 2 and 2. 6 In this embodiment, the backside routing bond pads 618 within the routing die 600 may include N arrays of backside routing bond pads 618. The backside routing bond pads 618 may be configured for metal-to-metal bonding, such as copper-to-copper bonding.

[0058] Alternatively, the backside routing bond pads 618 may be configured for C4 welding. In this embodiment, each backside routing bond pad 618 may include a layer stack including a metal nitride barrier liner (including a conductive metal nitride material such as TiN, TaN, WN or MoN), a copper layer, an adhesion layer that enhances the adhesion strength of subsequently deposited layers and includes a material such as Cr, Ti or a Cr / Ti alloy, a metal barrier layer including a diffusion barrier metal material such as W or Mo, and an under bump metallization (UBM) layer liner. The UBM layer may include a multi-layer stack, such as a copper layer, a nickel layer, and a gold layer. Alternative UBM layer compositions may also be used.

[0059] Generally, routing die 600 includes a backside routing dielectric layer 612 on the backside of routing substrate 608 and a backside routing bond pad 618 formed therein. Backside routing bond pad 618 contacts the end surface of routing through substrate via structure 604.

[0060] Reference Figure 8 , the memory die 800 can be bonded to the back side of the routing die 600. Each memory die 800 may include pads arranged in a mirror pattern of the pattern of the array of backside routing bonding pads 618. The bonding pads of the memory die 800 are referred to herein as memory die bonding pads 888. The memory die bonding pads 888 can be bonded to the backside routing bonding pads 618 by metal-to-metal bonding (such as copper-to-copper bonding) or by solder bonding (such as microbump bonding, i.e., chip connection bonding). If the backside routing bonding pads 618 within the routing die 600 include N arrays of backside routing bonding pads 618, then N memory dies 800 can be bonded to these N arrays of backside routing bonding pads 618. The memory die bonding pads 888 of the memory die 800 are electrically connected to the routing substrate through-hole structure 604.

[0061] In one embodiment, the memory die 800 includes a high bandwidth memory (HBM) memory die 800, which includes a corresponding vertical stack of dynamic random access memory (DRAM) chips 820 interconnected to each other through a chip connection (C2) joint. Each chip connection joint can use an array pair of micro-bump structures 838 connected to each other through an array of solder portions 835. Each micro-bump structure 838 may include a metal pillar structure, which includes a vertical layer stack, which includes a metal nitride barrier liner (including a conductive metal nitride material (such as TiN, TaN, WN or MoN)), a copper layer, an adhesion layer that enhances the adhesion strength of subsequent deposited layers and includes a material such as Cr, Ti or Cr / Ti alloy, a metal barrier layer including a diffusion barrier metal material (such as W or Mo) and an under-bump metallization (UBM) layer. A molding compound packaging structure 840 can be provided so that the micro-bump structure 838 and the solder portion 835 are encapsulated by the molding compound packaging architecture 840.

[0062] The memory die bonding pads 888 may be configured for metal-to-metal bonding or solder bonding. In embodiments where the memory die bonding pads 888 are configured for metal-to-metal bonding, each memory die bonding pad 888 may include a layer stack including a metal barrier nitride liner and a copper layer, the metal barrier nitride liner including a conductive metal nitride material (e.g., TiN, TaN, WN, and / or MoN). In this embodiment, the copper surface of the memory die bonding pad 888 may be bonded to the copper surface of the backside routing bonding pad 618 by metal-to-metal bonding (i.e., copper-to-copper bonding). In addition, the bottommost surface of each memory die 800 may include a dielectric material (e.g., silicon oxide) that may be used for dielectric-to-dielectric bonding. In this embodiment, a dielectric-to-dielectric bond may be provided between the bottommost surface of the memory die 800 and the backside routing dielectric layer 612.

[0063] Alternatively, in an embodiment where the memory die bond pad 888 and the backside routing bond pad 618 are configured for solder bonding (e.g., chip attach bonding), each of the memory die bond pad 888 and the backside routing bond pad 618 may include a corresponding microbump structure that may include a metal pillar structure that includes a vertical layer stack that includes a metal nitride barrier liner (including a conductive metal nitride material (e.g., TiN, TaN, WN, or MoN)), a copper layer, an adhesion layer that enhances the adhesion strength of subsequently deposited layers and includes a material such as Cr, Ti, or a Cr / Ti alloy, a metal barrier layer including a diffusion barrier metal material such as W or Mo, and an under bump metallization (UBM) layer. In this embodiment, a solder portion (not shown) may be used to provide a chip attach (C2) bond (also referred to as a microbump bond) between the memory die 800 and the routing die 600.

[0064] Typically, the memory die 800 includes a pad, namely a memory die bonding pad 888, which is electrically connected to the routing through substrate through via structure 604. In one embodiment, the memory die 800 includes a memory die bonding pad 888, which is electrically connected to the routing through substrate through via structure 604. In one embodiment, the memory die bonding pad 888 is bonded to the backside routing bonding pad 618 by metal-to-metal bonding. A reconstructed wafer is provided, which includes a carrier substrate 108, a two-dimensional array of interposers 100, a two-dimensional array of M processor dies 300, a two-dimensional array of routing dies 600, and a two-dimensional array of N memory dies 800.

[0065] refer to Fig. 9 , carrier substrate 108 may be removed from the assembly including the two-dimensional array of interposer 100, the two-dimensional array of the set of M processor dies 300, the two-dimensional array of routing dies 600, and the two-dimensional array of the set of N memory dies 800. For example, if interface material layer 109 includes a decomposable material that can be decomposed upon thermal activation or by other means, carrier substrate 108 may be cleaved by decomposing the interface material layer. Alternatively, carrier substrate 108 may be removed by grinding or polishing. Any remaining portions of interface material layer 109 may then be removed by performing a suitable cleaning process.

[0066] Reference Fig.10 , the bump structure may be formed on the back side of the interposer 100. In one embodiment, the bump structure may include a backside interposer bonding pad 118 and a solder portion 105. In this embodiment, each backside interposer bonding pad 118 may include a stack of a metal pad structure 118P and a metal bump layer 118B. Each metal pad structure 118P may include a stack of a metal nitride barrier liner (including a conductive metal nitride material (such as TiN, TaN, WN or MoN)) and a copper pad structure. Each metal bump layer 118B may include an adhesion layer that enhances the bonding strength of subsequently deposited layers and includes a material such as Cr, Ti or a Cr / Ti alloy, a metal barrier layer (including a diffusion barrier metal material such as W or Mo) and an under-bump metallization (UBM) layer. Alternatively, the bump structure on the back side of the interposer 100 may include an alternative bump structure, such as a metal pad (e.g., a copper pad) configured for direct metal-to-metal bonding. The bump structures on the backside surface of the interposer 100 may or may not be configured for hybrid bonding. In embodiments where the bump structures on the backside surface of the interposer 100 are configured for hybrid bonding, the bump structures may be embedded in the interposer dielectric material layer 160 such that the physically exposed surface of the metal pad is substantially coplanar with the backside surface of the interposer dielectric material layer 160.

[0067] Subsequently, an assembly including the two-dimensional array of interposers 100, the two-dimensional array of sets of M processor dies 300, the two-dimensional array of routing dies 600, the two-dimensional array of sets of N memory dies 800, and the backside interposer bonding pads 118 can be cut along cutting lanes. The cutting lanes correspond to the boundaries between adjacent pairs of interposers 100, which coincide with the boundaries between adjacent pairs of routing dies 600 in a plan view such as a top view. Each cut portion of the assembly includes a semiconductor assembly including the interposer 100, the set of M processor dies 300, the routing die 600, and the set of N memory dies 800. The physically exposed sidewalls of the interposer 100, the routing die 600, and the dielectric matrix 390 within each semiconductor assembly may coincide vertically with each other. As used herein, a first surface and a second surface coincide with each other in a vertical direction if the second surface is above or below the first surface and if the first surface and the second surface are located in the same vertical plane.

[0068] Reference Fig.11 , shows a semiconductor component formed by cutting a reconstructed wafer. In the example shown, the number N of memory dies 800 attached to the routing die 600 is 2 4 , that is 16.

[0069] Fig.12 It is shown Fig.10 and Fig.11 Schematic diagram of the operation of the semiconductor assembly shown in . Each processor die 300 may include a processing unit, which includes a combination of a core and a register. Each processor die 300 may also include an L1 cache memory (i.e., a first-level cache memory) and an L2 cache memory (i.e., a second-level cache memory) that communicate with the processing unit. M processor chips can be electrically connected to a routing die 600, which serves as an on-chip network routing, i.e., a chip that provides network connections to the processor die 300 and the memory die 800. The memory die 800 can be used as an L3 cache memory (i.e., a third-level cache memory), which can be accessed by each processor die 300 through the routing die 600.

[0070] Typically, the routing die 600 may be a passive routing chip that does not include a switching device therein. Thus, activation of the electrical connection between the processor die 300 and the memory die 800 may be controlled by the input / output control circuitry of the processor die 300. As described above, in an embodiment where M processor dies 300 and N memory dies 800 are connected to each other via the routing metal interconnect structure 680, M x N sets of electrical connections may be provided between the array of M front routing bond pads 688 and the array of N backside routing bond pads 618.

[0071] In one embodiment, the M x N sets of electrical connections may be electrically isolated from each other. Alternatively, the M x N sets of electrical connections may include a set of electrical signal paths shared with an array of multiple front routing bonding pads 688, or shared with an array of multiple backside routing bonding pads 618. In this embodiment, the input / output control device in the processor die 300 or the memory die 800 may electrically disconnect the inactive signal path by setting the state of the input / output control device of the unselected processor die 300 and / or the unselected memory die 800 to a high impedance state, i.e., a disconnected state. Therefore, data transmission between the M processor dies 300 and the N memory dies 800 may be achieved through the routing die 600 without using any intermediate switching devices.

[0072] The data transfer bandwidth provided by the routing die 600 of the present disclosure may be wider than the bandwidth provided by previously known data transfer schemes between a processor die and a memory die. Fig.13 Schematically illustrates the changes in the operating mechanism of a computing device that may include the semiconductor assembly of the present disclosure relative to previously known computing devices. In general, the performance of a computing system may be compute-limited, i.e., limited by the performance of the processing unit, and may also be memory-limited, i.e., limited by the speed of data transfer from the memory die to the processor die. Curve 1310 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1320 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1321 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1322 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1323 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1324 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1325 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1326 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1327 represents the performance limitation (measured in Giga Floating Point Operations Per Second (GFLOPS)) due to the memory wall problem in the prior art computing system. Curve 1328 represents the performance limitation (measured in Giga Floating Point Operations Fig.10 and Fig.11 The semiconductor assembly of the present disclosure can provide the highest level of performance, which is limited only by the performance of the processing unit 320, which has a lower operating intensity (measured in floating point operations per byte (FLOPS)). This operating mode consumes less power, generates less heat, and provides the highest possible performance level by increasing the data transfer bandwidth between the memory die 800 and the processor die 300.

[0073] In an embodiment where the memory die 800 includes a high bandwidth memory die, it is estimated that the routing substrate through via structure 604 can be formed with a pitch in the range of 10 microns to 60 microns, such as 20 microns to 40 microns. In a plan view such as a top view, the area of ​​the keep-out zone (KOZ) of the routing substrate through via structure 604 can be in the range of 1% to 10% of the total area of ​​the routing die 600. The memory die 800 can be arranged in a rectangular periodic array, or can be arranged in a staggered pattern, or any other bottom-up design pattern optimized for performance based on the arrangement of the processor die 300.

[0074] The architecture provided by the interposer structure, the M processor dies 300, the routing die 600, and the N memory dies can increase the total memory capacity and can reduce the memory latency, which results in Fig.13 1310 or 1320. The total number N of memory dies 800 that can be attached to routing die 600 generally depends on the area of ​​routing die 600, which can be the same as the area of ​​interposer 100. In an embodiment where routing die 600 has about three mask dimensions (corresponding to an area of ​​about 3 times 30 mm x 30 mm), up to 20 high bandwidth memory (HBM) dies can be attached to routing die 600 as memory dies 800. The memory capacity of each memory die 800 and the total number of memory dies can be increased to increase the memory capacity of the computing system, and the utilization of the increased memory capacity can be achieved through the data paths provided within routing die 600.

[0075] Reference Fig.14 , a flow chart showing general processing steps for forming the semiconductor assembly of the present disclosure.

[0076] Reference steps 1410 and Figure 1 and Figure 2 , a plurality of processor dies 300 may be attached to an interposer structure 100 , which includes an interposer dielectric material layer 160 in which an interposer metal interconnect structure 180 is formed.

[0077] Refer to step 1420 and Figure 3 , a dielectric matrix 390 may be formed around the plurality of processor dies 300 over the interposer 100 .

[0078] Refer to step 1430 and Figure 4 and Figure 5 , the routing die 600 can be attached to a plurality of processor dies 300. The routing die 600 includes a routing dielectric material layer 660 having a routing metal interconnect structure 680 formed therein and a routing substrate 608 having a routing through substrate via structure 604 formed therein.

[0079] Refer to step 1440 and Figure 6 and Figure 7 , the back side of the routing substrate 608 can be thinned. The end surface of the routing substrate through-via structure 604 is exposed.

[0080] Reference steps 1450 and Figure 8-Figure 11 After thinning the back side of the routing substrate 608, the memory die 800 can be attached to the routing substrate 608. The pads of the memory die 800, namely the memory die bonding pads 888, are electrically connected to the routing substrate through-substrate via structures 604.

[0081] With reference to all the accompanying drawings, according to various embodiments of the present disclosure, there is provided a semiconductor component, which includes: a plurality of processor dies 300 bonded to an interposer structure 100, the interposer structure including an interposer dielectric material layer 160 in which an interposer metal interconnect structure 180 is formed; a dielectric matrix 390 laterally surrounding the plurality of processor dies 300; a routing die 600 bonded to the plurality of processor dies 300 and including a routing dielectric material layer 660 in which a routing metal interconnect structure 680 is formed and a routing substrate 608 in which a routing substrate through-hole structure 604 is formed; and a memory die 800, including a bonding pad (i.e., a memory die bonding pad 888) electrically connected to the routing substrate through-hole structure 604.

[0082] In one embodiment, the plurality of processor dies 300 include: a processor die substrate 308 having a die substrate through-via structure 304 formed therein; and a backside processor bonding pad 318 located on the die substrate through-via structure 304 that is bonded to a front interposer bonding pad 188 formed within an interposer dielectric material layer 160 of the interposer structure 100.

[0083] In one embodiment, the plurality of processor dies 300 include a backside die dielectric layer 312 laterally surrounding a respective subset of the backside processor bond pads, and a surface of the backside die dielectric layer 312 is bonded to a surface segment of the interposer dielectric material layer 160 via a dielectric-to-dielectric bond. In one embodiment, the sidewalls of the interposer 100 are vertically coincident with the sidewalls of the routing die 600. In one embodiment, the front routing bond pads 688 formed in the routing dielectric material layer 660 are bonded to the front processor bond pads 388 formed in the die dielectric material layer 360 of the plurality of processor dies 300.

[0084] According to another aspect of the present invention, a semiconductor component is provided, which includes: an interposer structure 100, which includes an interposer dielectric material layer 160, in which an interposer metal interconnect structure 180 and a front interposer bonding pad 188 are formed; a plurality of processor die 300, which are embedded in a dielectric matrix 390 and include a first processor bonding pad (such as a backside processor bonding pad 318) bonded to the front interposer bonding pad 188; a routing die 600, which includes a routing dielectric material layer 660, in which a routing metal interconnect structure 680 and a front routing bonding pad 688 are formed, and also includes a routing substrate 608, in which a routing substrate through-hole structure 604 is formed, wherein the front routing bonding pad 688 is bonded to the first processor bonding pad (such as the front processor bonding pad 388) within the plurality of processor die 300; and a memory die 800, bonded to the routing die 600, wherein the memory die 800 includes a memory die bonding pad 888 electrically connected to the routing through the substrate through-hole structure 604.

[0085] In one embodiment, routing die 600 includes a backside routing dielectric layer 612 on the backside of routing substrate 608 and having formed therein a backside routing bond pad 618 in contact with an end surface of routing through substrate via structure 604. In one embodiment, memory die 800 includes a bond pad (i.e., memory die bond pad 888) bonded to backside routing bond pad 618 by metal-to-metal bonding.

[0086] In one embodiment, the sidewalls of the routing die 600 are vertically coincident with the sidewalls of the dielectric matrix 390. In one embodiment, the plurality of processor dies 300 include a die dielectric material layer 360 having a die metal interconnect structure and a front processor bond pad 388 formed therein; the routing dielectric material layer 660 having a front routing bond pad 688 formed therein; and the front routing bond pad 688 is bonded to the front processor bond pad 388 via metal-to-metal bonding.

[0087] Embodiments of the present disclosure may be used to provide a computing system using a passive routing die to provide increased bandwidth between a processor die 300 and a memory die 800. For example, a high bandwidth memory (HBM) chip (used as a memory die 800) may be integrated with an application specific integrated circuit (ASIC) chip (used as a processor die 300) to provide a computing system with enhanced computing performance. The routing die 600 is used as a network on chip (NoC) die that provides a data path for the HBM die, and the data flow may be controlled by the ASIC die. The computing system of the present disclosure may be manufactured using a substrate through-hole structure and a hybrid bonded substrate wafer chip (CoWoS) technology. The processor die 300 may include any type of processing unit and may therefore be any type of processor die known in the art.

[0088] According to one aspect of an embodiment of the present application, a method for forming a semiconductor component is provided, comprising: attaching a plurality of processor dies to an interposer structure, the interposer structure comprising an interposer dielectric material layer having an interposer metal interconnect structure formed therein; forming a dielectric matrix around the plurality of processor dies above the interposer structure; attaching a routing die to the plurality of processor dies, wherein the routing die comprises a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing substrate through-hole structure formed therein; thinning the back side of the routing substrate to expose an end face of the routing substrate through-hole structure; and after thinning the back side of the routing substrate, attaching a memory die to the routing substrate, wherein a bonding pad of the memory die is electrically connected to the routing substrate through-hole structure.

[0089] In some embodiments, the interposer structure includes a front interposer bonding pad formed within an interposer dielectric material layer; the plurality of processor dies include a processor die substrate having a die substrate through-substrate via structure formed therein; and when the plurality of processor dies are attached to the interposer structure, the substrate through-substrate via structure is electrically connected to the front interposer bonding pad.

[0090] In some embodiments, the plurality of processor dies include backside processor bond pads on the die substrate through via structure; and when the plurality of processor dies are attached to the interposer structure, the backside processor bond pads are bonded to the front interposer bond pads via metal-to-metal bonding.

[0091] In some embodiments, the plurality of processor dies include a backside die dielectric layer laterally surrounding respective subsets of the backside processor bond pads; and the backside die dielectric layer is bonded to a surface section of the intervening dielectric material layer via dielectric-to-dielectric bonding.

[0092] In some embodiments, the interposer is disposed on a top surface of the carrier substrate; and the method includes, after thinning the back side of the routing substrate, decoupling the carrier substrate from an assembly including the interposer, the plurality of processor dies, and the routing substrate.

[0093] In some embodiments, each of the multiple processor dies includes a corresponding subset of a die dielectric material layer, in which a corresponding subset of die metal interconnect structures and a corresponding subset of front processor bonding pads are formed; a routing dielectric material layer has front routing bonding pads formed therein; and when the routing die is attached to the multiple processor dies, the front routing bonding pad is electrically connected to a corresponding one of the front processor bonding pads.

[0094] In some embodiments, a routing die is attached to multiple processor dies by performing a hybrid bonding process such that: a front routing bonding pad is bonded to a corresponding one of the front processor bonding pads via metal-to-metal bonding; and a surface of a die dielectric material layer is bonded to a surface segment of an intermediate dielectric material layer via dielectric-to-dielectric bonding.

[0095] In some embodiments, a dielectric matrix is ​​formed by depositing a dielectric material within a gap between adjacent pairs of processor dies selected from a plurality of processor dies; and removing a portion of the dielectric material from above a horizontal plane including top surfaces of the plurality of processor dies, wherein the remaining portion of the dielectric material filling the gap comprises the dielectric matrix.

[0096] In some embodiments, the method further comprises: forming a backside routing dielectric layer on the backside of the routing substrate after thinning the routing substrate; and forming a backside routing bond pad in the backside routing dielectric layer on an end surface of the routing substrate through via structure.

[0097] In some embodiments, the memory die comprises a high bandwidth memory (HBM) memory die comprising a corresponding vertical stack of dynamic random access memory (DRAM) dies; and the bonding pads of the memory die are bonded to the backside routing bonding pads via metal-to-metal bonding.

[0098] According to another aspect of an embodiment of the present application, a semiconductor component is disclosed, comprising: a plurality of processor dies bonded to an intermediate structure, the intermediate structure comprising an intermediate dielectric material layer having an intermediate metal interconnect structure formed therein; a dielectric substrate laterally surrounding the plurality of processor dies; a routing die bonded to the plurality of processor dies and comprising a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing substrate through-hole structure formed therein; and a memory die comprising a bonding pad electrically connected to the routing substrate through-hole structure.

[0099] In some embodiments, the plurality of processor dies include: a processor die substrate having a through die substrate via structure formed therein; and a backside processor bonding pad located on the through die substrate via structure and bonded to a front interposer bonding pad formed in an interposer dielectric material layer of an interposer structure.

[0100] In some embodiments, the plurality of processor dies include a backside die dielectric layer laterally surrounding the backside processor bond pad; and a surface of the backside die dielectric layer is bonded to a surface segment of the intervening dielectric material layer via dielectric-to-dielectric bonding.

[0101] In some embodiments, sidewalls of the interposer vertically coincide with sidewalls of the routing die.

[0102] In some embodiments, front routing bond pads formed in the routing dielectric material layer are bonded to front processor bond pads formed in the die dielectric material of the plurality of processor dies.

[0103] According to another aspect of an embodiment of the present application, a semiconductor component is disclosed, including: an intermediate structure, including an intermediate dielectric material layer, in which an intermediate metal interconnect structure and a front intermediate bonding pad are formed; a plurality of processor dies, formed in a dielectric matrix and including a first processor bonding pad bonded to the front intermediate bonding pad; a routing die, including a routing dielectric material layer in which a routing metal interconnect structure and a front routing bonding pad are formed, and also including a routing substrate in which a routing substrate through-hole structure is formed, wherein the front routing bonding pad is bonded to a second processor bonding pad in the plurality of processor dies; and a memory chip bonded to the routing die, wherein the memory die includes a memory die bonding pad electrically connected to the routing substrate through-hole structure.

[0104] In some embodiments, the routing die includes a backside routing dielectric layer on a backside of the routing substrate and having backside routing bond pads formed therein in contact with end surfaces of the routing substrate through via structures.

[0105] In some embodiments, the memory die includes a bond pad bonded to the backside routing bond pad via a metal-to-metal bond.

[0106] In some embodiments, sidewalls of the routing die vertically coincide with sidewalls of the dielectric matrix.

[0107] In some embodiments, the plurality of processor dies include a die dielectric material layer having a die metal interconnect structure and a front processor bonding pad formed therein; a routing dielectric material layer having a front routing bonding pad formed therein; and the front routing pad bonded to the front processor bonding pad via metal-to-metal bonding.

[0108] The above outlines the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Unless otherwise explicitly disclosed herein, each embodiment described using the word "including" also inherently discloses other embodiments, where "including" is replaced by "substantially by" or "by". Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group including two or more lists of elements is also implicitly disclosed. Whenever the auxiliary verb "may" is used in the present disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such elements or such processing steps are not performed are also explicitly considered, provided that the resulting device or apparatus can provide equivalent results. Therefore, the auxiliary verb "may" applied to the formation of an element or the execution of a processing step should also be interpreted as "may" or "may or may not", as long as the formation of such an element or processing step is omitted to provide the same result or equivalent result, and the equivalent result includes slightly better results and slightly worse results. It should be understood by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor component, comprising: attaching a plurality of processor dies to an interposer structure comprising an interposer dielectric material layer having an interposer metal interconnect structure formed therein; forming a dielectric matrix around the plurality of processor dies over the interposer; attaching a routing die to the plurality of processor dies, wherein the routing die includes a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing through substrate via structure formed therein; thinning the back side of the routing substrate to expose end faces of the routing substrate through-via structures; and After thinning the backside of the routing substrate, a memory die is attached to the routing substrate, wherein bond pads of the memory die are electrically connected to the routing substrate through-substrate via structures.

2. The method according to claim 1, wherein: The interposer structure includes a front interposer bonding pad formed within the interposer dielectric material layer; The plurality of processor dies includes a processor die substrate having a through die substrate via structure formed therein; as well as The through substrate via structure is electrically connected to the front interposer bond pad when the plurality of processor dies are attached to the interposer structure.

3. The method according to claim 2, wherein: the plurality of processor dies including backside processor bond pads located on the die substrate through via structures; as well as When attaching the plurality of processor dies to the interposer structure, the backside processor bond pads are bonded to the front interposer bond pads via metal-to-metal bonding.

4. The method according to claim 3, wherein: The plurality of processor dies include a backside die dielectric layer laterally surrounding a respective subset of the backside processor bond pads; and The backside die dielectric layer is bonded to a surface section of the intervening dielectric material layer via dielectric-to-dielectric bonding.

5. The method according to claim 1, wherein: The interposer is disposed on a top surface of a carrier substrate; and The method includes, after thinning the backside of the routing substrate, decoupling the carrier substrate from an assembly including the interposer, the plurality of processor dies, and the routing substrate.

6. The method according to claim 1, wherein: Each of the plurality of processor dies includes a respective subset of die dielectric material layers having formed therein a respective subset of die metal interconnect structures and a respective subset of pre-processor bond pads; The routing dielectric material layer has a front routing bonding pad formed therein; as well as The front routing bond pad is electrically connected to a corresponding one of the front processor bond pads when the routing die is attached to the plurality of processor dies.

7. The method according to claim 6, wherein: The routing die is attached to the plurality of processor dies by performing a hybrid bonding process such that: The front routing bond pad is bonded to a corresponding one of the front processor bond pads via a metal-to-metal bond; and A surface of the die dielectric material layer is bonded to a surface section of the intervening dielectric material layer via dielectric-to-dielectric bonding.

8. The method according to claim 1, wherein: The dielectric matrix is ​​formed by the following steps: depositing a dielectric material within gaps between adjacent pairs of processor dies selected from the plurality of processor dies; as well as Portions of the dielectric material are removed from above a level that includes top surfaces of the plurality of processor dies, wherein remaining portions of the dielectric material filling the gaps include the dielectric matrix.

9. A semiconductor component comprising: a plurality of processor dies bonded to an interposer structure including an interposer dielectric material layer having an interposer metal interconnect structure formed therein; a dielectric substrate laterally surrounding the plurality of processor dies; a routing die bonded to the plurality of processor dies and comprising a routing dielectric material layer having a routing metal interconnect structure formed therein and a routing substrate having a routing through substrate via structure formed therein; as well as A memory die includes a bonding pad electrically connected to the routing through substrate via structure.

10. A semiconductor component comprising: An interposer structure includes an interposer dielectric material layer having an interposer metal interconnect structure and a front interposer bonding pad formed therein; a plurality of processor dies formed within the dielectric matrix and including a first processor bond pad bonded to the front interposer bond pad; a routing die including a routing dielectric material layer having a routing metal interconnect structure and a front routing bond pad formed therein, and further including a routing substrate having a routing through substrate via structure formed therein, wherein the front routing bond pad is bonded to a second processor bond pad within the plurality of processor dies; A memory chip is bonded to a routing die, wherein the memory die includes a memory die bond pad electrically connected to the routing through substrate via structure.

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