Integrated wafer packaging structure and packaging method thereof

Abstract

The invention discloses an integrated wafer packaging structure and a packaging method thereof, which can greatly avoid the waste of the area of a tube core and improve the integration level of a chip by preparing a groove and a cavity in a scribing channel. The first passivation layer comprises a first sub-passivation layer located on the first pressure welding blocks on one side of the first tube core substrate, a second sub-passivation layer located between the first pressure welding blocks and covering part of the first pressure welding blocks, and a third sub-passivation layer located on the other side of the first tube core substrate and covering part of the first pressure welding blocks. The second passivation layer comprises a fourth sub-passivation layer which is located between the second pressure welding blocks and covers part of the second pressure welding blocks and fifth sub-passivation layers which are located on the two sides of the second tube core substrate and cover part of the second pressure welding blocks, and a third passivation layer and the fourth passivation layer are formed on the side wall of the groove for passivation layer protection. Pollutants such as movable charges are prevented from invading from the side wall, the reliability of the device is improved, the thickness of the wafer can be further reduced, the groove depth of the scribing channel and the size of the cavity are adjusted according to requirements, and the cost of the chip is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing and packaging, and in particular relates to an integrated wafer packaging structure and a packaging method thereof. Background Art

[0002] Electronic devices and chips are developing in the direction of modularization and intelligence. The emergence of large-scale and ultra-large-scale integrated circuits has led to higher and higher integration of power electronic devices. The number and density of various chips assembled on the substrate are also increasing to reduce the volume of power electronic modules and further increase the power density. After the front process of the wafer is completed, in order to improve the performance and heat dissipation capacity of the power chip, the wafer is usually thinned. The thinning thickness is usually between 50μm-250μm according to the needs. After the thinning is completed, some power device products also need to grow metal on the back of the wafer. Then the wafer is shipped to the packaging factory, where the wafer is cut and diced, and then the pellets are packaged. However, how to reduce the size of the dicing road (the reduction of the dicing road size can directly reduce the chip cost) and reduce the dicing damage while ensuring the device yield, and improve the reliability of the device has always been the focus of scientific researchers. Therefore, it is urgent to provide an integrated wafer packaging structure and a packaging method thereof to solve the above-mentioned technical problems. Summary of the invention

[0003] In view of this, the present invention provides an integrated wafer packaging structure and a packaging method thereof, which can reduce the size of the dicing lanes, improve the utilization rate of the wafer, and avoid the problems of edge chipping and stress damage during cutting. The following technical solutions are specifically adopted to achieve this.

[0004] In a first aspect, the present invention provides an integrated wafer packaging structure, comprising: a first adhesive layer; A wafer packaging structure located on the first adhesion layer, the wafer packaging structure comprising at least two first tube core substrates arranged at intervals, a second tube core substrate located between the two first tube core substrates, first bonding blocks formed on the upper surface of the first tube core substrates and arranged at intervals, a first passivation layer located on the first bonding blocks and the first tube core substrate, second bonding blocks formed on the upper surface of the second tube core substrate and arranged at intervals, and a second passivation layer on the second bonding blocks; a scribe line located between the first tube core substrate and the second tube core substrate, the scribe line comprising a groove, and a cavity extending from the sidewall direction of the groove to the first adhesion layer, and a third passivation layer and a fourth passivation layer are formed on the first tube core substrate and the second tube core substrate corresponding to the sidewall of the groove, respectively; The first passivation layer includes a first sub-passivation layer located on the first bonding pad on one side of the first die substrate, a second sub-passivation layer located between the first bonding pads and covering a portion of the first bonding pad, and a third sub-passivation layer located on the other side of the first die substrate and covering a portion of the first bonding pad; the second passivation layer includes a fourth sub-passivation layer located between the second bonding pads and covering a portion of the second bonding pad, and a fifth sub-passivation layer located on both sides of the second die substrate and covering a portion of the second bonding pad; The wafer packaging structure also includes a first metal layer located on the lower surface of the first tube core substrate and the side wall of the cavity, and a second metal layer located on the lower surface of the second tube core substrate and the side wall of the cavity. The first metal layer on the lower surface of the first tube core substrate and the second metal layer on the lower surface of the second tube core substrate are both connected to the first adhesion layer.

[0005] As a preferred embodiment of the above technical solution, the first adhesion layer is a blue film, and the width of the groove in a direction parallel to the first adhesion layer is smaller than the diameter of the cavity.

[0006] As a preferred embodiment of the above technical solution, the size of the scribe line is 5-10 μm.

[0007] As a preferred embodiment of the above technical solution, the depth of the groove is 40-100 μm, and the diameter of the cavity is 20-60 μm.

[0008] In a second aspect, the present invention further provides a packaging method for an integrated wafer packaging structure, comprising the following steps: Providing a wafer, forming at least two first tube core substrates arranged at intervals, a second tube core substrate located between the two first tube core substrates, and a scribe line located between the first tube core substrate and the second tube core substrate on the upper surface of the wafer; Forming first and second bonding blocks arranged at intervals on the upper surface of the first tube core substrate and the upper surface of the second tube core substrate respectively, and performing photolithography etching on the scribe line to form a groove; Depositing a passivation layer on the first bonding block, the first tube core substrate, the second bonding block, the second tube core substrate and the groove, and photolithographically etching the passivation layer to form a first passivation layer located on the first bonding block and the first tube core substrate, a second passivation layer on the second bonding block and the second tube core substrate, a third passivation layer and a fourth passivation layer on the sidewall of the groove, wherein the first passivation layer includes a first sub-passivation layer located on the first bonding block on one side of the first tube core substrate, a second sub-passivation layer located between the first bonding blocks and covering a portion of the first bonding block, and a third sub-passivation layer located on the other side of the first tube core substrate and covering a portion of the first bonding block; the second passivation layer includes a fourth sub-passivation layer located between the second bonding blocks and covering a portion of the second bonding block, and a fifth sub-passivation layer located on both sides of the second tube core substrate and covering a portion of the second bonding block; Chemically etching the groove to form a cavity extending from the groove sidewall to the lower surface of the wafer, and bonding the first sub-passivation layer, the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer and the fifth sub-passivation layer with a second adhesive layer; Turning over the wafer and performing thinning and polishing on the lower surface of the wafer, removing the wafer extending along the cavity toward the second adhesion layer to separate the first tube die corresponding to the first tube die substrate and the second tube die corresponding to the second tube die substrate on both sides of the dicing road; Metal growth is performed on the lower surfaces of the first tube core, the second tube core and the sidewalls of the cavity to obtain a first metal layer and a second metal layer, and a first adhesion layer is bonded to the first metal layer and the second metal layer, and the second adhesion layer is removed to obtain a wafer packaging structure.

[0009] As a preferred embodiment of the above technical solution, after depositing a passivation layer on the first bonding block, the first die substrate, the second bonding block, the second die substrate and the groove, the method comprises: Applying photoresist to the passivation layer located on the upper surface of the first bonding pad, between the first bonding pads, the scribe line, between the second bonding pads, and on the upper surface of the second bonding pad; Performing photolithography etching on the first bonding pad, the second bonding pad, and the passivation layer at the bottom of the groove to expose the first bonding pad and the second bonding pad, and retaining the passivation layer on the sidewall of the groove to obtain the third sub-passivation layer and the fourth sub-passivation layer; The trench is chemically etched to form a cavity extending from the sidewall of the trench to the first adhesion layer.

[0010] As a preferred embodiment of the above technical solution, the chemical etching adopts isotropic etching, and the diameter of the cavity is 20-60 μm.

[0011] As a preferred embodiment of the above technical solution, the remaining photoresist is removed, and paraffin is used to adhere the second adhesive layer, the material of the second adhesive layer is an ordinary silicon wafer or a transparent quartz liner, and the thickness of the second adhesive layer is 200-600 μm.

[0012] As a preferred embodiment of the above technical solution, the stop position for thinning and polishing the lower surface of the wafer is the center of the cavity, and the first adhesion layer is a blue film.

[0013] As a preferred embodiment of the above technical solution, the depth from the upper surface of the wafer to the bottom of the cavity is 80-160 μm, the spacing between the first tube core and the second tube core is 5-20 μm, and the size of the dicing road is 5-10 μm.

[0014] The present invention provides an integrated wafer packaging structure and a packaging method thereof. By preparing a groove in a dicing road and a cavity extending from the side wall direction of the groove to the lower surface of the wafer, waste of the tube core area can be greatly avoided, and the integration of the chip is improved. The first passivation layer includes a first sub-passivation layer located on a first pressure welding block on one side of the first tube core substrate, a second sub-passivation layer located between the first pressure welding blocks and covering a part of the first pressure welding block, and a third sub-passivation layer located on the other side of the first tube core substrate and covering a part of the first pressure welding block. The second passivation layer includes a fourth sub-passivation layer located between the second pressure welding blocks and covering a part of the second pressure welding block, and a fifth sub-passivation layer located on both sides of the second tube core substrate and covering a part of the second pressure welding block. The third passivation layer and the fourth passivation layer are formed on the side wall of the groove for passivation layer protection, so as to prevent pollutants such as movable charges from invading from the side wall, thereby improving the working reliability of the device. The thickness of the wafer can be further thinned, and the groove depth and cavity size of the dicing road are adjusted according to needs, so as to reduce the chip cost and further improve the special needs of various tube cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of the structure of the integrated wafer packaging structure provided by the present invention; Figure 2 A flow chart of a packaging method for an integrated wafer packaging structure provided by the present invention; Figures 3 to 12 A packaging process diagram of the integrated wafer packaging structure provided by the present invention.

[0017] The main component symbols are described as follows: 10-first adhesion layer; 20-first tube core substrate; 30-second tube core substrate; 40-first welding block; 50-first passivation layer; 60-second welding block; 70-second passivation layer; 80-slice road; 90-groove; 100-cavity; 110-first sub-passivation layer; 120-second sub-passivation layer; 130-third sub-passivation layer; 140-fourth sub-passivation layer; 150-fifth sub-passivation layer; 160-third passivation layer; 170-fourth passivation layer; 180-first tube core; 190-second tube core; 200-first metal layer; 210-second metal layer; 220-second adhesion layer; 230-photoresist. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0020] See also Figure 1 The present invention provides an integrated wafer packaging structure, comprising: A first adhesive layer 10; A wafer packaging structure located on the first adhesion layer 10, the wafer packaging structure comprising at least two first tube core substrates 20 arranged at intervals, a second tube core substrate 30 located between the two first tube core substrates 20, first bonding blocks 40 formed on the upper surface of the first tube core substrates 20 and arranged at intervals, a first passivation layer 50 located on the first bonding blocks 40 and the first tube core substrate 20, second bonding blocks 60 formed on the upper surface of the second tube core substrate 30 and arranged at intervals, and a second passivation layer 70 on the second bonding blocks 60; a scribe line 80 located between the first tube core substrate 20 and the second tube core substrate 30, the scribe line 80 comprising a groove 90, a cavity 100 extending from the side wall direction of the groove 90 to the first adhesion layer 10, a third passivation layer 160 and a fourth passivation layer 170 are respectively formed on the first tube core substrate 20 and the second tube core substrate 30 corresponding to the side wall of the groove 90; the first passivation layer 50 comprises a first sub-passivation layer 110 located on the first bonding block 40 on one side of the first tube core substrate 20, a second sub-passivation layer 120 located between the first bonding blocks 40 and covering a part of the first bonding block 40, and a third sub-passivation layer 130 located on the other side of the first tube core substrate 20 and covering a part of the first bonding block 40; the second passivation layer 70 comprises a fourth sub-passivation layer 140 located between the second bonding blocks 60 and covering a part of the second bonding blocks 60, and a fifth sub-passivation layer 150 located on both sides of the second tube core substrate 30 and covering a part of the second bonding blocks 60; The wafer packaging structure also includes a first metal layer 200 located on the lower surface of the first tube core substrate 20 and the side wall of the cavity 100, and a second metal layer 210 located on the lower surface of the second tube core substrate 30 and the side wall of the cavity 100. The first metal layer 200 on the lower surface of the first tube core substrate 20 and the second metal layer 210 on the lower surface of the second tube core substrate 30 are both connected to the first adhesion layer 10.

[0021] In this embodiment, the pad (PAD) is an intermediate node connecting the internal circuit of the integrated circuit and the external package pin (Pin). The PAD is composed of the top metal in the integrated circuit and has an opening of a certain size. The specific PAD position is generally located at the edge of the entire chip. For some chips, the PAD position will be slightly away from the edge of the chip according to special needs. The first pad 40 and the second pad 60 are preferably of the same size and made of the same metal. The die is a tiny electronic device, usually made of semiconductor materials. It integrates a large number of circuit elements to achieve specific circuit functions. The size of the die is usually very small, perhaps only a few millimeters or even smaller, but it contains hundreds of millions of transistors and other circuit elements inside. These elements are interconnected by fine metal wires to form a complex circuit network. The first adhesion layer 10 is a blue film, the width of the groove 90 in the direction parallel to the first adhesion layer 10 is smaller than the diameter of the cavity 100, the size of the scribe line 80 is 5-10 μm, the depth of the groove 90 is 40-100 μm, the diameter of the cavity 100 is 20-60 μm, the cavity 100 is semicircular, the groove 90 and the cavity 100 are combined to form a funnel shape, the side wall of the cavity 100 is grown metal by magnetron sputtering or evaporation, and there are a third passivation layer 160 and a fourth passivation layer 170 on the side wall of the groove 90. The passivation of the side wall of the groove 90 can prevent pollutants such as movable charges from invading from the side wall, thereby improving the working reliability of the device.

[0022] It should be noted that in traditional processes, the chip size and spacing can be defined through processes such as lithography, etching, and diffusion, as well as the size of the scribe lane 80. In order to ensure that the subsequent diamond scribe will not damage the die, the reserved scribe lane 80 size is usually between 50 and 100 μm. If the chip size is small, the scribe lane 80 will greatly occupy the wafer area. When the die size is below 500 μm, the wafer area wasted by the scribe lane 80 will exceed 20%. In the actual scribe process, due to mechanical stress, it is inevitable that there will be a certain amount of edge collapse. When the edge collapse is too large, it will directly damage the die. In addition, due to the effect of mechanical stress, devices with normal computing surfaces may also potentially be damaged to a certain extent, thereby affecting the reliability of the device. When the wafer is very thin, it is easy to cause wafer fragments during mechanical scribe, and the die will be set with a lead frame for subsequent packaging. Therefore, the present invention prepares a groove 90 on the scribe line 80 and forms a cavity 100 under the groove 90, which can reduce the size of the scribe line 80 on the wafer from the traditional 50~100μm to 10μm, thereby improving the utilization rate of the wafer, and eliminating the physical cutting of the wafer through a special process, avoiding the problems of edge chipping and stress damage caused by cutting. The side walls of the device layer of the wafer are covered with a passivation layer for protection, thereby improving the reliability of the device.

[0023] It should be understood that by preparing a groove 90 in the scribe line 80 and a cavity 100 extending from the side wall direction of the groove 90 to the first adhesion layer 10, a third passivation layer 160 and a fourth passivation layer 170 are respectively formed on the first tube core substrate 20 and the second tube core substrate 30 corresponding to the side wall of the groove 90, which can greatly avoid the waste of tube core area and improve the integration of the chip; the first passivation layer 50 includes a first sub-passivation layer 110 located on the first bonding block 40 on one side of the first tube core substrate 20, a second sub-passivation layer 120 located between the first bonding blocks 40 and covering a portion of the first bonding blocks 40, and a second sub-passivation layer 120 located on the other side of the first tube core substrate 20 and the side wall of the groove 90 and covering a portion of the first bonding block 40. The third sub-passivation layer 130 of the block 40, the second passivation layer 70 includes a fourth sub-passivation layer 140 located between the second welding blocks 60 and covering a portion of the second welding blocks 60, and a fifth sub-passivation layer 150 located on both sides of the second tube core substrate 30 and the side wall of the groove 90 and covering a portion of the second welding block 60. The third passivation layer 160 and the fourth passivation layer 170 are formed on the side wall of the groove 90 for passivation layer protection to prevent contaminants such as movable charges from invading from the side wall, thereby improving the working reliability of the device; the thickness of the wafer can be further thinned, and the depth of the groove 90 of the dicing street 80 and the size of the cavity 100 can be adjusted according to needs to reduce chip costs and further improve the special needs of various tube cores.

[0024] See also Figure 2 , Figures 3 to 12 The present invention also provides a packaging method for an integrated wafer packaging structure, comprising the following steps: S1: providing a wafer, and forming at least two first tube core substrates 20 arranged at intervals, a second tube core substrate 30 located between the two first tube core substrates 20, and a scribe line 80 located between the first tube core substrate 20 and the second tube core substrate 30 on the upper surface of the wafer; In this embodiment, Figure 3 As shown, a wafer refers to a silicon wafer used to make silicon semiconductor circuits. Its original material is silicon. After high-purity polycrystalline silicon is melted, silicon crystal seeds are added, and then slowly pulled out to form a cylindrical single crystal silicon. After grinding, polishing, and slicing, the silicon crystal rod forms a silicon wafer, i.e., a wafer. The first tube core substrate 20 and the second tube core substrate 30 are both silicon wafers; there are usually hundreds to thousands of chips connected together on a wafer, and a certain gap is left between them for easy dicing. The gap can be called a dicing road 80. The chip size and spacing are defined by processes such as photolithography, etching, and diffusion, and the size of the dicing road 80 is determined. In order to ensure that the subsequent diamond dicing will not damage the tube core, the size of the reserved dicing road 80 is usually between 50 and 100 μm.

[0025] S2: forming first bonding blocks 40 and second bonding blocks 60 arranged at intervals on the upper surface of the first tube core substrate 20 and the upper surface of the second tube core substrate 30 respectively, and performing photolithography etching on the scribe line 80 to form a groove 90; In this embodiment, Figure 4 and Figure 5 As shown, after the scribe line 80 is determined, the device layer is completed, and metal interconnection needs to be made on the tube core, that is, the first pressure welding block 40 and the second pressure welding block 60 are formed. Preferably, the spacing between the first pressure welding block 40 and the second pressure welding block 60 is equal, and the spacing between every two first pressure welding blocks 40 and the spacing between every two second pressure welding blocks 60 are equal. The specific process is: the spacing between the device layer and the chip is defined by photolithography, and the spacing of the chip can be about 5-20μm, which is much smaller than the 50-100μm of the traditional process; then the scribe line 80 is photolithographically etched, and the width of the scribe line 80 is about 5-10μm. The etching depth is determined according to the final tube core thickness, usually between 40-100μm.

[0026] S3: depositing a passivation layer on the first bonding block 40, the first tube core substrate 20, the second bonding block 60, the second tube core substrate 30 and the groove 90, and photolithographically etching the passivation layer to form a first passivation layer 50 located on the first bonding block 40 and the first tube core substrate 20, a second passivation layer 70 on the second bonding block 60 and the second tube core substrate 30, a third passivation layer 160 and a fourth passivation layer 170 on the sidewall of the groove 90, wherein the first passivation layer 50 includes a first bonding block located on one side of the first tube core substrate 20 The first passivation layer 110 on the first die substrate 40, the second passivation layer 120 located between the first die substrate 40 and covering a portion of the first die substrate 40, and the third passivation layer 130 located on the other side of the first die substrate 20 and covering a portion of the first die substrate 40; the second passivation layer 70 includes a fourth passivation layer 140 located between the second die substrate 60 and covering a portion of the second die substrate 60, and a fifth passivation layer 150 located on both sides of the second die substrate 30 and the sidewalls of the groove 90 and covering a portion of the second die substrate 60; In this embodiment, Figure 6 As shown, the passivation layer is deposited and photolithography is performed: first, a passivation layer is deposited in the first welding block 40, the second welding block 60 and the groove 90, a photoresist 230 is coated and a portion of the photoresist is removed by etching to expose the welding block. At this time, the passivation layer is evenly grown on the inner side wall and the bottom of the groove 90, and the passivation layer at the bottom of the groove 90 is etched and the side wall is retained.

[0027] S4: chemically etching the groove 90 to form a cavity 100 extending from the sidewall of the groove 90 to the lower surface of the wafer, and bonding the first sub-passivation layer 110, the second sub-passivation layer 120, the third sub-passivation layer 130, the fourth sub-passivation layer and the fifth sub-passivation layer 150 with a second adhesion layer 220; In this embodiment, Figure 7 and Figure 8 As shown, after the passivation layer is deposited on the first welding block 40, the first tube core substrate 20, the second welding block 60, the second tube core substrate 30 and the groove 90, the method includes: coating the passivation layer located on the upper surface of the first welding block 40, between the first welding blocks 40, the scribe line 80, between the second welding blocks 60 and the upper surface of the second welding block 60 with a photoresist 230; photolithography is performed on the passivation layer at the bottom of the first welding block 40, the second welding block 60 and the groove 90 to expose the first welding block 40 and the second welding block 60, and the passivation layer on the side wall of the groove 90 is retained to obtain the third passivation layer 160 and the fourth passivation layer 170; the groove 90 is chemically corroded to form a cavity 100 extending from the side wall direction of the groove 90 to the lower surface of the wafer. The wafer is chemically etched inside the groove 90, preferably isotropically, because the sidewalls are protected by the passivation layer, and the etching starts from the bottom, and finally a cavity 100 is formed inside the wafer. The diameter of the cavity 100 is about 20-60μm, and the final depth from the wafer surface to the bottom of the cavity 100 is about 80-160μm. The cavity 100 is etched using a chemical etching (wet etching) method. After the etching is completed, the surface stress of the wafer can be eliminated to a certain extent, preventing the wafer from warping and deformation during the manufacturing process. Among them, HF or HNO3 can be used for chemical etching. Wafer warping refers to the bending or twisting of the wafer during the packaging process. Wafer warping may cause alignment deviation, welding problems and device performance degradation during the packaging process.

[0028] S5: turning over the wafer and performing thinning and polishing on the lower surface of the wafer, removing the wafer extending along the cavity 100 toward the second adhesive layer 220 to separate the first tube die 180 corresponding to the first tube die substrate 20 and the second tube die 190 corresponding to the second tube die substrate 30 on both sides of the dicing road 80; In this embodiment, Fig. 9 and Fig.10After removing all the photoresist 230, the front side is adhered with paraffin or other easily removable adhesives to adhere the liner, i.e., the second adhesive layer 220. The thickness of the liner is between 200-600 μm, and the liner can be a common silicon wafer or a transparent quartz wafer. Turn over the wafer and perform thinning and polishing on the back side of the wafer. The thinning stop position is preferably at the center of the cavity 100. At this time, the tube core is completely separated from the scribe line 80, and the back side corners of the tube core (cavity sidewall) are removed. The distance between the first tube core 180 and the second tube core 190 on the back side is enlarged, so that it is not easy to stick together and is easier to separate in the subsequent metallization and film pasting and tearing processes. Among them, the stopping position for thinning and polishing the lower surface of the wafer is the center position of the cavity 100, the depth from the upper surface of the wafer to the bottom of the cavity 100 is 80~160μm, the spacing between the first tube core 180 and the second tube core 190 is 5~20μm, and the size of the dicing road 80 is 5~10μm.

[0029] S6: Perform metal growth on the lower surfaces of the first tube core 180, the second tube core 190 and the sidewalls of the cavity 100 to obtain the first metal layer 200 and the second metal layer 210, and adhere the first adhesion layer 10 to the first metal layer 200 and the second metal layer 210, and remove the second adhesion layer 220 to obtain a wafer packaging structure.

[0030] In this embodiment, Fig.11 and Fig.12 As shown, a metal layer is grown on the back of the wafer through evaporation, electroplating and other processes. The vertical side walls of the tube core are protected by a passivation layer and cannot be grown by evaporation or electroplating. However, metal will still grow at the sharp corners of the tube core on the back. Then a blue film is applied to the back, and the front lining is removed by heating and melting paraffin. The adhesive is cleaned with an organic solvent such as acetone. At this time, the tube cores on the wafer are separated, and the tube cores are completely transferred from the lining to the blue film. After that, the normal packaging process can be used for particle selection packaging. The first adhesive layer 10 is a blue film, which is also called electronic grade tape. It is known for its low cost and good Toughness and chemical stability have a place in the semiconductor industry. Its main features include: (1) Protecting the wafer surface: Blue film has strong toughness and can effectively prevent the wafer from being damaged during the cutting process, thereby protecting the integrity of the wafer; (2) Improving process stability: Blue film is resistant to high temperatures and has stable chemical properties. It can maintain good physical and chemical properties during the dicing process, reduce process fluctuations caused by environmental changes, and improve the stability of the overall process; (3) Improving cutting accuracy: Blue film can ensure that the wafer remains stable during the cutting process, making the cutting lines smoother, thereby improving the cutting accuracy of the chip.

[0031] It should be noted that the advantages of the present invention over the traditional process are: (1) the size of the dicing lane 80 can be reduced from the traditional 50-100 μm to 5-10 μm, which can greatly avoid the waste of the die area, improve the chip integration, and reduce the chip cost; (2) the traditional dicing process is abandoned, the dicing edge collapse and fragmentation are avoided, the packaging cost is reduced, the mechanical stress of dicing is eliminated, and the reliability of the die is improved; (3) the device layer on the side wall of the die is covered with a passivation layer for protection to prevent contaminants such as movable charges from invading from the side wall, thereby improving the reliability of the device; (4) due to the presence of the liner, the thickness of the wafer can be further thinned. The groove depth and cavity size of the dicing lane can be adjusted as needed, and it can be thinned to less than 10 μm, further meeting the special needs of various dies.

[0032] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0034] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An integrated wafer packaging structure, characterized in that: include: a first adhesive layer; A wafer packaging structure located on the first adhesion layer, the wafer packaging structure comprising at least two first tube core substrates arranged at intervals, a second tube core substrate located between the two first tube core substrates, first bonding blocks formed on the upper surface of the first tube core substrates and arranged at intervals, a first passivation layer located on the first bonding blocks and the first tube core substrate, second bonding blocks formed on the upper surface of the second tube core substrate and arranged at intervals, and a second passivation layer on the second bonding blocks; A scribe line located between the first tube core substrate and the second tube core substrate, the scribe line comprising a groove, a cavity extending from the side wall of the groove to the first adhesion layer, and a third passivation layer and a fourth passivation layer formed on the first tube core substrate and the second tube core substrate corresponding to the side wall of the groove, respectively; The first passivation layer includes a first sub-passivation layer located on the first bonding pad on one side of the first die substrate, a second sub-passivation layer located between the first bonding pads and covering a portion of the first bonding pad, and a third sub-passivation layer located on the other side of the first die substrate and covering a portion of the first bonding pad; the second passivation layer includes a fourth sub-passivation layer located between the second bonding pads and covering a portion of the second bonding pad, and a fifth sub-passivation layer located on both sides of the second die substrate and covering a portion of the second bonding pad; The wafer packaging structure also includes a first metal layer located on the lower surface of the first tube core substrate and the side wall of the cavity, and a second metal layer located on the lower surface of the second tube core substrate and the side wall of the cavity. The first metal layer on the lower surface of the first tube core substrate and the second metal layer on the lower surface of the second tube core substrate are both connected to the first adhesion layer.

2. The integrated wafer packaging structure according to claim 1, characterized in that: The first adhesion layer is a blue film, and the width of the groove in a direction parallel to the first adhesion layer is smaller than the diameter of the cavity.

3. The integrated wafer packaging structure according to claim 2, characterized in that: The size of the scribe line is 5-10 μm.

4. The integrated wafer packaging structure according to claim 2, characterized in that: The depth of the groove is 40-100 μm, and the diameter of the cavity is 20-60 μm.

5. A packaging method for an integrated wafer packaging structure, characterized in that: The following steps are involved: Providing a wafer, forming at least two first tube core substrates arranged at intervals, a second tube core substrate located between the two first tube core substrates, and a scribe line located between the first tube core substrate and the second tube core substrate on the upper surface of the wafer; Forming first and second bonding blocks arranged at intervals on the upper surface of the first tube core substrate and the upper surface of the second tube core substrate respectively, and performing photolithography etching on the scribe line to form a groove; Depositing a passivation layer on the first bonding block, the first tube core substrate, the second bonding block, the second tube core substrate and the groove, and photolithographically etching the passivation layer to form a first passivation layer located on the first bonding block and the first tube core substrate, a second passivation layer on the second bonding block and the second tube core substrate, a third passivation layer and a fourth passivation layer on the sidewall of the groove, wherein the first passivation layer includes a first sub-passivation layer located on the first bonding block on one side of the first tube core substrate, a second sub-passivation layer located between the first bonding blocks and covering a portion of the first bonding block, and a third sub-passivation layer located on the other side of the first tube core substrate and covering a portion of the first bonding block; the second passivation layer includes a fourth sub-passivation layer located between the second bonding blocks and covering a portion of the second bonding block, and a fifth sub-passivation layer located on both sides of the second tube core substrate and covering a portion of the second bonding block; Chemically etching the groove to form a cavity extending from the groove sidewall to the lower surface of the wafer, and bonding the first sub-passivation layer, the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer and the fifth sub-passivation layer with a second adhesive layer; Turning over the wafer and performing thinning and polishing on the lower surface of the wafer, removing the wafer extending along the cavity toward the second adhesion layer to separate the first tube die corresponding to the first tube die substrate and the second tube die corresponding to the second tube die substrate on both sides of the dicing road; Metal growth is performed on the lower surfaces of the first tube core, the second tube core and the sidewalls of the cavity to obtain a first metal layer and a second metal layer, and a first adhesion layer is bonded to the first metal layer and the second metal layer, and the second adhesion layer is removed to obtain a wafer packaging structure.

6. The packaging method of the integrated wafer packaging structure according to claim 5, characterized in that: After depositing a passivation layer on the first bonding block, the first die substrate, the second bonding block, the second die substrate and the groove, the method comprises: Applying photoresist to the passivation layer located on the upper surface of the first bonding pad, between the first bonding pads, the scribe line, between the second bonding pads, and on the upper surface of the second bonding pad; Performing photolithography etching on the first bonding pad, the second bonding pad, and the passivation layer at the bottom of the groove to expose the first bonding pad and the second bonding pad, and retaining the passivation layer on the sidewall of the groove to obtain the third sub-passivation layer and the fourth sub-passivation layer; The trench is chemically etched to form a cavity extending from the sidewall of the trench to the first adhesion layer.

7. The packaging method of the integrated wafer packaging structure according to claim 6, characterized in that: The chemical etching adopts isotropic etching, and the diameter of the cavity is 20-60 μm.

8. The packaging method of the integrated wafer packaging structure according to claim 6, characterized in that: Also includes: The remaining photoresist is removed, and the second adhesive layer is adhered with paraffin wax. The material of the second adhesive layer is a common silicon wafer or a transparent quartz liner, and the thickness of the second adhesive layer is 200-600 μm.

9. The packaging method of the integrated wafer packaging structure according to claim 5, characterized in that: The stop position for thinning and polishing the lower surface of the wafer is the center position of the cavity, and the first adhesion layer is a blue film.

10. The packaging method of the integrated wafer packaging structure according to claim 5, characterized in that: The depth from the upper surface of the wafer to the bottom of the cavity is 80-160 μm, the spacing between the first tube core and the second tube core is 5-20 μm, and the size of the dicing road is 5-10 μm.

Images