Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first substrate, a first semiconductor chip on an upper surface of the first substrate, a first bump between the first substrate and the first semiconductor chip, a first underfill layer filling a central portion of a space between the first substrate and the first semiconductor chip, and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling a peripheral portion of a space between the first substrate and the first semiconductor chip, a volume occupied by the first molding member in a space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0153099 filed in the Korean Intellectual Property Office on November 7, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, to a semiconductor package having improved reliability and a method of manufacturing the semiconductor package. Background Art

[0004] Recently, the demand for portable devices in the electronic product market has increased rapidly, and therefore, there is a continuous need for miniaturization and light weight of electronic components mounted on electronic products. In order to miniaturize electronic components and make them light, it is necessary for the semiconductor packages mounted thereon to process a large amount of data while reducing defects of the semiconductor packages.

[0005] Currently, a molding process of molding a semiconductor chip using a sealing resin such as epoxy molded plastic (EMC) is performed to prevent the semiconductor chip from being damaged by external impact, light, etc. In the trend of gradual reduction in thickness of semiconductor packages, the size of the space between the semiconductor chip and the substrate is also reduced, and thus, a problem of generating a void in the space arises. Summary of the invention

[0006] Embodiments of the present disclosure provide a semiconductor package that reduces a gap generated between a first semiconductor chip and a first substrate, and a method of manufacturing the semiconductor package.

[0007] Furthermore, problems solved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and other problems solved by the embodiments of the present disclosure may be clearly understood by a person of ordinary skill in the art from the following description.

[0008] According to an aspect of an embodiment, a semiconductor package is provided, comprising: a first substrate; a first semiconductor chip located on an upper surface of the first substrate; at least one first bump located between the first substrate and the first semiconductor chip, the at least one first bump being configured to electrically connect the first substrate to the first semiconductor chip; a first bottom filling layer filling a central portion of a space between the first substrate and the first semiconductor chip; and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling a peripheral portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first bottom filling layer in the space between the first substrate and the first semiconductor chip.

[0009] According to one aspect of an embodiment, a semiconductor package is provided, comprising: a first substrate; a first semiconductor chip located on an upper surface of the first substrate; at least one first bump located between the first substrate and the first semiconductor chip and configured to electrically connect the first substrate to the first semiconductor chip, the thickness of the at least one first bump in a vertical direction being equal to or less than 10 μm; a first bottom filling layer filling a central portion of a space between the first substrate and the first semiconductor chip; and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling a peripheral portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first bottom filling layer in the space between the first substrate and the first semiconductor chip, and wherein a volume occupied by the first bottom filling layer in an area other than a volume occupied by the at least one first bump in the space between the first substrate and the first semiconductor chip is in a range of 5% to 50%.

[0010] According to an aspect of an embodiment, a semiconductor package is provided, the semiconductor package comprising: a first substrate including wiring and an insulating layer surrounding the wiring; a first semiconductor chip located on an upper surface of the first substrate; at least one first bump located between the first substrate and the first semiconductor chip and configured to electrically connect the first substrate to the first semiconductor chip, each of the at least one first bump having a thickness in a vertical direction of equal to or less than 10 μm; a first underfill layer filling a central portion of a space between the first substrate and the first semiconductor chip; and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling the first underfill layer. A peripheral portion of a space between a substrate and a first semiconductor chip, wherein each of a first molding member and a first bottom filling layer includes a filler, a filler content of the first bottom filling layer is in a range of 70% to 90%, and a filler content of the first molding member is in a range of 5% to 40%, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first bottom filling layer, and wherein, in the space between the first substrate and the first semiconductor chip, a volume occupied by the first bottom filling layer in an area other than a volume occupied by at least one first bump is in a range of 5% to 50%.

[0011] According to one aspect of an embodiment, a method for manufacturing a semiconductor package is provided, the method comprising: preparing a carrier substrate; attaching a first substrate to the carrier substrate; arranging a first semiconductor chip on an upper surface of the first substrate; forming a first structure by arranging a first bottom filling ball adjacent to a side wall of the first semiconductor chip on the upper surface of the first substrate; providing the first structure to a molding device; and compressing the first molding ball onto the first structure by closing the molding device, wherein after compressing the first molding ball, in a space between the first substrate and the first semiconductor chip, a volume of the first bottom filling ball is smaller than a volume of the first molding ball. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1A is a schematic cross-sectional view of a semiconductor package according to an embodiment;

[0014] Figure 1B is along Figure 1A A cross-sectional view of the semiconductor package taken along line X1-X1' in FIG.

[0015] Figure 2 is a schematic cross-sectional view of a semiconductor package according to an embodiment;

[0016] Figure 3Ais a schematic cross-sectional view of a semiconductor package according to an embodiment;

[0017] Figure 3B yes Figure 3A An enlarged view of area AA in FIG.

[0018] Figure 4A is a schematic cross-sectional view of a semiconductor package according to an embodiment;

[0019] Figure 4B yes Figure 4A an enlarged view of area BB in FIG.

[0020] Figures 5 to 12 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, non-limiting exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof may be omitted.

[0022] Figure 1A is a schematic cross-sectional view of a semiconductor package 10 according to an embodiment. Figure 1B is along Figure 1A 1 is a cross-sectional view of the semiconductor package 10 taken along line X1 - X1 ′ in FIG.

[0023] Reference Figure 1A and Figure 1B , the semiconductor package 10 may include a first substrate 100 , a first semiconductor chip 200 , a conductive pillar 380 , a first underfill layer 270 , and a first molding member 390 .

[0024] The first substrate 100 may be electrically connected to each of the first semiconductor chip 200, the conductive pillars 380, and the external connection terminals 160, and may include a wiring 130 and an insulating layer 110 surrounding the wiring 130. In some embodiments, at least one of the upper and lower surfaces of the first substrate 100 may have a flat shape.

[0025] Hereinafter, in the drawings, the X-axis direction and the Y-axis direction may indicate directions parallel to the upper surface or the lower surface of the first substrate 100, and the X-axis direction and the Y-axis direction may be perpendicular to each other. The Z-axis direction may indicate a direction perpendicular to the upper surface or the lower surface of the first substrate 100. In other words, the Z-axis direction may include a direction perpendicular to the XY plane.

[0026] In addition, below, the first horizontal direction, the second horizontal direction, and the vertical direction in the drawings may be understood as follows: the first horizontal direction may be understood as the X-axis direction, the second horizontal direction may be understood as the Y-axis direction, and the vertical direction may be understood as the Z-axis direction.

[0027] The wiring 130 may be formed to penetrate one or more of the insulating layers 110 from the upper surface to the lower surface of the first substrate 100, and the insulating layers 110 surrounding the wiring 130 may be stacked on each other in the vertical direction Z. In this case, the wiring 130 may serve as an electrical connection path that penetrates the first substrate 100 from the upper surface to the lower surface of the first substrate 100. The first semiconductor chip 200, the conductive pillars 380, and the external connection terminals 160 may be electrically connected to each other via the wiring 130 of the first substrate 100.

[0028] In some embodiments, the first substrate 100 may include a ceramic substrate, a printed circuit board (PCB), or an organic substrate. In this case, the wiring 130 may include copper, nickel, stainless steel, or beryllium copper, and the insulating layer 110 may include at least one material selected from flame retardant 4 (FR-4), tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene oxide, bismaleimide triazine (BT), thermosetting resin, cyanate ester, polyimide, and liquid crystal polymer.

[0029] In some embodiments, the first substrate 100 may include a rewiring structure formed by using a rewiring process. In this case, the wiring 130 of the first substrate 100 may be understood as a rewiring pattern, and the insulating layer 110 of the first substrate 100 may be understood as a rewiring insulating layer. In this case, the wiring 130 may include a metal (such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru) or a combination thereof), but is not limited thereto, and in some embodiments, the wiring 130 may be formed by stacking a metal or a metal alloy on a seed layer including Cu, Ti, titanium nitride or titanium tungsten. In addition, the insulating layer 110 may be formed of, for example, a photoimageable dielectric (PID) or a photosensitive polyimide (PSPI).

[0030] The wiring 130 may include a line pattern 133 and a via pattern 131. The line pattern 133 may have a shape extending in a horizontal direction along at least one of an upper surface and a lower surface of each of a plurality of insulating layers 110 stacked in a vertical direction Z. The via pattern 131 may have a shape extending in the vertical direction Z and penetrating the insulating layer 110. The via pattern 131 may electrically connect the line patterns 133 at different vertical levels. In some embodiments, at least some of the line patterns 133 may be formed as one body with some of the via patterns 131.

[0031] The first semiconductor chip 200 may be arranged on the upper surface of the first substrate 100. According to some embodiments, the first semiconductor chip 200 may include a memory chip. The memory chip may include, for example, a volatile memory chip (such as a dynamic random access memory (RAM) (DRAM) and a static RAM (SRAM)) or a non-volatile memory chip (such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), and a resistive RAM (RRAM)). In addition, the first semiconductor chip 200 may include a logic chip. The logic chip may include, for example, a microprocessor (such as a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP)), an analog device, or a digital signal processor. However, the first semiconductor chip 200 is not limited to a memory chip or a logic chip, and the first semiconductor chip 200 may also have a chip structure including both a memory chip and a logic chip.

[0032] The first semiconductor chip 200 may be mounted on the first substrate 100 in a flip-chip manner by using the first bumps 250. The first semiconductor chip 200 may be electrically connected to the first substrate 100 via the first bumps 250. The first bumps 250 may physically contact each of pads formed on the upper surface of the first substrate 100 and pads formed under the lower surface of the first semiconductor chip 200, and may be electrically connected to the first substrate 100 and the first semiconductor chip 200.

[0033] According to some embodiments, the first bump 250 may have a column structure or a ball structure, or include a solder layer. According to some embodiments, the first bump 250 may include a micro bump. In this case, the micro bump may be understood as a bump having a critical dimension of less than about 20 μm. For example, when the first bump 250 has a spherical shape, the diameter of the first bump 250 may be less than about 20 μm.

[0034] The first bump 250 may be provided in plurality. The plurality of first bumps 250 may be provided separately from each other in the first horizontal direction X. According to some embodiments, the distance from the center of any one first bump 250 to the center of another first bump 250 directly adjacent thereto may be less than about 50 μm. According to some embodiments, the distance from the center of any one first bump 250 to the center of another first bump 250 directly adjacent thereto may be in the range of about 10 μm to about 50 μm.

[0035] The first substrate 100 and the first semiconductor chip 200 may be arranged to be separated from each other in the vertical direction Z by the first bumps 250. A distance D1 between the first substrate 100 and the first semiconductor chip 200 in the vertical direction Z may be equal to or less than about 10 μm. A thickness of the first bumps 250 in the vertical direction Z may be equal to or less than about 10 μm.

[0036] Since the first substrate 100 and the first semiconductor chip 200 are separated from each other in the vertical direction Z by the first bumps 250 , a space may be formed between the first substrate 100 and the first semiconductor chip 200 .

[0037] The first underfill layer 270 and the first molding member 390 may be arranged in the space between the first substrate 100 and the first semiconductor chip 200. According to some embodiments, each of the first underfill layer 270 and the first molding member 390 may include epoxy resin. Each of the first underfill layer 270 and the first molding member 390 may include a filler, and the filler content of the first underfill layer 270 may be in the range of about 70% to about 95%, and the filler content of the first molding member 390 may be in the range of about 5% to about 40%. In this case, the filler content may be understood as a mass ratio.

[0038] According to some embodiments, the first underfill layer 270 may be arranged to overlap with a central portion of the first semiconductor chip 200 in the vertical direction Z. The first underfill layer 270 may be formed to fill a region corresponding to a central portion of a space between the first substrate 100 and the first semiconductor chip 200. In this case, the first underfill layer 270 may be formed only in a central portion of the space between the first substrate 100 and the first semiconductor chip 200, and may not be formed in a region corresponding to a peripheral portion of the space between the first substrate 100 and the first semiconductor chip 200.

[0039] According to some embodiments, in the space between the first substrate 100 and the first semiconductor chip 200, the volume occupied by the first underfill layer 270 in the region other than the volume occupied by the first bump 250 may be in the range of about 5% to about 50%. In some embodiments, in the space between the first substrate 100 and the first semiconductor chip 200, the volume occupied by the first underfill layer 270 in the region other than the volume occupied by the first bump 250 may be in the range of about 10% to about 30%. When the volume ratio occupied by the first underfill layer 270 in the space between the first substrate 100 and the first semiconductor chip 200 is in the range of about 10% to about 30%, the first underfill layer 270 may fill the region where the first underfill layer 270 overlaps with the first semiconductor chip 200 in the vertical direction Z in the space between the first substrate 100 and the first semiconductor chip 200, but may not fill the region where the first underfill layer 270 does not overlap with the first semiconductor chip 200 in the vertical direction Z.

[0040] The first molding member 390 may be formed to cover the first semiconductor chip 200 and the conductive pillars 380. The first molding member 390 may cover both the upper surface and the side surface of the first semiconductor chip 200. In addition, the first molding member 390 may be formed in the space between the first substrate 100 and the first semiconductor chip 200. The first molding member 390 may be formed to fill the area corresponding to the peripheral portion of the space between the first substrate 100 and the first semiconductor chip 200. In other words, the first molding member 390 may be formed to fill the area of ​​the space between the first substrate 100 and the first semiconductor chip 200 except the portion where the first bottom filling layer 270 is formed. The first molding member 390 arranged between the first substrate 100 and the first semiconductor chip 200 may not overlap with the central portion of the first semiconductor chip 200 in the vertical direction Z. The first molding member 390 formed between the first substrate 100 and the first semiconductor chip 200 may surround the first bump 250.

[0041] A plurality of first bumps 250 may be disposed between the first substrate 100 and the first semiconductor chip 200, and a first bump 250 among the plurality of first bumps 250 that overlaps with a central portion of the first semiconductor chip 200 may be surrounded by the first bottom filling layer 270, while a first bump 250 among the plurality of first bumps 250 that does not overlap with a central portion of the first semiconductor chip 200 may be surrounded by the first molding member 390 instead of being surrounded by the first bottom filling layer 270.

[0042] The volume occupied by the first molding member 390 in the space between the first substrate 100 and the first semiconductor chip 200 may be greater than the volume occupied by the first underfill layer 270. According to some embodiments, in the space between the first substrate 100 and the first semiconductor chip 200, the volume occupied by the first molding member 390 in the region other than the volume occupied by the first bump 250 may be in the range of about 70% to about 90%. In the space between the first substrate 100 and the first semiconductor chip 200, in addition to the first bump 250, two heterogeneous materials may be provided.

[0043] According to some embodiments, Figure 1B As shown, the first underfill layer 270 may be formed in the central portion of the space between the first substrate 100 and the first semiconductor chip 200. When the first underfill layer 270 is viewed in the vertical direction Z, at least a portion of the peripheral region of the first underfill layer 270 may have a shape protruding toward the first molding member 390. However, the shape of the first underfill layer 270 viewed from the vertical direction Z is not limited thereto, and when the first underfill layer 270 is viewed from the vertical direction Z, the peripheral region thereof may also have a circular or elliptical shape.

[0044] The conductive pillar 380 may be arranged on the upper surface of the first substrate 100 in a horizontal direction and separated from the first semiconductor chip 200. The conductive pillar 380 may penetrate the first molding member 390 and extend in the vertical direction Z. The conductive pillar 380 may include, for example, a through-molding via or a conductive straight pillar. The conductive pillar 380 may include, for example, copper. According to some embodiments, the conductive pillar 380 may be provided in plurality. In this case, the plurality of conductive pillars 380 may be arranged in a horizontal direction and separated from each other.

[0045] The external connection terminal 160 may be arranged below the lower surface of the first substrate 100. The external connection terminal 160 may be electrically connected to an external connection device via a pad formed below the lower surface of the first substrate 100. The external connection device may include, for example, a motherboard PCB. According to some embodiments, the external connection terminal 160 may include a solder ball. In addition, in some embodiments, the external connection terminal 160 may also have a structure including a column and a solder. The external connection terminal 160 may include at least one of Cu, silver (Ag), gold (Au), and tin (Sb).

[0046] The semiconductor package 10 according to an embodiment of the present disclosure may include a first underfill layer 270 and a first molding member 390 disposed between the first substrate 100 and the first semiconductor chip 200. In this case, the first underfill layer 270 may be formed in a region corresponding to a central portion of a space between the first substrate 100 and the first semiconductor chip 200, and the first molding member 390 may be formed in a region corresponding to a peripheral portion of the space between the first substrate 100 and the first semiconductor chip 200.

[0047] In the comparative embodiment, when the space between the first substrate 100 and the first semiconductor chip 200 is filled by the first molding member 390 during the molding underfill process, and when the distance D1 between the upper surface of the first substrate 100 and the lower surface of the first semiconductor chip 200 in the vertical direction Z is equal to or less than about 10 μm, there may be a problem that the first molding member 390 is unevenly formed and voids are formed between the first molding members 390. In addition, there is a tendency that a large number of voids are generated in a region corresponding to a central portion in the space between the first substrate 100 and the first semiconductor chip 200.

[0048] However, in the semiconductor package 10 according to the embodiment of the present disclosure, the first underfill layer 270 may be arranged in a region corresponding to a central portion where a large number of voids occur in the space between the first substrate 100 and the first semiconductor chip 200, and the first molding member 390 may be arranged to surround the first underfill layer 270 to reduce the occurrence of voids. In other words, both the first underfill layer 270 and the first molding member 390 may be arranged in the space between the first substrate 100 and the first semiconductor chip 200 to reduce the defect that the space between the first substrate 100 and the first semiconductor chip 200 is not completely filled.

[0049] In addition, the reliability of the semiconductor package 10 can be improved by arranging the first bottom filling layer 270 only in areas where gaps frequently appear in the space between the first substrate 100 and the first semiconductor chip 200, and arranging the first molding member 390 including a material having greater properties (for example, greater thermal conductivity and greater compressive strength) than the first bottom filling layer 270 in other areas of the space between the first substrate 100 and the first semiconductor chip 200.

[0050] Figure 2 is a schematic cross-sectional view of a semiconductor package 11 according to an embodiment. Figure 1A and Figure 1B The repeated description of the semiconductor package 10 is given applicable to the semiconductor package 11 , and the differences thereof are mainly described.

[0051] Reference Figure 2 The semiconductor package 11 may include a first substrate 100 , a first semiconductor chip 200 , a conductive pillar 380 , a first underfill layer 270 , a first molding member 390 , a second substrate 300 , a second semiconductor chip 400 , a second underfill layer 470 , and a second molding member 490 .

[0052] The first substrate 100 may be electrically connected to each of the first semiconductor chip 200 , the conductive pillars 380 , and the external connection terminals 160 , and may include a wiring 130 and an insulating layer 110 surrounding the wiring 130 .

[0053] The first semiconductor chip 200 may be arranged on the upper surface of the first substrate 100. The first semiconductor chip 200 may be mounted on the upper surface of the first substrate 100 by using the first bumps 250. The conductive pillars 380 may be arranged in a horizontal direction on the upper surface of the first substrate 100, separated from the first semiconductor chip 200. The conductive pillars 380 may include a vertical connection conductive material for electrically connecting the first substrate 100 to the second substrate 300.

[0054] The first underfill layer 270 may be disposed in the space between the first substrate 100 and the first semiconductor chip 200. The first underfill layer 270 may be disposed in a region corresponding to a central portion in the space between the first substrate 100 and the first semiconductor chip 200. The first underfill layer 270 may be formed to surround the first bump 250.

[0055] The first molding member 390 may be formed to surround the first semiconductor chip 200 and the conductive pillars 380 between the first substrate 100 and the second substrate 300. According to some embodiments, the first molding member 390 may be formed to fill a region corresponding to a peripheral portion in the space between the first substrate 100 and the first semiconductor chip 200. According to some embodiments, a volume occupied by the first molding member 390 in the space between the first substrate 100 and the first semiconductor chip 200 may be greater than a volume occupied by the first underfill layer 270 in the space between the first substrate 100 and the first semiconductor chip 200.

[0056] The second substrate 300 may be disposed on an upper surface of the first molding member 390 and may include a substrate on which the second semiconductor chip 400 is mounted. The second substrate 300 may be electrically connected to each of the conductive pillars 380 and the second semiconductor chip 400. The second substrate 300 may include a wiring 330 and at least one insulating layer 310 surrounding the wiring 330.

[0057] The wiring 330 may include a line pattern 333 and a via pattern 331. The line pattern 333 may have a shape extending in a horizontal direction along at least one of an upper surface and a lower surface of each of at least one insulating layer 310 stacked in a vertical direction Z. The via pattern 331 may have a shape extending in the vertical direction Z and penetrating the insulating layer 310. The via pattern 331 may electrically connect the line patterns 333 at different vertical levels. In some embodiments, at least a portion of the line pattern 333 may be formed as one body with a portion of the via pattern 331.

[0058] In some embodiments, the second substrate 300 may include a ceramic substrate, a PCB, or an organic substrate. In addition, in some embodiments, the second substrate 300 may include a rewiring structure formed by using a rewiring process.

[0059] The second semiconductor chip 400 may be disposed on an upper surface of the second substrate 300. According to some embodiments, the second semiconductor chip 400 may include at least one of a memory chip and a logic chip.

[0060] The second semiconductor chip 400 may be mounted on the second substrate 300 in a flip chip manner by using the second bumps 450. The second semiconductor chip 400 may be electrically connected to the second substrate 300 via the second bumps 450. The second bumps 450 may be electrically connected to the second substrate 300 and the second semiconductor chip 400 by physical contact with both the pads formed on the upper surface of the second substrate 300 and the pads formed under the lower surface of the second semiconductor chip 400. The thickness of the second bumps 450 in the vertical direction Z may be equal to or less than 10 μm.

[0061] The second substrate 300 and the second semiconductor chip 400 may be separated from each other in the vertical direction Z by the second bumps 450 . Since the second substrate 300 and the second semiconductor chip 400 are separated from each other in the vertical direction Z by the second bumps 450 , a space may be formed between the second substrate 300 and the second semiconductor chip 400 .

[0062] The second bottom fill layer 470 and the second molding member 490 may be arranged in the space between the second substrate 300 and the second semiconductor chip 400. According to some embodiments, the second bottom fill layer 470 and the second molding member 490 may each include an epoxy resin. Each of the second bottom fill layer 470 and the second molding member 490 may include a filler, and the filler content of the second bottom fill layer 470 may be in the range of about 70% to about 95%, and the filler content of the second molding member 490 may be in the range of about 5% to about 40%. In this case, the filler content may be understood as a mass ratio.

[0063] According to some embodiments, the second underfill layer 470 may be arranged to overlap with a central portion of the second semiconductor chip 400 in the vertical direction Z. The second underfill layer 470 may be formed to fill a region corresponding to a central portion of the space between the second substrate 300 and the second semiconductor chip 400. In this case, the second underfill layer 470 may be formed only in a central portion of the space between the second substrate 300 and the second semiconductor chip 400, and may not be formed in a region corresponding to a peripheral portion of the space between the second substrate 300 and the second semiconductor chip 400.

[0064] According to some embodiments, in the space between the second substrate 300 and the second semiconductor chip 400 , a volume occupied by the second underfill layer 470 in a region excluding a volume occupied by the second bumps 450 may be in a range of about 5% to about 50%.

[0065] The second molding member 490 may be formed on the upper surface of the second substrate 300, and may be formed to cover the second semiconductor chip 400. The second molding member 490 may cover the upper surface and the side surface of the second semiconductor chip 400. In addition, the second molding member 490 may be formed in the space between the second substrate 300 and the second semiconductor chip 400. The second molding member 490 may be formed to fill the area corresponding to the peripheral portion of the space between the second substrate 300 and the second semiconductor chip 400. In other words, the second molding member 490 may be formed to fill the area of ​​the space between the second substrate 300 and the second semiconductor chip 400 except the portion where the second bottom filling layer 470 is formed. The second molding member 490 arranged between the second substrate 300 and the second semiconductor chip 400 may not overlap with the central portion of the second semiconductor chip 400 in the vertical direction Z. The second molding member 490 formed between the second substrate 300 and the second semiconductor chip 400 may surround the second bump 450.

[0066] A plurality of second bumps 450 may be disposed between the second substrate 300 and the second semiconductor chip 400, and a second bump 450 among the plurality of second bumps 450 that overlaps with a central portion of the second semiconductor chip 400 may be surrounded by a second bottom filling layer 470, while a second bump 450 among the plurality of second bumps 450 that does not overlap with a central portion of the second semiconductor chip 400 may be surrounded by a second molding member 490.

[0067] The volume occupied by the second molding member 490 in the space between the second substrate 300 and the second semiconductor chip 400 may be greater than the volume occupied by the second underfill layer 470. According to some embodiments, the volume occupied by the second molding member 490 in the region other than the volume occupied by the second bump 450 in the space between the second substrate 300 and the second semiconductor chip 400 may be in the range of about 70% to about 90%. In the space between the second substrate 300 and the second semiconductor chip 400, two heterogeneous materials may be provided in addition to the second bump 450.

[0068] When the second underfill layer 470 is viewed in the vertical direction Z, a portion of the peripheral region of the second underfill layer 470 may have a shape protruding toward the second molding member 490. However, the shape of the second underfill layer 470 viewed from the vertical direction Z is not limited thereto, and when the second underfill layer 470 is viewed from the vertical direction Z, the peripheral region thereof may also have a circular or elliptical shape.

[0069] The semiconductor package 11 according to an embodiment of the present disclosure may include a first underfill layer 270 and a first molding member 390 disposed between the first substrate 100 and the first semiconductor chip 200, and include a second underfill layer 470 and a second molding member 490 disposed between the second substrate 300 and the second semiconductor chip 400. Therefore, voids generated inside the semiconductor package 11 may be reduced, and the reliability of the semiconductor package 11 may be improved.

[0070] Figure 3A is a schematic cross-sectional view of a semiconductor package 20 according to an embodiment. Figure 3B yes Figure 3A In the following, the enlarged view of the area AA in FIG. Figure 1A and Figure 1B The semiconductor package 10 and Figure 3A and Figure 3B The description of the semiconductor package 20 will be repeated, and the differences between them will be mainly described.

[0071] Reference Figure 3A and Figure 3B The semiconductor package 20 may include a first substrate 100 , an interposer substrate 150 , a first semiconductor chip 201 , a second semiconductor chip 400 , an underfill material layer 170 , a first underfill layer 270 , a second underfill layer 470 , and a first molding member 390 .

[0072] Because the first substrate 100 and the reference Figure 1A and Figure 1B The described first substrate 100 is substantially the same or similar, so repeated description thereof may be omitted.

[0073] The insert substrate 150 may be arranged on the upper surface of the first substrate 100. The insert substrate 150 may be formed of silicon, and the first semiconductor chip 201 may be electrically connected to the second semiconductor chip 400. According to some embodiments, the insert substrate 150 may be electrically connected to the first substrate 100 via a bump 171. An underfill material layer 170 surrounding the bump 171 may be arranged between the first substrate 100 and the insert substrate 150. The underfill material layer 170 may include, for example, an epoxy resin formed by using a capillary underfill method. However, in some embodiments, the first molding member 390 may also directly fill the space between the first substrate 100 and the insert substrate 150 by using a molding underfill process. In this case, the underfill material layer 170 may be omitted.

[0074] The interposer substrate 150 may include a wiring layer 151 and a body layer 155. The wiring layer 151 may be arranged on an upper surface of the body layer 155. The wiring layer 151 may include a wiring pattern 153. The wiring pattern 153 may electrically connect the first semiconductor chip 201 to the second semiconductor chip 400, or may electrically connect the first semiconductor chip 201 and one or more through electrodes 157 together, and electrically connect the second semiconductor chip 400 and one or more through electrodes 157 together.

[0075] The through electrode 157 may be formed inside the body layer 155. The through electrode 157 may penetrate the body layer 155 in the vertical direction Z. According to some embodiments, the through electrode 157 may include a through silicon via (TSV). The through electrode 157 may be electrically connected to the bump 171 via a pad formed under the lower surface of the body layer 155.

[0076] Each of the first semiconductor chip 201 and the second semiconductor chip 400 may be arranged on an upper surface of the interposer substrate 150. The first semiconductor chip 201 may be mounted on the upper surface of the interposer substrate 150 via the first bumps 250, and the second semiconductor chip 400 may be mounted on the upper surface of the interposer substrate 150 via the second bumps 450.

[0077] The first underfill layer 270 and the first molding member 390 may be disposed between the interposer substrate 150 and the first semiconductor chip 201 , and the second underfill layer 470 and the first molding member 390 may be disposed between the interposer substrate 150 and the second semiconductor chip 400 .

[0078] The first underfill layer 270 may be arranged to overlap the central portion of the first semiconductor chip 201 in the vertical direction Z. The first underfill layer 270 may be formed to fill a region corresponding to the central portion of the space between the interposer substrate 150 and the first semiconductor chip 201. In this case, the first underfill layer 270 may be formed only in the central portion of the space between the interposer substrate 150 and the first semiconductor chip 201, and may not be formed in a region corresponding to a peripheral portion of the space between the interposer substrate 150 and the first semiconductor chip 201.

[0079] The second underfill layer 470 may be arranged to overlap the central portion of the second semiconductor chip 400 in the vertical direction Z. The second underfill layer 470 may be formed to fill a region corresponding to the central portion of the space between the interposer substrate 150 and the second semiconductor chip 400. In this case, the second underfill layer 470 may be formed only in the central portion of the space between the interposer substrate 150 and the second semiconductor chip 400, and may not be formed in a region corresponding to a peripheral portion of the space between the interposer substrate 150 and the second semiconductor chip 400.

[0080] The first molding member 390 may cover the first semiconductor chip 201, the second semiconductor chip 400, and the intermediate insert substrate 150. The first molding member 390 may fill the space between the insert substrate 150 and the first semiconductor chip 201 and the space between the insert substrate 150 and the second semiconductor chip 400. The first molding member 390 may be formed to fill an area corresponding to the peripheral portion of each of the space between the insert substrate 150 and the first semiconductor chip 201 and the space between the insert substrate 150 and the second semiconductor chip 400. In other words, the first molding member 390 may be formed to fill an area except a portion where the first bottom fill layer 270 is formed in the space between the insert substrate 150 and the first semiconductor chip 201, and fill an area except a portion where the second bottom fill layer 470 is formed in the space between the insert substrate 150 and the second semiconductor chip 400. The first molding member 390 arranged between the insert substrate 150 and the first semiconductor chip 201 may not overlap with the central portion of the first semiconductor chip 201 in the vertical direction Z, and the first molding member 390 arranged between the insert substrate 150 and the second semiconductor chip 400 may not overlap with the central portion of the second semiconductor chip 400 in the vertical direction Z.

[0081] According to some embodiments, in the space between the interposer substrate 150 and the first semiconductor chip 201, the volume occupied by the first molding member 390 may be greater than the volume occupied by the first underfill layer 270. In addition, in the space between the interposer substrate 150 and the second semiconductor chip 400, the volume occupied by the first molding member 390 may be greater than the volume occupied by the second underfill layer 470.

[0082] According to some embodiments, the first semiconductor chip 201 may include a plurality of semiconductor chips stacked in a vertical direction Z. In this case, the first semiconductor chip 201 may be understood as a chip stacking structure. The semiconductor chips included in the first semiconductor chip 201 may be semiconductor chips used in a high bandwidth memory (HBM) DRAM chip included in an HBM package. According to some embodiments, referring to Figure 3B , the first semiconductor chip 201 may include a substrate chip 213 and at least one HBM chip 215 stacked on the substrate chip 213 in the vertical direction Z. The substrate chip 213 may be the lowermost portion of the first semiconductor chip 201. Each of the substrate chip 213 and the HBM chip 215 may include at least one through-electrode 220 therein. On the other hand, the top HBM chip 211 (i.e., the uppermost HBM chip among the HBM chips 215) may not include the through-electrode 220.

[0083] According to some embodiments, the substrate chip 213 may include a logic device. Therefore, the substrate chip 213 may include a logic chip. The substrate chip 213 may be arranged below the HBM chip 215, combine the signals of the HBM chip 215 to be transmitted to the outside, and further, may transmit signals and power from the outside to the HBM chip 215. Therefore, the substrate chip 213 may be referred to as a buffer chip or a control chip. The HBM chip 215 may be referred to as a memory chip or a core chip.

[0084] The HBM chip 215 may be stacked on the substrate chip 213 by using pad-to-pad bonding, bonding using bonding members, or bonding using anisotropic conductive film (ACF). According to some embodiments, the HBM chip 215 may be stacked in a flip chip manner by using at least one third bump 245. The third bump 245 may include a micro bump. An underfill material layer 260 may be formed between the substrate chip 213 and the lowest HBM chip in the HBM chip 215, and between the HBM chips 215. The underfill material layer 260 may fix the third bump 245, the substrate chip 213, and the HBM chip 215.

[0085] At least one through electrode 220 formed in the substrate chip 213 and the HBM chip 215 may also be electrically connected to the at least one third bump 245. The through electrode 220 may extend in the vertical direction Z. The through electrode 220 may have a tapered shape in which a horizontal width of the through electrode 220 decreases as the vertical level decreases.

[0086] In the semiconductor package 20 according to the embodiment of the present disclosure, the first underfill layer 270 and the first molding member 390 may be arranged in the space between the interposer substrate 150 and the first semiconductor chip 201, and the second underfill layer 470 and the first molding member 390 may be arranged in the space between the interposer substrate 150 and the second semiconductor chip 400. Therefore, voids generated in the semiconductor package 20 may be reduced, and the reliability of the semiconductor package 20 may be improved.

[0087] Figure 4A is a schematic cross-sectional view of a semiconductor package 30 according to an embodiment. Figure 4B yes Figure 4A Magnified view of area BB.

[0088] In the following, references may be omitted. Figure 1A and Figure 1B A repeated description of the semiconductor package 10 is given that is applicable to the semiconductor package 30 , and the differences thereof are mainly described.

[0089] Reference Figure 4A and Figure 4B, the semiconductor package 30 may include a first substrate 100 , a first semiconductor chip 202 , a second semiconductor chip 402 , a first underfill layer 270 , and a first molding member 390 .

[0090] Because the first substrate 100 and the reference Figure 1A and Figure 1B The described first substrate 100 is substantially the same or similar, so repeated description thereof may be omitted.

[0091] The first semiconductor chip 202 may be arranged on the upper surface of the first substrate 100 by using the first bumps 250. The first underfill layer 270 and the first molding member 390 may be arranged in the space between the first substrate 100 and the first semiconductor chip 202. The first underfill layer 270 may be arranged to overlap the central portion of the first semiconductor chip 202 in the vertical direction Z.

[0092] The first underfill layer 270 may be formed to fill a region corresponding to a central portion of a space between the first substrate 100 and the first semiconductor chip 202. In this case, the first underfill layer 270 may be formed only in a central portion of the space between the first substrate 100 and the first semiconductor chip 202, and may not be formed in a region corresponding to a peripheral portion of the space between the first substrate 100 and the first semiconductor chip 202.

[0093] The first molding member 390 may be formed to cover the first semiconductor chip 202 and the second semiconductor chip 402. In this case, the first molding member 390 may be formed in the space between the first substrate 100 and the first semiconductor chip 202. The first molding member 390 may be formed to fill the area corresponding to the peripheral portion of the space between the first substrate 100 and the first semiconductor chip 202. In other words, the first molding member 390 may be formed to fill the area of ​​the space between the first substrate 100 and the first semiconductor chip 202 except for the portion where the first bottom filling layer 270 is formed. The first molding member 390 arranged between the first substrate 100 and the first semiconductor chip 202 may not overlap with the central portion of the first semiconductor chip 202 in the vertical direction Z. The first molding member 390 formed between the first substrate 100 and the first semiconductor chip 202 may surround the first bump 250.

[0094] The second semiconductor chip 402 may be mounted on an upper surface of the first semiconductor chip 202. The second semiconductor chip 402 may be electrically connected to the first semiconductor chip 202. According to some embodiments, each of the first semiconductor chip 202 and the second semiconductor chip 402 may include a logic chip and a memory chip. For example, both the first semiconductor chip 202 and the second semiconductor chip 402 may include the same type of memory chip, or one of the first semiconductor chip 202 and the second semiconductor chip 402 may include a memory chip and the other may include a logic chip. In some embodiments, at least one of the first semiconductor chip 202 and the second semiconductor chip 402 may have a chiplet structure including a plurality of chiplets.

[0095] The adhesive layer 370 may be configured to adhere the first semiconductor chip 202 to the second semiconductor chip 402. The adhesive layer 370 may be disposed between the first semiconductor chip 202 and the second semiconductor chip 402. According to some embodiments, the adhesive layer 370 may include a non-conductive film (NCF) and a die attach film (DAF).

[0096] The first semiconductor chip 202 may include a first semiconductor substrate 234 , a first semiconductor device layer 231 , at least one first bump pad 233 , and at least one second bump pad 236 .

[0097] The first semiconductor substrate 234 may include an upper surface and a lower surface facing each other. The upper surface may be a surface facing the second semiconductor chip 402, and the lower surface may be a surface facing the first substrate 100. The upper surface may be referred to as an inactive surface, and the lower surface may be referred to as an active surface.

[0098] The first semiconductor substrate 234 may include silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first semiconductor substrate 234 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). On the other hand, the first semiconductor substrate 234 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 234 may include a buried oxide (BOX) layer. The first semiconductor substrate 234 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. In addition, the first semiconductor substrate 234 may have various device isolation structures, such as a shallow trench isolation (STI) structure.

[0099] The first semiconductor device layer 231 may include a first wiring pattern 232 electrically connected to a plurality of semiconductor devices formed on a first semiconductor substrate 234. The first wiring pattern 232 may include a metal wiring layer and a via plug. For example, the first wiring pattern 232 may have a multilayer structure in which two or more metal wiring layers are alternately stacked or two or more via plugs are alternately stacked.

[0100] According to some embodiments, the first semiconductor device layer 231 may be formed below a lower surface (e.g., an active surface) of the first semiconductor substrate 234. According to some embodiments, the first semiconductor device layer 231 may be formed below the first semiconductor substrate 234. The first semiconductor substrate 234 may be separated from the first substrate 100, with the first semiconductor device layer 231 between the first semiconductor substrate 234 and the first substrate 100. The first semiconductor chip 202 may include at least one through electrode 235 penetrating a portion of the first semiconductor device layer 231 and the first semiconductor substrate 234.

[0101] The first bump pad 233 may be disposed under the lower surface of the first semiconductor device layer 231 and may be electrically connected to the first wiring pattern 232 inside the first semiconductor device layer 231. The first bump pad 233 may be electrically connected to the through electrode 235 via the first wiring pattern 232.

[0102] The through electrode 235 may penetrate the first semiconductor substrate 234 and a portion of the first semiconductor device layer 231. The through electrode 235 may extend from the first semiconductor device layer 231 toward the upper surface of the first semiconductor substrate 234 in the vertical direction Z, and may be electrically connected to the first wiring pattern 232 provided in the first semiconductor device layer 231. Therefore, the first bump pad 233 may be electrically connected to the through electrode 235 via the first wiring pattern 232. The through electrode 235 may have a tapered shape, wherein the horizontal width of the through electrode 235 decreases or increases as the level of the through electrode 235 in the vertical direction Z increases. At least a portion of the through electrode 235 may have a columnar shape. The through electrode 235 may include a silicon through electrode.

[0103] The second bump pad 236 may be formed on the upper surface of the first semiconductor substrate 234, that is, on the inactive surface of the first semiconductor substrate 234. The second bump pad 236 may include a material substantially the same as that of the first bump pad 233. In addition, according to some embodiments, a passivation layer may be formed to surround a portion of a side surface of the second bump pad 236 on the upper surface of the first semiconductor substrate 234.

[0104] The first bump 250 may be arranged to contact the first bump pad 233. The first semiconductor chip 202 may receive at least one of a control signal, a power signal, and a ground signal for operation of the first semiconductor chip 202 from the outside via the first bump 250, receive a data signal to be stored in the first semiconductor chip 202 from the outside, or may provide data stored in the first semiconductor chip 202 to the outside.

[0105] The second semiconductor chip 402 may include a second semiconductor substrate 434, a second semiconductor device layer 431, and at least one third bump pad 433. Since the second semiconductor chip 402 is the same as or has similar characteristics to the first semiconductor chip 202, the differences from the first semiconductor chip 202 are mainly described.

[0106] The second semiconductor substrate 434 may include a lower surface and an upper surface opposite to each other. The lower surface of the second semiconductor substrate 434 may face the first semiconductor chip 202, and its upper surface may be opposite to the lower surface. The upper surface of the second semiconductor substrate 434 may be referred to as an inactive surface, and the lower surface of the second semiconductor substrate 434 may be referred to as an active surface.

[0107] The second semiconductor device layer 431 may include a second wiring pattern 432 electrically connected to a plurality of semiconductor devices formed on a second semiconductor substrate 434. The second wiring pattern 432 may include a metal wiring layer and a via plug. For example, the second wiring pattern 432 may have a multilayer structure in which two or more metal wiring layers are alternately stacked or two or more via plugs are alternately stacked.

[0108] According to some implementations, the second semiconductor device layer 431 may be formed on a lower surface (e.g., an active surface) of the second semiconductor substrate 434. The second semiconductor device layer 431 may be below the second semiconductor substrate 434. The second semiconductor substrate 434 may be separated from the first semiconductor chip 202 in the vertical direction Z, with the second semiconductor device layer 431 between the second semiconductor substrate 434 and the first semiconductor chip 202.

[0109] The third bump pad 433 may be disposed under a lower surface of the second semiconductor device layer 431 and may be electrically connected to the second wiring pattern 432 in the second semiconductor device layer 431 .

[0110] The adhesive layer 370 may be disposed between the first semiconductor chip 202 and the second semiconductor chip 402. The adhesive layer 370 may fix the second semiconductor chip 402 onto the first semiconductor chip 202.

[0111] At least one fourth bump 371 may be arranged to contact at least one second bump pad 236 and at least one third bump pad 433. The fourth bump 371 may be electrically connected to the first semiconductor chip 202 and the second semiconductor chip 402. The second semiconductor chip 402 may be electrically connected to the first semiconductor chip 202 via the fourth bump 371 arranged between the first semiconductor chip 202 and the second semiconductor chip 402. The second semiconductor chip 402 may receive at least one of a control signal, a power signal, and a ground signal for operation of the second semiconductor chip 402 from the outside via the fourth bump 371, receive a data signal to be stored in the second semiconductor chip 402, or may provide data stored in the second semiconductor chip 402 to the outside.

[0112] Since the first underfill layer 270 and the first molding member 390 are arranged between the first substrate 100 and the first semiconductor chip 202 in the semiconductor package 30 according to the embodiment of the present disclosure, voids generated in the semiconductor package 30 may be reduced and the reliability of the semiconductor package 30 may be improved.

[0113] Figures 5 to 12 is a schematic cross-sectional view showing a method for manufacturing a semiconductor package according to an embodiment. Figure 1A and Figure 1B A repeated description of the semiconductor package 10 is given, and the differences thereof are mainly described.

[0114] Reference Figure 5 and Figure 6 , the first substrate 100 may be arranged on the carrier substrate 800. Figure 1A and Figure 1B The first substrate 100 described is substantially the same or similar, so repeated description thereof may be omitted. According to some embodiments, the first substrate 100 may be formed on the carrier substrate 800 without a gap. In other words, the footprint of the first substrate 100 may be substantially the same as the footprint of the carrier substrate 800.

[0115] Reference Figure 7, at least one first semiconductor chip 200 and at least one conductive pillar 380 may be arranged on the first substrate 100. On the first substrate 100, a plurality of first semiconductor chips 200 and conductive pillars 380 may be arranged. According to some embodiments, the conductive pillars 380 may be formed by filling copper or the like into a photoresist opening, wherein the photoresist opening is formed by using a photoresist doping process, an exposure process, and an etching process. The first semiconductor chip 200 may be mounted on the first substrate 100 in a flip chip manner by using at least one first bump 250. The footprint of the first substrate 100 is larger than the footprint of the first semiconductor chip 200.

[0116] Reference Figure 8 , the first structure 1000 may be formed by releasing at least one first bottom fill ball 270-B on the first substrate 100. The first bottom fill ball 270-B may include a material in a state before curing (e.g., an epoxy resin including a filler). The first bottom fill ball 270-B may be released onto the upper surface of the first substrate 100 and may not be in contact with the conductive pillar 380. According to some embodiments, the first bottom fill ball 270-B may be located between the first semiconductor chip 200 and the conductive pillar 380. In some embodiments, at least a portion of the first bottom fill ball 270-B may overlap with the first semiconductor chip 200 in the vertical direction Z. In other words, at least a portion of the first bottom fill ball 270-B may be located between the first substrate 100 and the first semiconductor chip 200.

[0117] Reference Fig. 9 , can be set in the molding device 900 Figure 8 The first structure 1000 of the present invention is provided. The molding device 900 may include an upper mold 910 and a lower mold 930. According to some embodiments, the first structure 1000 may be provided to the upper mold 910, and may be provided in a state where the first structure 1000 is turned over in the vertical direction Z. The first molded ball 390-B may be provided on the lower mold 930. The first molded ball 390-B may include a material in a state before curing (e.g., epoxy resin including a filler).

[0118] The upper mold 910 and the lower mold 930 may be provided in an open state. That is, the upper mold 910 and the lower mold 930 may be provided in a state of being separated in the vertical direction Z. An empty space may be formed between the upper mold 910 and the lower mold 930. According to some embodiments, at least one of the upper mold 910 and the lower mold 930 may be movable in the vertical direction Z.

[0119] Reference Fig.10 , by closing a portion of the molding device 900 and allowing the first molded ball 390-B to Fig. 9The first structure 1000 is contacted to form a first structure 1001.

[0120] The first molded ball 390-B may partially cover the first structure 1001. In addition, due to the pressure applied to the first structure 1001, the first underfill ball 270-B formed adjacent to the first semiconductor chip 200 may move to the space between the first substrate 100 and the first semiconductor chip 200. In other words, the first underfill ball 270-B may move to the center of the first semiconductor chip 200.

[0121] Reference Fig.11 , the molding device 900 may be completely closed, and the first molded ball 390-B may completely cover the first structure 1001 to form the first structure 1002. The first molded ball 390-B may completely cover the first structure 1002. In addition, due to the pressure applied to the first structure 1001, the first bottom fill ball 270-B may move to a region where the first bottom fill ball 270-B overlaps with the central portion of the first semiconductor chip 200 in the vertical direction Z. In other words, the first bottom fill ball 270-B may move to a region corresponding to the central portion of the space between the first substrate 100 and the first semiconductor chip 200.

[0122] Reference Fig.12 , after removing from the molding device 900 Fig.11 After forming the first structure 1002 in the mold, by curing the first underfill balls 270 -B and the first mold balls 390 -B of the first structure 1002 and performing a grinding process, the semiconductor package 10 may be provided.

[0123] While non-limiting example embodiments of the present disclosure have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a first substrate; a first semiconductor chip located on the upper surface of the first substrate; at least one first bump located between the first substrate and the first semiconductor chip, the at least one first bump being configured to electrically connect the first substrate to the first semiconductor chip; a first underfill layer filling a central portion of a space between the first substrate and the first semiconductor chip; as well as a first molding member that covers an upper surface and side surfaces of the first semiconductor chip and fills a peripheral portion of the space between the first substrate and the first semiconductor chip, Herein, a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is larger than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.

2. The semiconductor package according to claim 1, wherein: A distance between an upper surface of the first substrate and a lower surface of the first semiconductor chip in a vertical direction is equal to or less than 10 μm.

3. The semiconductor package according to claim 1, wherein: The at least one first bump includes a plurality of micro bumps, wherein the critical dimension of each of the plurality of micro-bumps is less than 20 μm, and Wherein, a distance from a center of one of the plurality of microbumps to a center of another microbump of the plurality of microbumps directly adjacent to the one of the plurality of microbumps is less than 50 μm.

4. The semiconductor package according to claim 1, wherein: Each of the first molding member and the first underfill layer includes a filler, wherein the filler content of the first bottom filling layer is in the range of 70% to 90%, and Wherein, the filler content of the first molding member is in the range of 5% to 40%.

5. The semiconductor package according to claim 1, wherein: The first underfill layer overlaps a central portion of the first semiconductor chip in a vertical direction, and The first molding member surrounds the first bottom filling layer.

6. The semiconductor package according to claim 1, further comprising: a conductive pillar located on the upper surface of the first substrate and spaced apart from the first semiconductor chip in a horizontal direction; a second substrate located on an upper surface of the first molding member; a second semiconductor chip located on the upper surface of the second substrate; at least one second bump located between the second substrate and the second semiconductor chip; a second underfill layer filling a central portion of a space between the second substrate and the second semiconductor chip; as well as A second molding member fills a peripheral portion of the space between the second substrate and the second semiconductor chip.

7. The semiconductor package according to claim 1, wherein: At least a portion of a peripheral area of ​​the first underfill layer includes a shape that protrudes toward the first molding member when the first underfill layer is viewed in a vertical direction.

8. The semiconductor package according to claim 1, further comprising: a second semiconductor chip; an interposer substrate located on an upper surface of the first substrate, wherein the first semiconductor chip and the second semiconductor chip are located on the upper surface of the interposer substrate; and a second underfill layer and a second molding member between the interposer substrate and the second semiconductor chip; wherein the first underfill layer and the first molding member are located between the interposer substrate and the first semiconductor chip, and The first bottom filling layer overlaps with a central portion of the first semiconductor chip in a vertical direction, and the second bottom filling layer overlaps with a central portion of the second semiconductor chip in the vertical direction.

9. The semiconductor package according to claim 1, further comprising a second semiconductor chip on an upper portion of the first semiconductor chip, in, The first semiconductor chip includes a first semiconductor substrate and a through-electrode penetrating the first semiconductor substrate in a vertical direction.

10. The semiconductor package according to claim 1, wherein: In the space between the first substrate and the first semiconductor chip, a volume occupied by the first underfill layer in a region excluding a volume occupied by the at least one first bump is in a range of 5% to 50%.

11. A semiconductor package, comprising: a first substrate; a first semiconductor chip located on the upper surface of the first substrate; at least one first bump located between the first substrate and the first semiconductor chip, and the at least one first bump is configured to electrically connect the first substrate to the first semiconductor chip, the at least one first bump having a thickness equal to or less than 10 μm in a vertical direction; a first underfill layer filling a central portion of a space between the first substrate and the first semiconductor chip; as well as a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling a peripheral portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is larger than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip, and Wherein, in the space between the first substrate and the first semiconductor chip, a volume occupied by the first underfill layer in a region other than a volume occupied by the at least one first bump is in a range of 5% to 50%.

12. The semiconductor package according to claim 11, further comprising: a conductive pillar located on the upper surface of the first substrate and spaced apart from the first semiconductor chip in a horizontal direction; a second substrate located on an upper surface of the first molding member; a second semiconductor chip located on the upper surface of the second substrate; at least one second bump located between the second substrate and the second semiconductor chip; a second underfill layer filling a central portion of a space between the second substrate and the second semiconductor chip; as well as a second molding member filling a peripheral portion of the space between the second substrate and the second semiconductor chip, Wherein, a distance between an upper surface of the second substrate and a lower surface of the second semiconductor chip is equal to or less than 10 μm.

13. The semiconductor package according to claim 11, wherein: At least a portion of the first underfill layer includes a shape that protrudes toward the first molding member when the first underfill layer is viewed in the vertical direction.

14. The semiconductor package according to claim 11, further comprising: a second semiconductor chip; an interposer substrate located on an upper surface of the first substrate, wherein the first semiconductor chip and the second semiconductor chip are located on the upper surface of the interposer substrate; a second underfill layer and a second molding member located between the interposer substrate and the second semiconductor chip, wherein the first underfill layer and the first molding member are located between the interposer substrate and the first semiconductor chip, The second semiconductor chip includes a substrate chip and a high-bandwidth memory chip, and the high-bandwidth memory chip is located on the substrate chip, and The first bottom filling layer overlaps with a central portion of the first semiconductor chip in the vertical direction, and the second bottom filling layer overlaps with a central portion of the second semiconductor chip in the vertical direction.

15. The semiconductor package according to claim 11, further comprising a second semiconductor chip located on an upper portion of the first semiconductor chip, in, The first semiconductor chip includes a first semiconductor substrate, a first semiconductor device layer, and a through electrode penetrating the first semiconductor substrate in the vertical direction. The second semiconductor chip includes a second semiconductor substrate, and The first semiconductor chip is arranged such that the first semiconductor substrate faces the second semiconductor chip.

16. The semiconductor package according to claim 11, wherein: Each of the first molding member and the first underfill layer includes a filler, wherein the filler content of the first bottom filling layer is in the range of 70% to 90%, and Wherein, the filler content of the first molding member is in the range of 5% to about 40%.

17. The semiconductor package according to claim 11, wherein: The footprint of the first substrate is larger than the footprint of the first semiconductor chip.

18. A semiconductor package, comprising: A first substrate including wiring and an insulating layer surrounding the wiring; a first semiconductor chip located on the upper surface of the first substrate; at least one first bump located between the first substrate and the first semiconductor chip, and the at least one first bump is configured to electrically connect the first substrate to the first semiconductor chip, each of the at least one first bump having a thickness equal to or less than 10 μm in a vertical direction; a first underfill layer filling a central portion of a space between the first substrate and the first semiconductor chip; as well as a first molding member that covers an upper surface and side surfaces of the first semiconductor chip and fills a peripheral portion of the space between the first substrate and the first semiconductor chip, wherein each of the first molding member and the first underfill layer includes a filler, the filler content of the first underfill layer is in the range of 70% to 90%, and the filler content of the first molding member is in the range of 5% to 40%, wherein, in a space between the first substrate and the first semiconductor chip, a volume occupied by the first molding member is larger than a volume occupied by the first underfill layer, and Wherein, in the space between the first substrate and the first semiconductor chip, a volume occupied by the first underfill layer in a region other than a volume occupied by the at least one first bump is in a range of 5% to 50%.

19. The semiconductor package according to claim 18, further comprising: a conductive pillar located on the upper surface of the first substrate and spaced apart from the first semiconductor chip in a horizontal direction; a second substrate located on an upper surface of the first molding member; a second semiconductor chip located on the upper surface of the second substrate; at least one second bump located between the second substrate and the second semiconductor chip; a second underfill layer filling a central portion of a space between the second substrate and the second semiconductor chip; as well as a second molding member filling a peripheral portion of the space between the second substrate and the second semiconductor chip, Wherein, a distance between an upper surface of the second substrate and a lower surface of the second semiconductor chip is equal to or less than 10 μm.

20. The semiconductor package of claim 18, further comprising: a second semiconductor chip; an interposer substrate located on an upper surface of the first substrate, wherein the first semiconductor chip and the second semiconductor chip are located on the upper surface of the interposer substrate; and a second underfill layer and a second molding member between the interposer substrate and the second semiconductor chip, wherein the first underfill layer and the first molding member are located between the interposer substrate and the first semiconductor chip, The second semiconductor chip includes a substrate chip and a high-bandwidth memory chip, and the high-bandwidth memory chip is located on the substrate chip, and The first bottom filling layer overlaps with a central portion of the first semiconductor chip in the vertical direction, and the second bottom filling layer overlaps with a central portion of the second semiconductor chip in the vertical direction.

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