Semiconductor package and method of forming same

Abstract

The invention provides a semiconductor package and a method of forming the same. The semiconductor package includes an oxide layer, and a waveguide and a photonic component on a first side of the oxide layer. The semiconductor package also includes a heater element adjacent to the photonic component and configured to provide thermal energy to the photonic component. The semiconductor package also includes a redistribution structure on a second side of the oxide layer opposite the first side. The redistribution structure includes a plurality of dielectric layers and conductive features in the dielectric layers. In addition, the semiconductor package includes a thermoelectric cooling device embedded in the dielectric layer of the redistribution structure and located directly under the photonic component.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor packages and methods of forming the same. Background Art

[0002] Electrical signaling and processing is a technology used to transmit and process signals. In addition, in recent years, optical signaling and processing has been used in an increasing number of applications, especially through the use of optical fiber related applications for signal transmission.

[0003] Optical signal conduction and processing are often combined with electrical signal conduction and processing to provide comprehensive applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals can be used for short-distance signal transmission and processing and control. Therefore, devices integrating optical components and electronic components are produced to convert between optical signals and electrical signals, as well as for processing optical signals and electrical signals. Therefore, a package (also called a photonic package) can include an optical (photonic) die (including optical devices) and an electronic die (including electronic devices). Summary of the invention

[0004] An embodiment of the present disclosure provides a semiconductor package, comprising: an oxide layer; a waveguide and a photonic component located on a first side of the oxide layer; a heater element adjacent to the photonic component; a redistribution structure located on a second side of the oxide layer opposite to the first side, wherein the redistribution structure comprises a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and a thermoelectric cooling device embedded in the plurality of dielectric layers of the redistribution structure and directly beneath the photonic component.

[0005] Another embodiment of the present disclosure provides a semiconductor package, comprising: an oxide layer; a photonic component located on a first side of the oxide layer; a heater element adjacent to the photonic component; a redistribution structure located on a second side of the oxide layer opposite to the first side, wherein the redistribution structure comprises a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and a thermoelectric cooling device embedded in the plurality of dielectric layers of the redistribution structure, and wherein the thermoelectric cooling device is directly arranged in a region of the plurality of dielectric layers directly below the photonic component, or adjacent to the region of the plurality of dielectric layers directly below the photonic component.

[0006] Yet another embodiment of the present disclosure provides a method for forming a semiconductor package, comprising: forming a waveguide and a photonic component on a first side of an oxide layer; forming a first redistribution structure above the waveguide and the photonic component, wherein the first redistribution structure includes a plurality of first dielectric layers and a first conductive component located in the plurality of first dielectric layers; providing a heater element in one of the plurality of first dielectric layers of the first redistribution structure; bonding an electronic die to the first redistribution structure, wherein the electronic die is electrically connected to the photonic component through the first conductive component; forming a second redistribution structure on a second side of the oxide layer opposite to the first side, wherein the second redistribution structure includes a plurality of second dielectric layers and a second conductive component located in the plurality of second dielectric layers; and providing a thermoelectric cooling device in the plurality of second dielectric layers of the second redistribution structure, wherein the thermoelectric cooling device is directly located below the photonic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a cross-sectional view of a photonic package in which localized hot spots occur within one or more dielectric layers, according to some embodiments.

[0009] Figure 2 is a cross-sectional view of a photonic package having an embedded thermoelectric cooling (TEC) device in one or more dielectric layers according to some embodiments.

[0010] Figure 3 is a diagram showing a method according to some embodiments Figure 2 Schematic diagram of the working principle of the thermoelectric cooling device shown.

[0011] Figure 4 FIG. 2 is a diagram showing a heater element, a photonic component (eg, a modulator), and a Figure 2 A plan view (eg, top view) of an arrangement of thermoelectric cooling devices shown in FIG.

[0012] FIG. 5A to FIG. 5M shows the formation according to some embodiments Figure 2 Cross-sectional views of intermediate steps of a photonic package are shown.

[0013] Figure 6 is a cross-sectional view of a photonic package having an embedded thermoelectric cooling device in one or more dielectric layers, according to some embodiments.

[0014] Figure 7 is a diagram showing a method according to some embodiments Figure 6 A plan view (eg, top view) of the arrangement of a heater element, photonic component (eg, modulator), heat sink, and thermoelectric cooling device shown in FIG.

[0015] Figure 8 is a cross-sectional view of a photonic package having an embedded thermoelectric cooling device in one or more dielectric layers, according to some embodiments.

[0016] Fig. 9 is a cross-sectional view of a photonic package having an embedded thermoelectric cooling device in one or more dielectric layers, according to some embodiments.

[0017] Fig.10 is a diagram showing a method according to some embodiments Fig. 9 A plan view (eg, top view) of the arrangement of a heater element, photonic component (eg, modulator), heat sink, and thermoelectric cooling device shown in FIG.

[0018] Fig.11 is a cross-sectional view of a semiconductor package according to some embodiments, the semiconductor package including a Figure 2 The photonic package shown. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0021] According to some embodiments of the present disclosure, a semiconductor package (e.g., a photonic package) and a method for forming the same are provided. In some embodiments, a heater element is integrated into the photonic package to transfer high-power energy to a silicon photonic component (e.g., a modulator) to keep the modulator operating at a desired high temperature. However, inevitably, the thermal energy generated by the heater element will also be transferred to nearby components (e.g., some dielectric layers below the modulator) through the heated modulator, thereby generating local hot spots in the area of ​​the dielectric layer directly below the modulator. According to some embodiments, a thermoelectric cooling (TEC) device is provided (e.g., embedded) in the dielectric layer to remove and dissipate heat from the dielectric layer, thereby reducing the thermal risk of the dielectric layer. As a result, the reliability of the dielectric layer and the entire package is improved.

[0022] The embodiments discussed herein provide examples of being able to make or use the disclosed heating subject matter, and those of ordinary skill in the art will readily appreciate that modifications can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0023] Figure 1 is a cross-sectional view of a photonic package 100 according to some embodiments. In some cases, the photonic package 100 can be part of a semiconductor package or another structure. The photonic package 100 can provide an input / output (I / O) interface between optical signals and electrical signals in the semiconductor package. In some embodiments, the photonic package 100 provides an optical network for signal communication between components within the photonic package 100 (e.g., photonic components, integrated circuits, coupling to external optical fibers, etc.). In some cases, the photonic package 100 can be considered an "optical engine." Figure 1 In the example of FIG. 1 , the photonic package 100 includes an electronic die 102 attached (eg, bonded) to a photonic die 101 .

[0024] The electronic die 102 can be, for example, a semiconductor device, die, or chip that communicates with the photonic die 101 using electrical signals. In the illustrated embodiment, the electronic die 102 does not receive, transmit, or process optical signals. In the discussion herein, the term "electronic die" is used to distinguish it from the term "photonic die" (e.g., 101), which refers to a die that can receive, transmit, or process optical signals, such as converting optical signals to electrical signals, or vice versa. In addition to optical signals, the photonic die 101 can also send, receive, or process electrical signals. Figure 1In the example of FIG. 1 , one electronic die 102 is shown, but in other embodiments, the photonic package 100 may include two or more electronic dies 102. In some cases, multiple electronic dies 102 may be combined into a single photonic package 100 to reduce processing costs. The electronic die 102 includes a die connector 124, which may be, for example, a conductive pad, a conductive column, etc. The electronic die 102 is bonded to the topmost conductive feature (e.g., die connector 116) of the redistribution structure 120 (sometimes also referred to as the interconnect structure 120) of the photonic die 101 via the die connector 124.

[0025] The electronic die 102 may include an integrated circuit for interfacing with the photonic component 106 of the photonic die 101. The electronic die 102 may include circuits for controlling the operation of the photonic component 106. For example, the electronic die 102 may include a controller, a driver, a transimpedance amplifier, etc., or a combination thereof. In some embodiments, the electronic die 102 may also include a central processing unit (CPU). In some embodiments, the electronic die 102 includes circuits for processing electrical signals received from the photonic component 106. In some embodiments, the electronic die 102 may control the high-frequency signal conduction of the photonic component based on an electrical signal (digital or analog) received from another device or die. In some embodiments, the electronic die 102 may be an electronic integrated circuit (EIC) or the like that provides a serializer / deserializer (SerDes) function. In this way, the electronic die 102 may be used as part of an I / O interface between optical signals and electrical signals within the photonic package 100. In some embodiments, the photonic package 100 described herein may be considered a system on chip (SoC) or a system on integrated circuit (SoIC) device.

[0026] In some embodiments, a dielectric layer 126 is formed around the electronic die 102 above the redistribution structure 120 of the photonic die 101. The dielectric layer 126 can be a gap-filling material, which can include silicon oxide, silicon nitride, a polymer, etc., or a combination thereof. In some embodiments, the dielectric layer 126 can be a material (e.g., silicon oxide) that is substantially transparent to light of a wavelength suitable for transmitting an optical signal or optical power between the photonic structure (e.g., optical coupler 107) of the photonic die 101 and an external optical fiber 160 attached to the photonic package 100.

[0027] In some embodiments, an optional support 128 is attached to the top surface of the electronic die 102 and the dielectric layer 126 using an adhesive layer 127 according to some embodiments. The support 128 is a rigid structure to provide structural or mechanical stability to the package. One or more external optical fibers 160 can be attached (e.g., fixed) to the support 128 using glue 162, which can be an adhesive, optical glue, etc., to provide optical signals or optical power to the photonic die 101.

[0028] Still refer to Figure 1 , the photonic die 101 includes one or more dielectric layers 190, conductive features (e.g., wires (not shown for simplicity) and vias 136) formed in the dielectric layers 190, and various photonic devices formed in the dielectric layers 190, such as waveguides 104, photonic components 106, and optical couplers 107. In some cases, the waveguides 104, photonic components 106, and optical couplers 107 may be collectively referred to as a "photonic layer" or a "photonic integrated circuit (PIC)".

[0029] In some embodiments, the waveguide 104 is a silicon waveguide formed by patterning a silicon layer. One waveguide 104 or multiple waveguides 104 can be patterned from a silicon layer. If multiple waveguides 104 are formed, the multiple waveguides 104 can be separate waveguides 104, or connected into a single continuous structure. In some embodiments, one or more waveguides 104 form a continuous ring.

[0030] The photonic component 106 may be integrated with the waveguide 104 and may be formed together with the waveguide 104. The photonic component 106 may be optically coupled to the waveguide 104 to interact with the optical signal within the waveguide 104. In some embodiments, the photonic component 106 may include, for example, photonic devices, such as a photodetector 106A and a modulator 106B. For example, the photodetector 106A may be optically coupled to the waveguide 104 to detect the optical signal within the waveguide 104 and generate an electrical signal corresponding to the optical signal. The modulator 106B may be optically coupled to the waveguide 104 to receive the electrical signal and generate a corresponding optical signal within the waveguide 104 by modulating the optical power within the waveguide 104. In this manner, the photonic component 106 facilitates the input / output (I / O) of the optical signal to the waveguide 104. In some cases, the photonic component 106 includes a silicon material and may therefore also be referred to herein as a silicon photonic component 106. In other embodiments, the photonic assembly 106 may include other active or passive components, such as a laser diode, an optical signal splitter, or other types of photonic structures or devices. Optical power may be provided to the waveguide 104 by, for example, an optical fiber 160 coupled to an external light source (not shown). Contacts 113 (e.g., copper vias) are formed to electrically couple the photonic assembly 106 to the redistribution structure 120 of the photonic die 101.

[0031] One or more optical couplers 107 may be integrated with the waveguide 104 and may be formed with the waveguide 204. Each optical coupler 107 (e.g., a grating coupler or an edge coupler) is a photonic structure that allows optical signals and / or optical power to be transmitted between a corresponding waveguide 104 and a photonic component (such as an optical fiber 160 or a waveguide of another photonic system).

[0032] Figure 1 Also shown is a redistribution structure 120 (also referred to herein as a first redistribution structure 120) of the photonic die 101 located above the dielectric layer 190. The redistribution structure 120 includes one or more dielectric layers 115 and conductive features 114 (e.g., wires and vias) formed in the dielectric layer 116 and can provide interconnects and circuit routing. The die connectors 116 (e.g., copper pillars, copper pads, etc.) of the photonic die 101 are formed at the upper surface of the photonic die 101 (e.g., the topmost surface of the redistribution structure 120) and are electrically coupled to the conductive features 114 of the redistribution structure 110.

[0033] The photonic die 101 also includes a conductive connector 144 below the dielectric layer 190, which can be used to electrically connect the photonic package 100 to an external structure, such as a package substrate, an interposer, a printed circuit board (PCB), etc. The conductive connector 144 can be electrically coupled to the conductive features 114 of the redistribution structure 120 through the vias 136. In some cases, an optional passivation layer 140 can be formed below the dielectric layer 190 to provide protection, and an under bump metallization (UBM) 142 can be formed within the passivation layer 140 to make physical and electrical contact with the vias 136. In the illustrated embodiment, the buried oxide ("BOX") substrate 103 (e.g., see Figure 5A )'s oxide layer 103B and the conductive features embedded therein (including conductive lines (not shown for simplicity) and vias 136) form a second redistribution structure 130, which can provide additional interconnection and circuit routing.

[0034] Note that Figure 1In an example of , a heater element 150 is provided within the dielectric layer 115 of the redistribution structure 120 to provide thermal energy (indicated by arrows) to the silicon photonic component below (e.g., the modulator 106B) to keep the modulator 106B operating at a desired high temperature. For example, in some cases where the modulator 106B is a microring modulator (MRM), the heater element 150 will be designed to provide thermal energy at a high power density (e.g., several hundred watts per square millimeter) to keep the modulator 106B operating at a desired high temperature, for example, around 278 degrees Celsius. The modulator 106B operating at such a desired high temperature will expand, allowing the optical signal within the waveguide 104 to accurately enter the modulator 106B. In this way, the thermal drift effects of the silicon photonic component (i.e., the modulator 106B) can be eliminated. The heater element 150 can include any type of heater element that is configured to provide heat to the modulator 106B below. For example, in some embodiments, the heater element 150 may include an embedded resistive coil heater having a temperature control mechanism (not shown) configured to control the temperature of the heater element 150 to a predetermined target temperature.

[0035] However, inevitably, the thermal energy generated by the heater element 150 is also transferred to nearby components (e.g., one or more dielectric layers 190 of the second redistribution structure 130 below the oxide layer 103B) through the heated modulator 106B, thereby generating local hot spots in the region HSR of the dielectric layer 190 directly below the modulator 106B, such as Figure 1 As shown. Local hot spots within the dielectric layer 190 may pose a thermal risk to the dielectric layer 190. For example, when the temperature of the material of the dielectric layer 190 in the region HSR exceeds a threshold temperature (e.g., about 150 degrees Celsius), the weight loss of the dielectric layer 190 may be greater than 5%, resulting in reduced reliability. Therefore, it is desirable to provide a solution to effectively remove heat from the local hot spot region HSR of the dielectric layer 190 to reduce the thermal risk of the dielectric layer 190 of the second redistribution structure 130 and improve the reliability of the entire package.

[0036] Figure 2 is a cross-sectional view of a photonic package 100' according to some embodiments. The photonic package 100' is similar to Figure 1 The photonic package 100 shown in FIG. 1 further includes a thermoelectric cooling (TEC) device 200 in addition to the photonic package 100′. The TEC device 200 provides (e.g., is embedded in) a local hot spot region HSR (e.g., see FIG. 1 ) of the dielectric layer 190 of the second redistribution structure 130 (located below the oxide layer 103B). Figure 1) to remove or dissipate heat from the dielectric layer 190. The thermoelectric cooling device 200 is configured to cool the dielectric layer 190 (eg, a local hot spot region HSR) of the second redistribution structure 130 based on a thermoelectric effect such as a Peltier effect.

[0037] refer to Figure 2 The thermoelectric cooling device 200 includes an n-type semiconductor structure 201 extending vertically through a dielectric layer 190, a p-type semiconductor structure 202 extending vertically through the dielectric layer 190, a first conductive layer 204 (also referred to as a junction 204) coupled to the upper surface of the n-type semiconductor structure 201 and the upper surface of the p-type semiconductor structure 202, and a second conductive layer 206 having a first portion 206A (also referred to as an n-type contact 206A) coupled to the lower surface of the n-type semiconductor structure 201 and a second portion 206B (also referred to as a p-type contact 206B) coupled to the lower surface of the p-type semiconductor structure 202. In the illustrated embodiment, the first conductive layer 204 is in direct contact with the oxide layer 103B above, but the embodiments of the present disclosure are not limited thereto (for example, in other embodiments, a dielectric layer may be interposed between the first conductive layer 104 and the oxide layer 103B). The first portion 206A and the second portion 206B of the second conductive layer 206 are electrically separated from each other and electrically coupled to two separate conductive connections 144.

[0038] In some embodiments, the control circuit 208 electrically connects the n-type semiconductor structure 201 (via the n-type contact 206A and the corresponding conductive connection 144) and the p-type semiconductor structure 202 (via the p-type contact 206B and the corresponding conductive connection 144) to a power source 210 (e.g., a voltage source or a current source). Fig.11 As shown, the photonic package 100' is connected to a printed circuit board (eg, 400, see Fig.11 ) in some cases of external structure, the control circuit 208 and the power supply 210 can be part of the printed circuit board 400.

[0039] Figure 3 is a diagram showing a method according to some embodiments Figure 2 Schematic diagram of the working principle of the thermoelectric cooling device 200 shown. Figure 3 As shown, the thermoelectric cooling device 200 can be arranged between a cooling side 212 and a heat dissipation side 214. In the embodiment shown, the cooling side 212 is connected to a heat source (e.g., a heated modulator 106B and / or a heater element 150, see Figure 2) is adjacent to the power supply 210, and the heat dissipation side 214 is adjacent to the conductive connector 144. The n-type semiconductor structure 201 and the p-type semiconductor structure 202 are thermally connected in parallel. Specifically, the first ends (e.g., upper surfaces) of the n-type semiconductor structure 201 and the p-type semiconductor structure 202 are connected to the cooling side 212 (e.g., through the junction 204), and the second ends (e.g., lower surfaces) of the n-type semiconductor structure 201 and the p-type semiconductor structure 202 are connected to the heat dissipation side 214 (e.g., through the n-type contact 206A and the p-type contact 206B, respectively). The n-type semiconductor structure 201 and the p-type semiconductor structure 202 are electrically connected in series because the conductive path runs from the first terminal of the power supply 210 through the n-type semiconductor structure 201 (e.g., through the n-type contact 206A), through the p-type semiconductor structure 202 (e.g., through the junction 204), and reaches the second terminal of the power supply 210 (e.g., through the p-type contact 206B).

[0040] In operation, power source 210 provides an input to control circuit 208. The input causes current to flow from power source 210 to n-type contact 206A through control circuit 208, from n-type contact 206A through n-type semiconductor structure 201 to junction 204, from junction 204 through p-type semiconductor structure 202 to p-type contact 206B, and from p-type contact 206B to power source 210. n-type semiconductor structure 201 (e.g., including one or more n-type semiconductor materials and / or one or more n-doped semiconductor materials) includes an excess of electrons, and p-type semiconductor structure 202 (e.g., including one or more p-type semiconductor materials and / or one or more p-doped semiconductor materials) includes an excess of holes (and therefore, a deficiency of electrons). The current flows through the n-type semiconductor structure 201 and the p-type semiconductor structure 202, causing excess charge carriers (e.g., electrons of the n-type semiconductor structure 201 and holes of the p-type semiconductor structure 202) to migrate from the junction 204 to the corresponding contacts (e.g., n-type contact 206A for the n-type semiconductor structure 201 and p-type contact 206B for the p-type semiconductor structure 202). The migrated excess carriers transfer heat from the cooling side 212 to the heat dissipation side 214, and then the heat dissipation side 214 dissipates the heat to the printed circuit board 400 through the conductive connection 144 (see Fig.11 ) and / or an additional heat sink (not shown) thereon. Thus, the thermoelectric cooling device 200 cools the local hot spot region HSR (see Figure 1 ).

[0041] Return to reference Figure 2, in the vertical direction (e.g., Z direction), the n-type semiconductor structure 201 and the p-type semiconductor structure 202 have a first thickness H1, the junction 204 has a second thickness H2, and the n-type contact 206A and the p-type contact 206B have a third thickness H3. In some embodiments, the first thickness H1 can be in a range between about 4 μm and about 20 μm, the second thickness H2 can be in a range between about 2 μm and about 3 μm, and the third thickness H3 can be in a range between about 1 μm and about 2 μm (i.e., the total thickness (H1+H2+H3) of the thermoelectric cooling device 200 can be in a range between about 7 μm and about 25 μm), but other suitable thickness values ​​of the components of the thermoelectric cooling device 200 and / or other suitable total thickness values ​​of the thermoelectric cooling device 200 can be used in other embodiments.

[0042] Figure 4 FIG. 1 is a diagram showing a heater element 150 (eg, an embedded resistive coil heater), a photonic component (eg, a modulator 106B, such as a micro-ring modulator), and a Figure 2 200 . It should be noted that for simplicity, the n-type contact 206A and the p-type contact 206B below the n-type semiconductor structure 201 and the p-type semiconductor structure 202 of the thermoelectric cooling device 200 are not shown. Figure 4 In some cases, the heater element 150 can be directly above the modulator 106B (e.g., the center of the circular modulator 106B can be vertically aligned with the center of the annular coil portion of the heater element 150 in a plan view). The diameter D1 of the heater element 150 can be substantially equal to or less than the diameter D2 of the modulator 106B. For example, in some embodiments, the diameter D1 can be in a range between about 5 μm and about 10 μm (e.g., 5 μm), and the diameter D2 can be in a range between about 5 μm and about 10 μm (e.g., 7.5 μm), although other suitable diameter values ​​of the heater element 150 and the modulator 106B can be used in other embodiments.

[0043] exist Figure 4In the example of , the thermoelectric cooling device 200 can have a substantially rectangular shape in a plan view. In particular, the junction 204 at the topmost layer of the thermoelectric cooling device 200 can have a substantially rectangular shape in a plan view, and each of the n-type semiconductor structure 201 and the p-type semiconductor structure 202 below can have a substantially square shape in a plan view. In some embodiments, the thermoelectric cooling device 200 can be directly below the modulator 106B (e.g., the center of the circular modulator 106B can be vertically aligned with the geometric center of the rectangular junction 204 in a plan view). In a plan view, the n-type semiconductor structure 201 and the p-type semiconductor structure 202 can be located on opposite sides of the modulator 106B. For example, as Figure 4 As shown, in some cases, each of the n-type semiconductor structure 201 and the p-type semiconductor structure 202 partially overlaps with the modulator 106B in a plan view. In some embodiments, the n-type semiconductor structure 201 and the p-type semiconductor structure 202 can both have a size (e.g., side length L1) in a range between about 20 μm and about 100 μm, and a pitch P1 between the n-type semiconductor structure 201 and the p-type semiconductor structure 202 can be in a range between about 2 μm and about 20 μm, but other suitable size values ​​and other suitable pitch values ​​can be used in other embodiments.

[0044] It should be noted that Figure 4 The shapes of the components of the thermoelectric cooling device 200 and / or the arrangement and configuration of the components of the thermoelectric cooling device 200 shown in are merely non-limiting examples, and other shapes of the components and other arrangements and configurations of the components are possible and are fully intended to be included within the scope of the present disclosure.

[0045] FIG. 5A to FIG. 5M shows the formation according to some embodiments Figure 2 The cross-sectional view of the intermediate step of the photonic package 100 ′ is shown. Figure 5AAccording to some embodiments, a buried oxide ("BOX") substrate 103 is provided. The BOX substrate 103 includes an oxide layer 103B formed on a substrate 103C and a silicon layer 103A formed on the oxide layer 103B. The substrate 103C may include materials such as glass, ceramics, dielectrics, semiconductors, etc., or combinations thereof. In some embodiments, the substrate 103C is a semiconductor substrate, such as a bulk semiconductor substrate, etc., which may be doped or undoped. The substrate 103C may be a wafer, such as a silicon wafer, etc. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 103C may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. The oxide layer 103B may include, for example, silicon oxide, etc.

[0046] exist Figure 5B In some embodiments, the silicon layer 103A is patterned to form silicon regions for the waveguide 104, the photonic component 106, and the optical coupler 107. The silicon layer 103A can be patterned using suitable photolithography and etching techniques. For example, in some embodiments, a hard mask layer (e.g., a nitride layer, not shown) can be formed over the silicon layer 103A and patterned. The pattern of the hard mask layer can then be transferred to the silicon layer 103A using one or more etching techniques (such as dry etching and / or wet etching techniques). For example, the silicon layer 103A can be etched to form a groove that defines the waveguide 104, and the sidewalls of the remaining unrecessed portions define the sidewalls of the waveguide 104.

[0047] The photonic component 106 may be integrated with the waveguide 104 and may be formed together with the waveguide 104. In some embodiments, the photonic component 106 may include, for example, photonic devices such as a photodetector 106A and a modulator 106B. In some embodiments, the photodetector 106A may be formed by, for example, partially etching a region of the waveguide 104 and growing an epitaxial material on the remaining silicon of the etched region. The waveguide 104 may be etched using acceptable photolithography and etching techniques. The epitaxial material may include, for example, a semiconductor material such as germanium (Ge), which may be doped or undoped. In some embodiments, an implantation process may be performed to introduce dopants into the silicon of the etched region as part of the formation of the photodetector 106A. The silicon of the etched region may be doped with a p-type dopant, an n-type dopant, or a combination thereof. In some embodiments, the modulator 106B may be formed by, for example, partially etching a region of the waveguide 104 and then implanting appropriate dopants into the remaining silicon of the etched region. In some embodiments, the etched region for the photodetector 106A and the etched region for the modulator 106B may be formed using one or more of the same photolithography or etching steps. In some embodiments, the etched regions for the photodetectors 106A and the etched regions for the modulators 106B may be implanted using one or more of the same implantation steps.

[0048] In some embodiments, one or more optical couplers 107 can be integrated with the waveguide 104 and can be formed together with the waveguide 204. The optical coupler 107 can include a grating coupler and / or an edge coupler. In some embodiments, the photonic package 100' can include a single optical coupler 107, a plurality of optical couplers 107, or multiple types of optical couplers 107. The optical coupler 107 can be formed using acceptable lithography and etching techniques. In some embodiments, the optical coupler 107 is formed using the same lithography or etching steps as the waveguide 104 and / or the photonic component 106. In other embodiments, the optical coupler 107 is formed after the waveguide 104 and / or the photonic component 106 are formed.

[0049] exist Figure 5C According to some embodiments, on the front side of the BOX substrate 103 (eg, Figure 5CA dielectric layer 108 is formed on the side of the waveguide 104 facing upward) to form a photon routing structure 110. The dielectric layer 108 is formed over the waveguide 104, the photonic component 106, the optical coupler 107, and the oxide layer 103B. The dielectric layer 108 may be formed of one or more layers of silicon oxide, silicon nitride, etc., or a combination thereof, and may be formed by any acceptable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), lamination, etc., or a combination thereof. Other suitable dielectric materials formed by any acceptable process may be used.

[0050] In some embodiments, dielectric layer 108 is then thinned using a planarization process such as a chemical mechanical polishing (CMP) process, a grinding process, etc. In some cases, a thinner dielectric layer 108 can allow optical coupler 107 and vertically mounted photonic components (e.g., Figure 2 In other embodiments, the planarization process may expose the surface of the waveguide 104, the photonic component 106, and / or the optical coupler 107.

[0051] Due to the difference in refractive index of the materials of the waveguide 104 and the dielectric layer 108, the waveguide 104 has a high internal reflection such that light is substantially confined within the waveguide 104, depending on the wavelength of the light and the refractive index of the corresponding materials. In some embodiments, the refractive index of the material of the waveguide 104 is higher than the refractive index of the material of the dielectric layer 108. For example, the waveguide 104 may include silicon, and the dielectric layer 108 may include silicon oxide and / or silicon nitride.

[0052] exist Figure 5DIn some embodiments, a conductive via 112 extending into the substrate 103C is formed. The via 112 may be formed, for example, by first forming an opening (not shown separately) extending into the substrate 103C. The opening is formed to extend through the dielectric layer 108 and the oxide layer 103B, and partially extends into the substrate 103C. The opening may be formed by acceptable photolithography and etching techniques. A conductive material is then formed in the opening, thereby forming the via 112. In some embodiments, a liner (not shown) such as a diffusion barrier layer (e.g., a layer made of tantalum, tantalum nitride, titanium, titanium nitride, etc.) may be formed in the opening, and the liner may be formed using a suitable deposition process such as ALD, etc. In some embodiments, a seed layer (not shown) may then be deposited in the opening, and the seed layer may include copper or a copper alloy. The conductive material of the conductive via 112 may be formed in the opening using, for example, electroplating or chemical plating. The conductive material may include, for example, a metal or a metal alloy such as copper, silver, gold, tungsten, cobalt, aluminum, or an alloy thereof. A planarization process (eg, a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the dielectric layer 108 so that the via 112 and the top surface of the dielectric layer 108 are flush.

[0053] Figure 5D Also shown is the formation of contacts 113 that extend through dielectric layer 108 and are electrically connected to photonic components 106 (including 106A and 106B). Contacts 113 allow power or electrical signals to be transmitted to photonic components 106, and allow electrical signals to be transmitted from photonic components 106. In this way, photonic components 106 can transmit electrical signals (e.g., from electronic die 102, see Fig. 5F ) is converted into an optical signal transmitted by the waveguide 104, and / or the optical signal from the waveguide 104 is converted into an electrical signal (for example, an electrical signal that can be received by the electronic tube core 104). The contact 113 can be formed before or after the formation of the through hole 112, and the formation of the contact 113 and the formation of the through hole 112 can share some steps, such as the deposition and planarization of the conductive material. In some embodiments, the contact can be formed by a damascene process, for example, single damascene, dual damascene, etc. For example, in some embodiments, an opening (not shown) for the contact 113 is first formed in the dielectric layer 108 using acceptable photolithography and etching techniques. Then, a conductive material can be formed in the opening to form the contact 113. Excess conductive material can be removed using a CMP process or the like. The conductive material of the contact 113 can be formed of a metal or metal alloy including aluminum, copper, tungsten, etc., which can be the same as the conductive material of the through hole 112. In other embodiments, the contact 113 can be formed using other techniques or materials.

[0054] exist Figure 5EIn some embodiments, a (first) redistribution structure 120 is formed over the dielectric layer 108. The redistribution structure 120 includes a dielectric layer 115 and a conductive feature 114 formed in the dielectric layer 115, the conductive feature 114 providing interconnects and circuit routing. For example, the redistribution structure 120 may connect the vias 112, the contacts 113, and / or the devices thereon, such as the electronic die 102 (see Fig. 5F ). Dielectric layer 115 may include one or more materials similar to those described above for dielectric layer 108, such as silicon oxide or silicon nitride, or may include different materials. Dielectric layer 115 may be transparent to light of approximately the same wavelength as dielectric layer 108. Dielectric layer 115 may be formed using techniques similar to those described above for dielectric layer 108 or using different techniques. Conductive features 114 may include conductive lines and vias (which may be made of the same or similar metal or metal alloy material as vias 112 and / or contacts 113), and may be formed by a damascene process, for example, single damascene, dual damascene, etc.

[0055] like Figure 5E As shown, a die connector 116 (e.g., a copper pillar, a copper pad, etc.) is formed in the topmost layer of the dielectric layer 115. After forming the die connector 116, a planarization process (e.g., a CMP process, etc.) may be performed so that the surface of the die connector 116 and the topmost dielectric layer 115 are substantially coplanar. Figure 5E The redistribution structure 120 may include more or fewer dielectric layers 115 , conductive features 114 , or die connectors 116 than shown.

[0056] In some embodiments, some areas of the redistribution structure 120 are substantially free of conductive features 114 or conductive pads 116 to allow optical power or optical signals to be transmitted through the dielectric layer 115. For example, these metal-free areas may be between the optical coupler 107 and the external optical fiber 160 (see Figure 2 ) to allow optical power or optical signals to be coupled from waveguide 104 to optical fiber 160 and / or from optical fiber 160 to waveguide 104.

[0057] Figure 5E Also shown is a heater element 150 formed within a suitable dielectric layer 115 of the redistribution structure 120 and vertically aligned with the silicon photonic component (eg, modulator 106B). Figure 1As discussed above, the heater element 150 is configured to provide thermal energy to the underlying modulator 106B to keep the modulator 106B operating at a desired high temperature, thereby eliminating thermal drift effects of silicon photonic components (e.g., the modulator 106B). The heater element 150 may include any type of heater element that is configured to provide heat to the underlying modulator 106B. In some embodiments, the heater element 150 is an embedded resistive coil heater that may be formed together with (i.e., simultaneously with) some of the conductive features 114 and may be formed using the same materials and the same process steps as discussed above for the conductive features 114. Other types of heater elements 150 and / or other formation techniques may be used in other embodiments.

[0058] exist Fig. 5F In some embodiments, the electronic die 102 is bonded to the redistribution structure 120. Each electronic die 102 can be, for example, a semiconductor device, die, or chip that can communicate with the photonic component 106 using electrical signals. In some embodiments, the electronic die 102 includes a substrate (e.g., a semiconductor substrate such as silicon, etc., not shown separately). Electronic components (not shown) (such as transistors, diodes, capacitors, resistors, etc.) can be formed in and / or on the substrate and can be interconnected by an interconnect structure (not shown) to form an integrated circuit, wherein the interconnect structure is formed by, for example, a metallization pattern (e.g., wires and vias) in one or more dielectric layers above the substrate. The electronic die 102 also includes a pad (not shown), such as an aluminum pad, on which external connections are made. The pad is located on the active side (or front side) of the electronic die 102. One or more passivation layers (not shown) are formed at the front side of the electronic die 102 and on portions of the pad. Die connectors 124, such as conductive pillars (e.g., including metal such as copper), are formed to extend through the passivation layer and are mechanically and electrically coupled to corresponding pads. The electronic die 102 may be obtained by, for example, sawing or dicing a semiconductor wafer (having a plurality of integrated circuit dies formed thereon) along scribe lines to separate the semiconductor wafer into a plurality of individual semiconductor dies.

[0059] In some embodiments, the electronic die 102 is bonded to the redistribution structure 120 using dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In such embodiments, dielectric-to-dielectric bonding may occur between the topmost dielectric layer 115 of the redistribution structure 120 and a bonding layer (not separately shown) of the electronic die 102. During bonding, metal-to-metal bonding may also occur between the die connector 124 of the electronic die 102 and the topmost conductive feature (e.g., die connector 116) of the redistribution structure 120.

[0060] In some embodiments, surface treatment is performed on the redistribution structure 120 and / or the electronic die 102 before performing the bonding process. In some embodiments, the bonding surface of the redistribution structure 120 and / or the electronic die 102 may be activated first using, for example, dry treatment, wet treatment, plasma treatment, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, etc., or a combination thereof. However, any suitable activation process may be used. After the activation process, the redistribution structure 120 and / or the electronic die 102 may be cleaned using, for example, a chemical rinse. Then, the electronic die 102 is aligned with the redistribution structure 120 using, for example, a pick-and-place process, and is placed in physical contact with the redistribution structure 120. Then, the redistribution structure 120 and the electronic die 102 may be subjected to a heat treatment and / or pressed against each other (e.g., by applying contact pressure) to bond the redistribution structure 20 and the electronic die 102. For example, the redistribution structure 120 and the electronic die 102 may be subjected to a pressure of about 200 kPa or less and a temperature in a range of about 200° C. to about 400° C. The redistribution structure 120 and the electronic die 102 may then be subjected to a temperature equal to or higher than the eutectic point of the materials of the die connector 116 and the die connector 124 (e.g., a temperature in a range of about 150° C. to about 650° C.) to melt the die connectors 116 and 124. In this manner, a dielectric-to-dielectric bond and / or a metal-to-metal bond of the redistribution structure 120 and the electronic die 102 forms a bonded structure. In some embodiments, the bonded structure is baked, annealed, pressed, or otherwise treated to strengthen or complete the bond.

[0061] Fig. 5F Also shown is a dielectric layer 126 formed over the electronic die 102 and the redistribution structure 120 according to some embodiments. The dielectric layer 126 can be formed of silicon oxide, silicon nitride, polymer, etc. or a combination thereof, and can be formed by CVD, PVD, ALD, spin-on dielectric processes, etc. or a combination thereof. In some embodiments, the dielectric layer 126 is a gap-filling material, which can include one or more of the example materials described above. In some embodiments, the dielectric layer 126 can be a gap-filling material suitable for use between the optical coupler 107 and the external optical fiber 160 (see Figure 2 ) between the electronic die 102 and the dielectric layer 126. In some embodiments, the dielectric layer 126 may be a material similar to the dielectric layer 115 and / or the dielectric layer 108. Other dielectric materials formed by any acceptable process may be used. The dielectric layer 126 may then be planarized using a planarization process such as a CMP process, a grinding process, etc. In some embodiments, the planarization process may expose the electronic die 102 so that the surfaces of the electronic die 122 and the dielectric layer 126 are coplanar.

[0062] exist Figure 5G In some embodiments, an optional support 128 is attached to the above structure. The support 128 is a rigid structure that is attached to the structure to provide structural or mechanical stability. The use of the support 128 can reduce warping or bending, which can improve the performance of the optical structure (such as the waveguide 104 and / or the photonic component 106). The support 128 may include one or more materials, such as silicon (e.g., a silicon wafer, etc.), silicon oxide, silicon oxynitride, silicon carbonitride, metal, organic core material, etc. In some embodiments, the support 128 can be attached to the structure (e.g., to the dielectric layer 126 and / or the electronic tube core 102) using an adhesive layer 127. In some other embodiments, the support 128 can be attached using direct bonding (e.g., dielectric to dielectric bonding or fusion bonding) or another suitable technique. In some embodiments, the support 128 can be subsequently thinned using a CMP process, a grinding process, etc. Although not shown, in some embodiments, the support member 128 may also include a lens structure and / or an anti-reflection coating formed on its surface to facilitate the attachment of the optical fiber 160 and the optical coupler 107 (see Figure 2 ) between them.

[0063] exist Figure 5H According to some embodiments, flipping Figure 5G The resulting structure shown is removed and substrate 103C is removed. In some cases, the structure may be attached to a temporary carrier (not shown) before removing substrate 103C. According to some embodiments, substrate 103C may be removed to expose oxide layer 103B and vias 112. Substrate 103C may be removed using a CMP process, mechanical grinding, an etching process, etc., or a combination thereof. In some embodiments, oxide layer 103B is thinned during removal of substrate 103C or using a separate process step.

[0064] FIG. 5I to FIG. 5L The second redistribution structure 130 is shown formed over the oxide layer 103B according to some embodiments (see FIG. Figure 5L ) and forming a thermoelectric cooling (TEC) device 200 (see Figure 5L ). Note that for simplicity, some wires and interconnects within the second redistribution structure 130 are not shown in these figures, but they actually exist. Fig.5I, a dielectric layer 131 is formed over the oxide layer 103B. The dielectric layer 131 may include, for example, a polymer such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc., and may be formed by spin coating, lamination, CVD, PVD, ALD, etc. Then, conductive components (e.g., wires (not shown) and vias 132) of the thermoelectric cooling device 200 and the first conductive layer 204 are formed in the dielectric layer 131 using materials and techniques similar to those previously described for forming the vias 112. Fig.5I As shown, via 132 may be vertically aligned with and in contact with underlying via 112, and first conductive layer 204 may be vertically aligned with underlying modulator 106B and in contact with oxide layer 103B.

[0065] exist Figure 5J In the embodiment, the n-type semiconductor structure 201 and the p-type semiconductor structure 202 of the thermoelectric cooling device 200 are formed on and in contact with the first conductive layer 204. The n-type semiconductor structure 201 may include one or more n-type semiconductor materials and / or one or more n-doped semiconductor materials, and the p-type semiconductor structure 202 may include one or more p-type semiconductor materials and / or one or more p-doped semiconductor materials. In an exemplary embodiment, as an example, the n-type semiconductor structure 201 includes Bi2Te3, and the p-type semiconductor structure 202 includes Sb2Te3, but other suitable n-type and p-type semiconductor materials may be used in other embodiments. The n-type semiconductor structure 201 and the p-type semiconductor structure 202 may be formed by, for example, forming a patterned mask layer (not shown) above the first conductive layer 204, wherein the pattern of the openings in the patterned mask layer corresponds to the pattern of the n-type semiconductor structure 201 and the p-type semiconductor structure 202 formed subsequently. Then, an appropriate deposition process (such as sputtering) is used to form an n-type semiconductor material and a p-type semiconductor material (as described above) in the opening of the patterned mask layer, thereby forming an n-type semiconductor structure 201 and a p-type semiconductor structure 202 on the first conductive layer 204. In some embodiments, after the n-type semiconductor structure 201 and the p-type semiconductor structure 202 are formed, the patterned mask layer can be removed by an ashing process or other acceptable etching process. In other embodiments, other suitable processes for forming the n-type semiconductor structure 201 and the p-type semiconductor structure 202 can be used.

[0066] exist Figure 5KIn some embodiments, a dielectric layer 133 is formed over dielectric layer 131, first conductive layer 204, via 132, n-type semiconductor structure 201, and p-type semiconductor structure 202 using materials and techniques similar to those previously described for forming dielectric layer 131. Then, dielectric layer 133 is thinned using a planarization process such as a CMP process, a grinding process, etc., until the top surfaces of n-type semiconductor structure 201 and p-type semiconductor structure 202 are exposed.

[0067] exist Figure 5L In some embodiments, dielectric layer 135 is formed on dielectric layer 133, n-type semiconductor structure 201, and p-type semiconductor structure 202 using materials and techniques similar to those previously described for forming dielectric layer 131. Through-hole 134 is then formed using materials and techniques similar to those previously described for forming through-hole 112, and through-hole 134 extends through dielectric layer 135 and dielectric layer 133 to contact through-hole 132 below. In the description herein, through-hole 134, through-hole 132, and through-hole 112 that are stacked and connected to each other may be collectively referred to as through-hole 136 (see also Figure 2 ), the via 136 extends through the dielectric layer 108, the oxide layer 103B, the dielectric layer 131, the dielectric layer 133 and the dielectric layer 135 (these layers may be collectively referred to herein as one or more dielectric layers 190, such as Figure 2 Some dielectric layers 190 (eg, 131, 133, and 135) above the oxide layer 103B and conductive features (including conductive lines (not shown) and vias 136) embedded therein form a second redistribution structure 130 (see also Figure 2 ).

[0068] Figure 5L Also shown is a second conductive layer 206 of the thermoelectric cooling device 200 formed in the dielectric layer 135. According to some embodiments, the second conductive layer 206 may be formed in the dielectric layer 135 using materials and techniques similar to those previously described for forming the via 112. In some embodiments, the second conductive layer 206 of the thermoelectric cooling device 200 may be formed before or after forming the via 134. The second conductive layer 206 may include a first portion 206A in contact with the n-type semiconductor structure 201 (i.e., the n-type contact 206A) and a second portion 206B in contact with the p-type semiconductor structure 202 (i.e., the p-type contact 206B).

[0069] The first conductive layer 204, the n-type semiconductor structure 201, the p-type semiconductor structure 202, and the first portion 206A and the second portion 206B of the second conductive layer 206 within the dielectric layers 131, 133, and 135 (which may be made of polyimide and may therefore also be referred to as polyimide layers in some cases) constitute the thermoelectric cooling device 200. As discussed above, the thermoelectric cooling device 200 is compatible with existing semiconductor manufacturing processes and may be manufactured simultaneously with the manufacture of the second redistribution structure 130. For example, in some embodiments, the first conductive layer 204 and the second conductive layer 206 of the thermoelectric cooling device 200 may be formed in the same step as the formation of the conductive components (e.g., the conductive lines (not shown) and the vias 136) of the second redistribution structure 130.

[0070] exist Figure 5M In some embodiments, a conductive connector 144 is formed over the via 136. In some embodiments, an optional passivation layer 140 is formed over the second redistribution structure 130 before the conductive connector 144 is formed. The passivation layer 140 may include, for example, a polymer such as PBO, PI, BCB, etc., and may be formed by spin coating, lamination, CVD, PVD, ALD, etc. In some embodiments, an under bump metallization (UBM) 142 may be formed within the passivation layer 140 to make physical and electrical contact with the via 136. The UBM 142 may be formed from one or more suitable conductive materials using a suitable process such as plating. According to some embodiments, a conductive connector 144 is then formed on the UBM 142 using a suitable process such as plating, printing, solder transfer, ball placement, etc. The conductive connector 144 may be, for example, a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 144 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof.

[0071] Still refer to Figure 5M , and then a singulation process is performed by, for example, sawing along the scribe line 149 of the package structure to separate the plurality of photon packages within the package structure into individual photon packages 100 ′, such as Figure 2 The individual photonic packages 100' are shown. In some cases, the package structure can be flipped over and attached to a temporary carrier (not shown) before the singulation process. A debonding process can then be performed after the singulation process to debond or remove the carrier from the photonic package 100'. The carrier can be removed by any acceptable process, such as an etching process, a CMP process, a grinding process, etc., or other acceptable removal process. Although not shown, in some cases, the optical fiber 160 (e.g., see Figure 2) may be attached to the support 128 of the photonic package 100 ′ within the packaging structure.

[0072] Figure 6 is a cross-sectional view of a photonic package 100' according to some embodiments. The photonic package 100" is similar to Figure 2 The photonic package 100' shown in the figure, in addition to the photonic package 100" further includes a heat sink 300 (e.g., a copper (Cu) heat sink), the heat sink 300 provides (e.g., is embedded in) the local hot spot region HSR (e.g., see Figure 1 ) and is vertically arranged between the heated modulator 106B and the thermoelectric cooling device 200. The heat sink 300 is configured to allow heat to diffuse rapidly on the heat sink 300 from a local hot spot (e.g., directly below the heated modulator 106B) in a horizontal direction (e.g., in an XY plane), and then the heat is transferred from the cooling side (e.g., adjacent to the heat sink 300) to the heat dissipation side by the thermoelectric cooling device 200, and then the heat dissipation side dissipates the heat to the printed circuit board and / or an additional heat sink (not shown) thereon through the conductive connector 144. Therefore, the cooling efficiency of the thermoelectric cooling device 200 is improved by the heat sink 300. According to some embodiments, the heat sink 300 can be formed using materials and techniques similar to those previously described for forming the through-hole 112.

[0073] In some embodiments, the thickness H4 of the heat sink 300 (eg, in a range between about 5 μm and about 10 μm) is greater than the thickness H2 of the first conductive layer 204 of the thermoelectric cooling device 200 (see Figure 2 ) to obtain better horizontal heat dissipation capability. In some embodiments, the heat sink 300 is disposed in the topmost dielectric layer 190 of the second redistribution structure 130 and contacts the oxide layer 103B. In some embodiments, the dielectric layer 190 is inserted between the heat sink 300 and the first conductive layer 204 of the thermoelectric cooling device 200 to prevent a wire (not shown) located at the same layer as the heat sink 300 from forming a short circuit with the first conductive layer 104. In other embodiments, if there is no short circuit problem, the dielectric layer 190 between the heat sink 300 and the first conductive layer 204 can be omitted.

[0074] Figure 7 is a diagram showing a method according to some embodiments Figure 6 0 is a plan view (e.g., top view) of an arrangement of a heater element 150 (e.g., an embedded resistive coil heater), a photonic component (e.g., a modulator 106B, such as a micro-ring modulator), a heat sink 300, and a thermoelectric cooling device 200 shown in FIG. Figure 7The arrangement of the heater element 150, modulator 106B and thermoelectric cooling device 200 shown may be similar to Figure 4 The heater element 150, modulator 106B, and thermoelectric cooling device 200 shown are identical, so the details are not repeated here. Figure 7 In the example of FIG. 1 , the heat sink 300 can have a substantially rectangular shape in plan view, and in some cases can be directly located above the junction 204 of the thermoelectric cooling device 200 (e.g., the geometric center of the rectangular heat sink 300 can be vertically aligned with the geometric center of the rectangular junction 204 in plan view). The size of the heat sink 300 (i.e., the area in the XY plane) can be equal to or greater than the size of the junction 204 of the thermoelectric cooling device 200. Other shapes and / or other arrangements of the heat sink 300 are also possible and are fully intended to be included within the scope of the present disclosure.

[0075] Figure 8 is a cross-sectional view of a photonic package 100'' according to some embodiments. The photonic package 100'' is similar to Figure 6 The photonic package 100' is shown, except that the thermoelectric cooling device 200 is replaced by a thermoelectric cooling device 200'. The thermoelectric cooling device 200' includes a first n-type semiconductor structure 201, a first p-type semiconductor structure 202, a second n-type semiconductor structure 201A, a second p-type semiconductor structure 202A, a first conductive layer 204, and a second conductive layer 206. The first conductive layer 204 has a first portion 204A coupled to an upper surface of the first n-type semiconductor structure 201 and an upper surface of the first p-type semiconductor structure 202 (also referred to as a first junction 204A) and a second portion 204B coupled to an upper surface of the second n-type semiconductor structure 201A and an upper surface of the second p-type semiconductor structure 202A (also referred to as a second junction 204B). The second conductive layer 206 has a first portion 204A coupled to an upper surface of the first n-type semiconductor structure 201 and an upper surface of the first p-type semiconductor structure 202. The first portion 206A (also referred to as the n-type contact 206A) of the lower surface of the structure 201, the second portion 206B (also referred to as the third junction 206B) coupled to the lower surface of the first p-type semiconductor structure 202 and the lower surface of the second n-type semiconductor structure 201A, and the third portion 206C (also referred to as the p-type contact 206C) coupled to the lower surface of the second p-type semiconductor structure 202A. The first portion 204A and the second portion 204B of the first conductive layer 204 are electrically separated from each other. The first portion 206A, the second portion 206B, and the third portion 206C of the second conductive layer 206 are electrically separated from each other, and the first portion 206A (i.e., the n-type contact 206A) and the third portion 206C (i.e., the p-type contact 206C) are electrically coupled to two separate conductive connections 144.

[0076] In the illustrated embodiment, the first n-type semiconductor structure 201, the first p-type semiconductor structure 202, the first portion 204A of the first conductive layer 204, and the first portion 206A of the second conductive layer 206 form a first thermoelectric device. The second n-type semiconductor structure 201A, the second p-type semiconductor structure 202A, the second portion 204B of the first conductive layer 204, and the second portion 206B and the third portion 206C of the second conductive layer 206 form a second thermoelectric device. The first thermoelectric device and the second thermoelectric device are connected in series to form a serially connected thermoelectric cooling device 200', and Figure 2 or Figure 6 The thermoelectric cooling device 200 shown has improved cooling efficiency. When the heat sink 300 (e.g., a copper heat sink) is vertically disposed between the heated modulator 106B and the thermoelectric cooling device 200', each of the first portion 204A and the second portion 204B of the first conductive layer 204 partially overlaps the heat sink 300 in the vertical direction (e.g., the Z direction), so that the first thermoelectric device and the second thermoelectric device of the thermoelectric cooling device 200' can be thermally coupled to the heat sink 300.

[0077] Fig. 9 is a cross-sectional view of a photonic package 100"" according to some embodiments. The photonic package 100"" is similar to Figure 2 The photonic package 100' shown in FIG. 1 includes a heat sink 300' (e.g., a Cu heat sink) provided (e.g., embedded) within the oxide layer 103B and vertically disposed between the heated modulator 106B and the thermoelectric cooling device 200. In some embodiments, the heat sink 300' extends through the entire thickness of the oxide layer 103B, or extends from the bottom surface of the oxide layer 103B to a depth below the top surface of the oxide layer 103B (i.e., not exposed from the top surface of the oxide layer 103B). It should be noted that although in Fig. 9 In the example of , the thermoelectric cooling device 200 (e.g., the first conductive layer 204) is depicted as being in direct contact with the oxide layer 103B (and the heat sink 300'), but in other embodiments, the thermoelectric cooling device 200 (e.g., the first conductive layer 204) can be separated from the oxide layer 103B (and the heat sink 300') by the dielectric layer 190. In addition, Fig. 9 The heat sink 300 ′ in the example has a hollow ring structure different from the heat sink 300 described above.

[0078] Fig.10 is a diagram showing a method according to some embodiments Fig. 90 is a plan view (eg, top view) of an arrangement of a heater element 150 (eg, an embedded resistive coil heater), a photonic component (eg, a modulator 106B, such as a micro-ring modulator), a heat sink 300 ′, and a thermoelectric cooling device 200 shown in FIG. Fig.10 The arrangement of the heater element 150, modulator 106B and thermoelectric cooling device 200 shown may be similar to Figure 4 The heater element 150, modulator 106B, and thermoelectric cooling device 200 shown are identical, so the details are not repeated here. Fig.10 In some cases, the heat sink 300' is directly above the modulator 106B (e.g., the center of the circular modulator 106B can be vertically aligned with the center of the annular heat sink 300' in plan view). In some embodiments, the inner diameter D3 of the annular heat sink 300' can be slightly larger than the diameter D2 of the modulator 106B (e.g., see Figure 4 ), for example, in a range between about 6 μm and about 10 μm (e.g., 8 μm), so that the heat sink 300' and the modulator 106B do not contact each other. This prevents the modulator 106B from shorting with the wires or interconnects of the second redistribution structure 130 (or the thermoelectric cooling device 200) through the heat sink 300'.

[0079] According to some embodiments, heat spreader 300' may be formed within oxide layer 103B using materials and techniques similar to those previously described for forming via 112. For example, in some cases, before second redistribution structure 130 is formed over oxide layer 103B (e.g., before Figure 5H In the step shown), a patterned mask layer (not shown) may be formed over the oxide layer 103A, wherein the pattern of the openings within the patterned mask layer corresponds to the pattern of the heat sink 300' to be formed. Then, the pattern of the mask layer may be transferred to the oxide layer 103B using one or more etching techniques, such as dry etching and / or wet etching techniques. A conductive material (e.g., Cu) is then formed in the openings of the oxide layer 103B, thereby forming the heat sink 300'. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the oxide layer 103B, so that the heat sink 300' and the top surface of the oxide layer 103B (i.e., Fig. 9 bottom surface shown) is flush.

[0080] Similarly, the heat sink 300' allows heat to be rapidly diffused in the horizontal direction (e.g., in the XY plane) from a local hot spot (e.g., directly below the heated modulator 106B) on the heat sink 300', and then the heat is transferred from the cooling side (e.g., adjacent to the heat sink 300') to the heat dissipation side by the thermoelectric cooling device 200, and then the heat dissipation side dissipates the heat to the printed circuit board and / or an additional heat sink (not shown) thereon through the conductive connector 144. Therefore, the cooling efficiency of the thermoelectric cooling device 200 is improved by the heat sink 300'.

[0081] In some other embodiments, the heat sink 300' embedded in the oxide layer 103B may be formed by Figure 6 and Figure 7 The heat sink 300 shown has the same shape and structure.

[0082] Fig.11 is a cross-sectional view of a semiconductor package according to some embodiments, the semiconductor package including a semiconductor device mounted on a printed circuit board (PCB) 400 Figure 2 The photon package 100' shown. In some cases, the photon package 100' is bonded to the PCB 400 using the conductive connector 144. The bottom fill layer 410 can be formed in the gap between the photon package 100' and the PCB 400 to surround and protect the conductive connector 144 and enhance the connection between the photon package 100' and the PCB 400. The bottom fill material of the bottom fill layer 410 can include, for example, epoxy, resin, filler material, stress release agent (SRA), adhesion promoter, another suitable material, or a combination thereof. In some embodiments, the bottom fill material can be applied in liquid form and then cured by a reflow process to form the bottom fill layer 410. It should also be understood that since the thermoelectric cooling device 200 can effectively transfer heat from the dielectric layer 190 adjacent to the bottom of the photon package 100' to the PCB 400 (the heat can then be dissipated through the PCB 400), it can also reduce the thermal risk caused by heat accumulation in the dielectric layer 107 to the adjacent bottom fill layer 410. Therefore, the reliability of the underfill layer 410 and the entire semiconductor package is further improved.

[0083] It should be understood that the structures, configurations, and manufacturing methods described herein are exemplary only and are not intended to and should not be construed as limiting the present disclosure. Once informed by the present disclosure, many alternatives and modifications will be apparent to those skilled in the art. For example, although the present disclosure is described using embodiments in which thermoelectric cooling devices are disposed within local hot spot regions of some dielectric layers directly beneath a heated modulator, embodiments in which thermoelectric cooling devices are disposed within local hot spot regions of some dielectric layers directly beneath other types of heated silicon photonic components are expressly contemplated herein. In addition, although in the above-described embodiments, the thermoelectric cooling devices are disposed within local hot spot regions of some dielectric layers directly beneath a heated photonic component, the thermoelectric cooling devices may also be placed in the vicinity of a local hot spot region of a dielectric layer (e.g., not directly beneath a heated photonic component) as long as it can effectively cool the local hot spot region of the dielectric layer.

[0084] Embodiments of the present disclosure discussed herein may have advantages. By providing (e.g., embedding) a thermoelectric cooling device in some dielectric layers located below a heated silicon photonic component (e.g., a modulator), heat in the dielectric layer (e.g., a local hot spot area) may be effectively removed and dissipated, thereby reducing the thermal risk of the dielectric layer. As a result, the reliability of the dielectric layer and the entire package is improved. In addition, the thermoelectric cooling device is compatible with existing semiconductor manufacturing processes and can be manufactured simultaneously with the manufacture of the redistribution structure of the photonic package.

[0085] According to some embodiments, a semiconductor package is provided. The semiconductor package includes an oxide layer and a waveguide and a photonic component located on a first side of the oxide layer. The semiconductor package also includes a heater element adjacent to the photonic component and configured to provide thermal energy to the photonic component. The semiconductor package also includes a redistribution structure located on a second side of the oxide layer opposite to the first side. The redistribution structure includes a plurality of dielectric layers and a conductive component located in the dielectric layer. In addition, the semiconductor package includes a thermoelectric cooling device embedded in the dielectric layer of the redistribution structure and directly below the photonic component.

[0086] According to some embodiments, a semiconductor package is provided. The semiconductor package includes an oxide layer and a photonic component located on a first side of the oxide layer. The semiconductor package also includes a heater element adjacent to the photonic component and configured to provide thermal energy to the photonic component. The semiconductor package also includes a redistribution structure located on a second side of the oxide layer opposite to the first side. The redistribution structure includes a plurality of dielectric layers and a conductive component located in the dielectric layer. In addition, the semiconductor package includes a thermoelectric cooling device embedded in the dielectric layer of the redistribution structure. The thermal energy provided by the heater element is also transferred to the dielectric layer through the photonic component, resulting in a local hot spot in a region of the dielectric layer directly below the photonic component. The thermoelectric cooling device is arranged directly in a region of the dielectric layer or adjacent to a region of the dielectric layer.

[0087] According to some embodiments, a method for forming a semiconductor package is provided. The method includes: forming a waveguide and a photonic component on a first side of an oxide layer. The method also includes forming a first redistribution structure above the waveguide and the photonic component, wherein the first redistribution structure includes a plurality of first dielectric layers and a first conductive component located in the first dielectric layer. The method also includes providing a heater element in one of the plurality of first dielectric layers of the first redistribution structure to provide thermal energy to the photonic component. The method also includes bonding an electronic die to the first redistribution structure, wherein the electronic die is electrically connected to the photonic component through the first conductive component. The method also includes forming a second redistribution structure on a second side of the oxide layer opposite to the first side, wherein the second redistribution structure includes a plurality of second dielectric layers and a second conductive component located in the second dielectric layer. In addition, the method includes providing a thermoelectric cooling device in a second dielectric layer of the second redistribution structure, wherein the thermoelectric cooling device is directly below the photonic component.

[0088] Some embodiments of the present application provide a semiconductor package, comprising: an oxide layer; a waveguide and a photonic component located on a first side of the oxide layer; a heater element adjacent to the photonic component; a redistribution structure located on a second side of the oxide layer opposite to the first side, wherein the redistribution structure comprises a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and a thermoelectric cooling device embedded in the plurality of dielectric layers of the redistribution structure and directly beneath the photonic component.

[0089] In some embodiments, the photonic component is a silicon photonic component comprising silicon. In some embodiments, the photonic component is a modulator, and wherein the heater element is configured to provide thermal energy to the photonic component. In some embodiments, the thermoelectric cooling device comprises: an n-type semiconductor structure and a p-type semiconductor structure extending vertically through at least some of the plurality of dielectric layers; a first conductive layer coupled to an upper surface of the n-type semiconductor structure and an upper surface of the p-type semiconductor structure; and a second conductive layer having a first portion coupled to a lower surface of the n-type semiconductor structure and a second portion coupled to a lower surface of the p-type semiconductor structure. In some embodiments, the semiconductor package further comprises a plurality of conductive connectors located below the redistribution structure, wherein the first portion and the second portion of the second conductive layer are electrically separated from each other and electrically coupled to two of the plurality of conductive connectors. In some embodiments, the first conductive layer is in direct contact with the oxide layer, and the first conductive layer overlaps the photonic component in a plan view. In some embodiments, the semiconductor package further comprises a heat sink vertically arranged between the photonic component and the first conductive layer of the thermoelectric cooling device. In some embodiments, the heat sink is embedded in the topmost dielectric layer of the plurality of dielectric layers of the redistribution structure and is in direct contact with the oxide layer. In some embodiments, the heat sink is embedded in the oxide layer and is separated from the photon component by a portion of the oxide layer. In some embodiments, the heat sink has a hollow ring structure, and an inner diameter of the hollow ring structure is greater than a diameter of the photon component. In some embodiments, the thermoelectric cooling device includes: a first n-type semiconductor structure, a first p-type semiconductor structure, a second n-type semiconductor structure, and a second p-type semiconductor structure, extending vertically through at least some of the multiple dielectric layers; a first conductive layer, having a first portion and a second portion, the first portion coupled to an upper surface of the first n-type semiconductor structure and an upper surface of the first p-type semiconductor structure, and the second portion coupled to an upper surface of the second n-type semiconductor structure and an upper surface of the second p-type semiconductor structure; and a second conductive layer, having a first portion coupled to a lower surface of the first n-type semiconductor structure, a second portion coupled to a lower surface of the first p-type semiconductor structure and a lower surface of the second n-type semiconductor structure, and a third portion coupled to a lower surface of the second p-type semiconductor structure, wherein the first portion and the second portion of the first conductive layer are electrically separated from each other, and the first portion, the second portion, and the third portion of the second conductive layer are electrically separated from each other.In some embodiments, the semiconductor package further comprises: an interconnect structure located above the waveguide and the photonic component on the oxide layer; and an electronic die located above the interconnect structure and interconnected with the photonic component through the interconnect structure, wherein the heater element is embedded in a dielectric layer of the interconnect structure.

[0090] Other embodiments of the present application provide a semiconductor package, comprising: an oxide layer; a photonic component located on a first side of the oxide layer; a heater element adjacent to the photonic component; a redistribution structure located on a second side of the oxide layer opposite to the first side, wherein the redistribution structure comprises a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and a thermoelectric cooling device embedded in the plurality of dielectric layers of the redistribution structure, and wherein the thermoelectric cooling device is directly arranged in a region of the plurality of dielectric layers directly below the photonic component, or adjacent to the region of the plurality of dielectric layers directly below the photonic component.

[0091] In some embodiments, the semiconductor package further comprises: a printed circuit board electrically connected to the redistribution structure and the thermoelectric cooling device through a plurality of conductive connections located below the redistribution structure; and an underfill layer formed in a gap between the redistribution structure and the printed circuit board to surround the plurality of conductive connections. In some embodiments, the heater element is configured to provide thermal energy to the photon assembly, and wherein the thermal energy provided by the heater element is also transferred to the plurality of dielectric layers through the photon assembly to generate a local hot spot in a region of the plurality of dielectric layers directly below the photon assembly.

[0092] Some other embodiments of the present application provide a method for forming a semiconductor package, comprising: forming a waveguide and a photonic component on a first side of an oxide layer; forming a first redistribution structure above the waveguide and the photonic component, wherein the first redistribution structure includes a plurality of first dielectric layers and a first conductive component located in the plurality of first dielectric layers; providing a heater element in one of the plurality of first dielectric layers of the first redistribution structure; bonding an electronic die to the first redistribution structure, wherein the electronic die is electrically connected to the photonic component through the first conductive component; forming a second redistribution structure on a second side of the oxide layer opposite to the first side, wherein the second redistribution structure includes a plurality of second dielectric layers and a second conductive component located in the plurality of second dielectric layers; and providing a thermoelectric cooling device in the plurality of second dielectric layers of the second redistribution structure, wherein the thermoelectric cooling device is directly located below the photonic component.

[0093] In some embodiments, providing the thermoelectric cooling device includes: forming an n-type semiconductor structure and a p-type semiconductor structure extending vertically through at least some of the plurality of second dielectric layers; forming a first conductive layer, the first conductive layer coupled to an upper surface of the n-type semiconductor structure and an upper surface of the p-type semiconductor structure; and forming a second conductive layer, the second conductive layer having a first portion coupled to a lower surface of the n-type semiconductor structure and a second portion coupled to a lower surface of the p-type semiconductor structure, wherein the first portion and the second portion of the second conductive layer are electrically separated from each other, and the first conductive layer is closer to the oxide layer than the second conductive layer. In some embodiments, the method further includes: providing a first conductive connector coupled to the first portion of the second conductive layer; and providing a second conductive connector coupled to the second portion of the second conductive layer. In some embodiments, the n-type semiconductor structure, the p-type semiconductor structure, the first conductive layer, and the second conductive layer of the thermoelectric cooling device are formed during the formation of the second redistribution structure. In some embodiments, the method further includes: providing a heat sink in the topmost dielectric layer of the plurality of second dielectric layers of the second redistribution structure, and the heat sink is vertically arranged between the photonic component and the first conductive layer of the thermoelectric cooling device; or providing a heat sink in the oxide layer, and the heat sink is vertically arranged between the photonic component and the first conductive layer of the thermoelectric cooling device, wherein the heat sink is electrically isolated from the photonic component by a portion of the oxide layer.

[0094] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: Oxide layer; a waveguide and a photonic component located on a first side of the oxide layer; a heater element adjacent to the photonic assembly; a redistribution structure located on a second side of the oxide layer opposite to the first side, wherein the redistribution structure comprises a plurality of dielectric layers and conductive features located in the plurality of dielectric layers; as well as A thermoelectric cooling device is embedded in the plurality of dielectric layers of the redistribution structure and is directly beneath the photonic component.

2. The semiconductor package according to claim 1, wherein: The photonic component is a silicon photonic component comprising silicon.

3. The semiconductor package according to claim 2, wherein: The photonic component is a modulator, and wherein the heater element is configured to provide thermal energy to the photonic component.

4. The semiconductor package according to claim 1, wherein: The thermoelectric cooling device comprises: an n-type semiconductor structure and a p-type semiconductor structure extending vertically through at least some of the plurality of dielectric layers; a first conductive layer coupled to an upper surface of the n-type semiconductor structure and an upper surface of the p-type semiconductor structure; and The second conductive layer has a first portion coupled to the lower surface of the n-type semiconductor structure and a second portion coupled to the lower surface of the p-type semiconductor structure.

5. The semiconductor package according to claim 4, further comprising a plurality of conductive connections located below the redistribution structure, wherein: The first portion and the second portion of the second conductive layer are electrically separated from each other and electrically coupled to two of the plurality of conductive connections.

6. The semiconductor package according to claim 4, wherein: The first conductive layer is in direct contact with the oxide layer, and the first conductive layer overlaps the photonic component in a plan view. 7 . The semiconductor package of claim 4 , further comprising a heat sink vertically disposed between the photonic assembly and the first conductive layer of the thermoelectric cooling device.

8. The semiconductor package according to claim 7, wherein: The heat spreader is embedded in a topmost dielectric layer of the plurality of dielectric layers of the redistribution structure and is in direct contact with the oxide layer.

9. A semiconductor package, comprising: Oxide layer; a photonic component disposed on the first side of the oxide layer; a heater element adjacent to the photonic assembly; a redistribution structure on a second side of the oxide layer opposite the first side, wherein the redistribution structure comprises a plurality of dielectric layers and conductive features in the plurality of dielectric layers; and A thermoelectric cooling device is embedded in the plurality of dielectric layers of the redistribution structure, and wherein the thermoelectric cooling device is arranged directly in or adjacent to a region of the plurality of dielectric layers directly beneath the photonic component.

10. A method of forming a semiconductor package, comprising: forming a waveguide and a photonic component on a first side of the oxide layer; forming a first redistribution structure over the waveguide and the photonic component, wherein the first redistribution structure comprises a plurality of first dielectric layers and a first conductive feature in the plurality of first dielectric layers; providing a heater element in one of the plurality of first dielectric layers of the first redistribution structure; bonding an electronic die to the first redistribution structure, wherein the electronic die is electrically connected to the photonic component through the first conductive feature; forming a second redistribution structure on a second side of the oxide layer opposite to the first side, wherein the second redistribution structure comprises a plurality of second dielectric layers and a second conductive feature in the plurality of second dielectric layers; and A thermoelectric cooling device is provided in the plurality of second dielectric layers of the second redistribution structure, wherein the thermoelectric cooling device is located directly below the photonic component.

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