Stacked semiconductor module with double-sided heat dissipation structure and manufacturing method thereof

Abstract

The present invention provides a stacked semiconductor module having a double-sided heat dissipation structure in which a semiconductor die is arranged in a stacked structure with a heat dissipation substrate therebetween, the stacked semiconductor module having a double-sided heat dissipation structure according to an embodiment of the present invention comprising: a first heat dissipation substrate; a second heat dissipation substrate disposed on a lower side of the first heat dissipation substrate so as to face the first heat dissipation substrate; a first semiconductor die module mounted between the first heat dissipation substrate and the second heat dissipation substrate; a third heat dissipation substrate disposed on the lower side of the second heat dissipation substrate so as to face the second heat dissipation substrate; and a second semiconductor die module mounted between the second heat dissipation substrate and the third heat dissipation substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor module, and more particularly to a semiconductor module with a double-sided heat dissipation structure. Background Art

[0002] Recently, as the demand for semiconductors in various fields has increased, various research and development efforts have been conducted to improve the functions of semiconductors under specific conditions in addition to the main functions of semiconductors.

[0003] Generally speaking, a semiconductor module includes at least one semiconductor device in a package. In particular, a semiconductor module including a semiconductor device whose physical properties change due to an increase in heat generated by high internal pressure and high current includes a heat dissipation unit for heat dissipation. Semiconductor modules including a heat dissipation unit are divided into semiconductor modules with a single-sided heat dissipation structure and semiconductor modules with a double-sided heat dissipation structure.

[0004] In particular, a semiconductor module having a double-sided heat dissipation structure can release heat from both the upper and lower parts of each semiconductor device, and therefore is known to be very beneficial to the heat dissipation effect.

[0005] The semiconductor module with the double-sided heat dissipation structure adopts a structure in which semiconductor bare chips are installed between two heat dissipation substrates. The number of semiconductor bare chips that can be installed per process unit area is limited. Therefore, there is a limitation that the more semiconductor bare chips are to be installed, the more surface area required. Summary of the invention

[0006] Technical issues

[0007] The present invention is proposed to solve the above-mentioned problem. The purpose of the present invention is to provide a stacked semiconductor module with a double-sided heat dissipation structure and a manufacturing method thereof. The stacked semiconductor module can arrange semiconductor bare chips in a stacked structure by providing a heat dissipation substrate between two semiconductor bare chips.

[0008] Furthermore, another object of the present invention is to provide a stacked semiconductor module having a double-sided heat dissipation structure and a method for manufacturing the same, wherein the stacked semiconductor module can increase the heat dissipation area of ​​a heat dissipation substrate disposed between semiconductor bare chips configured in a stacked structure.

[0009] Furthermore, another object of the present invention is to provide a stacked semiconductor module with a double-sided heat dissipation structure and a manufacturing method thereof, wherein a wiring layer of a semiconductor die is formed by a re-distribution layer (RDL) process.

[0010] Technical Solution

[0011] In order to achieve the above-mentioned purpose, a stacked semiconductor module with a double-sided heat dissipation structure according to one embodiment of the present invention includes: a first heat dissipation substrate; a second heat dissipation substrate, which is opposite to the first heat dissipation substrate and installed on the lower side of the first heat dissipation substrate; a first semiconductor bare chip module, which is installed between the first heat dissipation substrate and the second heat dissipation substrate; a third heat dissipation substrate, which is opposite to the second heat dissipation substrate and installed on the lower side of the second heat dissipation substrate; and a second semiconductor bare chip module, which is installed between the second heat dissipation substrate and the third heat dissipation substrate.

[0012] Furthermore, another embodiment of the present invention provides a method for manufacturing a stacked semiconductor module having a double-sided heat dissipation structure, which includes: the steps of manufacturing a first semiconductor bare chip module and a second semiconductor bare chip module including at least one semiconductor bare chip; the steps of installing the first semiconductor bare chip module between a first heat dissipation substrate and a second heat dissipation substrate, and installing the second semiconductor bare chip module between the second heat dissipation substrate and the third heat dissipation substrate; and the step of injecting a molding material into the space between the first heat dissipation substrate and the second heat dissipation substrate and between the second heat dissipation substrate and the third heat dissipation substrate to form a first molding component.

[0013] Technical Effects

[0014] According to the present invention, in a semiconductor bare chip, a first semiconductor bare chip is arranged between a first heat dissipation substrate and a second heat dissipation substrate, and a second semiconductor bare chip is arranged between the second heat dissipation substrate and a third heat dissipation substrate. Therefore, the first semiconductor bare chip and the second semiconductor bare chip are arranged in a stacked structure with the first heat dissipation substrate provided therebetween, thereby increasing the number of semiconductor bare chips that can be installed per process unit area, thereby being able to reduce the area required for installing the same number of semiconductor bare chips.

[0015] Furthermore, according to the present invention, since the first auxiliary heat dissipation substrate extending from one side of the first heat dissipation substrate and the second auxiliary heat dissipation substrate extending from the other side of the first heat dissipation substrate are exposed outside the first molding member, the heat dissipation area of ​​the first heat dissipation substrate can be increased, thereby maximizing the heat dissipation effect of the semiconductor module.

[0016] Furthermore, according to the present invention, the wiring layer of the semiconductor bare chip is formed by the RDL process, so the spacers required in the existing semiconductor module can be removed, thereby improving the misalignment problem, deviation problem, flatness problem and poor electrical connection problem caused by the spacers. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 1 is a top view schematically showing a stacked semiconductor module structure having a double-sided heat dissipation structure according to a first embodiment of the present invention.

[0018] Figure 2 Cut along line A-A' Figure 1 A cross-sectional view of a stacked semiconductor module with a double-sided heat dissipation structure is shown.

[0019] Figure 3 The figure shows a section along the line BB'. Figure 1 FIG. 1 is a schematic diagram of an example of a cross section of a stacked semiconductor module having a double-sided heat dissipation structure.

[0020] Figure 4 It is a schematic diagram Figure 2 and Figure 3 A schematic diagram of the structure of a semiconductor die is shown.

[0021] Figure 5 The figure shows a section along the line BB'. Figure 1 Another schematic diagram of a cross section of a stacked semiconductor module with a double-sided heat dissipation structure is shown.

[0022] Figure 6 FIG. 4 is a cross-sectional view of a stacked semiconductor module having a double-sided heat dissipation structure according to a second embodiment of the present invention, taken along line AA′.

[0023] Figure 7 FIG. 4 is a cross-sectional view of a stacked semiconductor module with a double-sided heat dissipation structure according to a second embodiment of the present invention, taken along line BB′.

[0024] Figure 8 is a schematic circuit diagram of a power device using a semiconductor module with a double-sided heat dissipation structure according to an embodiment of the present invention.

[0025] Figures 9 to 16B FIG. 4 is a schematic diagram showing a method for manufacturing a stacked semiconductor module with a double-sided heat dissipation structure according to a first embodiment of the present invention.

[0026] FIG. 17A to FIG. 17F FIG. 4 is a schematic diagram showing a method for manufacturing a stacked semiconductor module with a double-sided heat dissipation structure according to a second embodiment of the present invention.

[0027] Description of Reference Numerals

[0028] 100: A stacked semiconductor module having a double-sided heat dissipation structure;

[0029] 110: a first heat dissipation substrate; 120: a first heat dissipation substrate;

[0030] 130: a third heat dissipation substrate; 140: a first semiconductor bare chip module;

[0031] 142a-142c: a first semiconductor bare chip;

[0032] 144, 154: second molding member;

[0033] 146, 156: upper wiring reset layer;

[0034] 148, 158: lower wiring reset layer;

[0035] 150: a second semiconductor bare die module;

[0036] 152a-152c: second semiconductor bare chip;

[0037] 160: a first molding component; 170: a first auxiliary heat dissipation substrate;

[0038] 180: second auxiliary heat dissipation substrate; 190, 195: lead frame DETAILED DESCRIPTION

[0039] Throughout the specification, the same reference numerals represent substantially the same constituent elements. In the following description, detailed descriptions that are not related to the core structure of the present invention and are related to the functions of the structures known in the technical field of the present invention have been omitted. The meanings of the terms described in this specification should be understood as follows.

[0040] The advantages and features of the present invention and the methods for achieving the same can be made clearer by referring to the embodiments described in conjunction with the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms. The embodiments are only provided to make the disclosure of the present invention more complete and to fully inform the scope of the present invention to the ordinary technicians in the technical field to which the present invention belongs. The present invention will be defined by the scope of the claims.

[0041] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of illustrating the embodiments of the present invention are merely illustrative, and the present invention is not limited to the contents shown in the drawings. Throughout the entire specification, the same reference numerals refer to the same constituent elements. Furthermore, in the process of describing the present invention, if it is determined that the specific description of the related known technology will confuse the gist of the present invention, the detailed description thereof will be omitted.

[0042] The terms "including", "having", and "comprising" mentioned in this specification may include other parts unless the term "only to" is used. When a constituent element is expressed in a singular form, the plural form is included unless otherwise specified.

[0043] When interpreting constituent elements, they should be understood as including the range of error even if there is no additional explicit description.

[0044] When describing the positional relationship, for example, when describing the positional relationship of two parts by using "~on", "~above", "~below", "~on one side", etc., unless "just" or "directly" is used, one or more other parts may be arranged between the two parts.

[0045] When describing a temporal relationship, for example, when describing a temporal sequence using “after,” “continuing from,” “after,” “before,” etc., discontinuous situations may also be included unless “just” or “directly” is used.

[0046] In order to describe various components, the terms first, second, etc. are used, but these components are not limited to these terms. These terms are used only to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0047] The term "at least one" should be understood to include all combinations that can be obtained through more than one related item. For example, the meaning of "at least one of the first item, the second item, and the third item" can mean not only the first item, the second item, or the third item, but also all combinations of two or more than two of the first item, the second item, and the third item.

[0048] The various features of the multiple embodiments of the present invention may be partially or completely combined or combined with each other, and various linkages and drives may be technically realized. The various embodiments may be implemented independently of each other, or may be implemented together through an associated relationship.

[0049] Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 is a top view schematically showing a stacked semiconductor module structure having a double-sided heat dissipation structure according to a first embodiment of the present invention, Figure 2 Cut along line A-A' Figure 1 A cross-sectional view of a stacked semiconductor module with a double-sided heat dissipation structure is shown. Figure 3 It is cut along the B-B' line Figure 1 A cross-sectional view of a stacked semiconductor module with a double-sided heat dissipation structure is shown.

[0051] like Figures 1 to 3 As shown, a stacked semiconductor module (100, hereinafter referred to as “stacked semiconductor module”) with a double-sided heat dissipation structure according to a first embodiment of the present invention includes a first heat dissipation substrate 110, a second heat dissipation substrate 120, a third heat dissipation substrate 130, a first semiconductor bare chip (die) module 140, a second semiconductor bare chip module 150 and a first molding component 160.

[0052] The first heat dissipation substrate 110 releases heat generated in the first semiconductor die module 140 to the outside. The first heat dissipation substrate 110 includes a first substrate 112 , a first metal wiring layer 114 , and a first heat dissipation metal layer 116 .

[0053] The first substrate 112 electrically insulates the first metal wiring layer 114 from the first heat dissipation metal layer 116. The first substrate 112 includes a ceramic material having high thermal conductivity.

[0054] The first metal wiring layer 114 is formed on the first surface 112a of the first substrate 112 that is opposite to the second heat dissipation substrate 120. The first metal wiring layer 114 is patterned with predetermined circuit wiring.

[0055] One surface of the first heat dissipation metal layer 116 is bonded to the second surface 112b of the first substrate 112, and the other surface thereof releases heat to the outside. A heat dissipation unit containing a cooling medium is disposed near the other surface of the first heat dissipation metal layer 116.

[0056] The second heat dissipation substrate 120 is disposed between the first heat dissipation substrate 110 and the third heat dissipation substrate 130. More specifically, the second heat dissipation substrate 120 is disposed on the lower side of the first heat dissipation substrate 110 and the upper side of the third heat dissipation substrate 130. Through the above structure, the first semiconductor bare die module 140 is installed between the first heat dissipation substrate 110 and the second heat dissipation substrate 120, and the second semiconductor bare die module 150 is installed between the second heat dissipation substrate 120 and the third heat dissipation substrate 130.

[0057] The second heat dissipation substrate 120 includes a second substrate 122 , a second metal wiring layer 124 , and a third metal wiring layer 126 .

[0058] The second substrate 122 electrically insulates the second metal wiring layer 124 from the third metal wiring layer 126. The second substrate 122 is made of a ceramic material having high thermal conductivity.

[0059] The second metal wiring layer 124 is formed on the first surface 122a of the second substrate 122 opposite to the third heat dissipation substrate 130, and the third metal wiring layer 126 is formed on the second surface 122b of the second substrate 122 opposite to the first heat dissipation substrate 110. In one embodiment, the second metal wiring layer 124 and the third metal wiring layer 126 are patterned with predetermined circuit wiring.

[0060] Unlike the first heat dissipation substrate 110 and the third heat dissipation substrate 130, the second heat dissipation substrate 120 is not exposed to the outside, and a first semiconductor bare chip module 140 is configured on the upper side of the second heat dissipation substrate 120, and a second semiconductor bare chip module 150 is configured on the lower side of the second heat dissipation substrate 120. Therefore, metal wiring layers 124 and 126 are formed on both sides 122a and 122b of the second substrate 122, but no heat dissipation metal layer is formed.

[0061] The third heat dissipation substrate 130 releases heat generated in the second semiconductor die module 150 to the outside. The third heat dissipation substrate 130 is disposed under the second heat dissipation substrate 120. The third heat dissipation substrate 130 includes a third substrate 132, a fourth metal wiring layer 134 and a second heat dissipation metal layer 136.

[0062] The third substrate 132 electrically insulates the fourth metal wiring layer 134 from the second heat dissipation metal layer 136. The third substrate 132 includes a ceramic material having high thermal conductivity.

[0063] The fourth metal wiring layer 134 is formed on the first surface 132a of the third substrate 132 that is opposite to the second heat dissipation substrate 120. A predetermined circuit wiring is patterned on the fourth metal wiring layer 134.

[0064] One side of the second heat dissipation metal layer 136 is bonded to the second side 132 b of the third substrate 132 , and the other side releases heat. A heat dissipation unit containing a cooling medium is disposed near the other side of the second heat dissipation metal layer 136 .

[0065] In addition, in the above embodiment, the first heat dissipation metal layer 116 and the second heat dissipation metal layer 136 of the first heat dissipation substrate 110 and the third heat dissipation substrate 130 are exposed to the outside, but because the second heat dissipation substrate 120 is arranged between the first heat dissipation substrate 110 and the third heat dissipation substrate 130, the second heat dissipation substrate 120 cannot be exposed to the outside, so that the heat dissipation performance of the second heat dissipation substrate is reduced, which is different from the first heat dissipation substrate 110 and the third heat dissipation substrate.

[0066] Therefore, if Figure 1 As shown, in order to improve the heat dissipation performance of the second heat dissipation substrate 120 , the present invention further includes a first auxiliary heat dissipation substrate 170 and a second auxiliary heat dissipation substrate 180 .

[0067] The first auxiliary heat dissipation substrate 170 extends from one side of the second heat dissipation substrate 120 to the outside of the first molding member 160 , increasing the heat dissipation area of ​​the second heat dissipation substrate 120 , thereby improving the heat dissipation performance of the second heat dissipation substrate 120 .

[0068] The first auxiliary heat dissipation substrate 170 includes a first auxiliary substrate 172 , a first auxiliary heat dissipation metal layer 174 , and a second auxiliary heat dissipation metal layer 176 .

[0069] The first auxiliary substrate 172 electrically insulates the first auxiliary heat dissipation metal layer 174 from the second auxiliary heat dissipation metal layer 176. The first auxiliary substrate 172 includes a ceramic material with high thermal conductivity. In one embodiment, the first auxiliary substrate 172 is formed integrally with the second substrate 122. In the above embodiment, the first auxiliary substrate 172 is formed by extending from one side of the second substrate 122 toward the outer side of the first molding member 160.

[0070] The first auxiliary heat dissipation metal layer 174 is combined with one side of the first auxiliary substrate 172 and releases heat to the outside, and the second auxiliary heat dissipation metal layer 176 is combined with the other side of the first auxiliary substrate 172 and releases heat to the outside. The first auxiliary heat dissipation metal layer 174 is formed together with the second metal wiring layer 124, and the second auxiliary heat dissipation metal layer 176 is formed together with the third metal wiring layer 126. A heat dissipation unit including a cooling medium is disposed near the first auxiliary heat dissipation metal layer 174 and the second auxiliary heat dissipation metal layer 176.

[0071] The second auxiliary heat dissipation substrate 180 is extended from the other side of the second heat dissipation substrate 120 to the outside of the first molding member 160 , thereby increasing the heat dissipation area of ​​the second heat dissipation substrate 120 to improve the heat dissipation performance of the second heat dissipation substrate 120 .

[0072] The second auxiliary heat dissipation substrate 180 includes a second auxiliary substrate 182 , a third auxiliary heat dissipation metal layer 184 , and a fourth auxiliary heat dissipation metal layer 186 .

[0073] The second auxiliary substrate 182 electrically insulates the third auxiliary heat dissipation metal layer 184 from the fourth auxiliary heat dissipation metal layer 186. The second auxiliary substrate 182 includes a ceramic material with high thermal conductivity. In one embodiment, the second auxiliary substrate 182 is formed integrally with the second substrate 122. In the above embodiment, the second auxiliary substrate 182 is formed by extending from the other side of the second substrate 122 toward the outer side of the first molding member 160.

[0074] The third auxiliary heat dissipation metal layer 184 is combined with one side of the second auxiliary substrate 182 to release heat to the outside, and the fourth auxiliary heat dissipation metal layer 186 is combined with the other side of the second auxiliary substrate 182 to release heat to the outside. The third auxiliary heat dissipation metal layer 184 is formed together with the second metal wiring layer 124, and the fourth auxiliary heat dissipation metal layer 186 is formed together with the third metal wiring layer 126. A heat dissipation unit including a cooling medium is arranged near the third auxiliary heat dissipation metal layer 184 and the fourth auxiliary heat dissipation metal layer 186.

[0075] like Figure 1As shown, the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 are formed to extend from two sides of the four sides of the second heat dissipation substrate 120 where the lead frames 190 and 195 are not formed, toward the outside of the first molding member 160 .

[0076] As described above, the stacked semiconductor module 100 according to the present invention includes a first auxiliary heat dissipation substrate 170 and a second auxiliary heat dissipation substrate 180 formed to be exposed to the outside of the first molding member 160, and a heat dissipation unit containing a cooling medium can be additionally provided on the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180, so that the heat dissipation performance of the stacked semiconductor module 100 can be maximized.

[0077] In the above embodiment, the first to fourth metal wiring layers 114, 124, 126, 134, the first heat dissipation metal layer 116 and the second heat dissipation metal layer 136, and the first to fourth auxiliary heat dissipation metal layers 174, 176, 184, 186 are made of copper series metal. In the above embodiment, the first to third heat dissipation substrates 110-130 and the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 are formed by one of the direct bonded copper (DBC) method, the active material brazing (AMB) method and the direct plating copper (DPC) method.

[0078] The first semiconductor die module 140 is installed between the first heat dissipation substrate 110 and the second heat dissipation substrate 120 , and the second semiconductor die module 150 is installed between the second heat dissipation substrate 120 and the third heat dissipation substrate 130 .

[0079] In one embodiment, the first semiconductor die module 140 is bonded to the first heat dissipation substrate 110 and the second heat dissipation substrate 120 by a bonding member (not shown), and the second semiconductor die module 150 is bonded to the second heat dissipation substrate 120 and the third heat dissipation substrate 130 by a bonding member. At this time, the bonding member may be a Sn-Ag series bonding member or an Ag series bonding member. In the above embodiment, the first semiconductor die module 140 or the second semiconductor die module 150 is bonded to the first to third heat dissipation substrates 110, 120, 130 by a welding process or a sintering process.

[0080] The first semiconductor die module 140 includes one or more first semiconductor dies 142 a - 142 c , a second molding member 144 , an upper wiring reset layer 146 , and a lower wiring reset layer 148 .

[0081] The first semiconductor dies 142a-142c represent semiconductor devices manufactured by a wafer-level process. In one embodiment, the semiconductor devices included in the first semiconductor dies 142a-142c are power semiconductor devices. The power semiconductor device performs an operation of converting power supplied from a power supply unit such as a battery into power for driving a motor through a switching operation.

[0082] As an example, the first semiconductor dies 142a-142c include power semiconductor devices such as gate turn-off thyristors (GTOs), insulated gate bipolar transistors (IGBTs), or metal oxide semiconductor field effect transistors (MOSFETs), or include semiconductor devices such as diodes.

[0083] Figure 4 FIG. 2 is a schematic diagram schematically showing a semiconductor die structure according to an embodiment of the present invention. Figure 4 As shown, the first semiconductor dies 142 a - 142 c according to an embodiment of the present invention include a first electrode 410 , a semiconductor layer 420 and a second electrode 430 .

[0084] The first electrode 410 is disposed on the semiconductor layer 420. In one embodiment, when the first semiconductor dies 142a-142c include a power semiconductor device such as a MOSFET, the first electrode 410 includes a gate electrode 412 and a source electrode 414. In this case, the gate electrode 412 and the source electrode 414 are electrically insulated from each other. As another example, when the first semiconductor dies 142a-142c include a power semiconductor device such as an IGBT, the first electrode 410 includes a gate electrode 412 and an emitter electrode 414. In this case, the gate electrode 412 and the emitter electrode 414 are electrically insulated from each other.

[0085] The second electrode 430 is disposed below the semiconductor layer 420. In one embodiment, when the first semiconductor dies 142a-142c include power semiconductor devices such as MOSFETs, the second electrode 430 includes a drain electrode. As another example, when the first semiconductor dies 142a-142c include power semiconductor devices such as IGBTs, the second electrode 430 includes a collector electrode.

[0086] In the above embodiment, the first electrode 410 is composed of Al series metal, the second electrode 430 is composed of Ti / Ni / Ag metal or NiV / Ag, V (vanadium) / Ni / Ag, etc. including a Ti layer, a Ni layer, and an Ag layer, and the semiconductor layer 420 is composed of silicon carbide (SiC).

[0087] In one embodiment, when the first semiconductor die module 140 includes a plurality of first semiconductor dies 142a-142c, the plurality of first semiconductor dies 142a-142c all include the same type of semiconductor devices. As another example, a portion of the plurality of first semiconductor dies 142a-142c may be other types of semiconductor devices.

[0088] In the above embodiment, when the first semiconductor die module 140 includes multiple first semiconductor die 142a~142c, the first electrodes 410 of a portion of the first semiconductor die 142a~142c face upward and the second electrodes 430 face downward, and the first electrodes 410 of the remaining portions of the first semiconductor die 142a~142c face downward and the second electrodes 430 face upward.

[0089] In another embodiment, the first semiconductor dies 142a-142c are disposed between the first heat dissipation substrate 110 and the second heat dissipation substrate 120, so that the same electrodes of the first semiconductor dies are all oriented in the same direction. For example, the first electrodes 410 of the first semiconductor dies 142a-142c are all oriented toward the upper side, and the second electrodes 430 of the first semiconductor dies 142a-142c are all oriented toward the lower side. As another example, the first electrodes 410 of the first semiconductor dies 142a-142c are all oriented toward the lower side, and the second electrodes 430 of the first semiconductor dies 142a-142c are all oriented toward the upper side.

[0090] Although in Figures 1 to 3 The first semiconductor die module 140 shown in the figure includes three first semiconductor die 142a-142c, but this is only an example, and the number of the first semiconductor die 142a-142c may vary according to the type of application using the stacked semiconductor module 100 of the present invention.

[0091] The second molding member 144 has the function of protecting the first semiconductor dies 142a to 142c from the influence of oxidizing substances and fixing the first semiconductor dies 142a to 142c. The structure of the second molding member 144 is to expose the upper surface and the bottom surface of the first semiconductor dies 142a to 142c and surround the side surfaces of the first semiconductor dies 142a to 142c. That is, the second molding member 144 is not arranged on the upper side and the lower side of the first semiconductor dies 142a to 142c, and the second molding member 144 is arranged only on the side surfaces of the first semiconductor dies 142a to 142c. Through such a structure, the first electrodes 410 and the second electrodes 430 of the first semiconductor dies 142a to 142c are exposed from the upper side and the lower side, so as to be electrically connected to the wiring arranged on the upper wiring reset layer 146 and the lower wiring reset layer 148.

[0092] In one embodiment, the second molding member 144 is formed of epoxy molding compound (EMC).

[0093] A through hole 144a filled with a conductive material is formed in the second molding member 144. In one embodiment, the through hole 144a is formed in the second molding member 144 by a drilling process. At this time, the conductive material filled in the through hole 144a is the same material as the material forming the upper wiring reset layer 146 or the lower wiring reset layer 148. The upper wiring reset layer 146 and the lower wiring reset layer 148 are electrically connected through the through hole 144a.

[0094] The upper wiring reset layer 146 is disposed on the upper surface of the second molding member 144 and the first semiconductor die 142a to 142c. The upper wiring reset layer 146 is provided with a first wiring. The first wiring electrically connects the electrodes of the first semiconductor die 142a to 142c that are exposed from the upper side. For example, when the first semiconductor die 142a has the first electrode 410 located on the upper side and the first semiconductor die 142b has the second electrode 430 located on the upper side, one of the first wirings can electrically connect the first electrode 410 of the first semiconductor die 142a and the second electrode 430 of the first semiconductor die 142b. The first wiring can also electrically connect the electrodes of the first semiconductor die 142a to 142c that are exposed from the upper side to the lead frames 190 and 195.

[0095] In one embodiment, the first wiring is made of copper-based metal. The wirings insulated from each other in the first wiring are physically separated by the first insulating member 146a. The first insulating member 146a is made of photoresist.

[0096] The lower wiring reset layer 148 is arranged on the bottom surface of the second molding member 144 and the first semiconductor die 142a to 142c. The lower wiring reset layer 148 is arranged with a second wiring. The second wiring electrically connects the electrodes of the first semiconductor die 142a to 142c that are exposed from the lower side. For example, when the second electrode 430 of the first semiconductor die 142a is located on the lower side and the first electrode 410 of the first semiconductor die 142b is located on the lower side, one of the second wirings electrically connects the second electrode 430 of the first semiconductor die 142a and the first electrode 410 of the first semiconductor die 142b. The second wiring also electrically connects the electrodes of the first semiconductor die 142a to 142c that are exposed from the lower side to the lead frames 190 and 195.

[0097] In one embodiment, the second wiring is made of copper-based metal. The second wirings that are insulated from each other are physically separated by the second insulating member 148a. The second insulating member 148a is made of photoresist.

[0098] In the above embodiment, at least a portion of the first wirings of the upper wiring reset layer 146 and at least a portion of the second wirings of the lower wiring reset layer 148 are electrically connected through the through holes 144 a formed in the first molding member 144 .

[0099] In addition, if Figure 2 and Figure 3 As shown, the first semiconductor bare chips 142a~142c included in the first semiconductor bare chip module 140 are installed in a specified area between the first heat dissipation substrate 110 and the second heat dissipation substrate 120, and the second semiconductor bare chips 152a~152c included in the second semiconductor bare chip module 150 are installed in an area corresponding to the specified area between the second heat dissipation substrate 120 and the third heat dissipation substrate 130. Therefore, the first semiconductor bare chips 142a~142c included in the first semiconductor bare chip module 140 and the second semiconductor bare chips 152a~152c included in the second semiconductor bare chip module 150 form a stacked structure with the second heat dissipation substrate 120 in between.

[0100] The second semiconductor die module 150 includes one or more second semiconductor dies 152a-152c, a second molding member 154, an upper wiring reset layer 156, and a lower wiring reset layer 158. The second semiconductor dies 142a-142c, the second molding member 144, the upper wiring reset layer 156, and the lower wiring reset layer 158 are the same as the first semiconductor dies 142a-142c, the second molding member 154, the upper wiring reset layer 146, and the lower wiring reset layer 148 in their functions, so their detailed description is omitted.

[0101] As described above, according to the present invention, since the first semiconductor bare chips 142a~142c included in the first semiconductor bare chip module 140 and the second semiconductor bare chips 152a~152c included in the second semiconductor bare chip module 150 form a stacked structure with the second heat dissipation substrate 120 in between, the number of semiconductor bare chips that can be installed per process unit area is increased, thereby reducing the area required to install the same number of semiconductor bare chips.

[0102] The first molding member 160 is formed in the space between the first heat dissipation substrate 110 and the second heat dissipation substrate 120 and the space between the second heat dissipation substrate 120 and the third heat dissipation substrate 130. The first molding member 160 is formed by injecting a molding substance into the space between the first heat dissipation substrate 110 and the second heat dissipation substrate 120 and the space between the second heat dissipation substrate 120 and the third heat dissipation substrate 130. In one embodiment, the molding substance may be EMC.

[0103] The function of the first molding component 160 is to increase the insulation distance between the first heat dissipation substrate 110 and the second heat dissipation substrate 120 and the insulation distance between the second heat dissipation substrate 120 and the third heat dissipation substrate 130, protect the first semiconductor die 142a~142c and the second semiconductor die 152a~152c included in the first semiconductor die module 140 and the second semiconductor die module 150 from the influence of oxidizing substances, and fix the first semiconductor die 142a~142c and the second semiconductor die 152a~152c.

[0104] In addition, if Figure 1 and Figure 3 As shown, the stacked semiconductor module 100 according to the present invention further includes lead frames 190 and 195. The lead frames 190 and 195 include a first lead frame 190 connected to one side of the second heat dissipation substrate 120 and a second lead frame 195 connected to the other side of the second heat dissipation substrate 120.

[0105] One end of the first lead frame 190 is electrically connected to the second metal wiring layer 124 and the third metal wiring layer 126 on one side of the second heat dissipation substrate 120 , and the other end is exposed to the outside of the first molding member 160 and connected to an external connection terminal (not shown).

[0106] One end of the second lead frame 195 is electrically connected to the second metal wiring layer 124 and the third metal wiring layer 126 on the other side of the second heat dissipation substrate 120 , and the other end is exposed to the outside of the first molding member 160 and connected to the external connection terminal.

[0107] In the above embodiment, the first lead frame 190 and the second lead frame 195 are connected to different electrodes of the first semiconductor die 142a-142c and the second semiconductor die 152a-152c, and the external connection terminals are electrically connected to the motor, input power supply, inverter controller, etc.

[0108] Although Figure 3 In the figure, the lead frames 190, 195 are only connected to one side and the other side of the second heat dissipation substrate 120, but in another embodiment, as shown in FIG. Figure 5 As shown, one end of the lead frame 190, 195 is electrically connected to the first metal wiring layer 114 of the first heat dissipation substrate 110, the third metal wiring layer 126 of the second heat dissipation substrate 120, and the fourth metal wiring layer 134 of the third heat dissipation substrate 130, and the other end of the lead frame 190, 195 is exposed to the outside of the first molding component 160 and connected to the external connection terminal.

[0109] Figure 6 and Figure 7 FIG. 1 is a schematic diagram schematically showing a stacked semiconductor module structure with a double-sided heat dissipation structure according to a second embodiment of the present invention. Compared with the stacked semiconductor module 100 with a double-sided heat dissipation structure according to the first embodiment, Figure 6 and Figure 7 The stacked semiconductor module 600 with a double-sided heat dissipation structure shown has the same structure except that the first semiconductor bare chip module 540 and the second semiconductor bare chip module 550 are different. Therefore, for the sake of convenience, only the structure of the first semiconductor bare chip module 540 and the second semiconductor bare chip module 550 will be described below.

[0110] The first semiconductor die module 540 includes one or more first semiconductor die 542 a ˜ 542 c and a first spacer 544 .

[0111] The first semiconductor dies 542 a ˜ 542 c are the same as the first semiconductor dies 142 a ˜ 142 c according to the first embodiment, and thus detailed description thereof is omitted.

[0112] The first spacer 544 is combined with one side of the first semiconductor die 542a-542c to maintain the spacing distance between the first heat dissipation substrate 110 and the second heat dissipation substrate 120. In one embodiment, the first spacer 544 is formed of a conductive material, for example, copper-molybdenum Cu-Mo.

[0113] One side of the first spacer 544 is bonded to the first semiconductor die 542a-542c of the first semiconductor die module 540 through a bonding member, and the other side of the first spacer 544 is bonded to the first heat dissipation substrate 110 or the second heat dissipation substrate 120 through a bonding member. In one embodiment, the bonding member is a Sn-Ag series bonding member or an Ag series bonding member, and the first spacer 544 is bonded to the first semiconductor die 542a-542c, the first heat dissipation substrate 110 or the second heat dissipation substrate 120 through a welding method or a sintering method.

[0114] In one embodiment, when the first semiconductor die module 540 includes a plurality of first semiconductor die 542a to 542c, a portion of the first semiconductor die 542a to 542c are configured such that their first electrodes 410 face upward and their second electrodes 430 face downward, and the remaining portions of the first semiconductor die 542a to 542c are configured such that their first electrodes 410 face downward and their second electrodes 430 face upward.

[0115] According to the above embodiment, the first spacer 544 is bonded to the surface of the first semiconductor dies 542a-542c on which the first electrode 410 is formed. Alternatively, the first spacer 544 may be bonded to the surface of the first semiconductor dies 542a-542c on which the second electrode 430 is formed.

[0116] In another embodiment, the first semiconductor dies 542a-542c are disposed between the first heat dissipation substrate 510 and the second heat dissipation substrate 520, and the same electrodes of the first semiconductor dies are all oriented in the same direction. For example, the first electrodes 410 of the first semiconductor dies 542a-542c are all oriented upward, and the second electrodes 430 of the first semiconductor dies 542a-542c are all oriented downward. As another example, the first electrodes 410 of the first semiconductor dies 542a-542c can all be oriented downward, and the second electrodes 430 of the first semiconductor dies 542a-542c can all be oriented upward.

[0117] According to the above embodiment, the first spacer 544 is bonded to the surface of the first semiconductor dies 542a-542c on which the first electrode 410 is formed. Alternatively, the first spacer 544 may be bonded to the surface of the first semiconductor dies 542a-544c on which the second electrode 430 is formed.

[0118] The second semiconductor die module 550 includes one or more second semiconductor die 552a-552c and a second spacer 554. Compared with the first semiconductor die 542a-542c and the first spacer 544, the one or more second semiconductor die 552a-552c and the second spacer 554 are the same as the first semiconductor die 542a-542c and the first spacer 544 except that they are arranged between the second heat dissipation substrate 120 and the third heat dissipation substrate 130, so the detailed description is omitted.

[0119] Figure 8 Is adopted Figures 1 to 7 The schematic circuit diagram of a power device of a stacked semiconductor module with a double-sided heat dissipation structure is shown in FIG. Figure 8 As shown, the power device 800 includes an inverter 810 and a motor 820 .

[0120] The inverter 810 supplies AC power to the motor 820. After the inverter 810 receives direct current (DC) power from a battery or a fuel cell and converts it into AC power, it outputs the converted AC power to the motor 820. Figure 8 As shown, the inverter 810 includes six semiconductor dies 810a-810f. Figure 1 and Figure 7 The stacked semiconductor module 100 , 600 shown includes six semiconductor dies, and thus the stacked semiconductor module 100 , 600 according to the present invention can perform the function of the inverter 810 of the power device 800 .

[0121] The motor 820 provides power to electric vehicles, fuel cell vehicles, etc. The motor 820 can be driven by receiving three-phase alternating current (AC) power.

[0122] Below, refer to Figures 9 to 16B A method for manufacturing a stacked semiconductor module having a double-sided heat dissipation structure according to a first embodiment of the present invention is described.

[0123] Fig. 9 (a) Fig.10 (a) Fig.11 (a) Fig.12 (a) and Fig.13 (a) is a schematic process top view showing a method for manufacturing a stacked semiconductor module having a double-sided heat dissipation structure (hereinafter referred to as a “stacked semiconductor module”) according to a first embodiment of the present invention, Fig. 9 (b) Fig.10 (b) Fig.11 (b) Fig.12 (b) Fig.13 (b) Figures 14 to 16B 1 is a schematic process cross-sectional view showing a method for manufacturing a stacked semiconductor module according to a first embodiment of the present invention.

[0124] First, refer to Figures 9 to 13 A method for manufacturing the first semiconductor bare die module is described. Fig. 9 (a) and Fig. 9 (b), first semiconductor bare chips 142a-142f are arranged at predetermined positions on the carrier film 700. Fig. 9 (a) and Fig. 9 As shown in (b), although six semiconductor bare chips 142a~142f are arranged on the carrier film 700, this is only an example, and the number of semiconductor bare chips can vary depending on the type of application to which the stacked semiconductor module of the present invention is applied.

[0125] In one embodiment, the plurality of first semiconductor dies 142a-142f include power semiconductor devices. In this case, a portion 142a, 142d, 142c, 142f and the remaining portion 142b, 142e of the first semiconductor dies 142a-142f are arranged in opposite vertical directions.

[0126] Then, if Fig.10 (a) and Fig.10 As shown in (b), a second molding member 144 is formed on the carrier film 700 to surround the side surfaces of the first semiconductor dies 142a to 142f. That is, the second molding member 144 is not formed on the upper surface and the bottom surface of the first semiconductor dies 142a to 142f, and the second molding member 144 is formed only on the side surfaces of the first semiconductor dies 142a to 142f, so that the first electrode 410 and the second electrode 430 formed on the upper surface and the bottom surface of the first semiconductor dies 142a to 142f are exposed to the outside. The position of the first semiconductor dies 142a to 142f is fixed by the second molding member 144.

[0127] In one embodiment, the second molding member 144 is made of EMC, and the second molding member 144 is formed by injecting EMC into the periphery of the first semiconductor dies 142 a ˜ 142 f .

[0128] Then, if Fig.11 (a) and Fig.11As shown in (b), an upper wiring reset layer 146 is formed on the upper surface of the second molding member 144 and the first semiconductor dies 142a to 142f. The upper wiring reset layer 146 includes a plurality of first wirings (not shown). In one embodiment, the upper wiring reset layer 146 is formed by electroless gold plating and is formed of a copper series metal. The upper wiring reset layer 146 can be formed by an RDL (Re-Distribution Layer) process.

[0129] The mutually insulated wirings among the first wirings included in the upper wiring reset layer 146 are physically separated by the first insulating member 146a. In one embodiment, the first insulating member 146a is made of photoresist.

[0130] Then, if Fig.12 (a) and Fig.12 As shown in (b), a hole is formed through the upper wiring reset layer 146 and the second molding member 144, and a through hole 144a is formed by filling the hole with a conductive material. The through hole 144a electrically connects a part of the second wiring included in the lower wiring reset layer 148 described later and a part of the first wiring included in the upper wiring reset layer 146.

[0131] Afterwards, if Fig.13 (a) and Fig.13 As shown in (b), the first semiconductor die module 140 in the process can be turned over so that the process surface is reversed. At this time, the carrier film 700 can be removed. Fig.13 (a) shows the bottom side of the first semiconductor bare die module 140 during the process.

[0132] like Fig.13 Part (a) and Fig.13 As shown in part (b) of FIG. 1 , a lower wiring reset layer 148 is formed on the bottom surface of the second molding member 144 and the first semiconductor die 142a to 142f. The lower wiring reset layer 148 includes a plurality of second wirings (not shown). In one embodiment, the lower wiring reset layer 148 is formed by electroless gold plating and is formed of a copper series metal. The lower wiring reset layer 148 is formed by an RDL (Re-Distribution Layer) process.

[0133] The second wirings included in the lower wiring reset layer 148 are physically separated from each other by the second insulating member 148a. In one embodiment, the second insulating member 148a is made of photoresist.

[0134] In one embodiment, the above Fig.12 (a) and Fig.12The step of forming the through hole 144a shown in (b) can also be performed in Fig.13 (a) and Fig.13 The process of forming the lower wiring reset layer 148 shown in (b) is performed after that. That is, a hole is formed to penetrate the lower wiring reset layer 148 and the second molding member 144, and a conductive material is filled in the hole to form a through hole 144a. A part of the first wiring included in the upper wiring reset layer 146 and a part of the second wiring included in the lower wiring reset layer 148 are electrically connected through the through hole 144a.

[0135] This can be done by Figures 9 to 13 The second semiconductor die module 150 is manufactured by the same process as shown.

[0136] Afterwards, if Fig.14 As shown, a first semiconductor bare chip module 140 is installed between the first heat dissipation substrate 110 and the second heat dissipation substrate 120, and a second semiconductor module is installed between the second heat dissipation substrate 120 and the third heat dissipation substrate 130. In one embodiment, the first to third heat dissipation substrates 110, 120, 130 can be formed by one of DBC (Direct Bonded Copper), AMB (Active Metal Brazing), and DPC (Direct Plating Copper) processes.

[0137] Specifically, a second heat dissipation substrate 120 is configured on the lower side of the first heat dissipation substrate 110, and a third heat dissipation substrate 130 is configured on the lower side of the second heat dissipation substrate 120, so that a first semiconductor bare chip module 140 is installed between the first heat dissipation substrate 110 and the second heat dissipation substrate 120, and a second semiconductor bare chip module 150 is installed between the second heat dissipation substrate 120 and the third heat dissipation substrate 130.

[0138] like Fig.14 As shown, the first heat dissipation substrate 110 includes a first substrate 112, a first metal wiring layer 114 and a first heat dissipation metal layer 116, the second heat dissipation substrate 120 includes a second substrate 122, a second metal wiring layer 124 and a third metal wiring layer 126, and the third heat dissipation substrate 130 includes a third substrate 132, a fourth metal wiring layer 134 and a second heat dissipation metal layer 136.

[0139] Predetermined circuit wirings are patterned on the first to fourth metal wiring layers 114 , 124 , 126 , and 134 , and a heat dissipation unit including a cooling medium is disposed near the first heat dissipation metal layer 116 and the second heat dissipation metal layer 136 .

[0140] In one embodiment, the first heat dissipation substrate 110 and the second heat dissipation substrate 120 are bonded to the first semiconductor die module 140 by a bonding member. Specifically, the first metal wiring layer 114 is bonded to the upper surface of the first semiconductor die module 140 by a bonding member, and the second metal wiring layer 124 is bonded to the bottom surface of the first semiconductor die module 140 by a bonding member.

[0141] Furthermore, the second heat dissipation substrate 120 and the third heat dissipation substrate 130 are bonded to the second semiconductor die module 150 by means of bonding members. Specifically, the third metal wiring layer 126 is bonded to the upper surface of the second semiconductor die module 150 by means of bonding members, and the fourth metal wiring layer 134 is bonded to the bottom surface of the second semiconductor die module 150 by means of bonding members.

[0142] In the above embodiment, the bonding member is a Sn-Ag series bonding member or an Ag series bonding member. At this time, the first heat dissipation substrate 110 and the second heat dissipation substrate 120 are combined with the first semiconductor bare chip module 140 through a welding process or a sintering process, and the second heat dissipation substrate 120 and the third heat dissipation substrate 130 are combined with the second semiconductor bare chip module 150 through a welding process or a sintering process.

[0143] In addition, in the above-mentioned embodiment, the first heat dissipation metal layer 116 and the second heat dissipation metal layer 136 of the first heat dissipation substrate 110 and the third heat dissipation substrate 130 are exposed to the outside, but the second heat dissipation substrate 120 is arranged between the first heat dissipation substrate 110 and the third heat dissipation substrate 130 and is not exposed to the outside. Therefore, compared with the first heat dissipation substrate 110 and the third heat dissipation substrate, the heat dissipation performance of the second heat dissipation substrate 120 is reduced. Therefore, in order to improve the heat dissipation performance of the second heat dissipation substrate 120, as shown in FIG. Fig.14 As shown, the present invention further includes a first auxiliary heat dissipation substrate 170 and a second auxiliary heat dissipation substrate 180 .

[0144] In one embodiment, the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 are integrally formed with the second heat dissipation substrate 120. In the above embodiment, the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 are formed together with the second heat dissipation substrate 120 when manufacturing the second heat dissipation substrate 120.

[0145] The first auxiliary heat dissipation substrate 170 is extended from one side of the second heat dissipation substrate 120 to the outside of the first molding component 160 described later, and the second auxiliary heat dissipation substrate 180 is extended from the other side of the second heat dissipation substrate 120 to the outside of the first molding component 160, thereby increasing the heat dissipation area of ​​the second heat dissipation substrate 120 to improve the heat dissipation performance of the second heat dissipation substrate 120.

[0146] The first auxiliary heat dissipation substrate 170 includes a first auxiliary substrate 172 , a first auxiliary heat dissipation metal layer 174 and a second auxiliary heat dissipation metal layer 176 . The second auxiliary heat dissipation substrate 180 includes a second auxiliary substrate 182 , a third auxiliary heat dissipation metal layer 184 and a fourth auxiliary heat dissipation metal layer 186 .

[0147] The first auxiliary substrate 172 and the second auxiliary substrate 182 are integrally formed with the second substrate 122. The first auxiliary substrate 172 extends from one side of the second substrate 122 to the outside of the first molding member 160, and the second auxiliary substrate 182 extends from the other side of the second substrate 122 to the outside of the first molding member 160.

[0148] The first to fourth auxiliary heat dissipation metal layers 174, 176, 184, 186 are exposed to the outside of the first molding member 160 to release heat to the outside. A heat dissipation unit including a cooling medium is disposed near the first to fourth auxiliary heat dissipation metal layers 174, 176, 184, 186.

[0149] In the above embodiment, if Figure 1 As shown, the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 are formed to extend from the sides of the second heat dissipation substrate 120 where the lead frames 190 and 195 are not formed, toward the outside of the first molding member 160 .

[0150] As described above, the present invention includes a first auxiliary heat dissipation substrate 170 and a second auxiliary heat dissipation substrate 180 formed by being exposed to the outside of the first molding component 160, and the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 are further configured with a heat dissipation unit containing a cooling medium, so that the heat dissipation performance of the stacked semiconductor module 100 can be maximized.

[0151] Afterwards, if Fig.15 As shown, lead frames 190 and 195 are provided, one end of each of the lead frames 190 and 195 is connected to one side and the other side of the second heat dissipation substrate 120, and the other end is connected to the external input terminal. At this time, the lead frames 190 and 195 are connected to one side and the other side of the second heat dissipation substrate 120 on the sides where the first auxiliary heat dissipation substrate 170 and the second auxiliary heat dissipation substrate 180 do not extend among the four sides of the second heat dissipation substrate 120.

[0152] Afterwards, if Fig.16A and Fig. 16B As shown, the first molding member 160 is formed by injecting a molding substance into the space between the first heat dissipation substrate 110 and the second heat dissipation substrate 120 and the space between the second heat dissipation substrate 120 and the third heat dissipation substrate 130. The molding substance is composed of EMC.

[0153] Below, refer to FIG. 17A to FIG. 17F A method for manufacturing a stacked semiconductor module having a double-sided heat dissipation structure according to a second embodiment of the present invention will be described.

[0154] FIG. 17A to FIG. 17F 1 is a schematic cross-sectional view showing a method for manufacturing a stacked semiconductor module having a double-sided heat dissipation structure according to a second embodiment of the present invention.

[0155] First, if Fig.17A As shown, the first semiconductor die module 540 is manufactured by bonding a first spacer 544 to one side of the first semiconductor dies 542a-542c. The first spacer 544 is formed of copper-molybdenum Cu-Mo.

[0156] In one embodiment, the first spacer 544 is bonded to one side of the first semiconductor die 542a-542c by a bonding member. In one embodiment, the bonding member is a Sn-Ag series bonding member or an Ag series bonding member, and the first spacer 544 is bonded to the first semiconductor die 542a-542c by a welding process or a sintering process.

[0157] In addition, through Fig.17A The second semiconductor die module 550 is manufactured by the same process as shown.

[0158] Then, if Fig. 17B As shown, the first semiconductor die module 540 is combined with the first heat dissipation substrate 610, and the second semiconductor die module 550 is combined with the second heat dissipation substrate 620. Fig. 17B As shown, a portion of the first semiconductor die module 540 and the second semiconductor die module 550 has its first or second spacer 544, 554 located on the upper surface, and the remaining portion has its first or second spacer 544, 554 located on the bottom surface. In another embodiment, the first semiconductor die module 540 and the second semiconductor die module 550 are both oriented in the same direction so that their first or second spacer 544, 554 are located on the upper surface, or are both oriented in the same direction so that their first or second spacer 544, 554 are located on the bottom surface.

[0159] In one embodiment, the first heat dissipation substrate 610 includes a first substrate 612, a first metal wiring layer 614, and a first heat dissipation metal layer 616, and the second heat dissipation substrate 620 includes a second substrate 622, a second metal wiring layer 624, and a third wiring metal layer 626. In the above embodiment, the first semiconductor die module 540 is bonded to the first metal wiring layer 614 of the first heat dissipation substrate 610 by a bonding member, and the second semiconductor die module 550 is bonded to the second metal wiring layer 624 of the second heat dissipation substrate 620 by a bonding member. In one embodiment, the bonding member is a Sn-Ag series bonding member or an Ag series bonding member, and the first and second semiconductor die modules 540 and 550 are respectively bonded to the first and second heat dissipation substrates 610 and 620 by a welding process or a sintering process.

[0160] in addition, Fig. 17B The stacked semiconductor module shown is also the same as the first embodiment, in order to increase the heat dissipation area of ​​the second heat dissipation substrate 620, further includes a first auxiliary heat dissipation substrate 670 and a second auxiliary heat dissipation substrate 680 extending from the second heat dissipation substrate 620. The first and second auxiliary heat dissipation substrates 670 and 680 are connected to the Fig.14 The same as shown, the detailed description is omitted.

[0161] Then, if Fig. 17C As shown, the first heat dissipation substrate 610 and the second heat dissipation substrate 630 are combined so that the first semiconductor die module 540 is disposed between the first heat dissipation substrate 610 and the second heat dissipation substrate 620, and the second semiconductor module 650 is disposed between the second heat dissipation substrate 620 and the third heat dissipation substrate 630. In one embodiment, the first to third heat dissipation substrates 610, 620, 630 are formed by one of the DBC (Direct Bonded Copper), AMB (Active Metal Brazing), and DPC (Direct Plating Copper) processes.

[0162] Then, if Fig.17D As shown, lead frames 690 and 695 are provided, one end of the lead frames 690 and 695 is connected to one side and the other side of the second heat dissipation substrate 620, and the other end is connected to the external input terminal. At this time, the lead frames 690 and 695 are connected to one side and the other side of the second heat dissipation substrate 620 at the sides where the first auxiliary heat dissipation substrate 670 and the second auxiliary heat dissipation substrate 680 are not extended among the four sides of the second heat dissipation substrate 620.

[0163] Then, if Fig.17E and Fig.17FAs shown, the first molding member 660 is formed by injecting molding material into the space between the first heat dissipation substrate 610 and the second heat dissipation substrate 620 and the space between the second heat dissipation substrate 620 and the third heat dissipation substrate 630. The molding material is composed of EMC.

[0164] It can be understood by those skilled in the art to which the present invention pertains that the present invention can be implemented in other specific embodiments without changing the technical concept or essential technical features of the present invention described above.

[0165] Therefore, the embodiments described above should be understood to be illustrative rather than restrictive in all aspects. With the detailed description described above, the scope of the present invention is limited by the appended claims, and all changes or variant embodiments derived from the meaning and scope of the claims and their equivalent concepts should be understood to fall within the scope of the present invention.

Claims

1. A stacked semiconductor module with a double-sided heat dissipation structure, wherein: include: a first heat dissipation substrate; a second heat dissipation substrate, which is opposite to the first heat dissipation substrate and is arranged on the lower side of the first heat dissipation substrate; A first semiconductor bare chip module is mounted between the first heat dissipation substrate and the second heat dissipation substrate; a third heat dissipation substrate, which is opposite to the second heat dissipation substrate and is disposed on a lower side of the second heat dissipation substrate; and The second semiconductor bare die module is mounted between the second heat dissipation substrate and the third heat dissipation substrate.

2. The stacked semiconductor module with a double-sided heat dissipation structure according to claim 1, wherein: Also includes: a first molding member formed in a space between the first heat dissipation substrate and the second heat dissipation substrate and a space between the second heat dissipation substrate and the third heat dissipation substrate; a first auxiliary heat dissipation substrate extending from one side of the second heat dissipation substrate toward the outside of the first molding member; as well as A second auxiliary heat dissipation substrate extends from the other side of the second heat dissipation substrate toward the outside of the first molding member.

3. The stacked semiconductor module with a double-sided heat dissipation structure according to claim 2, wherein: The invention also includes a lead frame, one end of which is electrically connected to the first surface of the second heat dissipation substrate and the second surface which is the opposite surface of the first surface, and the other end of which is exposed to the outside of the first molding component. The first and second auxiliary heat dissipation substrates are formed by extending from a region of the second heat dissipation substrate to which the lead frame is not connected.

4. The stacked semiconductor module with a double-sided heat dissipation structure according to claim 2, wherein: The first to third heat dissipation substrates and the first and second auxiliary heat dissipation substrates include: substrate; A first metal layer formed on a first surface of the substrate; and a second metal layer formed on the second surface of the substrate, Circuit wiring having a pattern is patterned on the first metal layers of the first and third heat dissipation substrates and the first and second metal layers of the second heat dissipation substrate. A cooling medium is disposed on the second metal layers of the first and third heat dissipation substrates and the first and second metal layers of the first and second auxiliary heat dissipation substrates.

5. The stacked semiconductor module with a double-sided heat dissipation structure according to claim 1, wherein: The first semiconductor die module includes one or more first semiconductor dies and a first spacer disposed between the one or more first semiconductor dies and the second heat dissipation substrate. The second semiconductor die module further includes one or more second semiconductor dies and a second spacer disposed between the second semiconductor die and the third heat dissipation substrate.

6. The stacked semiconductor module with a double-sided heat dissipation structure according to claim 1, wherein: The first semiconductor die module and the second semiconductor die module include: One or more semiconductor die; a second molding member exposing an upper surface and a bottom surface of the semiconductor die and surrounding a side surface of the semiconductor die; a first wiring reset layer disposed on the upper surface of the second molding member and the semiconductor die; and The second wiring reset layer is disposed on the second molding member and the bottom surface of the semiconductor die.

7. A method for manufacturing a stacked semiconductor module having a double-sided heat dissipation structure, wherein: include: The step of manufacturing a first semiconductor die module and a second semiconductor die module including at least one semiconductor die; The step of installing the first semiconductor bare die module between a first heat dissipation substrate and a second heat dissipation substrate, and installing the second semiconductor bare die module between the second heat dissipation substrate and a third heat dissipation substrate; as well as A step of injecting a molding material into a space between the first heat dissipation substrate and the second heat dissipation substrate and between the second heat dissipation substrate and the third heat dissipation substrate to form a first molding member.

8. The method for manufacturing a stacked semiconductor module with a double-sided heat dissipation structure according to claim 7, wherein: A first auxiliary heat dissipation substrate is further formed on one side of the second heat dissipation substrate and extends toward the outside of the first molding member. A second auxiliary heat dissipation substrate is formed on the other side of the second heat dissipation substrate and extends toward the outside of the first molding member.

9. The method for manufacturing a stacked semiconductor module with a double-sided heat dissipation structure according to claim 8, wherein: Also includes: forming a lead frame, wherein one end of the lead frame is electrically connected to a first surface of the second heat dissipation substrate and a second surface which is an opposite surface to the first surface, and the other end of the lead frame is exposed to the outside of the first molding member, The first and second auxiliary heat dissipation substrates are formed by extending from a region of the second heat dissipation substrate to which the lead frame is not connected.

10. The method for manufacturing a stacked semiconductor module with a double-sided heat dissipation structure according to claim 7, wherein: The steps of manufacturing the first semiconductor die module and the second semiconductor die module include: the step of configuring said at least one semiconductor die; forming a second molding member exposed to the upper and bottom surfaces of the semiconductor die and surrounding the side surfaces of the semiconductor die; and The first semiconductor die module and the second semiconductor die module are formed by forming a first wiring reset layer on the upper surfaces of the second molding member and the semiconductor die, and forming a second wiring reset layer on the bottom surfaces of the second molding member and the semiconductor die.

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