Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; an epitaxial layer; a plurality of source regions; the partial surface, close to the substrate, of the first metal layer is in contact with the partial surface, away from the substrate, of the epitaxial layer; an interconnection metal layer; the heat conduction layers are located on the side, close to or away from the substrate, of the first metal layer or located in the interconnection metal layer, and the heat conductivity of the heat conduction layers is larger than that of the interconnection metal layer; the interconnection metal layer is located on the surface, away from the substrate, of the heat conduction layer and the partial surface, away from the substrate, of the first metal layer, and when the heat conduction layer is located on the side, close to the substrate, of the first metal layer or located in the interconnection metal layer, the interconnection metal layer is located on the surface, away from the substrate, of the first metal layer. The problem that in the prior art, heat of a chip is concentrated at the source electrode contact position, transient temperature rise is caused, and gate source short circuit failure is caused is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a semiconductor device. Background Art

[0002] As a wide bandgap semiconductor material, silicon carbide has broad application prospects in high voltage, high power, high temperature and high frequency application fields due to its advantages such as wide bandgap, high critical electric field strength, high thermal conductivity and high saturation drift velocity.

[0003] Short circuit failure usually occurs when heat is concentrated at the source contact position during the short circuit (on the one hand, the current is conducted from the bonding wire to the chip; on the other hand, the current density is high in the channel position and low in the drift region; on the third hand, the electric field on the surface of the chip is high and the power is high). The thermal mismatch between different materials can cause microcracks in the material and changes in the material interface gap. Due to the low melting point of Al, Al enters the gap, causing a gate-source short circuit failure.

[0004] Therefore, how to make the temperature distribution on the chip surface more uniform and how to accelerate the heat transfer from the chip surface to the outside have become the improvement directions for improving short-circuit tolerance from the perspective of heat dissipation. Summary of the invention

[0005] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to solve the problem in the prior art that the heat of the chip is concentrated at the source contact position, resulting in gate-source short circuit failure caused by transient temperature rise.

[0006] To achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer, located on the surface of the substrate; a plurality of spaced source regions, located in the epitaxial layer, the surface of the source region away from the substrate overlaps with the partial surface of the epitaxial layer away from the substrate; a first metal layer, located on the side of the epitaxial layer away from the substrate, the partial surface of the first metal layer close to the substrate contacts with the partial surface of the epitaxial layer away from the substrate; an interconnection metal layer; a plurality of spaced heat-conducting layers, the heat-conducting layers are located on the side of the first metal layer away from or close to the substrate, or are located in the interconnection metal layer, the thermal conductivity of the heat-conducting layers is greater than the thermal conductivity of the interconnection metal layer; in the case where the heat-conducting layer is located on the side of the first metal layer away from the substrate, the interconnection metal layer is located on the surface of the heat-conducting layer away from the substrate and on the partial surface of the first metal layer away from the substrate, and in the case where the heat-conducting layer is located on the side of the first metal layer close to the substrate, or is located in the interconnection metal layer, the interconnection metal layer is located on the surface of the first metal layer away from the substrate.

[0007] Optionally, a work function of the interconnect metal layer is different from a work function of the first metal layer.

[0008] Optionally, the heat conducting layer includes a single layer or multiple layers of graphene.

[0009] Optionally, the semiconductor structure further includes: a plurality of spaced-apart gate structures and gate-source dielectric layers, the gate structure including a gate and a gate oxide layer located between the gate and the epitaxial layer; when the thermal conductive layer is located on a side of the first metal layer away from the substrate, or is located in the interconnect metal layer, the gate structure is located between the epitaxial layer and the first metal layer, and the gate-source dielectric layer is located between the gate structure and the first metal layer; when the thermal conductive layer is located on a side of the first metal layer close to the substrate, the gate structure is located between the epitaxial layer and the thermal conductive layer, and the gate-source dielectric layer is located between the gate structure and the thermal conductive layer.

[0010] Optionally, the semiconductor structure further includes: a first doped region located in the epitaxial layer and on a surface of the source region away from the first metal layer, and a doping type of the first doped region is different from a doping type of the source region.

[0011] Optionally, there are two source regions, and the semiconductor structure further includes: a second doped region, located between the two source regions and in contact with side walls of the two source regions, the doping type of the second doped region being the same as the doping type of the first doped region; and a plurality of third doped regions arranged at intervals, the third doped regions being located on a surface of the source region away from the second doped regions, the doping type of the third doped regions being the same as the doping type of the first doped regions.

[0012] Optionally, the semiconductor structure further includes: a second metal layer located on a surface of the substrate away from the epitaxial layer.

[0013] Optionally, the doping type of the epitaxial layer is the same as the doping type of the source region, and the doping concentration of the source region is greater than the doping concentration of the epitaxial layer.

[0014] Optionally, the doping concentration of the third doping region is lower than the doping concentration of the first doping region, and the doping concentration of the first doping region is lower than the doping concentration of the second doping region.

[0015] Optionally, the shape of the heat-conducting layer includes one of the following: strip, ring, square, hexagon, octagon and other polygons.

[0016] According to another aspect of the present application, a semiconductor device is provided, comprising any one of the semiconductor structures described above.

[0017] Applying the technical solution of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a plurality of spaced source regions located in the epitaxial layer, a first metal layer located on a side of the epitaxial layer away from the substrate, an interconnecting metal layer, and a plurality of spaced heat-conducting layers, wherein the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the interconnecting metal layer. When the heat-conducting layer is located on a side of the first metal layer away from the substrate, the interconnecting metal layer is located on a surface of the heat-conducting layer away from the substrate and on a portion of a surface of the first metal layer away from the substrate. When the heat-conducting layer is located on a side of the first metal layer close to the substrate or is located in the interconnecting metal layer, the interconnecting metal layer is located on a surface of the first metal layer away from the substrate. Compared with the problem in the prior art that the heat of the chip is concentrated at the source contact position, resulting in transient temperature rise, causing the interconnect metal layer to melt and enter the semiconductor gap, resulting in gate-source short circuit failure, the present application arranges the thermal conductive layer between the first metal layer and the interconnect metal layer, or arranges it below the interconnect metal layer and the first metal layer, or arranges it in the interconnect metal layer. Since the first metal layer is in contact with the epitaxial layer, the first metal layer and the epitaxial layer form an ohmic contact. By utilizing the advantage that the thermal conductivity of the thermal conductive layer is higher than that of the interconnect metal layer, the heat at the ohmic contact position is quickly transferred to various parts of the interconnect metal layer, thereby accelerating the realization of uniform temperature distribution in the interconnect metal layer, improving the problem of melting of the interconnect metal layer caused by heat concentration, and helping to improve the problem of gate-source short circuit failure caused by transient temperature rise. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0019] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided according to an embodiment of the present application is shown;

[0020] Figure 2 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0021] Figure 3 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0022] Figure 4 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0023] Figure 5 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0024] Figure 6A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0025] Figure 7 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0026] Figure 8 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0027] Fig. 9 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0028] Fig.10 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown;

[0029] Fig.11 A schematic cross-sectional structure diagram of another semiconductor structure provided according to an embodiment of the present application is shown.

[0030] The above drawings include the following reference numerals:

[0031] 10. Substrate; 11. Epitaxial layer; 12. Source region; 13. First metal layer; 14. Thermal conductive layer; 15. Interconnect metal layer; 16. Gate structure; 17. Gate-source dielectric layer; 18. First doped region; 19. Second doped region; 20. Third doped region; 21. Second metal layer; 161. Gate oxide layer; 162. Gate; 22. Third metal layer. DETAILED DESCRIPTION

[0032] It should be noted that the following detailed descriptions are illustrative and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0033] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0035] As introduced in the background technology, in the prior art, the heat of the chip is concentrated at the source contact position, resulting in transient temperature rise and causing gate-source short circuit failure. To solve the above problem, the embodiments of the present application provide a semiconductor structure and a semiconductor device.

[0036] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0037] In this embodiment, a semiconductor structure is provided, such as Figures 1 to 11 As shown, including:

[0038] Substrate 10;

[0039] An epitaxial layer 11 is located on the surface of the substrate 10;

[0040] A plurality of spaced source regions 12 are located in the epitaxial layer 11, and the surface of the source region 12 away from the substrate 10 overlaps with a portion of the surface of the epitaxial layer 11 away from the substrate 10;

[0041] A first metal layer 13 is located on a side of the epitaxial layer 11 away from the substrate 10, and a portion of the surface of the first metal layer 13 close to the substrate 10 is in contact with a portion of the surface of the epitaxial layer 11 away from the substrate 10;

[0042] Interconnect metal layer 15;

[0043] A plurality of heat-conducting layers 14 arranged at intervals, wherein the heat-conducting layers 14 are located on a side of the first metal layer 13 away from or close to the substrate 10, or are located in the interconnecting metal layer 15, and the thermal conductivity of the heat-conducting layers 14 is greater than the thermal conductivity of the interconnecting metal layer 15;

[0044] like Figures 2 to 4 As shown, in the case where the heat conducting layer is located on the side of the first metal layer away from the substrate, the interconnecting metal layer 15 is located on the surface of the heat conducting layer 14 away from the substrate 10 and on a part of the surface of the first metal layer 13 away from the substrate 10, as shown in FIG. Figure 1 , Figure 5 and Figure 6 As shown, the heat conducting layer 14 is located on the side of the first metal layer 13 close to the substrate 10, as shown in FIG. Fig.10 As shown, or in the case where it is located in the above-mentioned interconnection metal layer 15, the above-mentioned interconnection metal layer 15 is located on the surface of the above-mentioned first metal layer 13 away from the above-mentioned substrate 10.

[0045] Through the above embodiments, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a plurality of spaced source regions located in the epitaxial layer, a first metal layer located on a side of the epitaxial layer away from the substrate, an interconnecting metal layer, and a plurality of spaced heat-conducting layers, wherein the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the interconnecting metal layer, and in the case where the heat-conducting layer is located on a side of the first metal layer away from the substrate, the interconnecting metal layer is located on the surface of the heat-conducting layer away from the substrate and on a portion of the surface of the first metal layer away from the substrate, and in the case where the heat-conducting layer is located on a side of the first metal layer close to the substrate or is located in the interconnecting metal layer, the interconnecting metal layer is located on the surface of the first metal layer away from the substrate. Compared with the problem in the prior art that the heat of the chip is concentrated at the source contact position, resulting in transient temperature rise, causing the interconnect metal layer to melt and enter the semiconductor gap, resulting in gate-source short circuit failure, the present application arranges the thermal conductive layer between the first metal layer and the interconnect metal layer, or arranges it below the interconnect metal layer and the first metal layer, or arranges it in the interconnect metal layer. Since the first metal layer is in contact with the epitaxial layer, the first metal layer and the epitaxial layer form an ohmic contact. By utilizing the advantage that the thermal conductivity of the thermal conductive layer is higher than that of the interconnect metal layer, the heat at the ohmic contact position is quickly transferred to various parts of the interconnect metal layer, thereby accelerating the realization of uniform temperature distribution in the interconnect metal layer, improving the problem of melting of the interconnect metal layer caused by heat concentration, and helping to improve the problem of gate-source short circuit failure caused by transient temperature rise.

[0046] Specifically, Figures 1 to 11 As shown, at least a portion of the first metal layer 13 in contact with the epitaxial layer 11 is not covered by the thermal conductive layer 14 .

[0047] In the actual application process, those skilled in the art can flexibly select the appropriate thickness and doping type of the substrate, the thickness and doping type of the epitaxial layer, the thickness and doping type of the source region, the thickness of the first metal layer, the thickness of the thermal conductive layer, and the thickness of the interconnect metal layer according to actual needs, and this application does not impose specific restrictions on this. In the embodiment of this application, the doping type of the epitaxial layer is N-type doping, and the doping type of the source region is N-type doping.

[0048] In the embodiment of the present application, the work function of the first metal layer is 3eV-9eV, and the resistivity of the ohmic contact formed between the first metal layer and the epitaxial layer is less than 1eV. -3 Ω cm 2 .

[0049] Specifically, the material of the interconnect metal layer includes Al.

[0050] In an optional solution, the work function of the interconnect metal layer is different from the work function of the first metal layer.

[0051] In another optional solution, the thermal conductive layer includes a single or multiple graphene layers. In this embodiment, due to the high thermal conductivity of graphene, the heat at the ohmic contact position can be further quickly transferred to all parts of the interconnect metal layer, further improving the melting problem of the interconnect metal layer caused by heat concentration, and further improving the gate-source short circuit failure problem caused by transient temperature rise.

[0052] Specifically, graphene is not easy to break because of its strong toughness; and graphene has excellent electrical conductivity, which is conducive to the conduction of current in the metal interconnect layer, and thus conducive to the current balancing characteristics; graphene is composed of carbon and is easy to etch into different patterns. Specifically, graphene can be generated by carbonization of materials such as photoresist.

[0053] In an exemplary embodiment, Figures 1 to 11 As shown, the semiconductor structure further includes: a plurality of spaced-apart gate structures 16 and a gate-source dielectric layer 17, the gate structure 16 including a gate 162 and a gate oxide layer 161 located between the gate 162 and the epitaxial layer 11; when the thermal conductive layer 14 is located on a side of the first metal layer 13 away from the substrate 10, or is located in the interconnect metal layer 15, the gate structure 16 is located between the epitaxial layer 11 and the first metal layer 13, and the gate-source dielectric layer 17 is located between the gate structure 16 and the first metal layer 13; when the thermal conductive layer 14 is located on a side of the first metal layer 13 close to the substrate 10, the gate structure 16 is located between the epitaxial layer 11 and the thermal conductive layer 14, and the gate-source dielectric layer 17 is located between the gate structure 16 and the thermal conductive layer 14. In this embodiment, the gate structure is used to control the current flow and switch control of the device, ensuring good performance of the device. The gate-source dielectric layer is used to isolate the gate structure from the first metal layer or the thermal conductive layer, that is, to isolate the current between different layers and prevent the current from short-circuiting between different layers. The gate dielectric layer is used to isolate the gate from the semiconductor to prevent current leakage and short-circuiting of the device, thereby further ensuring good performance of the device.

[0054] Specifically, the cross-sectional shape of the gate-source dielectric layer may be a rectangle, a regular trapezoid, or other shapes, and the present application does not impose any specific restrictions on this. Figures 1 to 10 As shown, the cross-sectional shape of the gate-source dielectric layer 17 is a regular trapezoid.

[0055] Specifically, Figures 1 to 11 As shown, the gate-source dielectric layer 17 covers the gate structure 16 .

[0056] Specifically, those skilled in the art can flexibly select a suitable thickness of the above-mentioned gate structure according to actual needs, and this application does not impose any specific limitation on this.

[0057] In other embodiments, Figures 1 to 11 As shown, the semiconductor structure further includes: a first doping region 18, which is located in the epitaxial layer 11 and on the surface of the source region 12 away from the first metal layer 13, and the doping type of the first doping region 18 is different from the doping type of the source region 12. In this embodiment, the doping type of the first doping region is different from the doping type of the source region, so that the first doping region and the source region form a PN junction, which ensures good stability of the device switch.

[0058] In actual application, those skilled in the art can flexibly select a suitable thickness of the first doping region according to actual needs, and this application does not impose any specific limitation on this.

[0059] In the embodiment of the present application, the first doped region is P-type doped.

[0060] In some other exemplary embodiments, Figures 1 to 11 As shown, there are two source regions 12, and the semiconductor structure further includes: a second doping region 19, which is located between the two source regions 12 and in contact with the sidewalls of the two source regions 12, and the doping type of the second doping region 19 is the same as the doping type of the first doping region 18; and a plurality of third doping regions 20 arranged at intervals, the third doping regions 20 are located on the surface of the source region 12 away from the second doping region 19, and the doping type of the third doping region 20 is the same as the doping type of the first doping region 18. In this embodiment, the second doping region is located between the two source regions, the third doping region is located on the surface of the source region away from the second doping region, and the doping type of the second doping region and the doping type of the third doping region are different from the doping type of the source region, which ensures that the on-state voltage of the device is low, and further ensures that the performance of the device is good.

[0061] In actual application, those skilled in the art can flexibly select appropriate thicknesses of the second doping region and the third doping region according to actual needs, and the present application does not impose any specific restrictions on this.

[0062] In the embodiment of the present application, the second doping region is P-type doped, and the third doping region is P-type doped.

[0063] Some options include Figures 1 to 11As shown, the semiconductor structure further includes: a second metal layer 21, which is located on the surface of the substrate 10 away from the epitaxial layer 11. In this embodiment, the second metal layer serves as a drain of the semiconductor structure, and is used to collect the electron flow of the device, so as to control the switching and amplification functions of the device, and further ensures good stability of the device.

[0064] In actual application, those skilled in the art can flexibly select a suitable thickness of the second metal layer according to actual needs, and this application does not impose any specific limitation on this.

[0065] In some other optional solutions, the doping type of the epitaxial layer is the same as the doping type of the source region, and the doping concentration of the source region is greater than the doping concentration of the epitaxial layer. In this embodiment, the doping type of the epitaxial layer is the same as the doping type of the source region, and the doping concentration of the source region is greater than the doping concentration of the epitaxial layer, which ensures that the electron mobility of the device is high, and further ensures that the performance and stability of the device are good.

[0066] In some further optional solutions, the doping concentration of the third doping region is less than the doping concentration of the first doping region, and the doping concentration of the first doping region is less than the doping concentration of the second doping region. In this embodiment, the doping concentration of the third doping region is less than the doping concentration of the first doping region, and the doping concentration of the first doping region is less than the doping concentration of the second doping region, which further ensures that the electron mobility of the device is high, and further ensures that the performance and stability of the device are good.

[0067] Specifically, those skilled in the art can flexibly select appropriate thicknesses of the gate dielectric layer and the gate electrode according to actual needs, and the present application does not impose any specific limitation on this.

[0068] In other embodiments, Figures 7 to 9 As shown, in the case where the heat conducting layer 14 is located on the side of the first metal layer 13 away from the substrate 10 , the semiconductor structure further includes: a third metal layer 22 located between the heat conducting layer 14 and the interconnect metal layer 15 .

[0069] Specifically, Figures 7 to 9 As shown, the third metal layer 22 is located on the surface of the heat conducting layer 14 away from the substrate 10 and on a portion of the surface of the first metal layer 13 away from the substrate 10 .

[0070] In other embodiments, the shape of the heat-conducting layer includes one of the following: strip, ring, square, hexagon, octagon and other polygons.

[0071] In another embodiment, Fig.11As shown, the first metal layer 13 is located on a portion of the surface of the epitaxial layer 11 away from the substrate 10, a portion of the surface of the gate-source dielectric layer 17 away from the substrate 10, and a portion of the sidewall of the gate-source dielectric layer 17, the thermal conductive layer 14 is located on a portion of the surface of the gate-source dielectric layer 17 away from the substrate 10 and the sidewall of the first metal layer 13, and the interconnection metal layer 15 covers the thermal conductive layer 14 and the first metal layer 13. Specifically, the thermal conductive layer is directly in contact with the first metal layer and the gate-source dielectric layer.

[0072] According to another embodiment of the present application, a semiconductor device is provided, comprising any one of the above-mentioned semiconductor structures.

[0073] Through the above embodiments, the semiconductor device includes any semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a plurality of spaced source regions located in the epitaxial layer, a first metal layer located on a side of the epitaxial layer away from the substrate, an interconnecting metal layer, and a plurality of spaced heat-conducting layers, the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the interconnecting metal layer, when the heat-conducting layer is located on a side of the first metal layer away from the substrate, the interconnecting metal layer is located on a surface of the heat-conducting layer away from the substrate and on a portion of a surface of the first metal layer away from the substrate, and when the heat-conducting layer is located on a side of the first metal layer close to the substrate or in the interconnecting metal layer, the interconnecting metal layer is located on a surface of the first metal layer away from the substrate. Compared with the problem in the prior art that the heat of the chip is concentrated at the source contact position, resulting in transient temperature rise, causing the interconnect metal layer to melt and enter the semiconductor gap, resulting in gate-source short circuit failure, the present application arranges the thermal conductive layer between the first metal layer and the interconnect metal layer, or arranges it below the interconnect metal layer and the first metal layer, or arranges it in the interconnect metal layer. Since the first metal layer is in contact with the epitaxial layer, the first metal layer and the epitaxial layer form an ohmic contact. By utilizing the advantage that the thermal conductivity of the thermal conductive layer is higher than that of the interconnect metal layer, the heat at the ohmic contact position is quickly transferred to various parts of the interconnect metal layer, thereby accelerating the realization of uniform temperature distribution in the interconnect metal layer, improving the problem of melting of the interconnect metal layer caused by heat concentration, and helping to improve the problem of gate-source short circuit failure caused by transient temperature rise.

[0074] Through the above embodiments, the semiconductor device of the present application includes a semiconductor structure, wherein:

[0075] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0076] 1) In the semiconductor structure of the present application, the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a plurality of spaced source regions located in the epitaxial layer, a first metal layer located on a side of the epitaxial layer away from the substrate, an interconnecting metal layer, and a plurality of spaced heat-conducting layers, wherein the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the interconnecting metal layer. When the heat-conducting layer is located on a side of the first metal layer away from the substrate, the interconnecting metal layer is located on a surface of the heat-conducting layer away from the substrate and on a portion of a surface of the first metal layer away from the substrate. When the heat-conducting layer is located on a side of the first metal layer close to the substrate or in the interconnecting metal layer, the interconnecting metal layer is located on a surface of the first metal layer away from the substrate. Compared with the problem in the prior art that the heat of the chip is concentrated at the source contact position, resulting in transient temperature rise, causing the interconnect metal layer to melt and enter the semiconductor gap, resulting in gate-source short circuit failure, the present application arranges the thermal conductive layer between the first metal layer and the interconnect metal layer, or arranges it below the interconnect metal layer and the first metal layer, or arranges it in the interconnect metal layer. Since the first metal layer is in contact with the epitaxial layer, the first metal layer and the epitaxial layer form an ohmic contact. By utilizing the advantage that the thermal conductivity of the thermal conductive layer is higher than that of the interconnect metal layer, the heat at the ohmic contact position is quickly transferred to various parts of the interconnect metal layer, thereby accelerating the realization of uniform temperature distribution in the interconnect metal layer, improving the problem of melting of the interconnect metal layer caused by heat concentration, and helping to improve the problem of gate-source short circuit failure caused by transient temperature rise.

[0077] 2) In the semiconductor device of the present application, the semiconductor device includes any semiconductor structure, wherein the semiconductor structure includes a substrate, an epitaxial layer located on the surface of the substrate, a plurality of spaced source regions located in the epitaxial layer, a first metal layer located on a side of the epitaxial layer away from the substrate, an interconnecting metal layer, and a plurality of spaced heat-conducting layers, the thermal conductivity of the heat-conducting layer is greater than the thermal conductivity of the interconnecting metal layer, when the heat-conducting layer is located on a side of the first metal layer away from the substrate, the interconnecting metal layer is located on the surface of the heat-conducting layer away from the substrate and on a portion of the surface of the first metal layer away from the substrate, when the heat-conducting layer is located on a side of the first metal layer close to the substrate, or is located in the interconnecting metal layer, the interconnecting metal layer is located on the surface of the first metal layer away from the substrate. Compared with the problem in the prior art that the heat of the chip is concentrated at the source contact position, resulting in transient temperature rise, causing the interconnect metal layer to melt and enter the semiconductor gap, resulting in gate-source short circuit failure, the present application arranges the thermal conductive layer between the first metal layer and the interconnect metal layer, or arranges it below the interconnect metal layer and the first metal layer, or arranges it in the interconnect metal layer. Since the first metal layer is in contact with the epitaxial layer, the first metal layer and the epitaxial layer form an ohmic contact. By utilizing the advantage that the thermal conductivity of the thermal conductive layer is higher than that of the interconnect metal layer, the heat at the ohmic contact position is quickly transferred to various parts of the interconnect metal layer, thereby accelerating the realization of uniform temperature distribution in the interconnect metal layer, improving the problem of melting of the interconnect metal layer caused by heat concentration, and helping to improve the problem of gate-source short circuit failure caused by transient temperature rise.

[0078] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; an epitaxial layer located on the surface of the substrate; A plurality of spaced source regions are located in the epitaxial layer, and surfaces of the source regions away from the substrate overlap with a portion of a surface of the epitaxial layer away from the substrate; A first metal layer is located on a side of the epitaxial layer away from the substrate, and a portion of the surface of the first metal layer close to the substrate is in contact with a portion of the surface of the epitaxial layer away from the substrate; Interconnect metal layer; A plurality of heat-conducting layers arranged at intervals, wherein the heat-conducting layers are located on a side of the first metal layer away from or close to the substrate, or are located in the interconnecting metal layer, and the thermal conductivity of the heat-conducting layers is greater than the thermal conductivity of the interconnecting metal layer; In the case where the heat-conducting layer is located on a side of the first metal layer away from the substrate, the interconnecting metal layer is located on a surface of the heat-conducting layer away from the substrate and on a partial surface of the first metal layer away from the substrate; in the case where the heat-conducting layer is located on a side of the first metal layer close to the substrate or is located in the interconnecting metal layer, the interconnecting metal layer is located on the surface of the first metal layer away from the substrate.

2. The semiconductor structure according to claim 1, characterized in that: The work function of the interconnect metal layer is different from the work function of the first metal layer.

3. The semiconductor structure according to claim 1, characterized in that: The heat conducting layer includes a single layer or multiple layers of graphene.

4. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: A plurality of gate structures and gate-source dielectric layers are arranged at intervals, wherein the gate structure includes a gate and a gate oxide layer located between the gate and the epitaxial layer; when the thermal conductive layer is located on a side of the first metal layer away from the substrate, or is located in the interconnect metal layer, the gate structure is located between the epitaxial layer and the first metal layer, and the gate-source dielectric layer is located between the gate structure and the first metal layer; when the thermal conductive layer is located on a side of the first metal layer close to the substrate, the gate structure is located between the epitaxial layer and the thermal conductive layer, and the gate-source dielectric layer is located between the gate structure and the thermal conductive layer.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: A first doped region is located in the epitaxial layer and on a surface of the source region away from the first metal layer, and a doping type of the first doped region is different from a doping type of the source region.

6. The semiconductor structure according to claim 5, characterized in that: There are two source regions, and the semiconductor structure further includes: a second doping region, located between the two source regions and in contact with sidewalls of the two source regions, wherein the doping type of the second doping region is the same as the doping type of the first doping region; A plurality of third doping regions are arranged at intervals, wherein the third doping regions are located on a surface of the source region away from the second doping region, and the doping type of the third doping regions is the same as the doping type of the first doping regions.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The second metal layer is located on a surface of the substrate away from the epitaxial layer.

8. The semiconductor structure according to claim 1, characterized in that: The doping type of the epitaxial layer is the same as the doping type of the source region, and the doping concentration of the source region is greater than the doping concentration of the epitaxial layer.

9. The semiconductor structure according to claim 6, characterized in that: The doping concentration of the third doping region is less than the doping concentration of the first doping region, and the doping concentration of the first doping region is less than the doping concentration of the second doping region.

10. The semiconductor structure according to claim 1, wherein: The shape of the heat-conducting layer includes one of the following: strip, ring, square, hexagon, octagon and other polygons.

11. A semiconductor device, characterized in that: A semiconductor structure comprising any one of claims 1 to 10.

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