Semiconductor module and method for manufacturing semiconductor module

Abstract

The invention provides a semiconductor module and a manufacturing method of the semiconductor module, which can reduce thermal stress applied to an electrode, reduce deformation of the electrode and improve reliability. A semiconductor module is provided with: a laminated substrate (5) on which a semiconductor element (1) is mounted; a lead frame (10) electrically connected to the semiconductor element (1); and a sealing resin (8) that seals a member to be sealed, which includes the semiconductor element (1), the lead frame (10), and the laminated substrate (5). The lead frame (10) is provided with a plurality of recesses (23) on the upper surface of a bonding portion (31) bonded to the semiconductor element (1).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module and a method for manufacturing the semiconductor module. Background Art

[0002] Conventionally, there is a known semiconductor device in which a roughened area is formed on the lead by laser irradiation before the wire is bonded to the lead, so that the bonded portion of the wire is surrounded by an area having high adhesion to the molded resin, thereby suppressing wire breakage caused by stress (see Patent Document 1 below).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2018-157023 Summary of the invention

[0004] Technical issues Conventional semiconductor modules have problems such as separation between a lead frame and a sealing resin due to thermal stress, cracks occurring in electrodes of semiconductor elements, and separation between electrodes and bonding materials such as solder.

[0005] An object of the present disclosure is to provide a semiconductor module and a method for manufacturing the semiconductor module that can reduce thermal stress applied to electrodes, reduce deformation of electrodes, and improve reliability in order to solve the above-mentioned problems of the prior art.

[0006] Technical Solution In order to solve the above problems and achieve the purpose of the present disclosure, the semiconductor module disclosed in the present disclosure has the following features. The semiconductor module comprises a laminated substrate on which a semiconductor element is mounted, a lead frame electrically connected to the semiconductor element, and a sealing resin for sealing a sealed component including the semiconductor element, the lead frame and the laminated substrate, wherein the lead frame has a plurality of recesses on the upper surface of a joint portion joined to the semiconductor element.

[0007] In order to solve the above problems and achieve the purpose of the present disclosure, the manufacturing method of the semiconductor module disclosed in the present disclosure has the following characteristics. It includes: a first step of bonding a semiconductor element to a laminated substrate; a second step of bonding the semiconductor element to a lead frame having a plurality of recesses; a third step of sealing the laminated substrate with a resin; and a fourth step of curing the resin; before the second step, a step of forming the plurality of recesses at a bonding portion of the lead frame bonded to the semiconductor element.

[0008] According to the above disclosure, by providing a plurality of recessed portions on the bonding portion of the lead frame, the thermal stress applied to the upper surface electrode can be reduced, the deformation of the upper surface electrode can be reduced, and the reliability of the semiconductor module can be improved.

[0009] Technical Effects According to the semiconductor module and the method for manufacturing the semiconductor module of the present disclosure, it is possible to reduce the thermal stress applied to the electrode, reduce the deformation of the electrode, and achieve the effect of improving the reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a cross-sectional view showing the structure of a semiconductor module according to an embodiment.

[0011] Figure 2 It is a cross-sectional view showing the structure of a bonding portion between a semiconductor chip and a lead frame in a semiconductor module according to an embodiment.

[0012] Figure 3 It is a plan view showing the structure of a lead frame of the semiconductor module according to the embodiment.

[0013] Figure 4 It is a plan view showing the structure of a lead frame of the semiconductor module according to the embodiment.

[0014] Figure 5 It is a perspective view showing the structure of a lead frame of the semiconductor module according to the embodiment.

[0015] Figure 6 Graph showing the relationship between the recess volume ratio and the deformation of the upper surface electrode of the semiconductor module according to the embodiment.

[0016] Figure 7 Graph showing the relationship between the longitudinal position of the installation recess and the deformation of the upper surface electrode of the semiconductor module according to the embodiment.

[0017] Figure 8 Graph (Part 1) showing the relationship between the longitudinal position of the installation recess and the deformation of the upper surface electrode of the semiconductor module according to the embodiment.

[0018] Fig. 9 This is a graph (part 2) showing the relationship between the longitudinal position of the installation recess and the deformation of the upper surface electrode of the semiconductor module according to the embodiment.

[0019] Fig.10 Graph (Part 1) showing the relationship between the longitudinal position of the installation recess and the deformation of the upper surface electrode of the semiconductor module according to the embodiment.

[0020] Fig.11 This is a graph (part 2) showing the relationship between the longitudinal position of the installation recess and the deformation of the upper surface electrode of the semiconductor module according to the embodiment.

[0021] Fig.12This is a graph showing deformation of the top surface electrode due to thermal stress in a conventional semiconductor module.

[0022] Fig.13 1 is a flowchart showing a method for manufacturing a semiconductor module according to an embodiment.

[0023] Explanation of symbols 1Semiconductor chip 2Insulation substrate 3. First conductive plate 4 Second conductive plate 5-layer substrate 7 Shell 8 Sealing resin 10 Lead Frame 21 Insulation protective film 22 Upper surface electrode 23 concavity 24 Bonding layer 25 bonding layer 26 heat dissipation base (cooler) 27 Bonding layer 31Joint 32 bending part 33 Rising part 34 Connection 50 semiconductor modules DETAILED DESCRIPTION

[0024] <Overview of Embodiments of the Present Disclosure> In order to solve the above problems and achieve the purpose of the present disclosure, the semiconductor module of the present disclosure has the following features. The semiconductor module comprises a laminated substrate on which a semiconductor element (also referred to as a semiconductor chip) is mounted, a lead frame electrically connected to the semiconductor element, and a sealing resin for sealing a sealed component including the semiconductor element, the lead frame and the laminated substrate, wherein the lead frame has a plurality of recesses on the upper surface of a joint portion joined to the semiconductor element.

[0025] According to the above disclosure, by providing a plurality of recesses on the upper surface of the bonding portion of the lead frame, thermal stress applied to the upper surface electrode can be reduced, deformation of the upper surface electrode can be reduced, and reliability of the semiconductor module can be improved.

[0026] In addition, the semiconductor module of the present disclosure is characterized in that, in the above disclosure, the hole diameter of the recessed portion of the semiconductor module is 0.05 mm to 0.4 mm, and the depth is 0.1 mm to 0.45 mm.

[0027] In addition, the semiconductor module of the present disclosure is characterized in that, in the above disclosure, a ratio of the volume of the recessed portion to the volume of the bonding portion is 5% or more.

[0028] According to the above disclosure, the maximum deformation of the upper surface electrode can be reduced by 4%.

[0029] In addition, the semiconductor module of the present disclosure is characterized in that, in the above disclosure, if the length of the joint is set to L, and the length from the root of the lead frame to the center of the recess is set to D, the recesses are arranged in a row in the depth direction of the lead frame, and the positions of the recesses are set at positions where the ratio D / L is less than 60%. It should be noted that, Figure 2 As shown, the root portion is a boundary portion between the bending portion 32 and the joint portion 31 of the guide wire frame.

[0030] According to the above disclosure, the deformation of the upper surface electrode can be reduced by more than 3%, and the reliability can be improved by more than 30%.

[0031] In addition, the semiconductor module of the present disclosure is characterized in that, in the above disclosure, the recessed portion is provided at a position where the ratio D / L is 10% or more and 40% or less.

[0032] According to the above disclosure, the deformation of the upper surface electrode is reduced by more than 3.5% and the reliability is improved by more than 40%.

[0033] In addition, the semiconductor module of the present invention is characterized in that, in the above invention, if the length of the joint is set to L, and the length from the root of the lead frame to the center of the recess farthest from the root is set to D, then the recess is provided in a plurality of rows in the depth direction of the lead frame until a ratio D / L is achieved, and the ratio D / L is greater than 5% and less than 20%.

[0034] According to the above disclosure, the deformation of the upper surface electrode can be reduced by more than 3%, and the reliability can be improved by more than 40%.

[0035] In addition, the semiconductor module of the present disclosure is characterized in that, in the above disclosure, the ratio D / L is 20% or more and 60% or less.

[0036] According to the above disclosure, the deformation of the upper surface electrode can be reduced by 4% or more, and the reliability can be improved by 50% or more.

[0037] In order to solve the above problems and achieve the purpose of the present disclosure, the manufacturing method of the semiconductor module disclosed in the present disclosure has the following characteristics. It includes: a first step of bonding a semiconductor element to a laminated substrate; a second step of bonding the semiconductor element to a lead frame having a plurality of recesses; a third step of sealing the laminated substrate with a resin; and a fourth step of curing the resin. Prior to the second step, it includes a step of forming the plurality of recesses at the joint portion of the lead frame that is bonded to the semiconductor element.

[0038] <Insights that form the basis of this disclosure> First, the problems of conventional semiconductor modules are described. Conventional semiconductor modules include semiconductor chips, laminated substrates, housings, heat sinks, and lead frames. The semiconductor chip is a power semiconductor chip such as a MOSFET, an IGBT, or a diode, and is bonded to the laminated substrate through a bonding layer such as solder. A substrate having a first conductive plate such as copper on the front of an insulating substrate such as a ceramic substrate and a second conductive plate such as copper on the back of an insulating substrate such as a ceramic substrate is called a laminated substrate. The laminated substrate is bonded to the heat sink through a bonding layer such as solder. In addition, in the case of a MOSFET, a source electrode pad is formed on the surface of the semiconductor chip as a power terminal electrode pad (current supply terminal). Furthermore, a conductive connecting component such as a lead frame or a metal wire is configured from the power terminal electrode pad as an output terminal. It should be noted that the power terminal electrode pad (upper surface electrode) of the semiconductor chip is bonded to the lead frame through a bonding layer such as solder. A housing is bonded to the semiconductor module, and a cover is installed for the metal terminal to penetrate and protrude to the outside. A sealing resin for insulating and protecting the laminated substrate and the semiconductor chip on the substrate is filled in the housing.

[0039] Fig.12 FIG. 1 is a graph showing deformation of the top surface electrode caused by thermal stress in a conventional semiconductor module. Fig.12 In FIG. 1 , the horizontal axis represents the distance from the end of the bonding layer 27 on the surface of the semiconductor chip, and the unit is mm. The vertical axis represents the deformation of the power terminal electrode pad (upper surface electrode) of the semiconductor chip, and the unit is %. Fig.12 It is the result of thermal stress analysis using the finite element method (FEM). Fig.12 In the figure, L11 is the part where the lead frame is joined to the upper surface electrode (joining part), and its length is about 3.0 mm. In addition, L12 is the part corresponding to the root part (bend part side) of the joint part of the lead frame. Fig.12 As shown, the electrode undergoes the maximum deformation (A11) at the root portion of the joint.

[0040] Thus, conventional semiconductor modules also have tensile stress acting in the horizontal direction of the upper surface electrode due to the thermal stress applied to the lead frame, so that deformation occurs on the upper surface electrode, cracks occur on the upper surface electrode, or the upper surface electrode and bonding materials such as solder peel off. In addition, there is a problem of peeling between the lead frame and the sealing resin due to thermal stress caused by power cycles, thermal cycles, etc.

[0041] Hereinafter, preferred embodiments of the semiconductor module and the method for manufacturing the semiconductor module of the present disclosure will be described in detail with reference to the drawings. However, the present disclosure is not limited to the embodiments described below.

[0042] (Implementation Method) Hereinafter, a semiconductor module according to an embodiment that solves the above-mentioned problems will be described. Figure 1 : is a cross-sectional view showing the structure of a semiconductor module 50 according to an embodiment. In the semiconductor module 50, a first conductive plate 3 made of copper is arranged on one surface, i.e., the front surface, of an insulating substrate 2, and a second conductive plate 4 made of copper or the like is arranged on the other surface, i.e., the back surface, to form a laminated substrate 5. On the front surface of the first conductive plate 3 of the laminated substrate 5, a plurality of semiconductor chips 1 are mounted via a bonding layer 24 made of solder or a sintered material. The first conductive plate 3 is formed on the front surface (first main surface) of the insulating substrate 2 in a predetermined circuit pattern. The second conductive plate 4 on the back surface of the laminated substrate 5 is bonded to the front surface of a heat dissipation base 26 via a bonding layer 25 made of solder and / or a sintered material or the like. The second conductive plate 4 may be a metal foil formed on the entire back surface of the insulating substrate 2.

[0043] A metal terminal (not shown) for outputting a signal to the outside is bonded to the housing 7. Moreover, a lead frame 10 as a conductive connection portion is mounted on the front surface of the semiconductor chip 1 (e.g., a source electrode pad) via a bonding layer 27. In addition, a sealing resin 8 is filled inside the housing 7. It should be noted that the structure of the semiconductor module 50 shown in the figure is an example, and the present disclosure is not limited to this structure. For example, a module structure without the housing 7 may also be used.

[0044] (Semiconductor chip 1) The semiconductor chip 1 is a power chip such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor) or an SBD (Schottky Barrier Diode), and as a semiconductor substrate, a device using Si, SiC, or GaN can be used. In particular, the present disclosure is effective for SiC chips and GaN chips with high power and high Young's modulus. The number of semiconductor chips 1 mounted can be one or more. It should be noted that an upper surface electrode 22 such as a source pad made of an aluminum alloy or the like is formed on the upper surface of the semiconductor chip 1.

[0045] (Laminated substrate 5) The laminated substrate 5 can be composed of an insulating substrate 2, a first conductive plate 3 formed into a predetermined shape on one main surface of the insulating substrate 2, and a second conductive plate 4 formed on the other main surface of the insulating substrate 2. The surface of the first conductive plate 3 is bonded to the back of the semiconductor chip 1 via a bonding layer 24. As the insulating substrate 2, a material with excellent electrical insulation and thermal conductivity can be used. As the material of the insulating substrate 2, for example, Al2O3, AlN, SiN, etc. can be listed. In particular, in high-voltage applications, materials with both electrical insulation and thermal conductivity are preferred. AlN and SiN can be used, but are not limited to these. As the first conductive plate 3 and the second conductive plate 4, Cu (copper) or Cu alloy with excellent processability can be used. It should be noted that the Cu alloy is an alloy containing more than 80% of Cu. Sometimes, the conductive plate that is not in contact with the semiconductor chip 1 among such conductive plates composed of Cu or Cu alloy is also called back copper foil or back conductive plate. As a method for arranging the conductive plate on the insulating substrate 2, a direct copper bonding method or an active metal brazing method can be cited. In addition, the surface of the conductive plate can be plated with Ni (nickel) to form a Ni or Ni alloy layer.

[0046] (Heat dissipation base 26) The heat dissipation base 26 is a heat dissipation plate, for example, in a roughly rectangular plane shape, formed of a metal such as Cu and Al with excellent thermal conductivity, and is also called a metal substrate. The surface of the heat dissipation base 26 may also be covered with a Ni film or a Ni alloy film having an anti-corrosion effect. The back of the heat dissipation base 26 may also be bonded to a cooling base portion (not shown). The heat dissipation base 26 can be bonded to the second conductive plate 4 of the stacked substrate 5 via the bonding layer 25, and conduct the heat generated in the semiconductor chip 1 and transferred via the stacked substrate 5 to the heat dissipation fin portion. The heat dissipation fin portion has a plurality of heat dissipation fins, which dissipate the heat conducted from the heat dissipation base 26. It should be noted that the heat dissipation base 26 itself may also be a cooling device such as a heat dissipation fin portion.

[0047] (Joint layer 27, junction layer 24, junction layer 25) The bonding layer 27, the bonding layer 24, and the bonding layer 25 can be formed using lead-free solder. For example, Sn-Sb system, Sn-Cu system, Sn-Ag system, Sn-Sb-Ag system, etc. can be used, but are not limited to these. In addition, it can also be formed using a connection material containing tiny metal particles such as a sintered body of nanosilver particles.

[0048] (Lead frame 10) The lead frame 10 is a conductive wiring that electrically connects the upper surface electrode 22 of the semiconductor chip 1 to the first conductive plate 3 of the laminate substrate 5 , an external output terminal (not shown), and the like via a bonding portion such as a bonding layer 27 . Figure 2 It is a cross-sectional view showing the structure of a bonding portion between a semiconductor chip and a lead frame in a semiconductor module according to an embodiment. Figure 3 It is a plan view showing the structure of a lead frame of the semiconductor module according to the embodiment.

[0049] like Figure 2 As shown, the lead frame 10 has a bonding portion 31 bonded to the bonding layer 27 on the upper surface electrode 22 of the semiconductor chip 1, a bent portion 32 connecting the bonding portion 31 to the rising portion 33, the rising portion 33 provided substantially perpendicularly from the upper surface of the semiconductor chip 1 and away from the upper surface electrode 22, a bent portion connecting the rising portion 33 to the connecting portion 34, and a connecting portion 34 substantially parallel to the upper surface of the semiconductor chip 1 and connected to other bonding portions (the first conductive plate 3, the external output terminal, etc.). The bonding portion 31 of the lead frame 10 is bonded to the upper surface electrode 22 of the semiconductor chip 1 via the bonding layer 27 provided in the opening of the insulating protective film 21. It should be noted that the root portion of the lead frame refers to the vicinity of the bent portion side of the bonding portion 31.

[0050] Figure 4 It is a plan view showing the structure of a lead frame of the semiconductor module according to the embodiment. Figure 5 This is a perspective view showing the structure of the lead frame of the semiconductor module of the embodiment. For example, the length L1 of the lead frame 10 in the longitudinal direction (x direction) is 3.5 mm, the length L2 (L) of the joint 31 is the length from the end (front end) E of the lead frame 10 to the bent portion 32, which is 2.8 mm, and the length L3 from the end (front end) E of the lead frame 10 to the rising portion 33 is 3.1 mm. In addition, the width W1 of the lead frame 10 in the depth direction (y direction) (the width of the joint 31) is 2.7 mm, and the width W2 of the connecting portion 34 is 2.0 mm. Figure 4 and Figure 5 The structure is an example, and other structures may be used. For example, the width of the joint portion 31 may be the same as the width of the connecting portion 34. Figure 4 , 5 As shown, in the rising portion 33, the width on the side of the joint portion 31 may be longer than the width on the side of the connecting portion 34. This is because the width of the rising portion 33 on the side of the connecting portion 34 is shorter, so that the thermal stress applied to the upper surface electrode 22 (the root portion of the lead frame 10) can be reduced. The lead frame 10 has a thickness of 0.5 mm and is made of copper. Ni (NiP) can be plated after forming the recessed portion 23 described later.

[0051] In an embodiment, if Figure 2 and Figure 3 As shown, the joint 31 has a plurality of recesses 23. It should be noted that the upper surface of the joint 31 refers to the surface on the side opposite to the semiconductor chip 1 side and in contact with the sealing resin 8. The recesses 23 are circular when viewed from above, and are arranged evenly in a dotted shape on the entire surface of the joint 31. It should be noted that the shape of the recesses 23 when viewed from above may be an ellipse, a quadrilateral, a rectangle, or a rhombus in addition to a circle. In addition, the cross-sectional shape of the recess 23 may be a shape with an internal bulge, a hemispherical shape, a rectangle, or a trapezoidal, triangular, or wedge-shaped shape in which the front end of the recess 23 is narrowed. The recess 23 may have a hole diameter of, for example, not less than 0.05 mm and not more than 0.4 mm, and a depth of not less than 0.1 mm and not more than 0.45 mm. For example, as Figure 3 As shown, the plurality of recesses 23 are formed by stamping into 6 rows (0.5 mm pitch P1) in the length direction and 5 rows (0.46 mm pitch P2) in the depth direction. The plurality of recesses 23 may also be formed by laser processing or the like. In addition, the row R1 closest to the rising portion 33 among the plurality of recesses 23 is separated from the end of the joint 31 close to the rising portion 33 by a distance E1 (for example, 0.15 mm), and the row R6 farthest from the rising portion 33 among the plurality of recesses 23 is separated from the end of the joint 31 far from the rising portion 33 by a distance E2 (for example, 0.15 mm).

[0052] Figure 6 Graph showing the relationship between the concave volume ratio and the deformation of the upper surface electrode of the semiconductor module according to the embodiment. Figure 2 , 3 As shown in FIG. 1 , the recessed portion 23 is uniformly provided on the entire upper surface of the bonding layer 27. It should be noted that the upper surface refers to the surface on the side in contact with the sealing resin 8. Figure 6 , the horizontal axis represents the ratio of the volume of the recess 23 to the volume of the bonding portion 31 of the lead frame 10 (volume ratio: volume of the recess 23 / volume of the bonding portion 31), in %. The vertical axis represents the standardized maximum deformation of the upper surface electrode 22 of the semiconductor chip 1, in %. Figure 6 This is the result of thermal stress analysis using FEM. In the embodiment, the maximum deformation occurs in the electrode at the root of the joint 31 as in the conventional example, and the maximum deformation is the deformation of the upper surface electrode 22 at the root of the joint 31. Figure 6 In the figure, the conventional example in which the recessed portion 23 is not provided is set to 100%.

[0053] Regarding the volume of the recess 23 , the depth of the recess 23 is set to 0.1 mm to 0.45 mm, and the hole diameter is set to 0.05 mm to 0.4 mm. The volume of the bonding portion 31 of the lead frame 10 is 3.1 mm×2.7 mm×0.5 mm.

[0054] like Figure 6 As shown in FIG. 1 , it can be seen that regardless of the volume ratio, the maximum deformation of the upper surface electrode 22 is reduced by providing the recess 23, and the effect is achieved at all volume ratios. Figure 6 As shown in A1 of FIG. 1 , if the volume ratio is set to 5% or more, the maximum deformation of the upper surface electrode can be reduced by 4%. For example, a volume ratio of 5.4% can be achieved by setting the aperture of the recess 23 to 0.2 mm and the depth to 0.4 mm. Thus, in the embodiment, by providing a plurality of recesses 23 on the lead frame 10, especially on the joint 31, the thermal stress applied to the upper surface electrode 22 can be reduced, the deformation of the upper surface electrode 22 can be reduced, and the reliability of the semiconductor module 50 can be improved.

[0055] (Shell 7) The lower end of a shell 7 made of resin or the like is bonded to the periphery of the heat dissipation base 26. The shell 7 is in a roughly rectangular cylindrical shape and surrounds the periphery of the front surface of the heat dissipation base 26. A box-shaped recess is formed with the front surface of the heat dissipation base 26 as the bottom surface and the inner wall of the shell 7 orthogonal to the front surface of the heat dissipation base 26 as the side wall. The semiconductor chip 1 wired by wiring components such as a lead frame 10, the laminated substrate 5, and wiring component parts are accommodated inside the recess. The material of the shell 7 can be, for example, a thermoplastic resin such as polyphenylene sulfide (PPS) and polybutylene terephthalate (PBT), or a thermosetting resin such as a phenolic resin. It should be noted that the semiconductor module 50 can be formed by forming the semiconductor chip 1, the laminated substrate 5, etc. using a sealing resin 8 without including the shell 7.

[0056] (Sealing resin 8) The sealing resin 8 is a sealing resin layer used to seal the sealed component, which is arranged in contact with the sealed component and mainly covers the semiconductor chip 1, the laminated substrate 5, the lead frame 10, etc. The sealing resin 8 can be composed of a thermosetting resin composition, and is particularly preferably composed of a thermosetting resin composition with high heat resistance. The thermosetting resin composition contains a thermosetting resin main agent, and can arbitrarily and selectively contain an inorganic filler, a curing agent, a curing accelerator and necessary additives. In the thermosetting resin composition constituting the sealing resin 8, a fluorine-based silane coupling agent may be included, or a fluorine-based silane coupling agent may not be included, but it is preferably not included. This is because the glass transition temperature (Tg) of the sealing resin 8 is sometimes reduced.

[0057] The main thermosetting resin is not particularly limited, and examples thereof include epoxy resins, phenolic resins, maleimide resins, and the like. Among them, epoxy resins having at least two epoxy groups in one molecule are particularly preferred because of their high dimensional stability, water resistance, chemical resistance, and electrical insulation. Specifically, aliphatic epoxy resins, alicyclic epoxy resins, or a mixture of aliphatic epoxy resins and alicyclic epoxy resins are preferably used.

[0058] In the thermosetting resin composition of the present embodiment, an inorganic filler (filler) may be included as an arbitrarily selected component. The inorganic filler may be a metal oxide or a metal nitride, for example, fused silica (fused silica), silica (silicon oxide), aluminum oxide (alumina), aluminum hydroxide, titanium dioxide (titanium oxide), zirconium oxide (zirconia), aluminum nitride, talc, clay, mica, glass fiber, etc., but not limited to these. Through these inorganic fillers, the thermal conductivity of the cured product can be improved and the thermal expansion coefficient can be reduced. In addition, these inorganic fillers can be used alone or in combination of two or more. In addition, these inorganic fillers can be micron fillers or nanofillers, and two or more inorganic fillers with different particle sizes and / or types can also be mixed and used. It should be noted that, from the point of view of adhesion, it is preferred that at least a part of the inorganic filler enters the concave portion 23, and it is preferred to include more inorganic fillers having a particle size smaller than the diameter (pore size) of the concave portion 23 when viewed from above than inorganic fillers having a particle size larger than the diameter (pore size) of the concave portion 23 when viewed from above. Specifically, the particle size (average particle size) of the inorganic filler is preferably 5 μm to 100 μm, and more preferably 20 μm to 60 μm. In addition, it is preferred to include 10% to 20% of an inorganic filler having a particle size of 5 μm to 10 μm smaller than the diameter of the concave portion 23 when viewed from above. It should be noted that the particle size of the inorganic filler can be measured using a particle size distribution measuring instrument using laser scattering, etc.

[0059] In the thermosetting resin composition, as an arbitrarily selected component, in addition to the thermosetting resin main agent, or in addition to the thermosetting resin main agent and the inorganic filler, a curing agent may also be included. As a curing agent, as long as it is a curing agent that can react and solidify with a thermosetting resin main agent, preferably an epoxy resin main agent, it is not particularly limited, and an anhydride curing agent is preferably used. As an anhydride curing agent, for example, aromatic anhydrides can be listed, specifically, phthalic anhydride, pyromellitic anhydride, trimellitic anhydride, etc. can be listed. Alternatively, cyclic aliphatic anhydrides, specifically, tetrahydrophthalic anhydride, methyltetrahydrophthalic anhydride, hexahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylnadic anhydride, etc., or aliphatic anhydrides, specifically succinic anhydride, polyadipic anhydride, polysebacic anhydride, polyazepam anhydride, etc. can be listed. In addition, when using bisphenol A epoxy resin alone or a mixture of bisphenol A epoxy resin and the high heat-resistant epoxy resin exemplified above as the thermosetting resin main agent, the heat resistance is improved when no curing agent is used, which is sometimes preferable.

[0060] A curing accelerator may be further added to the thermosetting resin composition as an optional component. As the curing accelerator, imidazole or its derivatives, tertiary amines, boric acid esters, Lewis acids, organic metal compounds, organic acid metal salts, etc. may be appropriately blended.

[0061] The thermosetting resin composition may further contain any selected additives within the range that does not impair its characteristics. Examples of additives include flame retardants, pigments for coloring the resin, plasticizers for improving crack resistance, and silicone elastomers, but are not limited thereto. These optional components and their addition amounts may be appropriately determined by those skilled in the art according to the specifications required by the semiconductor device and / or the sealing material.

[0062] (Method for Manufacturing Semiconductor Module According to Embodiment) Next, a method for manufacturing the semiconductor module according to the embodiment will be described. Fig.13 1 is a flowchart showing a method for manufacturing a semiconductor module according to an embodiment. First, the semiconductor chip 1 is bonded to the laminate substrate 5 using the bonding layer 24 (step S1: first process). Before bonding the lead frame 10, a plurality of recesses 23 are formed in the lead frame 10, for example, in the bonding portion 31, by stamping or laser processing (step S2: a process for forming a plurality of recesses).

[0063] Then, the lead frame 10 having a plurality of recesses 23 is bonded to the semiconductor chip 1 (step S3: second process). Next, the laminated substrate 5 is sealed with a thermosetting resin composition constituting the sealing resin 8 (step S4: third process). It should be noted that at least a portion of the lead frame may be sealed. Then, the sealing resin 8 is cured by heating (step S5: fourth process). Specifically, the sealing resin 8 is pre-cured at 100 to 120° C. for 10 to 120 minutes and formally cured at about 175 to 185° C. for 1 to 2 hours. In addition, in the case of a housing 7, before the sealing process, a process of mounting the laminated substrate 5 to the housing 7 is included, and then, in the housing 7, the sealing resin 8 is injected into the housing 7 and the sealing resin 8 is cured by heating. It should be noted that, in the case of using a heat dissipation base, a process of bonding the heat dissipation base 26 to the laminated substrate 5 using the bonding layer 25 may be included. Specifically, the heat dissipation base 26 may be bonded before bonding the semiconductor chip 1 to the laminated substrate 5.

[0064] As described above, according to the semiconductor module of the embodiment, by providing a plurality of recesses on the bonding portion of the lead frame, thermal stress applied to the upper surface electrode can be reduced, deformation of the upper surface electrode can be reduced, and reliability of the semiconductor module can be improved.

[0065] (Example) Hereinafter, the present disclosure will be described in more detail by listing the embodiments of the present disclosure. However, the present disclosure is not limited to the scope of the following embodiments. Table 1 is an example of providing only one row of recesses 23 in the depth direction (y direction) and confirming the dependence of the position (long side direction) of the recesses 23. Table 2 is an example of increasing the number of rows of recesses 23 from the root along the length direction (x direction) and confirming the dependence of the number of recesses 23. Comparative Example 1 is a shape in which no recess 23 is provided in the lead frame 10. The adhesion is evaluated by a shear test (a shear test for measuring the adhesion strength of the sealing resin), and the module reliability is evaluated by a power cycle test. The ratio of setting Comparative Example 1 to 1 is shown together with the evaluation value.

[0066]

Table 1

[0067] In Table 1, in Examples 1 to 6, the total length of the lead frame 10 is set to 3.8 mm, the length L of the bonding portion 31 is set to 3 mm, and the length from the root of the lead frame 10 (hereinafter referred to as the “root”) to the center of the recess 23 is set to D (refer to Figure 2), an example in which the position of the recess 23 from the root is changed. It should be noted that a row of recesses 23 is formed in such a manner that the hole diameter of the recess 23 is 0.2 mm, the depth is 0.4 mm, and the pitch in the depth direction is 0.5 mm. Example 1 is an example in which 5 recesses 23 are provided in column R1, and no recesses 23 are provided in columns R2 to R6. Example 2 is an example in which 5 recesses 23 are provided in column R2, and no recesses 23 are provided in columns R1, R3 to R6. The same is true for Examples 3 to 6. The root of the lead frame 10 is the boundary between the bonding portion 31 and the bending portion 32. The position of the recess in Table 1 (position from the root (mm), ratio) indicates the length D and the ratio D / L (%). The deformation reduction rate (%) indicates the reduction rate relative to the maximum deformation of the upper surface electrode 22 of Comparative Example 1, and thermal stress analysis is performed by FEM. Specifically, the ratio of the reduced deformation is taken as the reduction rate based on the maximum deformation of Comparative Example 1.

[0068] Figure 7 Graph showing the relationship between the longitudinal position of the recessed portion of the semiconductor module according to the embodiment and the deformation of the upper surface electrode. Graphing Table 1. Figure 7 In FIG. 1 , the horizontal axis represents the position of the recess 23 from the root as a ratio D / L, and the unit is %. The vertical axis represents the maximum deformation of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. Figure 7 The dotted line represents the deformation value of Comparative Example 1 in which no recessed portion is provided.

[0069] As shown in Table 1 and Figure 7 As shown, if a row of recesses 23 is provided at a position less than 60% from the root of the lead frame 10, the deformation of the upper surface electrode 22 can be reduced by more than 3%, and the reliability can be improved by more than 30% ( Figure 7 In particular, if the recess 23 is provided at a position not less than 10% and not more than 40% from the root of the lead frame 10 ( Figure 7 A2), the deformation of the upper surface electrode 22 is reduced by more than 3.5%, and the reliability is improved by more than 40%. On the other hand, if it is set at a position closer to the front end than 60%, the deformation increases, the reduction rate of the deformation becomes lower, and the reliability is hardly improved.

[0070] That is, it is found that even if the volume ratio of the recess 23 is the same, the reduction rate of the strain varies depending on the position of the recess 23 , and it is found that providing the recess 23 at the base of the joint 31 close to the rising portion 33 (bend portion 32 ) produces a better effect.

[0071]

Table 2

[0072] In Table 2, Examples 7 to 12 are examples in which the total length of the lead frame 10 is set to 3.8 mm, the length L of the joint 31 is set to 3 mm, the length from the root of the lead frame 10 to the center of the recess 23 is set to D, and the number of rows of the recess 23 is increased from the root. In the case where the recess 23 is in multiple rows as in Examples 8 to 12, the length D is the length from the root of the lead frame 10 to the center of the recess 23 farthest from the root of the lead frame 10. It should be noted that the recess 23 is formed in one row of recesses 23 with a hole diameter of 0.2 mm, a depth of 0.4 mm, and a pitch of 0.5 mm in the depth direction. The recess volume ratio of one row of recesses 23 is 0.9% (5.4 / 6%). Example 7 is an example in which five recesses 23 are arranged in one row in the depth direction (y direction) in row R1, and no recess 23 is arranged in rows R2 to R6. Example 8 is an example in which 5 recesses 23 are arranged in a row in the depth direction (y direction) of columns R1 and R2, and no recesses 23 are arranged in columns R3 to R6. The same is true for Examples 9 to 12. The position of the recess in Table 2 (position from the root (mm), ratio) represents the length D and the ratio D / L (%). The deformation reduction rate (%) represents the reduction rate of the maximum deformation of the upper surface electrode 22 relative to Comparative Example 1, and is the result of thermal stress analysis by FEM. Adhesion represents the adhesion strength when the recesses 23 of 5×6 columns in Example 12, 5×5 columns in Example 11, 5×4 columns in Example 10, 5×3 columns in Example 9, 5×2 columns in Example 8, and 5×1 column in Example 7 are arranged in the center of the cup (capc) (measurement area).

[0073] Figure 8 and Fig. 9 Graphs showing the relationship between the longitudinal position of the recessed portion of the semiconductor module according to the embodiment and the deformation of the upper surface electrode. Graphs of Table 2 are obtained. Figure 8 In FIG. 1 , the horizontal axis represents the position of the recess 23 from the root as a ratio D / L, and the unit is %. The vertical axis represents the maximum deformation of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. Figure 8 The dotted line represents the deformation value of Comparative Example 1 in which no recess is provided. Fig. 9 In the figure, the horizontal axis represents the position of the recess 23 from the root as a ratio D / L, and the unit is %. The vertical axis represents the standardized maximum deformation of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. Fig. 9 In the figure, the comparative example in which the recessed portion 23 is not provided is set to 100%.

[0074] As shown in Table 2, Figure 8 and Fig. 9As shown in FIG. 1 , if the recesses 23 are provided in increasing rows from the root to the front end of the lead frame 10, the deformation of the upper surface electrode 22 is reduced compared to the case where only one row of recesses 23 is provided. Furthermore, if the recesses 23 are provided to a position of 5% or more and 90% or less from the root, the deformation of the upper surface electrode 22 can be reduced by 3% or more ( Fig. 9 In particular, if the recess 23 is set to a position of more than 20% and less than 60% from the root, the deformation of the upper surface electrode 22 can be reduced by more than 4% ( Fig. 9 A5), which can improve reliability by more than 50%.

[0075] Therefore, it is preferable to provide the recessed portion 23 at least to a position not more than 20% from the root. That is, when the number of recessed portions 23 is increased from the root, the recessed portion 23 is provided from the root of the rising portion 33 (bend portion 32) close to the joint portion 31, thereby further reducing the deformation.

[0076] Fig.10 and Fig.11 Graph showing the relationship between the longitudinal position of the recessed portion and the deformation of the upper surface electrode of the semiconductor module according to the embodiment. Fig.10 and Fig.11 This is a summary of the results obtained in Tables 1 and 2. Fig.10 In the figure, the horizontal axis represents the position of the recess from the root as a ratio D / L, and the unit is %. The vertical axis represents the maximum deformation of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. Fig.10 The dotted line represents the deformation value of Comparative Example 1 in which no recess is provided. Fig.10 The thick line of △ indicates the case where only one row of recessed portions 23 is provided, and the thin line of ○ indicates the case where an additional row of recessed portions 23 is provided. Fig.11 In FIG. 1 , the horizontal axis represents the position of the recess from the root as a ratio D / L, and the unit is %. The vertical axis represents the normalized maximum strain of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. Fig.11 The thick line of △ indicates the case where only one row of recessed portions 23 is provided, and the thin line of ○ indicates the case where an additional row of recessed portions 23 is provided. Fig.11 In the figure, the comparative example in which the recessed portion 23 is not provided is set to 100%.

[0077] According to these results, by providing the recesses 23 in the lead frame 10, the deformation of the upper surface electrode 22 can be reduced. If the recesses 23 are provided in increasing columns from the root to the front end of the lead frame 10, the deformation of the upper surface electrode 22 is reduced compared to the case where only one column of recesses 23 is provided.

[0078] As a principle for reducing the deformation of the upper surface electrode 22, it is presumed that the stress caused by the reduction in the rigidity of the lead frame 10 is relieved by forming a recess 23 near the root of the lead frame 10 where the stress is concentrated. In addition, it is considered that the sealing resin 8 enters the recess 23, and the rigidity of the sealing resin 8 is lower than that of the lead frame 10, so the overall rigidity is reduced and deformation becomes easy to occur. Therefore, it is presumed that the sealing resin 8 in the recess 23 helps to relieve stress. It should be noted that even if the size of the joint 31 of the lead frame 10, the depth of the recess 23, the aperture, etc. are changed, the same effect as the embodiment can be obtained.

[0079] The following is a detailed description of the shear test and power cycle test performed in the embodiment. In the lead frame 10 used in the power cycle test, the cross-sectional shape of the recess 23 is formed into a trapezoidal shape with a wide opening and a narrow front end of the hole by punching (laser processing). The recess 23 is formed to have a hole diameter of 0.2 mm and a depth of 0.4 mm. The epoxy resin used is an epoxy resin generally used for sealing (the same applies to the filler).

[0080] The power cycle test is based on the conditions of ΔT = 135℃, Tjmax = 175℃, power-on operation for 1 second and rest for 9 seconds as one cycle, and the number of cycles when the thermal resistance increases by 20% or the resistance of the main current part increases by 5% is taken as the power cycle tolerance.

[0081] In the shear test, a concave portion 23 (pitch in the length direction: 0.5 mm, pitch in the depth direction: 0.46 mm) of a predetermined shape (0.2 mm Φ / depth 0.4 mm) is provided in a predetermined range on the surface of a 5 mm×5 mm copper plate imitating the joint portion 31 of the lead frame 10, and the copper plate is used as a substrate for the shear test. On the copper plate, an epoxy resin composition that can be used as a sealing material is formed into a bottom surface diameter of 3.6 mm, a top surface diameter of 3.0 mm, and a height of 3.0 mm, and a thermal curing reaction is performed at 100-180°C for 3 hours to obtain a test piece of epoxy resin cured product formed on the copper plate.

[0082] The shear strength was measured using a dynamometer (load measuring device: ZTA-1000N manufactured by IMADA Corporation). The measurement conditions were as follows: the epoxy resin cured material was pressed parallel to the adhesive surface at a speed (deformation speed) of 0.2 mm / s, and the strength at the time when the interface between the epoxy resin cured material and the resin composite substrate was peeled off and broken was taken as the adhesion strength.

[0083] As described above, the present disclosure can be variously modified within the scope of the main purpose of the present disclosure. In the above embodiments, for example, the size of each part, the impurity concentration, etc. are variously set according to the required specifications. In addition, in the above embodiments, as a semiconductor, in addition to silicon, wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) can also be applied.

[0084] Industrial Applicability As described above, the semiconductor module of the present disclosure, that is, the method for manufacturing a semiconductor module, is useful in power semiconductor modules used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles.

Claims

1. A semiconductor module, characterized in that: have: A laminate substrate having a semiconductor element mounted thereon; a lead frame electrically connected to the semiconductor element; and a sealing resin that seals a sealed component including the semiconductor element, the lead frame, and the laminated substrate, The lead frame has a plurality of recessed portions on an upper surface of a portion joined to the semiconductor element.

2. The semiconductor module according to claim 1, characterized in that The recessed portion has a hole diameter of 0.05 mm to 0.4 mm, and a depth of 0.1 mm to 0.45 mm.

3. The semiconductor module according to claim 1, characterized in that A ratio of the volume of the recessed portion to the volume of the joining portion is 5% or more.

4. The semiconductor module according to claim 1, characterized in that If the length of the joint is set to L, and the length from the root of the lead frame to the center of the recess is set to D, the recess is arranged in a row in the depth direction of the lead frame, and the position of the recess is set at a position where the ratio D / L is less than 60%.

5. The semiconductor module according to claim 4, characterized in that The position of the recessed portion is set at a position where the ratio D / L is 10% or more and 40% or less.

6. The semiconductor module according to claim 1, characterized in that If the length of the joint is set to L, and the length from the root of the lead frame to the center of the recess farthest from the root is set to D, the recess is arranged in multiple rows in the depth direction of the lead frame to a position up to a ratio D / L, and the ratio D / L is greater than 5% and less than 60%.

7. The semiconductor module according to claim 6, characterized in that The ratio D / L is 20% or more and 60% or less.

8. A method for manufacturing a semiconductor module, characterized in that: include: In a first step, a semiconductor element is bonded to a laminate substrate; The second step is to bond the semiconductor element to a lead frame having a plurality of recesses; A third step is to seal the laminated substrate with a resin; as well as The fourth step is to solidify the resin; Prior to the second step, a step of forming the plurality of recesses at a joint portion of the lead frame to be joined to the semiconductor element is included.

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