Integrated circuit, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses an integrated circuit, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The integrated circuit includes a power distribution network, a semiconductor structure, a gate line, a first pole, a power supply communication portion, a first electrode contact portion, a second electrode contact portion, and an isolation layer. And the power supply communication part is positioned between two adjacent semiconductor structures and is in contact with the power distribution network. The power supply connection part divides the grid line into a first sub-grid line and a second sub-grid line. And the first electrode contact part and the second electrode contact part are positioned on two opposite sides of the power supply communication part. The first electrode contact portion and the second electrode contact portion are both in contact with the first pole. The isolation layer isolates the power supply communication part from the first sub-grid line and the second sub-grid line. And the power supply communication part penetrates through the isolation layer and is in contact with the first electrode contact part and / or the second electrode contact part. Through the arrangement of the isolation layer, the risks of short circuit and breakdown between the power supply communication part and the first sub-grid line and between the power supply communication part and the second sub-grid line can be reduced, and the reliability of the integrated circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated circuit and a method for manufacturing the same, and an electronic device. Background Art

[0002] As semiconductor devices continue to shrink, the density of transistors in chips is getting higher and higher. Backside power delivery network (BSPDN) technology and buried power rail (BPR) technology have been proposed to free up more space and alleviate the shrinking pressure faced by metal interconnects. At the same time, they can also achieve the shrinking benefits of chip area, improve current resistance voltage drop (IR drop), enhance chip performance, and reduce power consumption. However, this technical solution has the problem of low reliability. Summary of the invention

[0003] The embodiments of the present application provide an integrated circuit and a method for manufacturing the same, and an electronic device, for improving the reliability of the integrated circuit.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, an integrated circuit is provided, which includes: a power distribution network, a plurality of semiconductor structures, a gate line, a first pole, a power supply connection part, a first electrode contact part, a second electrode contact part and an isolation layer. The power distribution network has a first surface. A plurality of semiconductor structures are located on the first surface. The plurality of semiconductor structures extend along a first direction and are arranged at intervals along a second direction. The first direction and the second direction are both parallel to the first surface and intersect. The gate line is arranged across the plurality of semiconductor structures, and the gate line extends along the second direction. The first pole is in contact with the semiconductor structure; along the first direction, the first pole is located on one side of the gate line. The power supply connection part is located between two adjacent semiconductor structures, and the power supply connection part is in contact with the power distribution network. The power supply connection part extends along the first direction, dividing the gate line into a first sub-gate line and a second sub-gate line. The first electrode contact part and the second electrode contact part are located on opposite sides of the power supply connection part along the second direction. The first electrode contact part and the second electrode contact part are located on different first poles and in contact with the corresponding first poles. The isolation layer is at least located on two opposite sides of the power supply connection part along the second direction, separating the power supply connection part from the first sub-grid line and the second sub-grid line. The power supply connection part also penetrates the isolation layer and contacts the first electrode contact part and / or the second electrode contact part.

[0006] The integrated circuits provided in some embodiments of the present application can use the isolation layer to separate the power connection part and the first sub-gate line, and separate the power connection part and the second sub-gate line, by setting an isolation layer around the power connection part, so as to achieve electrical insulation between the power connection part and the first sub-gate line, and achieve electrical insulation between the power connection part and the second sub-gate line.

[0007] The isolation layer has a self-alignment function, which is used to provide a self-alignment effect for the power connection part. In this way, after etching a groove penetrating the gate line between the two adjacent semiconductor structures, an isolation layer can be formed in the groove first, and then the power connection part can be formed in the groove. The material of the power connection part can be naturally filled in the area defined by the isolation layer based on the self-alignment effect provided by the isolation layer. In this way, there is no need to form an insulating layer in the groove, nor is there a need to form an electrical via in the insulating layer, and the problem of greater process difficulty caused by etching the electrical via can be avoided.

[0008] Moreover, the isolation layer has a certain thickness, and the thickness is relatively uniform. The embodiment of the present application can adopt an isolation layer to replace the above-mentioned insulating layer, so that there is a sufficient insulation distance between the power supply connection part and the first sub-gate line, and there is a sufficient insulation distance between the power supply connection part and the second sub-gate line, thereby reducing the risk of short circuit and breakdown between the power supply connection part and the first sub-gate line, and between the power supply connection part and the second sub-gate line, and improving the breakdown voltage between the power supply connection part and the first sub-gate line, and between the power supply connection part and the second sub-gate line, and improving the reliability of the integrated circuit.

[0009] In a possible design mode of the first aspect, the first electrode contact portion, the second electrode contact portion and the power supply connection portion are arranged in the same layer, so that the first electrode contact portion, the second electrode contact portion and the power supply connection portion can be formed simultaneously in the same patterning process, which is conducive to simplifying the preparation process of the integrated circuit.

[0010] In a possible design of the first aspect, the power supply connection part is in contact with the first electrode contact part and is an integral structure. Or, the power supply connection part is in contact with the second electrode contact part and is an integral structure. Or, the power supply connection part is in contact with the first electrode contact part and the second electrode contact part, and the three are an integral structure. In this way, the structural stability and electrical connection reliability between the power supply connection part and the first electrode contact part and / or the second electrode contact part can be improved, and the influence on the transmission of electrical signals between the power supply connection part and the first electrode contact part and / or the second electrode contact part can be avoided. Moreover, it is also helpful to reduce the difficulty of preparing and forming the power supply connection part and the first electrode contact part and / or the second electrode contact part.

[0011] In a possible design mode of the first aspect, the first electrode contact portion includes a first conductive layer and a first barrier layer, and the power supply connection portion includes a second conductive layer and a second barrier layer. When the power supply connection portion contacts the first electrode contact portion, the first conductive layer and the second conductive layer are connected to form an integral structure; the first barrier layer and the second barrier layer are connected to form an integral structure, and the first barrier layer and the second barrier layer jointly surround the first conductive layer and the second conductive layer. In this way, the first conductive layer and the second conductive layer can be used to reduce the contact resistance between the first electrode contact portion and the power supply connection portion, and the first barrier layer and the second barrier layer can be used to improve the adhesion between the first electrode contact portion, the power supply connection portion and the surrounding structures.

[0012] In a possible design mode of the first aspect, the power supply connection part includes a second conductive layer and a second barrier layer, and the second electrode contact part includes a third conductive layer and a third barrier layer. When the power supply connection part contacts the second electrode contact part, the second conductive layer and the third conductive layer are connected to form an integral structure; the second barrier layer and the third barrier layer are connected to form an integral structure, and the second barrier layer and the third barrier layer jointly surround the second conductive layer and the third conductive layer. In this way, the third conductive layer and the second conductive layer can be used to reduce the contact resistance between the second electrode contact part and the power supply connection part, and the third barrier layer and the second barrier layer can be used to improve the adhesion between the second electrode contact part, the power supply connection part and the surrounding structures.

[0013] In a possible design mode of the first aspect, the first electrode contact portion includes a first conductive layer and a first barrier layer, the power supply connection portion includes a second conductive layer and a second barrier layer, and the second electrode contact portion includes a third conductive layer and a third barrier layer. When the power supply connection portion contacts the first electrode contact portion and the second electrode contact portion, the first conductive layer, the second conductive layer and the third conductive layer are connected and form an integral structure; the first barrier layer, the second barrier layer and the third barrier layer are connected and form an integral structure; the first barrier layer, the second barrier layer and the third barrier layer surround the first conductive layer, the second conductive layer and the third barrier layer together. In this way, the first conductive layer, the third conductive layer and the second conductive layer can be used to reduce the contact resistance of the first electrode contact portion, the second electrode contact portion and the power supply connection portion, and the first barrier layer, the third barrier layer and the second barrier layer can be used to improve the adhesion between the first electrode contact portion, the second electrode contact portion, the power supply connection portion and the surrounding structures.

[0014] In a possible design of the first aspect, the material of the isolation layer includes at least one of silicon nitride, silicon carbide, silicon carbonitride, and silicon oxynitride.

[0015] In a possible design of the first aspect, the surface of the isolation layer close to the power distribution network is flush with the surface of the power connection part close to the power distribution network. In this way, the power connection part can be formed in one step, and the isolation layer can be avoided from being etched during the formation of the power connection part, which is conducive to simplifying the preparation process of the integrated circuit and improving the preparation efficiency of the integrated circuit.

[0016] In a possible design mode of the first aspect, the integrated circuit further includes: a second pole, a third electrode contact portion, a fourth electrode contact portion and an interconnection layer. The second pole contacts the semiconductor structure. Along the first direction, the second pole and the first pole are located on opposite sides of the gate line. The third electrode contact portion and the fourth electrode contact portion are located on opposite sides of the power supply contact portion along the second direction; the isolation layer separates the power supply contact portion and the third electrode contact portion, and separates the power supply contact portion and the fourth electrode contact portion. The third electrode contact portion and the fourth electrode contact portion are located on different second poles and contact the corresponding second poles. The interconnection layer is located on the third electrode contact portion and the fourth electrode contact portion, and is electrically connected to the third electrode contact portion and the fourth electrode contact portion. The electrical signal transmitted by the interconnection layer can be transmitted to the corresponding second pole via the third electrode contact portion, or transmitted to the corresponding second pole via the fourth electrode contact portion. By setting the interconnection layer, the interconnection of various components (such as transistors, capacitors, resistors, etc.) on the power distribution network can be achieved.

[0017] In a possible design mode of the first aspect, the third electrode contact portion, the fourth electrode contact portion and the power supply connection portion are arranged in the same layer, so that the third electrode contact portion, the fourth electrode contact portion and the power supply connection portion can be formed simultaneously in the same patterning process, which is conducive to simplifying the manufacturing process of the integrated circuit.

[0018] In a possible design of the first aspect, the integrated circuit further includes: at least two dummy gate lines. The dummy gate lines extend along the second direction. The gate line is located between two adjacent dummy gate lines, and the power supply connection portion also isolates the dummy gate lines.

[0019] In a second aspect, a method for preparing an integrated circuit is provided, the method comprising: forming an initial integrated circuit; the initial integrated circuit comprises a plurality of semiconductor structures, a first dielectric layer, a gate line, and a first pole; the plurality of semiconductor structures extend along a first direction and are arranged at intervals along a second direction; the first dielectric layer is filled between two adjacent semiconductor structures; the gate line is arranged across the plurality of semiconductor structures and extends along the second direction; the first pole is in contact with the semiconductor structure; along the first direction, the first pole is located on one side of the gate line. A first groove is formed between two adjacent semiconductor structures; the first groove passes through the gate line and the first dielectric layer; the first groove extends along the first direction, cutting the gate line into a first sub-gate line and a second sub-gate line. An isolation layer is formed in the first groove; the isolation layer covers the sidewalls of the first groove. An opening is formed in the isolation layer. A power supply connection part, a first electrode contact part and a second electrode contact part are formed; the power supply connection part is located in the first groove, and the first electrode contact part and the second electrode contact part are located on opposite sides of the power supply connection part along the second direction; the first electrode contact part and the second electrode contact part are located on different first poles and contact the corresponding first poles; the power supply connection part contacts the first electrode contact part and / or the second electrode contact part through the opening. A power distribution network is formed on the side of the semiconductor structure away from the gate line; the power distribution network contacts the power supply connection part; the power distribution network has a first surface, and the first direction and the second direction are both parallel to the first surface and intersect with each other.

[0020] The method for preparing an integrated circuit provided in the embodiment of the present application forms an isolation layer in a first trench formed between two adjacent semiconductor structures, thereby providing a self-alignment effect for a power connection part subsequently formed in the first trench, so that the material of the power connection part is naturally filled in the area defined by the isolation layer, wherein the required alignment, photolithography, etching and other processes are less difficult, which is conducive to increasing the process window.

[0021] Moreover, the embodiment of the present application does not need to etch the electrical via in the isolation layer, thus avoiding the problems caused by etching the electrical via. That is, the embodiment of the present application can utilize the isolation layer with relatively uniform thickness to realize the electrical insulation between the power supply connection part and the first sub-grid line, and realize the electrical insulation between the power supply connection part and the second sub-grid line, and at the same time, it can make the power supply connection part and the first sub-grid line have enough insulation distance, and make the power supply connection part and the second sub-grid line have enough insulation distance, thereby reducing the risk of short circuit and breakdown between the power supply connection part and the first sub-grid line, and between the power supply connection part and the second sub-grid line, and improving the breakdown voltage between the power supply connection part and the first sub-grid line, and between the power supply connection part and the second sub-grid line, and improving the reliability of the integrated circuit.

[0022] In a possible design mode of the second aspect, the initial integrated circuit also includes a second dielectric layer; along the first direction, the second dielectric layer is located on opposite sides of the gate line and covers the first electrode. Before forming the opening in the isolation layer, the preparation method also includes: forming a second groove in the second dielectric layer. The second groove exposes the first electrode; along the second direction, the second groove is located on opposite sides of the isolation layer; the opening connects the second groove and the first groove. Forming a power supply connection part, a first electrode contact part and a second electrode contact part includes: filling a conductive material in the first groove, the second groove and the opening to form a power supply connection part, a first electrode contact part and a second electrode contact part. In the same patterning process, the power supply connection part, the first electrode contact part and the second electrode contact part are formed simultaneously, which is conducive to simplifying the preparation process of the integrated circuit. Moreover, the structures of the power supply connection part, the first electrode contact part and the second electrode contact part are relatively simple, which is convenient for preparation and is conducive to improving the preparation efficiency of the integrated circuit.

[0023] In a possible design mode of the second aspect, before the conductive material is filled in the first trench, the second trench and the opening, the preparation method further includes: forming a barrier film that at least covers the sidewalls of the first trench, the sidewalls of the second trench and the sidewalls of the opening. When the power connection part is in contact with the first electrode contact part, the barrier film surrounds the power connection part and the first electrode contact part; when the power connection part is in contact with the second electrode contact part, the barrier film surrounds the power connection part and the second electrode contact part. This is conducive to simplifying the preparation process of the integrated circuit, and the second barrier film can be used to improve the adhesion between the conductive material and the surrounding dielectric layer (such as the second dielectric layer).

[0024] In a possible design mode of the second aspect, forming an isolation layer in the first trench includes: forming an isolation film; the isolation film covers the gate line, the sidewall and the bottom wall of the first trench. Forming a third dielectric layer; a portion of the third dielectric layer fills the first trench, and another portion is located on a side of the isolation film away from the gate line. The third dielectric layer and the portion of the isolation film located on the gate line are removed simultaneously, and the portion of the third dielectric layer filled in the first trench is etched.

[0025] In a possible design mode of the second aspect, the initial integrated circuit also includes a substrate, the substrate has a second surface and a third surface opposite to each other, the semiconductor structure is located on the second surface; the first groove also extends to the substrate. Before forming a power distribution network on the side of the semiconductor structure away from the gate line, the preparation method also includes: removing the substrate from the side where the third surface is located to expose the power connection part. In this way, it can be ensured that in the prepared integrated circuit, the end of the power connection part close to the power distribution network is located in the first dielectric layer, which is conducive to improving the performance of the prepared integrated circuit.

[0026] In a possible design mode of the second aspect, the initial integrated circuit also includes a second pole, which contacts the semiconductor structure. Along the first direction, the second pole and the first pole are located on opposite sides of the gate line. In the process of forming the power supply connection part, the first electrode contact part and the second electrode contact part, a third electrode contact part and a fourth electrode contact part are also formed; the third electrode contact part and the fourth electrode contact part are located on opposite sides of the power supply connection part along the second direction; the third electrode contact part and the fourth electrode contact part are located on different second poles and contact the corresponding second poles. Before forming a power distribution network on the side of the semiconductor structure away from the gate line, the preparation method also includes: forming an interconnection layer on the third electrode contact part and the fourth electrode contact part; the interconnection layer is electrically connected to the third electrode contact part and the fourth electrode contact part. This is conducive to simplifying the preparation process of the integrated circuit and can realize the interconnection of various components (such as transistors, capacitors, resistors, etc.) on the power distribution network.

[0027] In a third aspect, an electronic device is provided, the electronic device comprising a circuit board and an integrated circuit as described in any embodiment of the first aspect. The integrated circuit is connected to the circuit board.

[0028] The technical effects brought about by any design method in the third aspect can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0030] Figure 2 A partial structural diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 3 A structural diagram of an integrated circuit provided in an embodiment of the present application;

[0032] Figure 4 for Figure 3 A cross-sectional view of the integrated circuit shown along the CC direction;

[0033] Figure 5a for Figure 3 A cross-sectional view of the integrated circuit shown along the DD direction;

[0034] Figure 5b for Figure 3 Another cross-sectional view of the integrated circuit along the DD direction;

[0035] Figure 6 for Figure 3 A cross-sectional view of the integrated circuit shown along the EE direction;

[0036] Figure 7 for Figure 3 A cross-sectional view of the integrated circuit shown along the FF direction;

[0037] Figure 8 A structural diagram of another integrated circuit provided in an embodiment of the present application;

[0038] Fig. 9 A structural diagram of another integrated circuit provided in an embodiment of the present application;

[0039] Fig.10 A structural diagram of another integrated circuit provided in an embodiment of the present application;

[0040] Fig.11 A structural diagram of another integrated circuit provided in an embodiment of the present application;

[0041] Fig.12 A structural diagram of another integrated circuit provided in an embodiment of the present application;

[0042] Fig.13 A flowchart of a method for preparing an integrated circuit provided in an embodiment of the present application;

[0043] Figure 14a-Figure 29b A structural diagram corresponding to each step in a method for preparing an integrated circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0045] In the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one item" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one item of a, b, and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0046] "And / or" describes the relationship between the associated objects, indicating that there can be three relationships. For example, a and / or b can mean: a exists alone, a and b exist at the same time, and b exists alone, where a and b can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0047] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0048] When describing some embodiments, the expression "connected" and its derivatives are used. The term "connected" should be understood in a broad sense. For example, "connected" can be fixedly connected, detachably connected, or integrated; it can be directly connected or indirectly connected through an intermediate medium. In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more of the conditions or values ​​can be based on additional conditions or values ​​beyond the described values ​​in practice.

[0049] As used in the embodiments of the present application, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one of them. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, determined according to the actual process.

[0050] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the areas shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0052] The embodiment of the present application provides an electronic device. The electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device and / or a smart city device, etc. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.

[0053] Figure 1 This is a structural diagram of an electronic device provided in an embodiment of the present application. Figure 1 As shown, the electronic device 1000 includes: a memory 100, a processor 200, an input device 300, an output device 400 and other components. Those skilled in the art can understand that Figure 1The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device 1000. The electronic device 1000 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0054] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110 includes, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 120 includes, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a read-only memory, etc.

[0055] The processor 200 is the control center of the electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000. By running or executing software programs and / or modules stored in the memory 100, and calling data stored in the memory 100, it performs various functions of the electronic device 1000 and processes data, thereby monitoring the electronic device 1000 as a whole. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, and may also be other specific integrated circuits (application specific integrated circuits, ASICs), etc. Figure 1In the example, the processor 200 is a CPU, and the CPU may include an operator 210 and a controller 220. The operator 210 obtains data stored in the internal memory 120, processes the data stored in the internal memory 120, and generally sends the processed result back to the internal memory 120. The controller 220 may control the operator 210 to process the data, and the controller 220 may also control the external memory 110 and the internal memory 120 to store data or read data. The memory 100 may store data generated by the processor 200.

[0056] The input device 300 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device 1000. For example, the input device 300 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, a stylus, etc.), and drive the corresponding connection device according to a pre-set program. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the touch point coordinates, and then sends it to the processor 200, and can receive and execute the command sent by the processor 200. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic waves. Other input devices may include but are not limited to one or more of a physical keyboard, function keys (such as volume control keys, power switch keys, etc.), a trackball, a mouse, a joystick, etc. The controller 220 in the processor 200 can also control the input device 300 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 300, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 120.

[0057] The output device 400 is used to output a signal corresponding to the data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the processor 200 can also control the output device 400 to output a signal or not output a signal.

[0058] It should be noted that Figure 1The thick arrows in the figure are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 indicates that the data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the operator 210 and the internal memory 120 indicates that the data stored in the internal memory 120 can be transmitted to the operator 210, and the data processed by the operator 210 can be transmitted to the internal memory 120. Figure 1 The thin arrows in the figure represent components that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, and the like.

[0059] Optional, such as Figure 1 The electronic device 1000 shown may also include various sensors, such as a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which are not described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which are not described in detail here.

[0060] Figure 2 This is a partial structural diagram of an electronic device provided in an embodiment of the present application. Figure 2 As shown, the electronic device 1000 includes a circuit board 500 and an integrated circuit 600 . The integrated circuit 600 is disposed on the circuit board 500 and is electrically connected to the circuit board 500 .

[0061] like Figure 2 As shown, the electronic device 1000 further includes a connector disposed between the circuit board 500 and the integrated circuit 600, and the integrated circuit 600 is electrically connected to the circuit board 500 via the connector. The connector may be, for example, a ball grid array (BGA).

[0062] Optionally, other structures, such as a packaging substrate, may be provided between the connector and the circuit board 500. That is, the integrated circuit 600 may be packaged on the packaging substrate and then connected to the circuit board 500 via the packaging substrate.

[0063] The number of the integrated circuit 600 can be one or more. When the number of the integrated circuit 600 is more than one, the integrated circuits 600 can be arranged flat on the circuit board 500 or stacked on the circuit board 500.

[0064] The above-mentioned integrated circuit 600 can be a wafer or a chip. When the integrated circuit 600 is a chip, the chip can be a bare chip (also called a grain or particle) obtained by cutting the wafer, or it can be a packaged chip obtained by packaging the bare chip. Optionally, the above-mentioned integrated circuit 600 has a logic calculation function. In this case, the integrated circuit 600 can be applied to a logic device (such as the above-mentioned operator 210, controller 220, sensor, etc.); or, the above-mentioned integrated circuit 600 has a storage function. In this case, the integrated circuit 600 can also be applied to a storage device (such as the above-mentioned external memory 110, internal memory 120, etc.), which is not limited in this embodiment of the present application.

[0065] Some embodiments of the present application provide an integrated circuit and a method for manufacturing the same. The integrated circuit and the method for manufacturing the integrated circuit are schematically described below in conjunction with the accompanying drawings.

[0066] Figure 3 and Figure 8-Figure 12 The structures of an integrated circuit are respectively shown. Figure 4 Indicated Figure 3 The integrated circuit shown in FIG. is a cross-sectional structure along the CC direction. Figure 5a and Figure 5b They respectively indicated Figure 3 The integrated circuit shown in FIG. is a cross-sectional structure along the reference DD direction. Figure 6 Indicated Figure 3 The integrated circuit shown in FIG. is a cross-sectional structure along the reference EE direction. Figure 7 Indicated Figure 3 The integrated circuit shown in FIG. 1 is a cross-sectional structure along the reference FF direction.

[0067] Combination Figure 3-Figure 7 The integrated circuit 600 includes: a semiconductor structure 1, a first dielectric layer 2, a gate line 3, a first electrode 4, a second electrode 5, a second dielectric layer 6, and a power distribution network 7.

[0068] like Figure 3 , Figure 5a and Figure 5b As shown, the number of the semiconductor structures 1 can be multiple, and the multiple semiconductor structures 1 extend, for example, along the first direction X and are arranged at intervals along the second direction Y. Among the multiple semiconductor structures 1, along the second direction Y, the spacing between any two adjacent semiconductor structures 1 can be equal or unequal; along the second direction Y, the sizes of the semiconductor structures 1 can be the same or unequal; along the third direction Z, the sizes (also called heights) of the semiconductor structures 1 can be equal or unequal; the specific settings can be selected according to actual needs. Among them, any two of the first direction X, the second direction Y and the third direction Y are perpendicular to each other.

[0069] The number of semiconductor structures 1 can be selected and set according to actual needs, and the embodiment of the present application does not limit this, as long as it can meet the functional and structural requirements of the integrated circuit 600. For example, Figure 3 Four semiconductor structures 1 are schematically shown.

[0070] The semiconductor structure 1 can be arranged in a variety of ways, and can be selected according to actual needs. Figure 5a As shown, the semiconductor structure 1 is arranged in a fin shape. For another example, the semiconductor structure 1 is a nanosheet structure. Optionally, in the case where the semiconductor structure 1 is a nanosheet structure, the semiconductor structure 1 includes a plurality of nanosheets stacked at intervals along the third direction Z, and the plane where each nanosheet is located is parallel to the first direction X and the second direction Y.

[0071] like Figure 5a-Figure 7 As shown, the first dielectric layer 2 is located between any two adjacent semiconductor structures 1. Here, the first dielectric layer 2 can also be called a shallow trench isolation structure (STI), which is used to separate two adjacent semiconductor structures 1 to achieve isolation between adjacent devices. Figure 5a-Figure 7 In the embodiment, the lower surface of each semiconductor structure 1 is flush with the lower surface of the first dielectric layer 2. Optionally, the first dielectric layer 2 also covers each semiconductor structure 1.

[0072] like Figure 5a and Figure 5b As shown, the gate line 3 is located on the first dielectric layer 2 and straddles a plurality of semiconductor structures 1. For example, the number of semiconductor structures 1 straddled by the gate line 3 is three, six, eight or even more.

[0073] The number of gate lines 3 is multiple, and the multiple gate lines 3, for example, extend along the second direction Y and are arranged at intervals along the first direction X. Among the multiple gate lines 3, the spacing between any two adjacent gate lines 3 can be equal or unequal, and can be specifically selected and set according to actual needs. The number of semiconductor structures 1 spanned by different gate lines 3 can be equal or unequal, and can be specifically selected and set according to actual needs. The number of gate lines 3 can be selected and set according to actual needs, and the embodiments of the present application do not limit this, as long as it can meet the functional and structural requirements of the integrated circuit 600. For example, Figure 3 Two grid lines 3 are shown schematically, Figure 8 Four gate lines 3 are schematically shown, wherein each gate line 3 is arranged across four semiconductor structures 1 .

[0074] Combination Figure 3 , Figure 6 and Figure 7, the first electrode 4 and the second electrode 5 are both in contact with the semiconductor structure 1, and along the first direction X, the first electrode 4 and the second electrode 5 are located on opposite sides of the gate line 3. Exemplarily, the first electrode 4 and the second electrode 5 can be formed on the semiconductor structure 1 by an epitaxial process. One of the first electrode 4 and the second electrode 5 can be a source electrode, and the other can be a drain electrode, which can be selected and set according to actual needs. Optionally, the first electrode 4 is a source electrode, and the second electrode 5 is a drain electrode.

[0075] There are many ways to set the first electrode 4 and the second electrode 5 and the semiconductor structure 1, which can be selected according to actual needs. Figure 3 , Figure 6 and Figure 7 The semiconductor structure 1 is in the shape of a long strip, and a plurality of gate lines 3 are arranged across each semiconductor structure 1, and the first pole 4 and the second pole 5 are both located on the semiconductor structure 1; for another example, a gate line 3 is arranged across each semiconductor structure 1, and along the first direction X, a plurality of semiconductor structures 1 are arranged at intervals, and a first pole 4 or a second pole 5 is arranged between two adjacent semiconductor structures 1.

[0076] Combination Figure 5a , Figure 6 and Figure 7 , the portion of the gate line 3 that crosses the semiconductor structure 1 is used to form a gate, the portion of the semiconductor structure 1 covered by the gate line 3 is used to form a channel, and the gate, the channel, and the first electrode 4 and the second electrode 5 located on both sides of the gate are used to form a transistor. When the semiconductor structure 1 is arranged in a fin shape, the transistor can be a fin field effect transistor; when the semiconductor structure 1 is a nanosheet structure, the transistor can be a surround gate field effect transistor (also called a ring gate nanosheet structure field effect transistor). In other words, the same gate line 3 and the multiple semiconductor structures 1 it crosses can constitute multiple transistors, and the gate line 3 can simultaneously control the conduction or cutoff of the multiple transistors.

[0077] like Figure 3 As shown, the second dielectric layer 6 is located on the first dielectric layer 2 and is arranged across multiple semiconductor structures 1. There are multiple second dielectric layers 6, and the multiple second dielectric layers 6 extend, for example, along the second direction Y and are arranged at intervals along the first direction X. Along the first direction X, the second dielectric layers 6 and the gate lines 3 are alternately arranged. In this way, it is convenient to use the second dielectric layer 6 to isolate adjacent gate lines 3.

[0078] like Figure 5a and Figure 5bAs shown, the power distribution network 7 has a first surface B1, which is, for example, a plane. The semiconductor structure 1 and the first dielectric layer 2 are located on the first surface B1 and in contact with the first surface B1. The first direction X and the second direction Y are both parallel to the first surface B1, and the third direction Y is perpendicular to the first surface B1. When a plurality of semiconductor structures 1 are arranged at intervals and a first pole 4 or a second pole 5 is arranged between two adjacent semiconductor structures 1, the first pole 4 and the second pole 5 are also located on the first surface B1 and in contact with the first surface B1.

[0079] The power distribution network 7 includes a plurality of fourth dielectric layers spaced apart along the third direction Z, and a first metal wiring layer between two adjacent fourth dielectric layers. The metal wirings in different first metal wiring layers can be connected through through holes in the fourth dielectric layer. The power distribution network 7 includes, for example, a power supply (VSS or VDD, etc.), a ground, and other components. The power distribution network 7 can, for example, be electrically connected to the first electrode 4 of the transistor disposed on the first surface B1 to provide an operating voltage, etc., for the transistor.

[0080] In a possible implementation, a power connection structure is provided in the integrated circuit to connect the power distribution network 7 and the first electrode 4 of the transistor. In the process of forming the power connection structure, a deep hole penetrating the gate line 3 and the first dielectric layer 2 is first etched between the two adjacent semiconductor structures; then an insulating material is filled in the deep hole to form an insulating layer; then a power via is formed in the insulating layer, and a conductive material is filled in the power via to obtain the power connection structure.

[0081] However, the alignment, photolithography, etching and other processes required to form the electrical vias in the above-mentioned insulating layer are difficult. Moreover, when the alignment, photolithography, etching and other processes are deviated, the size of the electrical vias and the spacing between the electrical vias and the gate line 3 are affected, which may easily lead to a short circuit between the power supply connection structure and the gate line 3, or the power supply connection structure and the gate line 3 may be broken down due to insufficient insulation distance. This reduces the reliability of the integrated circuit.

[0082] Based on this, continue to refer to Figure 3 The integrated circuit 600 provided in the embodiment of the present application further includes: a first electrode contact portion 8, a second electrode contact portion 9, a power supply connection portion 10 and an isolation layer 11.

[0083] like Figure 3 , Figure 5a and Figure 5bAs shown, the power connection part 10 is located between two adjacent semiconductor structures 1. The power connection part 10 passes through the gate line 3 and the first dielectric layer 2, and divides the gate line 3 into a first sub-gate line 31 and a second sub-gate line 32. The power connection part 10 extends along the first direction X, and the orthographic projection of the power connection part 10 on the first surface B1 is in the shape of a strip. The power connection part 10 can divide a plurality of gate lines 3. Among them, the number of gate lines 3 divided by the power connection part 10 can be two, three, four or even more. For example, in Figure 3 In the example, the power supply connecting portion 10 separates two gate lines 3; Fig.10 In the example, the power supply connecting portion 10 blocks four gate lines 3; Figure 8 In the embodiment, the power supply connection portion 10 blocks at least four gate lines 3 .

[0084] The power connection part 10 is in contact with the power distribution network 7 (e.g., directly in contact) to form an electrical connection. The operating voltage provided by the power distribution network 7 can be transmitted to the power connection part 10. By setting the structure of the power connection part 10 as a strip structure, it is beneficial to reduce the resistance of the power connection part 10, reduce the voltage drop, and improve the accuracy of the operating voltage transmitted by it.

[0085] like Figure 3 and Figure 8 As shown, the first electrode contact portion 8 and the second electrode contact portion 9 are respectively located on opposite sides of the power supply connecting portion 10 along the second direction Y. For example, Figure 3 and Figure 8 In the embodiment, along the second direction Y, the first electrode contact portion 8 is located on the upper side of the power supply connecting portion 10 , and the second electrode contact portion 9 is located on the lower side of the power supply connecting portion 10 .

[0086] The first electrode contact portion 8 and the second electrode contact portion 9 are located on different first electrodes 4 and are in contact with the corresponding first electrodes 4 .

[0087] For example, combined with Figure 3 and Figure 6 The first electrode contact portion 8 penetrates the second dielectric layer 6 to the first electrode 4 located on the upper side of the power supply connection portion 10. The first electrode contact portion 8 is in contact with the first electrode 4 (e.g., directly in contact). The number of first electrodes 4 contacted by the same first electrode contact portion 8 can be multiple, which can be specifically set according to actual product requirements. For example, Figure 3 and Figure 6 In the embodiment, the number of first electrodes 4 contacting the same first electrode contact portion 8 is two.

[0088] The first electrode contact portion 8 extends along the second direction Y. Along the first direction X, the first electrode contact portion 8 is located on one side of the gate line 3. Figure 3 In the embodiment, the first electrode contact portion 8 is located on the left side of the gate line 3 .

[0089] For example, combined with Figure 3 and Figure 6 The second electrode contact portion 9 penetrates the second dielectric layer 6 to the first electrode 4 located at the lower side of the power supply connection portion 10. The second electrode contact portion 9 is in contact with the first electrode 4 (e.g., directly in contact). The number of first electrodes 4 contacted by the same second electrode contact portion 9 can be multiple, which can be set according to actual product requirements. For example, Figure 3 and Figure 6 In the embodiment, the number of first electrodes 4 contacting the same second electrode contact portion 9 is two.

[0090] The second electrode contact portion 9 extends along the second direction Y. Along the first direction X, the second electrode contact portion 9 is located on one side of the gate line 3. Figure 3 In the embodiment, the second electrode contact portion 9 is located on the left side of the gate line 3. The first electrode contact portion 8 and the second electrode contact portion 9 may be located on the same side of the gate line 3, or may be located on different sides of the gate line 3.

[0091] Exemplarily, the transistor corresponding to the first pole 4 contacted by the first electrode contact portion 8 is used to constitute a standard unit (or logic unit); the transistor corresponding to the first pole 4 contacted by the second electrode contact portion 9 is used to constitute a standard unit. These two standard units are different standard units. Correspondingly, it can also be considered that the power supply connection portion 10 is located between two adjacent standard units. Among them, the transistor corresponding to the first pole 4 contacted by the first electrode contact portion 8 and the transistor corresponding to the first pole 4 contacted by the second electrode contact portion 9 can both be N-type transistors or P-type transistors.

[0092] like Figure 3 , Figure 5a and Figure 5b As shown, the isolation layer 11 is at least located at the opposite sides of the power supply connection part 10 along the second direction Y, separating the power supply connection part 10 and the first sub-grid line 31 and the second sub-grid line 32. The material of the isolation layer 11 includes a dielectric material to realize the electrical insulation between the power supply connection part 10 and the first sub-grid line 31, and realizes the electrical insulation between the power supply connection part 10 and the second sub-grid line 32. The dielectric material includes but is not limited to one or more of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiNC), and silicon oxynitride (SiNO). The isolation layer 11 can be a structure consisting of a single-layer film, or a structure consisting of a multi-layer film stack.

[0093] The power supply connection portion 10 also penetrates the isolation layer 11 and contacts the first electrode contact portion 8 and / or the second electrode contact portion 9. Figure 8 and Fig. 9As shown, the power supply connection portion 10 can penetrate the isolation layer 11 and contact (for example, directly contact) the first electrode contact portion 8 to form an electrical connection. At this time, the operating voltage provided by the power distribution network 7 can be transmitted to the first electrode 4 electrically connected to the first electrode contact portion 8 through the power supply connection portion 10 and the first electrode contact portion 8 in sequence. Or, as Fig.10 As shown, the power supply connection portion 10 can penetrate the isolation layer 11 and contact (for example, directly contact) the second electrode contact portion 9 to form an electrical connection. At this time, the operating voltage provided by the power distribution network 7 can be transmitted to the first electrode 4 electrically connected to the second electrode contact portion 9 through the power supply connection portion 10 and the second electrode contact portion 9 in sequence. Alternatively, as Figure 3 , Fig.11 and Fig.12 As shown, the power supply connection part 10 can penetrate the isolation layer 11 and contact the first electrode contact part 8 and the second electrode contact part 9 to form an electrical connection. At this time, the operating voltage provided by the power distribution network 7 can be transmitted to the first pole 4 electrically connected to the first electrode contact part 8 and the first pole 4 electrically connected to the second electrode contact part 9 through the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9. Among them, the connection relationship between the power supply connection part 10 and the first electrode contact part 8 and the second electrode contact part 9 can be determined according to actual product requirements, and the embodiment of the present application does not limit this.

[0094] The positional relationship between the isolation layer 11 and the power supply connection portion 10 is related to the connection relationship between the power supply connection portion 10 , the first electrode contact portion 8 , and the second electrode contact portion 9 .

[0095] Alternatively, if Figure 3 , Fig.11 and Fig.12 As shown, the power supply connection portion 10 is in contact with the first electrode contact portion 8 and the second electrode contact portion 9 at the same time. At this time, at least one opening K is provided in the isolation layer 11. For example, Fig.12 In the embodiment, an opening K is provided in the isolation layer 11, and the opening K is located, for example, Fig.12 As shown in FIG. 1 , a portion of the power supply connecting portion 10 extends into the opening K to form an electrical connection with the first electrode contact portion 8 and the second electrode contact portion 9. Alternatively, as shown in FIG. Figure 3 and Fig.11As shown, two openings K are provided in the isolation layer 11, one of which is located on the side of the power supply connection part 10 close to the first electrode contact part 8, and a part of the power supply connection part 10 extends into the opening K to form an electrical connection with the first electrode contact part 8; the other opening K is located on the side of the power supply connection part 10 close to the second electrode contact part 9, and a part of the power supply connection part 10 extends into the opening K to form an electrical connection with the second electrode contact part 9. In the third direction Z, the size of the opening K is less than or equal to the size of the isolation layer 11. The orthographic projection of the isolation layer 11 on the first surface B1 is, for example, an open ring, or two U-shaped figures arranged opposite to each other, arranged around the power supply connection part 10.

[0096] Alternatively, if Figure 8 and Fig. 9 As shown, the power supply connection part 10 is in contact with the first electrode contact part 8. At this time, an opening K is provided in the isolation layer 11, and the opening K is located on the side of the power supply connection part 10 close to the first electrode contact part 8, and a part of the power supply connection part 10 extends into the opening K to form an electrical connection with the first electrode contact part 8. In the third direction Z, the size of the opening K is less than or equal to the size of the isolation layer 11. The orthographic projection of the isolation layer 11 on the first surface B1 is, for example, an open ring, and is arranged around the power supply connection part 10.

[0097] Alternatively, if Fig.10 As shown, the power supply connection part 10 is in contact with the second electrode contact part 9. At this time, an opening K is provided in the isolation layer 11, and the opening K is located on the side of the power supply connection part 10 close to the second electrode contact part 9, and a part of the power supply connection part 10 extends into the opening K to form an electrical connection with the second electrode contact part 9. In the third direction Z, the size of the opening K is less than or equal to the size of the isolation layer 11. The orthographic projection of the isolation layer 11 on the first surface B1 is, for example, an open ring, and is arranged around the power supply connection part 10.

[0098] It can be understood that the isolation layer 11 is used to provide a self-alignment effect for the power connection part 10. In this way, after etching a groove penetrating the gate line 3 and the first dielectric layer 2 between two adjacent semiconductor structures 1, the isolation layer 11 can be formed in the groove first, and then the power connection part 10 can be formed in the groove. The material of the power connection part 10 can be naturally filled in the area defined by the isolation layer 11 based on the self-alignment effect provided by the isolation layer 11. In this way, there is no need to form an insulating layer in the groove, nor is there a need to form an electrical via in the insulating layer, and the problem of greater process difficulty caused by etching the electrical via can be avoided.

[0099] Moreover, the isolation layer 11 has a certain thickness, and the thickness is relatively uniform. The embodiment of the present application adopts the isolation layer 11 to replace the above-mentioned insulating layer, so as to utilize the isolation layer 11 to realize the electrical insulation between the power supply communication part 10 and the first sub-grid line 31, and realize the electrical insulation between the power supply communication part 10 and the second sub-grid line 32, so that the power supply communication part 10 and the first sub-grid line 31 have enough insulation distances, so that the power supply communication part 10 and the second sub-grid line 32 have enough insulation distances, and then the risk of short circuit and breakdown between the power supply communication part 10 and the first sub-grid line 31 and the power supply communication part 10 and the second sub-grid line 32 can be reduced, the breakdown voltage between the power supply communication part 10 and the first sub-grid line 31 and the power supply communication part 10 and the second sub-grid line 32 is improved, and the reliability of the integrated circuit 600 is improved.

[0100] In some examples, such as Figure 5a and Figure 5b As shown, the side surface of the isolation layer 11 close to the power distribution network 7 is flush with the side surface of the power connection part 10 close to the power distribution network 7. The end of the power connection part 10 close to the power distribution network 7 does not protrude from the isolation layer 11, nor does it retract into the isolation layer 11.

[0101] In this way, the power connection portion 10 can be formed in one step, and the isolation layer 11 can be avoided from being etched during the formation of the power connection portion 10 , which is beneficial to simplifying the preparation process of the integrated circuit 600 and improving the preparation efficiency of the integrated circuit 600 .

[0102] Furthermore, if Figure 5a and Figure 5b As shown, the side surface of the isolation layer 11 away from the power distribution network 7 is flush with the side surface of the power supply connection part 10 away from the power distribution network 7. Accordingly, along the third direction Z, the maximum size of the isolation layer 11 is equal to the maximum size of the power supply connection part 10. The cross-sectional shape of the power supply connection part 10 can be a rectangle (such as Figure 5a As shown), it can also be an inverted trapezoid (as shown Figure 5b The cross section is perpendicular to the first direction X.

[0103] In some embodiments, Figure 3 , Figure 8-Figure 11 As shown, the first electrode contact portion 8, the second electrode contact portion 9 and the power supply connecting portion 10 are arranged in the same layer.

[0104] The "same layer" mentioned in this article refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using a single patterning process. Depending on the specific pattern, a single patterning process may include multiple etching processes or grinding processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0105] That is to say, the first electrode contact portion 8, the second electrode contact portion 9 and the power supply connection portion 10 are formed by patterning the same thin film. Accordingly, the first electrode contact portion 8, the second electrode contact portion 9 and the power supply connection portion 10 are made of the same material and have the same structure. In this way, the first electrode contact portion 8, the second electrode contact portion 9 and the power supply connection portion 10 can be formed simultaneously in the same patterning process, which is conducive to simplifying the preparation process of the integrated circuit 600.

[0106] Alternatively, if Figure 8 and Fig. 9 As shown, when the power supply connection part 10 is in contact with the first electrode contact part 8, the power supply connection part 10 and the first electrode contact part 8 are in an integral structure. That is, the power supply connection part 10 and the first electrode contact part 8 are integrally formed, and the power supply connection part 10 and the first electrode contact part 8 are continuous, and there is no interface between the two.

[0107] This can improve the structural stability and electrical connection reliability between the power connection part 10 and the first electrode contact part 8, avoid affecting the transmission of electrical signals between the power connection part 10 and the first electrode contact part 8, and also help reduce the difficulty of preparing and forming the power connection part 10 and the first electrode contact part 8.

[0108] Alternatively, if Fig.10 As shown, when the power supply connection part 10 is in contact with the second electrode contact part 9, the power supply connection part 10 and the second electrode contact part 9 are in an integrated structure. That is, the power supply connection part 10 and the second electrode contact part 9 are integrally formed, and the power supply connection part 10 and the second electrode contact part 9 are continuous, and there is no interface between the two.

[0109] This can improve the structural stability and electrical connection reliability between the power connection part 10 and the second electrode contact part 9, avoid affecting the transmission of electrical signals between the power connection part 10 and the second electrode contact part 9, and also help reduce the difficulty of preparing and forming the power connection part 10 and the second electrode contact part 9.

[0110] Alternatively, if Figure 3 and Fig.11As shown, when the power supply connection part 10 is in contact with the first electrode contact part 8 and the second electrode contact part 9 at the same time, the power supply connection part 10 is an integral structure with the first electrode contact part 8 and the second electrode contact part 9. That is, the power supply connection part 10 is integrally formed with the first electrode contact part 8 and the second electrode contact part 9, the power supply connection part 10 is continuous with the first electrode contact part 8 and the second electrode contact part 9, there is no interface between the power supply connection part 10 and the first electrode contact part 8, and there is no interface between the power supply connection part 10 and the second electrode contact part 9.

[0111] This can improve the structural stability and electrical connection reliability between the power connecting part 10 and the first electrode contact part 8, the second electrode contact part 9, avoid affecting the transmission of electrical signals between the power connecting part 10 and the first electrode contact part 8, the second electrode contact part 9, and also help reduce the difficulty of preparing and forming the power connecting part 10 and the first electrode contact part 8, the second electrode contact part 9.

[0112] The structures of the first electrode contact portion 8 include various ones, which can be selected and set according to actual needs.

[0113] In some examples, such as Figure 3 and Figure 8 As shown, the first electrode contact portion 8 is composed of a single-layer film. At this time, the material of the first electrode contact portion 8 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc.

[0114] In other examples, the first electrode contact portion 8 is formed by stacking multiple thin films. Figure 9-12 As shown, the first electrode contact portion 8 includes a first conductive layer 81 and a first barrier layer 82. The first barrier layer 82 is arranged around the first conductive layer 81. At this time, the material of the first conductive layer 81 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc. The material of the first barrier layer 82 includes but is not limited to one or more of titanium, titanium nitride, tantalum, tantalum nitride, etc. In this way, the first conductive layer 81 can be used to reduce the contact resistance of the first electrode contact portion 8 and the structure electrically connected thereto (such as the power supply connection portion 10), and the first barrier layer 82 can be used to improve the adhesion between the first electrode contact portion 8 and the dielectric layer (such as the second dielectric layer 6) surrounding it.

[0115] The second electrode contact portion 9 may have various structures, which may be selected according to actual needs.

[0116] In some examples, such as Figure 3 and Figure 8As shown, the second electrode contact portion 9 is composed of a single-layer film. At this time, the material of the second electrode contact portion 9 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc.

[0117] In other examples, the second electrode contact portion 9 is formed by stacking multiple thin films. Figure 9-12 As shown, the second electrode contact portion 9 includes a third conductive layer 91 and a third barrier layer 92. The third barrier layer 92 is arranged around the third conductive layer 91. At this time, the material of the third conductive layer 91 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc. The material of the third barrier layer 92 includes but is not limited to one or more of titanium, titanium nitride, tantalum, tantalum nitride, etc. In this way, the third conductive layer 91 can be used to reduce the contact resistance between the second electrode contact portion 9 and the structure electrically connected thereto (such as the power supply connection portion 10), and the third barrier layer 92 can be used to improve the adhesion between the second electrode contact portion 9 and the dielectric layer (such as the second dielectric layer 6) surrounding it.

[0118] The structure of the first electrode contact portion 8 and the structure of the second electrode contact portion 9 may be the same or different. When the structure of the first electrode contact portion 8 and the structure of the second electrode contact portion 9 are the same, the material of the first electrode contact portion 8 and the material of the second electrode contact portion 9 may be the same or different.

[0119] The power supply connection portion 10 may have various structures, which may be selected according to actual needs.

[0120] In some examples, such as Figure 3 and Figure 8 As shown, the power supply connection part 10 is composed of a single-layer film. At this time, the material of the power supply connection part 10 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc.

[0121] In other examples, the power supply connection portion 10 is formed by stacking multiple layers of thin films. Figure 9-12As shown, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102. The second barrier layer 102 is arranged around the second conductive layer 101. At this time, the material of the second conductive layer 101 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc. The material of the second barrier layer 102 is one or more of titanium, titanium nitride, tantalum, tantalum nitride, etc. In this way, the second conductive layer 101 can be used to reduce the contact resistance between the power supply connection part 10 and the structure electrically connected thereto (such as the power distribution network 7, the first electrode contact part 8, and the second electrode contact part 9), and the second barrier layer 102 can be used to improve the adhesion between the power supply connection part 10 and the dielectric layer (such as the isolation layer 11) surrounding it.

[0122] The structure of the power supply connection part 10 may be the same as or different from the structure of the first electrode contact part 8 and the second electrode contact part 9. When the structure of the power supply connection part 10 is the same as the structure of the first electrode contact part 8 and the second electrode contact part 9, the material of the power supply connection part 10 may be the same as or different from the material of the first electrode contact part 8 and the second electrode contact part 9.

[0123] It is understandable that there are multiple combinations of the structure of the power supply connection portion 10, the structure of the first electrode contact portion 8, and the structure of the second electrode contact portion 9. The multiple combinations are schematically described below in conjunction with the accompanying drawings.

[0124] In some examples, the power supply connection part 10 contacts the first electrode contact part 8. In this case, the combination of the structure of the power supply connection part 10 and the structure of the first electrode contact part 8 is as follows.

[0125] Alternatively, if Figure 8 As shown, the power supply connection part 10 and the first electrode contact part 8 are both made of a single-layer film. The power supply connection part 10 and the first electrode contact part 8 are in direct contact. The power supply connection part 10 and the first electrode contact part 8 are, for example, an integral structure.

[0126] Alternatively, if Fig. 9As shown, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102, and the first electrode contact part 8 includes a first conductive layer 81 and a first barrier layer 82. Among them, the second conductive layer 101 and the first conductive layer 81 are, for example, connected (or directly contacted) and are an integral structure. That is, the second conductive layer 101 and the first conductive layer 81 are integrally formed, and there is no interface between the two. Further, the second barrier layer 102 and the first barrier layer 82 are, for example, connected (or directly contacted) and are an integral structure. That is, the second barrier layer 102 and the first barrier layer 82 are integrally formed, and there is no interface between the two. Accordingly, the orthographic projections of the second barrier layer 102 and the first barrier layer 82 on the first surface B1 are closed figures, and the second barrier layer 102 and the first barrier layer 82 jointly surround the second conductive layer 101 and the first conductive layer 81.

[0127] Optionally, the power supply connection part 10 is composed of a single-layer film, and the first electrode contact part 8 includes a first conductive layer 81 and a first barrier layer 82, wherein the first barrier layer 82 is annular and surrounds the first conductive layer 81. The first electrode contact part 8 is in direct contact with the power supply connection part 10 through the first conductive layer 81.

[0128] Optionally, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102, wherein the second barrier layer 102 is annular and surrounds the second conductive layer 101. The first electrode contact part 8 is composed of a single-layer film and is in direct contact with the second barrier layer 102 of the power supply connection part 10.

[0129] In other examples, the power supply connection part 10 contacts the second electrode contact part 9. In this case, the combination of the structure of the power supply connection part 10 and the structure of the second electrode contact part 9 is as follows.

[0130] Optionally, the power supply connection part 10 and the second electrode contact part 9 are both made of a single-layer film. The power supply connection part 10 is in direct contact with the second electrode contact part 9. The power supply connection part 10 and the second electrode contact part 9 are, for example, an integral structure.

[0131] Alternatively, if Fig.10As shown, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102, and the second electrode contact part 9 includes a third conductive layer 91 and a third barrier layer 92. Among them, the second conductive layer 101 and the third conductive layer 91 are, for example, connected (or directly contacted) and are in an integral structure. That is, the second conductive layer 101 and the third conductive layer 91 are integrally formed, and there is no interface between the two. Further, the second barrier layer 102 and the third conductive layer 91 are, for example, connected (or directly contacted) and are in an integral structure. That is, the second barrier layer 102 and the third barrier layer 92 are integrally formed, and there is no interface between the two. Accordingly, the orthographic projections of the second barrier layer 102 and the third barrier layer 92 on the first surface B1 are closed figures, and the second barrier layer 102 and the third barrier layer 92 jointly surround the second conductive layer 101 and the third conductive layer 91.

[0132] Optionally, the power supply connection part 10 is composed of a single-layer film, and the second electrode contact part 9 includes a third conductive layer 91 and a third barrier layer 92, wherein the third barrier layer 92 is annular and surrounds the third conductive layer 91. The second electrode contact part 9 is in direct contact with the power supply connection part 10 through the third conductive layer 91.

[0133] Optionally, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102, wherein the second barrier layer 102 is annular and surrounds the second conductive layer 101. The second electrode contact part 9 is composed of a single-layer film and is in direct contact with the second barrier layer 102 of the power supply connection part 10.

[0134] In some other examples, the power supply connection portion 10 is in contact with the first electrode contact portion 8 and the second electrode contact portion 9 at the same time. Figure 3 and Fig.11 As shown in FIG. 1 , along the second direction Y, the first electrode contact portion 8 and the second electrode contact portion 9 are located on opposite sides of the power supply connecting portion 10. Alternatively, as shown in FIG. Fig.12 As shown, the first electrode contact portion 8 and the second electrode contact portion 9 are connected to form an integral structure; the power supply connecting portion 10 and the isolation layer 11 are located on one side of the first electrode contact portion 8 along the first direction X.

[0135] In this case, the structure of the power supply connection portion 10 and the structures of the first electrode contact portion 8 and the second electrode contact portion 9 can be combined in various ways. Of course, the combination is not limited to the following examples.

[0136] Alternatively, if Figure 3 As shown, the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 are all made of a single-layer film. The power supply connection part 10 is in direct contact with the first electrode contact part 8 and the second electrode contact part 9, and the three are in an integrated structure.

[0137] Alternatively, if Fig.11As shown, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102, the first electrode contact part 8 includes a first conductive layer 81 and a first barrier layer 82, and the second electrode contact part 9 includes a third conductive layer 91 and a third barrier layer 92. Among them, the first conductive layer 81, the second conductive layer 101 and the third conductive layer 91 are connected (or directly contacted), and the three are in an integrated structure. That is, the first conductive layer 81, the second conductive layer 101 and the third conductive layer 91 are integrally formed, and there is no interface between the three. Further, the first barrier layer 82, the second barrier layer 102 and the third barrier layer 92 are connected (or directly contacted), and the three are in an integrated structure. Accordingly, the orthographic projection of the first barrier layer 82, the second barrier layer 102 and the third barrier layer 92 on the first surface B1 is a closed figure, and the first barrier layer 82, the second barrier layer 102 and the third barrier layer 92 surround the first conductive layer 81, the second conductive layer 101 and the third conductive layer 91 together.

[0138] Alternatively, if Fig.12 As shown, the power supply connection part 10 includes a second conductive layer 101 and a second barrier layer 102, and the second barrier layer 102 surrounds the second conductive layer 101. The first electrode contact part 8 includes a first conductive layer 81 and a first barrier layer 82, and the second electrode contact part 9 includes a third conductive layer 91 and a third barrier layer 92. The first conductive layer 81 and the third conductive layer 91 are connected and form an integral structure, the first barrier layer 82 and the third barrier layer 92 are connected and form an integral structure, and the first barrier layer 82 and the third barrier layer 92 surround the first conductive layer 81 and the third conductive layer 91 together. The second barrier layer 102 of the power supply connection part 10 is in direct contact with the first barrier layer 82 and the third barrier layer 92.

[0139] Optionally, the power supply connection portion 10 includes a second conductive layer 101 and a second barrier layer 102, and the second barrier layer 102 surrounds the second conductive layer 101. The first electrode contact portion 8 includes a first conductive layer 81 and a first barrier layer 82, and the first barrier layer 82 surrounds the first conductive layer 81. The first electrode contact portion 8 is in direct contact with the second barrier layer 102 of the power supply connection portion 10 through the first barrier layer 82. The second electrode contact portion 9 includes a third conductive layer 91 and a third barrier layer 92, and the third barrier layer 92 surrounds the third conductive layer 91. The second electrode contact portion 9 is in direct contact with the second barrier layer 102 of the power supply connection portion 10 through the third barrier layer 92.

[0140] Of course, among the power connection part 10, the first electrode contact part 8 and the second electrode contact part 9, at least one can be composed of a single-layer film, and at least one can be composed of a plurality of layers of thin films stacked together. For details, please refer to the relevant descriptions of the contact between the power connection part 10 and the first electrode contact part 8, and the contact between the power connection part 10 and the second electrode contact part 9 in the above text, which will not be repeated here.

[0141] In some embodiments, in combination Figure 3 and Figure 7 The integrated circuit 600 provided in the embodiment of the present application further includes: a third electrode contact portion 12 , a fourth electrode contact portion 13 and an interconnection layer 14 .

[0142] like Figure 3 and Figure 7 As shown, the third electrode contact portion 12 and the fourth electrode contact portion 13 are respectively located on opposite sides of the power supply connecting portion 10 along the second direction Y. The isolation layer 11 also separates the power supply contact portion 10 from the third electrode contact portion 12, and separates the power supply contact portion 10 from the fourth electrode contact portion 13. For example, in Figure 3 In the embodiment, along the second direction Y, the third electrode contact portion 12 is located on the upper side of the power supply connecting portion 10 , and the fourth electrode contact portion 13 is located on the lower side of the power supply connecting portion 10 .

[0143] The third electrode contact portion 12 and the fourth electrode contact portion 13 are located on different second electrodes 5 and are in contact with the corresponding second electrodes 5 .

[0144] For example, combined with Figure 3 and Figure 7 The third electrode contact portion 12 penetrates the second dielectric layer 6 to the second electrode 5 located on the upper side of the power supply connection portion 10. The third electrode contact portion 12 is in contact with the second electrode 5 (for example, directly in contact). The number of second electrodes 5 contacted by the same third electrode contact portion 12 can be multiple, which can be set according to actual product requirements. For example, Figure 7 In the embodiment, the number of the second electrodes 5 contacting the same third electrode contact portion 12 is two.

[0145] The third electrode contact portion 12 extends along the second direction Y. Along the first direction X, the third electrode contact portion 12 and the first electrode contact portion 8 are located at two opposite sides of the gate line 3 .

[0146] For example, combined with Figure 3 and Figure 7 The fourth electrode contact portion 13 penetrates the second dielectric layer 6 to the second electrode 5 located at the lower side of the power supply connection portion 10. The fourth electrode contact portion 13 contacts the second electrode 5 (for example, directly contacts). The number of second electrodes 5 contacted by the same fourth electrode contact portion 13 can be multiple, which can be set according to actual product requirements. For example, Figure 7 In the embodiment, the number of the second electrodes 5 contacting the same fourth electrode contact portion 13 is two.

[0147] The fourth electrode contact portion 13 extends along the second direction Y. Along the first direction X, the fourth electrode contact portion 13 and the second electrode contact portion 9 are located at two opposite sides of the gate line 3 .

[0148] The interconnection layer 14 includes a plurality of fifth dielectric layers spaced apart along the third direction Z, and a second metal wiring layer located between two adjacent fifth dielectric layers. The metal wirings in different second metal wiring layers can be connected through the through holes in the fifth dielectric layer. Figure 7 As shown, the interconnection layer 14 is located on the third electrode contact portion 12 and the fourth electrode contact portion 13, and the metal wiring in the interconnection layer 14 is electrically connected to the third electrode contact portion 12 and the fourth electrode contact portion 13. The third electrode contact portion 12 and the fourth electrode contact portion 13 can receive electrical signals from the interconnection layer 14.

[0149] By providing the interconnection layer 14 , the interconnection of various elements (such as transistors, capacitors, resistors, etc.) on the power distribution network 7 can be achieved.

[0150] The third electrode contact portion 12 may have various structures, which may be selected according to actual needs.

[0151] In some examples, such as Figure 3 As shown, the third electrode contact portion 12 is composed of a single-layer film. At this time, the material of the third electrode contact portion 12 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc.

[0152] In other examples, such as Fig. 9 As shown, the third electrode contact portion 12 is composed of a plurality of thin film stacks. Exemplarily, the third electrode contact portion 12 includes a fourth conductive layer and a fourth barrier layer. The fourth barrier layer is arranged around the fourth conductive layer. At this time, the material of the fourth conductive layer includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc. The material of the fourth barrier layer includes but is not limited to one or more of titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0153] The fourth electrode contact portion 13 may have various structures, which may be selected according to actual needs.

[0154] In some examples, such as Figure 3 As shown, the fourth electrode contact portion 13 is composed of a single-layer film. At this time, the material of the fourth electrode contact portion 13 includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc.

[0155] In other examples, such as Fig. 9As shown, the fourth electrode contact portion 13 is composed of a multi-layer thin film stack. Exemplarily, the fourth electrode contact portion 13 includes a fifth conductive layer and a fifth barrier layer. The fifth barrier layer is arranged around the fifth conductive layer. At this time, the material of the fifth conductive layer includes a conductive material. For example, the conductive material includes but is not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc. The material of the fifth barrier layer includes but is not limited to one or more of titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0156] The structure of the third electrode contact portion 12 and the structure of the fourth electrode contact portion 13 may be the same or different. The material of the third electrode contact portion 12 and the material of the fourth electrode contact portion 13 may be the same or different.

[0157] Further, the structure of any one of the third electrode contact portion 12 and the fourth electrode contact portion 13, and the structure of any one of the first electrode contact portion 8 and the second electrode contact portion 9 may be the same or different. The material of any one of the third electrode contact portion 12 and the fourth electrode contact portion 13, and the material of any one of the first electrode contact portion 8 and the second electrode contact portion 9 may be the same or different.

[0158] In some examples, such as Figure 3 and Fig. 9 As shown, the third electrode contact portion 12, the fourth electrode contact portion 13 and the power supply connecting portion 10 are arranged in the same layer.

[0159] That is to say, the third electrode contact portion 12, the fourth electrode contact portion 13 and the power supply connection portion 10 are formed by patterning the same thin film. Accordingly, the third electrode contact portion 12, the fourth electrode contact portion 13 and the power supply connection portion 10 are made of the same material and have the same structure. In this way, the third electrode contact portion 12 and the power supply connection portion 10 can be formed simultaneously in the same patterning process, which is conducive to simplifying the preparation process of the integrated circuit 600.

[0160] Furthermore, the first electrode contact portion 8 , the second electrode contact portion 9 , the third electrode contact portion 12 , the fourth electrode contact portion 13 and the power supply connecting portion 10 are arranged in the same layer.

[0161] In some embodiments, Figure 3 As shown, the integrated circuit 600 provided in the embodiment of the present application further includes: at least two dummy gate lines 15. The dummy gate lines 15 are located on the first dielectric layer 2 and are arranged across multiple semiconductor structures 1. The number of semiconductor structures 1 across which the dummy gate lines 15 are arranged and the number of semiconductor structures 1 across which the gate lines 3 are arranged may be the same or different.

[0162] The at least two dummy gate lines 15 extend, for example, along the second direction Y and are arranged at intervals along the first direction X. Among the at least two dummy gate lines 15, at least two gate lines 3 are arranged between two adjacent dummy gate lines 15, and the at least two gate lines 3 are separated by the power supply connecting portion 10. Figure 3 As shown, the power supply connection portion 10 also blocks the dummy gate line 15 .

[0163] Optionally, the material of the dummy gate line 15 is the same as that of the gate line 3. The dummy gate line 15 is, for example, located in a dummy area that does not constitute a logic circuit, and the transistor located in the dummy area can be called a dummy transistor that does not transmit electrical signals. The dummy gate line 15 is, for example, used to separate two adjacent standard cells (or logic cells).

[0164] Some embodiments of the present application also provide a method for preparing an integrated circuit, which is used, for example, to prepare an integrated circuit 600 as described in any of the above examples. Fig.13 A flow chart of a method for preparing an integrated circuit is shown; Figure 14a-Figure 29b The structure corresponding to each step in a method for preparing an integrated circuit is schematically shown. Fig.14b , Fig.15b , Fig.16b , Fig.17b , Fig.18b , Fig.19b , Fig.20b , Figure 21b , Figure 23b , Fig.24a , Fig.25a , Fig.26a , Fig.27a , Fig.28a , Fig.29a (a) and (b) in the figure represent the cross-sectional structures of the structures prepared in the corresponding steps along the CC direction and the HH direction, respectively; Fig.14c , Fig.15c , Fig.16c , Fig.17c , Fig.18c , Fig.19c , Fig.20c , Fig.23c , Figure 24b , Fig.25b , Figure 26b , Figure 27b , Fig.28b , Fig.29b , respectively represent a cross-sectional structure of the structure formed in the corresponding steps along the DD direction. It should be understood that Fig.13 The steps shown are not exclusive and can also be Fig.13Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Fig.13 Executed in the order shown.

[0165] The following is a schematic illustration of the method for preparing an integrated circuit in conjunction with the accompanying drawings. Fig.13 As shown, the preparation method includes: S100-S600.

[0166] S100, such as Fig.14a , Fig.14b and Fig.14c As shown, an initial integrated circuit 600a is formed. The initial integrated circuit 600a includes a plurality of semiconductor structures 1, a first dielectric layer 2, a gate line 3, and a first pole 4. The plurality of semiconductor structures 1 extend along a first direction X and are arranged at intervals along a second direction Y. The first dielectric layer 2 is filled between two adjacent semiconductor structures 1. The gate line 3 is arranged across the plurality of semiconductor structures 1 and extends along the second direction Y. The first pole 4 is in contact with the semiconductor structure 1; along the first direction X, the first pole 4 is located on one side of the gate line 3. Optionally, the first dielectric layer 2 may also cover the semiconductor structure 1.

[0167] For example, Fig.14b and Fig.14c As shown, the initial integrated circuit 600 a further includes a substrate 16 , a second electrode 5 , a second dielectric layer 6 and a sixth dielectric layer 17 .

[0168] like Fig.14c As shown, the substrate 16 has a second surface B2 and a third surface B3 opposite to each other, and the semiconductor structure 1 and the first dielectric layer 2 are located on the second surface B2. The gate line 3 and the first pole 4 are located on the side of the semiconductor structure 1 away from the substrate 16. The substrate 16 is used to provide support for subsequent preparation process steps. Optionally, the material of the substrate 16 includes a semiconductor material. The semiconductor material includes but is not limited to silicon (Si), germanium, silicon germanium, silicon carbide, silicon on insulator, silicon germanium on insulator, or other III-group, V-group materials, etc.

[0169] The second pole 5 is in contact with the semiconductor structure 1, and along the first direction X, the second pole 5 and the first pole 4 are located on opposite sides of the gate line 3. The second dielectric layer 6 is located on the first dielectric layer 2, and is arranged across the plurality of semiconductor structures 1, and covers the first pole 4 and the second pole 5. There are a plurality of second dielectric layers 6, and the plurality of second dielectric layers 6 extend, for example, along the second direction Y and are arranged at intervals along the first direction X. Along the first direction X, the second dielectric layer 6 is located on opposite sides of the gate line 3. This makes it easy to isolate adjacent gate lines 3 using the second dielectric layer 6. The sixth dielectric layer 17 covers the gate line 3 and the second dielectric layer 6 to protect the gate line 3 and the second dielectric layer 6 in subsequent preparation process steps.

[0170] Regarding the arrangement of the semiconductor structure 1 , and the arrangement between the first electrode 4 and the second electrode 5 and the semiconductor structure 1 , reference may be made to the relevant descriptions above, which will not be repeated here.

[0171] S200, such as Fig.15a , Fig.15b and Fig.15c As shown, a first trench G1 is formed between two adjacent semiconductor structures 1. The first trench G1 penetrates the gate line 3 and the first dielectric layer 2. The first trench G1 extends along the first direction X, and cuts the gate line 3 into a first sub-gate line 31 and a second sub-gate line 32.

[0172] For example, in the embodiment of the present application, a photolithography process can be used to etch a portion of the sixth dielectric layer 17, the gate line 3, and the first dielectric layer 2 between the two adjacent semiconductor structures 1 to form a first trench G1. Along the first direction X, the first trench G1 is in a strip shape, and the first trench G1 can cut off a plurality of gate lines 3. The number of gate lines 3 cut off by the first trench G1 can be two, three, four, or even more. For example, in Fig.15a In the embodiment, the first trench G1 cuts off two gate lines 3 .

[0173] Furthermore, if Fig.15a As shown, the first trench G1 also cuts through the second dielectric layer 6 adjacent to the gate line 3. Of course, the first trench G1 may also only extend into the second dielectric layer 6 adjacent to the gate line 3 (eg Fig.15a The interior of the leftmost second dielectric layer 6 is not cut off.

[0174] Optionally, along the third direction Z, the first trench G1 may extend to the second surface B2 of the substrate 16, or, as shown in FIG. Fig.15b (a) and Fig.15c As shown, the first trench G1 may extend into the interior of the substrate 16. This is beneficial to improving the performance of the integrated circuit formed.

[0175] S300, such as Fig.16a , Fig.16b and Fig.16c As shown, an isolation layer 11 is formed in the first trench G1 . The isolation layer 11 covers the sidewalls of the first trench G1 . Accordingly, the isolation layer 11 contacts the first sub-gate line 31 and the second sub-gate line 32 .

[0176] Optionally, the isolation layer 11 also covers the bottom wall of the first trench G1. The isolation layer 11 does not fill up the first trench G1, and a space is reserved for the power supply connection portion 10. Fig.16cIn the example, the portion of the isolation layer 11 located in the first trench G1 is U-shaped. In the example, relative to the second surface B2 , the portion of the isolation layer 11 covering the first trench G1 is lower than the surface of the gate line 3 close to the substrate 16 .

[0177] Exemplarily, the method of forming the isolation layer 11 in the first trench G1 includes: S310 - S330 .

[0178] S310, such as Fig.17a , Fig.17b and Fig.17c As shown, an isolation film 11a is formed. The isolation film 11a covers the gate line 3 and the sidewalls and bottom wall of the first trench G1.

[0179] Illustratively, the embodiment of the present application may form the isolation film 11a by a deposition process. The material of the isolation film 11a includes but is not limited to at least one of silicon nitride, silicon carbide, silicon carbonitride, and silicon oxynitride. Optionally, the deposition process includes but is not limited to an atomic layer deposition process, and the isolation film 11a formed by the atomic layer deposition process has a uniform thickness.

[0180] Specifically, the isolation film 11 a contacts the first sub-gate line 31 and the second sub-gate line 32 , and a sixth dielectric layer 17 is disposed between the isolation film 11 a and the gate line 3 .

[0181] S320, such as Fig.18a , Fig.18b and Fig.18c As shown, a third dielectric layer 18 is formed. A portion of the third dielectric layer 18 is filled in the first trench G1 , and another portion is located on a side of the isolation film 11 a away from the gate line 3 .

[0182] For example, the third dielectric layer 18 may be formed by a deposition process in the embodiment of the present application. The deposition process includes but is not limited to a thin film deposition process of flowable chemical vapor deposition (FCVD), chemical vapor deposition, physical vapor deposition, atomic layer deposition or any combination thereof. The third dielectric layer 18 fills the area defined by the isolation film 11a in the first trench G1 and covers the isolation film 11a. The material of the third dielectric layer 18 includes but is not limited to silicon oxide and the like.

[0183] The material of the third dielectric layer 18 is different from that of the isolation film 11a, so that different etching selectivities can be achieved between the third dielectric layer 18 and the isolation film 11a, which facilitates the subsequent selective removal of the third dielectric layer 18.

[0184] S330, such as Figure 19a-Figure 20c As shown, the third dielectric layer 18 and the portion of the isolation film 11a located on the gate line 3 are removed simultaneously, and the portion of the third dielectric layer 18 filled in the first trench G1 is etched.

[0185] For example, Fig.19a , Fig.19b and Fig.19c As shown, the embodiment of the present application can firstly adopt a chemical mechanical polishing (CMP) process to grind away the third dielectric layer 18 and the portion of the isolation film 11a covering the sixth dielectric layer 17; then, as shown in FIG. Fig.20a , Fig.20b and Fig.20c As shown, a mask layer M is formed on the sixth dielectric layer 17 to expose the portion of the third dielectric layer 18 filled in the first trench G1 . Then, based on the mask layer M, the portion of the third dielectric layer 18 filled in the first trench G1 is etched away.

[0186] The portion of the third dielectric layer 18 located in the first trench G1 may be completely removed (eg Fig.17b (a) and Fig.17c As shown), you can also remove part of it (as shown Fig.20b (a) and Fig.20c When only a portion is removed, the remaining portion of the third dielectric layer 18, which is away from the side surface of the substrate 16, may be lower than the second surface B2 of the substrate 16, or may be located between the second surface B2 and the side surface of the gate line 3 close to the substrate 16 (as shown in FIG. Fig.20c As shown), to ensure that the surface of the remaining portion of the third dielectric layer 18 away from the substrate 16 is lower than the surface of the gate line 3 close to the substrate 16.

[0187] Optionally, before etching the portion of the third dielectric layer 18 filling the first trench G1, the portion of the third dielectric layer 18 and the isolation film 11a covering the sixth dielectric layer 17 may not be removed, or only the portion of the third dielectric layer 18 covering the isolation film 11a may be removed.

[0188] S400, such as Fig. 22 As shown, an opening K is formed in the isolation layer 11 .

[0189] Illustratively, in the embodiment of the present application, the isolation layer 11 may be etched by a photolithography process to form the opening K.

[0190] The position and number of the above-mentioned openings K are related to the connection relationship between the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 to be formed. For example, when the power supply connection part 10 and the first electrode contact part 8 are in contact, the portion of the isolation layer 11 located between the power supply connection part 10 and the first electrode contact part 8 can be etched and removed to form an opening K, so that the subsequently formed power supply connection part 10 can be in contact with the first electrode contact part 8 through the opening K. For another example, when the power supply connection part 10 and the second electrode contact part 9 are in contact, the portion of the isolation layer 11 located between the power supply connection part 10 and the second electrode contact part 9 can be etched and removed to form an opening K, so that the subsequently formed power supply connection part 10 can be in contact with the second electrode contact part 9 through the opening K. For another example, Fig. 22 As shown, in the case where the power supply connection part 10 is in contact with the first electrode contact part 8 and the second electrode contact part 9 at the same time, two openings K can be etched in the isolation layer 11, one of the openings K is located between the power supply connection part 10 and the first electrode contact part 8, so that the power supply connection part 10 formed subsequently can contact the first electrode contact part 8 through the opening K; the other opening K is located between the power supply connection part 10 and the second electrode contact part 9, so that the power supply connection part 10 formed subsequently can contact the second electrode contact part 9 through the opening K. Of course, in the case where the power supply connection part 10 is in contact with the first electrode contact part 8 and the second electrode contact part 9 at the same time, an opening K can also be etched in the isolation layer 11, and the power supply connection part 10 formed subsequently can pass through the opening K and contact the first electrode contact part 8 and the second electrode contact part 9 at the same time.

[0191] S500, such as Fig.23a , Figure 23b and Fig.23c As shown, a power supply connection portion 10, a first electrode contact portion 8 and a second electrode contact portion 9 are formed. The power supply connection portion 10 is located in the first groove G1, and the first electrode contact portion 8 and the second electrode contact portion 9 are located on opposite sides of the power supply connection portion 10 along the second direction Y. The first electrode contact portion 8 and the second electrode contact portion 9 are located on different first poles 4 and contact the corresponding first poles 4. The power supply connection portion 10 contacts the first electrode contact portion 8 and / or the second electrode contact portion 9 through the opening K.

[0192] Exemplarily, the embodiment of the present application may adopt a metal filling process, a chemical mechanical polishing process, etc. to form the power connection portion 10, the first electrode contact portion 8, and the second electrode contact portion 9. In the process of filling the required material in the first groove G1 to form the power connection portion 10, the isolation layer 11 can provide a self-alignment effect, so that the required material can be naturally filled in the area defined by the isolation layer 11 and the opening K of the isolation layer 11, and contact the first electrode contact portion 8 and / or the second electrode contact portion 9.

[0193] S600, such as Fig.26a and Figure 26b As shown, a power distribution network 7 is formed on a side of the semiconductor structure 1 away from the gate line 3. The power distribution network 7 contacts the power connection portion 10. The power distribution network 7 has a first surface B1, and the first direction X and the second direction Y are both parallel to the first surface B1 and intersect each other.

[0194] For example, when the initial integrated circuit 600a further includes a substrate 16, Fig.25a , Fig.25b As shown, before the power distribution network 7 is formed on the side of the semiconductor structure 1 away from the gate line 3, the preparation method further includes: removing the substrate 16 from the side where the third surface B3 is located to expose the power connection portion 10. This can ensure that in the prepared integrated circuit 600, the end of the power connection portion 10 close to the power distribution network 7 is located in the first dielectric layer 2, which is conducive to improving the performance of the prepared integrated circuit 600.

[0195] For example, Fig.25a and Fig.25b As shown, the method for removing the substrate 16 from the side where the third surface B3 is located includes: turning over the initial integrated circuit 600a, and then grinding and removing the substrate 16 by using a chemical mechanical grinding process. In the process of grinding and removing the substrate 16, the portion of the isolation layer 11 that also covers the bottom wall of the first groove G1 is also removed, so that the power supply connection part 10 and the power distribution network 7 are in contact to form an electrical connection.

[0196] The method for preparing an integrated circuit provided in the embodiment of the present application forms an isolation layer 11 in a first trench G1 formed between two adjacent semiconductor structures 1, thereby providing a self-alignment effect for a power connection portion 10 subsequently formed in the first trench G1, so that the material of the power connection portion 10 is naturally filled in the area defined by the isolation layer 11, wherein the required alignment, photolithography, etching and other processes are less difficult, which is conducive to increasing the process window.

[0197] Moreover, compared with the above-mentioned possible implementation mode, the embodiment of the present application does not need to etch and form an electric via in the isolation layer 11, and thus avoids the problem caused by etching and forming an electric via. That is, the embodiment of the present application can utilize the isolation layer 11 with a relatively uniform thickness to realize the electrical insulation between the power supply connection part 10 and the first sub-grid line 31, and realize the electrical insulation between the power supply connection part 10 and the second sub-grid line 32, and at the same time, it is possible to make the power supply connection part 10 and the first sub-grid line 31 have enough insulation distance, and make the power supply connection part 10 and the second sub-grid line 32 have enough insulation distance, and then it is possible to reduce the risk of short circuit and breakdown between the power supply connection part 10 and the first sub-grid line 31, and between the power supply connection part 10 and the second sub-grid line 32, and improve the breakdown voltage between the power supply connection part 10 and the first sub-grid line 31, and between the power supply connection part 10 and the second sub-grid line 32, and improve the reliability of the integrated circuit 600.

[0198] It can be understood that in the above S500, the method of forming the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 includes multiple methods. For example, the embodiment of the present application can first form the power supply connection part 10 in the above first groove G1 and the opening K, and then form the first electrode contact part 8 and the second electrode contact part 9 on one side of the gate line 3, so that the power supply connection part 10 contacts the first electrode contact part 8 and / or the second electrode contact part 9 through the opening K. For another example, the embodiment of the present application can first form the first electrode contact part 8 and the second electrode contact part 9 on one side of the gate line 3, and then form the power supply connection part 10 in the above first groove G1 and the opening K, so that the power supply connection part 10 contacts the first electrode contact part 8 and / or the second electrode contact part 9 through the opening K. For another example, the embodiment of the present application can simultaneously form the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 in the same patterning process.

[0199] In the same patterning process, the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 are formed simultaneously, which is conducive to simplifying the manufacturing process of the integrated circuit. In combination with the accompanying drawings, the manufacturing method of the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 is schematically described as an example.

[0200] In some examples, such as Fig.21a and Figure 21b As shown, before the above S400, that is, before forming the opening K in the isolation layer 11, the above preparation method further includes: forming a second trench G2 in the second dielectric layer 6. The second trench G2 exposes the first pole 4, and along the second direction Y, the second trench G2 is located on opposite sides of the isolation layer 11. The opening K connects the second trench G2 and the first trench G1.

[0201] Exemplarily, in the embodiment of the present application, the second dielectric layer 6 may be etched by a photolithography process to form a second groove G2 in the second dielectric layer 6. Along the third direction Z, the second groove G2 penetrates the sixth dielectric layer 17 and extends to the inside of the second dielectric layer 6, or extends to the first dielectric layer 2, and the first electrode 4 can be exposed. Along the first direction X, there is a spacing between the second groove G2 and the gate line 3, so that there is a dielectric material between the second groove G2 and the gate line 3, ensuring electrical insulation between the first electrode contact portion 8 and the gate line 3, and electrical insulation between the second electrode contact portion 9 and the gate line 3 formed subsequently.

[0202] After forming the second groove G2, an opening K can be formed in the isolation layer 11. When the power supply connection part 10 is in contact with the first electrode contact part 8, the opening K can connect the first groove G1 and the second groove G2 located above the isolation layer 11 along the second direction Y. Alternatively, when the power supply connection part 10 is in contact with the second electrode contact part 9, the opening K can connect the first groove G1 and the second groove G2 located below the isolation layer 11 along the second direction Y. Alternatively, Fig. 22 As shown, when the power supply connection portion 10 contacts the first electrode contact portion 8 and the second electrode contact portion 9 at the same time, along the second direction Y, the opening K can connect the first trench G1 and the second trench G2 located above and below the isolation layer 11 at the same time.

[0203] In some examples, such as Fig.23a , Figure 23b and Fig.23c As shown, in the above S500, the method for forming the power supply connecting portion 10, the first electrode contact portion 8 and the second electrode contact portion 9 includes: filling the first groove G1, the second groove G2 and the opening K with conductive material to form the power supply connecting portion 10, the first electrode contact portion 8 and the second electrode contact portion 9.

[0204] Optionally, the above-mentioned conductive materials include but are not limited to one or more of aluminum, copper, tungsten, molybdenum, cobalt, etc. The embodiment of the present application can adopt a metal filling process to fill the first trench G1, the second trench G2 and the opening K with conductive materials, and fill the first trench G1, the second trench G2 and the opening K. The conductive material will also be located on the sixth dielectric layer 17; then a chemical mechanical polishing process can be adopted to polish away part of the conductive material located on the sixth dielectric layer 17, and retain part of the conductive material located in the first trench G1, the second trench G2 and the opening K, so as to obtain the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9. The power supply connection part 10 is also located in the area defined by the isolation layer 11. In this case, the power supply connection part 10, the first electrode contact part 8 and the second electrode contact part 9 are, for example, all composed of a single-layer film, and the three materials are the same and have an integrated structure.

[0205] The power supply connection portion 10, the first electrode contact portion 8 and the second electrode contact portion 9 have relatively simple structures and are easy to prepare, which is beneficial to simplifying the preparation method of the integrated circuit and improving the preparation efficiency of the integrated circuit.

[0206] In addition, the power supply connection portion 10, the first electrode contact portion 8 and the second electrode contact portion 9 may also be formed by stacking multiple layers of thin films. Fig.27a , Figure 27b , Fig.28a and Fig.28b As shown, before the conductive material is filled in the first trench G1, the second trench G2 and the opening K, the preparation method further includes: forming a barrier film F that at least covers the sidewalls of the first trench G1, the second trench G2 and the opening K. When the power supply connection part 10 is in contact with the first electrode contact part 8, the barrier film F surrounds the power supply connection part 10 and the first electrode contact part 8; when the power supply connection part 10 is in contact with the second electrode contact part 9, the barrier film F surrounds the power supply connection part 10 and the second electrode contact part 9; when the power supply connection part 10 is in contact with the first electrode contact part 8 and the second electrode contact part 9, the barrier film F surrounds the power supply connection part 10 and the first electrode contact part 8 and the second electrode contact part 9.

[0207] The material of the barrier film F includes, but is not limited to, one or more of titanium, titanium nitride, tantalum, tantalum nitride, and the like.

[0208] The barrier film F also covers the sixth dielectric layer 17, the bottom wall of the first trench G1, the bottom wall of the second trench G2, and the bottom wall of the opening K. The barrier film F contacts the bottom and side surfaces of the power supply connection portion 10, the bottom and side surfaces of the first electrode contact portion 8, and the bottom and side surfaces of the second electrode contact portion 9. For example, Fig.28a and Fig.28b In the embodiment, the portion of the barrier film F located in the first groove G1 is U-shaped, and the power supply connection portion 10 is located in the area surrounded by the barrier film F. The portion of the barrier film F located in the second groove G2 is U-shaped, and the first electrode contact portion 8 or the second electrode contact portion 9 is located in the area surrounded by the barrier film F.

[0209] Combination Fig.28a , Fig.28b , Fig.29a and Fig.29bIn the process of removing the conductive material located on the sixth dielectric layer 17 by grinding with the chemical mechanical grinding process, the portion of the barrier film F covering the sixth dielectric layer 17 can also be removed by grinding, and the portion of the barrier film F covering the bottom wall and side wall of the first trench G1, the portion covering the bottom wall and side wall of the second trench G2, and the portion covering the bottom wall and side wall of the opening K are retained. Among them, the portion of the barrier film F located in the first trench G1 is used to form the second barrier layer 102, the portion of the conductive material located in the first trench G1 is used to form the second conductive layer 101, and the second conductive layer 101 and the second barrier layer 102 together form the power supply connection portion 10. The portion of the barrier film F located in the second trench G2 is used to form the first barrier layer 82 or the third barrier layer 92, the portion of the conductive material located in the second trench G2 is used to form the first conductive layer 81 or the third conductive layer 91, the first conductive layer 81 and the first barrier layer 82 together form the first electrode contact portion 8, and the third conductive layer 91 and the third barrier layer 92 together form the second electrode contact portion 9.

[0210] The provision of the barrier film F is beneficial to improving the adhesion between the conductive material and the surrounding dielectric layer (eg, the second dielectric layer 6).

[0211] In some embodiments, Fig.14b As shown in (b) , the second trench G2 also exposes the second electrode 5 , for example.

[0212] like Figure 21a-Figure 23b As shown, in the above S500, during the process of forming the power supply connection portion 10, the first electrode contact portion 8 and the second electrode contact portion 9, the third electrode contact portion 12 and the fourth electrode contact portion 13 are also formed. The third electrode contact portion 12 and the fourth electrode contact portion 13 are located on opposite sides of the power supply connection portion 10 along the second direction Y. The third electrode contact portion 12 and the fourth electrode contact portion 13 are located on different second poles 5 and are in contact with the corresponding second poles 5.

[0213] The method of forming the third electrode contact portion 12 and the fourth electrode contact portion 13 is the same as the method of forming the power supply connection portion 10, the first electrode contact portion 8 and the second electrode contact portion 9, and reference may be made to the relevant descriptions above, which will not be repeated here.

[0214] In the embodiment of the present application, the third electrode contact portion 12, the fourth electrode contact portion 13, the first electrode contact portion 8, the second electrode contact portion 9 and the power supply connection portion 10 are simultaneously formed in the same patterning process, which is beneficial to simplifying the manufacturing process of the integrated circuit.

[0215] Furthermore, if Fig.24a and Figure 24bAs shown, before the above S600, that is, before forming the power distribution network 7 on the side of the semiconductor structure 1 away from the gate line 3, the above preparation method further includes: forming an interconnection layer 14 on the third electrode contact portion 12 and the fourth electrode contact portion 13. The interconnection layer 14 is electrically connected to the third electrode contact portion 12 and the fourth electrode contact portion 13.

[0216] The interconnection layer 14 can transmit electrical signals to the third electrode contact portion 12 and the fourth electrode contact portion 13 .

[0217] In some embodiments, Fig.24a and Figure 24b As shown, after forming the interconnection layer 14 and before forming the power distribution network 7, the manufacturing method further includes: bonding a carrier wafer 21 on the interconnection layer 14. The carrier wafer 21 can be used to support the initial integrated circuit 600a.

[0218] Optionally, no components may be provided in the carrier wafer 21. In this way, after the integrated circuit is manufactured, the carrier wafer 21 may be peeled off and removed. Alternatively, a plurality of components (such as transistors, capacitors, resistors, etc.) may also be formed in the carrier wafer 21, and the plurality of components in the carrier wafer 21 are electrically connected to the interconnection layer 14. In this way, after the integrated circuit is manufactured, the carrier wafer 21 may be used as a part of the integrated circuit.

[0219] In the description of this specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner. The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field within the technical scope disclosed in this disclosure can think of changes or substitutions, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An integrated circuit, characterized in that: The integrated circuit comprises: A power distribution network having a first surface; A plurality of semiconductor structures are located on the first surface; the plurality of semiconductor structures extend along a first direction and are arranged at intervals along a second direction; the first direction and the second direction are both parallel to the first surface and intersect each other; A gate line is arranged across the plurality of semiconductor structures; the gate line extends along the second direction; A first electrode is in contact with the semiconductor structure; along the first direction, the first electrode is located at one side of the gate line; A power supply connection portion is located between two adjacent semiconductor structures; the power supply connection portion is in contact with the power distribution network; the power supply connection portion extends along the first direction to separate the gate line into a first sub-gate line and a second sub-gate line; A first electrode contact portion and a second electrode contact portion are located at opposite sides of the power supply connecting portion along the second direction; the first electrode contact portion and the second electrode contact portion are located on different first poles and are in contact with corresponding first poles; An isolation layer, at least located on two opposite sides of the power supply connection portion along the second direction, separating the power supply connection portion from the first sub-grid line and the second sub-grid line; The power supply connecting portion also penetrates the isolation layer and contacts the first electrode contact portion and / or the second electrode contact portion.

2. The integrated circuit according to claim 1, characterized in that The first electrode contact portion, the second electrode contact portion and the power supply connecting portion are arranged in the same layer.

3. The integrated circuit according to claim 1 or 2, characterized in that: The power supply connection portion is in contact with the first electrode contact portion and forms an integral structure; or, The power supply connecting portion is in contact with the second electrode contact portion and forms an integral structure; or, The power supply connecting portion contacts the first electrode contact portion and the second electrode contact portion, and the three form an integrated structure.

4. The integrated circuit according to any one of claims 1 to 3, characterized in that: The first electrode contact portion includes a first conductive layer and a first barrier layer, and the power supply connection portion includes a second conductive layer and a second barrier layer; When the power supply connection portion is in contact with the first electrode contact portion, The first conductive layer and the second conductive layer are connected to form an integral structure; The first barrier layer and the second barrier layer are connected to form an integral structure, and the first barrier layer and the second barrier layer jointly surround the first conductive layer and the second conductive layer.

5. The integrated circuit according to any one of claims 1 to 4, characterized in that: The power supply connection portion includes a second conductive layer and a second barrier layer, and the second electrode contact portion includes a third conductive layer and a third barrier layer; When the power supply connection portion is in contact with the second electrode contact portion, The second conductive layer and the third conductive layer are connected to form an integral structure; The second barrier layer and the third barrier layer are connected to form an integral structure, and the second barrier layer and the third barrier layer jointly surround the second conductive layer and the third conductive layer.

6. The integrated circuit according to any one of claims 1 to 5, characterized in that: The first electrode contact portion includes a first conductive layer and a first barrier layer, the power supply connection portion includes a second conductive layer and a second barrier layer, and the second electrode contact portion includes a third conductive layer and a third barrier layer; When the power supply connecting portion is in contact with the first electrode contact portion and the second electrode contact portion, The first conductive layer, the second conductive layer and the third conductive layer are connected and form an integral structure; The first barrier layer, the second barrier layer and the third barrier layer are connected and form an integral structure; the first barrier layer, the second barrier layer and the third barrier layer jointly surround the first conductive layer, the second conductive layer and the third barrier layer.

7. The integrated circuit according to any one of claims 1 to 6, characterized in that: The material of the isolation layer includes at least one of silicon nitride, silicon carbide, silicon carbonitride, and silicon oxynitride.

8. The integrated circuit according to any one of claims 1 to 7, characterized in that: A surface of one side of the isolation layer close to the power distribution network is flush with a surface of one side of the power supply connection portion close to the power distribution network.

9. The integrated circuit according to any one of claims 1 to 8, characterized in that: The integrated circuit further comprises: A second electrode is in contact with the semiconductor structure; along the first direction, the second electrode and the first electrode are located at opposite sides of the gate line; The third electrode contact portion and the fourth electrode contact portion are located on opposite sides of the power supply connection portion along the second direction; the isolation layer separates the power supply connection portion from the third electrode contact portion, and separates the power supply connection portion from the fourth electrode contact portion; the third electrode contact portion and the fourth electrode contact portion are located on different second poles, and are in contact with the corresponding second poles; The interconnection layer is located on the third electrode contact portion and the fourth electrode contact portion and is electrically connected to the third electrode contact portion and the fourth electrode contact portion.

10. The integrated circuit according to claim 9, characterized in that The third electrode contact portion, the fourth electrode contact portion and the power supply connecting portion are arranged in the same layer.

11. The integrated circuit according to any one of claims 1 to 10, characterized in that: The integrated circuit further includes: at least two dummy gate lines, the dummy gate lines extending along the second direction; The gate line is located between two adjacent dummy gate lines, and the power supply connecting portion further isolates the dummy gate lines.

12. A method for preparing an integrated circuit, characterized in that: The preparation method comprises: An initial integrated circuit is formed; the initial integrated circuit comprises a plurality of semiconductor structures, a first dielectric layer, a gate line, and a first electrode; the plurality of semiconductor structures extend along a first direction and are arranged at intervals along a second direction; the first dielectric layer is filled between two adjacent semiconductor structures; the gate line is arranged across the plurality of semiconductor structures and extends along the second direction; the first electrode is in contact with the semiconductor structure; along the first direction, the first electrode is located on one side of the gate line; A first trench is formed between two adjacent semiconductor structures; the first trench penetrates the gate line and the first dielectric layer; the first trench extends along the first direction to cut the gate line into a first sub-gate line and a second sub-gate line; forming an isolation layer in the first trench; the isolation layer covers the sidewalls of the first trench; forming an opening in the isolation layer; A power supply connection portion, a first electrode contact portion, and a second electrode contact portion are formed; the power supply connection portion is located in the first groove, and the first electrode contact portion and the second electrode contact portion are located on opposite sides of the power supply connection portion along the second direction; the first electrode contact portion and the second electrode contact portion are located on different first poles and contact the corresponding first poles; the power supply connection portion contacts the first electrode contact portion and / or the second electrode contact portion through the opening; A power distribution network is formed on a side of the semiconductor structure away from the gate line; the power distribution network is in contact with the power supply connection portion; the power distribution network has a first surface, and the first direction and the second direction are both parallel to the first surface and intersect each other.

13. The preparation method according to claim 12, characterized in that: The initial integrated circuit further includes a second dielectric layer; along the first direction, the second dielectric layer is located on opposite sides of the gate line and covers the first electrode; Before forming the opening in the isolation layer, the preparation method further comprises: A second trench is formed in the second dielectric layer; the second trench exposes the first electrode; along the second direction, the second trench is located at two opposite sides of the isolation layer; the opening connects the second trench and the first trench; The forming of the power supply connection part, the first electrode contact part and the second electrode contact part comprises: A conductive material is filled in the first trench, the second trench, and the opening to form the power supply connection portion, the first electrode contact portion, and the second electrode contact portion.

14. The preparation method according to claim 13, characterized in that: Before filling the first trench, the second trench and the opening with a conductive material, the preparation method further comprises: A barrier film is formed to cover at least the sidewalls of the first groove, the sidewalls of the second groove and the sidewalls of the opening; when the power supply connecting part is in contact with the first electrode contact part, the barrier film surrounds the power supply connecting part and the first electrode contact part; when the power supply connecting part is in contact with the second electrode contact part, the barrier film surrounds the power supply connecting part and the second electrode contact part.

15. The preparation method according to claim 12, characterized in that: The step of forming an isolation layer in the first trench comprises: forming an isolation film; the isolation film covers the gate line, the sidewall and the bottom wall of the first trench; forming a third dielectric layer; a portion of the third dielectric layer is filled in the first trench, and another portion is located on a side of the isolation film away from the gate line; The third dielectric layer and the isolation film are removed simultaneously and the portion located on the gate line is etched, and the portion of the third dielectric layer filled in the first trench is etched.

16. The preparation method according to claim 12, characterized in that: The initial integrated circuit further comprises a substrate, wherein the substrate has a second surface and a third surface opposite to each other, and the semiconductor structure is located on the second surface; the first trench further extends to the substrate; Before forming a power distribution network on a side of the semiconductor structure away from the gate line, the preparation method further comprises: The substrate is removed from the side where the third surface is located to expose the power supply connection portion.

17. The preparation method according to claim 12, characterized in that: The initial integrated circuit further includes a second electrode, the second electrode is in contact with the semiconductor structure; along the first direction, the second electrode and the first electrode are located at opposite sides of the gate line; In the process of forming the power supply connection part, the first electrode contact part and the second electrode contact part, a third electrode contact part and a fourth electrode contact part are also formed; the third electrode contact part and the fourth electrode contact part are located at opposite sides of the power supply connection part along the second direction; the third electrode contact part and the fourth electrode contact part are located on different second poles and contact with corresponding second poles; Before forming a power distribution network on a side of the semiconductor structure away from the gate line, the preparation method further comprises: forming an interconnection layer on the third electrode contact portion and the fourth electrode contact portion; The interconnection layer is electrically connected to the third electrode contact portion and the fourth electrode contact portion.

18. An electronic device, characterized in that: The electronic device comprises: Circuit boards; and, The integrated circuit as claimed in any one of claims 1 to 11, wherein the integrated circuit is connected to the circuit board.

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