IGBT and FRD power semiconductor module, motor controller, and automobile

Abstract

The application relates to an IGBT and FRD power semiconductor module, a motor controller and an automobile, which comprises a substrate, a plurality of power electrode terminals, a plurality of signal terminals, an upper bridge chip set, a lower bridge chip set, a signal connector, an interconnection pad high layer and an interconnection substrate; the substrate is provided with a signal copper layer area, a chip set area and a substrate power copper layer area; the plurality of power electrode terminals comprise a direct current negative power electrode terminal, a direct current positive power electrode terminal and an output power electrode terminal; each signal terminal is connected with a driving area on an IGBT power chip in the upper bridge chip set and the lower bridge chip set through a corresponding signal connector to form a driving path; the direct current positive power electrode terminal is connected with the direct current negative power electrode terminal through a power copper layer on the substrate, the chip set, the interconnection pad high layer and the interconnection substrate to form a power path. The application solves the problems of large electromagnetic interference and inconsistent dynamic and static current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor modules, in particular to an IGBT and FRD power semiconductor module, a motor controller and a vehicle. BACKGROUND

[0002] At present, the mainstream power semiconductor module structure is usually composed of power chips, copper-clad ceramic substrates, interconnection copper bars or bonding wires, power terminals, signal terminals, epoxy encapsulating materials or frame plastic housings, and various solders. This structure connects each component tightly together through a precise welding process to form a highly integrated power conversion unit. However, in the prior art, especially in the design of power modules using four parallel or more parallel schemes, there are some inherent technical difficulties.

[0003] As shown in Figure 1 and Figure 2 , in the traditional four-parallel power module, the power chips are arranged in a rectangular distribution in the upper and lower positions of the substrate in the long direction, and the power path (large current path) is: from the DC positive power electrode terminal 5, through the upper bridge drain power copper layer 20-a, the upper bridge chip set, the upper bridge source power interconnection copper bar 21-a, the second substrate upper and lower bridge power interconnection copper layer 20-c (lower bridge drain power copper layer), the upper and lower bridge interconnection copper bar 21-b, the first substrate upper and lower bridge power interconnection copper layer 20-b (lower bridge drain power copper layer), the lower bridge chip set, the lower bridge source power interconnection copper bar 21-c, the substrate power negative copper layer 20-d to the DC negative power electrode terminal 4. This layout has the following problems:

[0004] 1. Since the upper and lower bridge power paths exist vertically in the space, when the module is in the dead zone transient state, the upper and lower bridge commutation paths will produce strong magnetic field coupling effect in this area, and then form electromagnetic interference.

[0005] 2. The vertically overlapping area between the lower bridge drive path and the power path will also cause problems. The magnetic field generated by the large current on the power path will interfere with the signal on the drive path, causing signal oscillation, and thus increasing the loss of the module and reducing the consistency of dynamic and static current sharing. This not only reduces the efficiency of the module, but also may affect the stable operation of the module.

[0006] 3. Since the parasitic resistance and parasitic inductance of the upper and lower bridge drive paths are quite different, this will cause great differences in the design of the peripheral circuits of the upper and lower bridges. This difference will further affect the consistency of the upper and lower bridge signals, making it difficult for the module to achieve ideal control effect when running.

[0007] Therefore, it is necessary to develop a new IGBT and FRD power semiconductor module, a motor controller and a vehicle. SUMMARY

[0008] The application aims to provide an IGBT and FRD power semiconductor module, a motor controller and an automobile to solve the problems of large electromagnetic interference and inconsistent dynamic and static current.

[0009] In a first aspect, the application provides an IGBT and FRD power semiconductor module, comprising:

[0010] A substrate, on which an upper bridge chip set area, a substrate power negative copper layer and a lower bridge chip set area are sequentially arranged from one side to the other side, the upper bridge chip set area comprising a substrate upper bridge gate signal copper layer, a substrate upper bridge emitter signal copper layer and a substrate upper bridge collector power copper layer, and the lower bridge chip set area comprising a substrate lower bridge gate signal copper layer, a substrate lower bridge emitter signal copper layer and a substrate lower bridge collector power copper layer;

[0011] A plurality of power electrode terminals, comprising a direct current negative power electrode terminal, a direct current positive power electrode terminal and an output power electrode terminal connected to the substrate power negative copper layer, the substrate upper bridge collector power copper layer and the substrate lower bridge collector power copper layer respectively;

[0012] A plurality of signal terminals, comprising an upper bridge arm gate signal terminal, an upper bridge arm emitter signal terminal, a lower bridge arm gate signal terminal and a lower bridge arm emitter signal terminal connected to the substrate upper bridge gate signal copper layer, the substrate upper bridge emitter signal copper layer, the substrate lower bridge gate signal copper layer and the substrate lower bridge emitter signal copper layer respectively;

[0013] An upper bridge chip set, comprising an FRD power chip and an IGBT power chip arranged on the substrate upper bridge collector power copper layer respectively;

[0014] A lower bridge chip set, comprising an FRD power chip and an IGBT power chip arranged on the substrate lower bridge collector power copper layer respectively;

[0015] A signal connector for connecting the driving areas of the corresponding IGBT power chips with the substrate upper bridge gate signal copper layer, the substrate upper bridge emitter signal copper layer, the substrate lower bridge gate signal copper layer and the substrate lower bridge emitter signal copper layer;

[0016] An interconnection pad high layer arranged on the upper bridge chip set area, the lower bridge chip set area and the substrate power negative copper layer;

[0017] An interconnection substrate arranged on the interconnection pad high layer;

[0018] The upper bridge arm gate signal terminal, upper bridge arm emitter signal terminal, lower bridge arm gate signal terminal, and lower bridge arm emitter signal terminal are respectively connected to the driving areas of the IGBT power chips in the upper and lower bridge chipsets through corresponding signal connectors to form a driving path; the DC positive power electrode terminal is respectively connected to the DC negative power electrode terminal through the power copper layer, chipset, interconnect pad layer, and interconnect substrate on the substrate to form a power path; and the driving path and power path have no overlapping areas in space.

[0019] Optionally, the signal connector includes:

[0020] Connecting the upper bridge gate signal copper layer of the substrate to the upper bridge gate of the IGBT power chip;

[0021] Connecting the lower bridge gate signal copper layer of the substrate to the lower bridge gate of the IGBT power chip;

[0022] Connecting the upper bridge emitter signal copper layer of the substrate to the upper bridge emitter bonding wire of the IGBT power chip;

[0023] The lower bridge emitter signal copper layer of the substrate connects the lower bridge emitter signal layer to the IGBT power chip via a bonding wire.

[0024] Optionally, the driving path includes a gate path, which includes an upper bridge gate path and a lower bridge gate path, and the upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin.

[0025] The upper bridge gate path extends from the upper bridge arm gate signal terminal through the upper bridge gate signal copper layer on the substrate and the upper bridge gate bonding wire to the gate region of the IGBT power chip in the upper bridge chipset.

[0026] The lower bridge gate path extends from the lower bridge arm gate signal terminal through the lower bridge gate signal copper layer on the substrate and the lower bridge gate bonding wire to the gate region of the IGBT power chip in the lower bridge chipset.

[0027] Optionally, the drive path includes an emitter path, which includes an upper bridge emitter path and a lower bridge emitter path, and the upper bridge emitter path and the lower bridge emitter path are symmetrically arranged at 180° with the center as the origin;

[0028] The upper bridge emitter path runs from the upper bridge arm emitter signal terminal through the upper bridge emitter signal copper layer on the substrate and the upper bridge emitter bonding wire to the Kelvin emitter region of the IGBT power chip in the upper bridge chipset.

[0029] The lower bridge emitter path runs from the lower bridge arm emitter signal terminal through the lower bridge emitter signal copper layer on the substrate, the lower bridge emitter bonding wire, to the Kelvin emitter region of the IGBT power chip in the lower bridge chipset.

[0030] Optionally, the interconnect pad high layer includes an upper bridge emitter power interconnect pad high layer disposed on each upper bridge chip group, two upper and lower bridge power interconnect pad high layers disposed on the lower bridge collector power copper layer of the substrate, lower bridge emitter power interconnect pad high layers disposed on each lower bridge chip group, and four lower bridge and DC negative interconnect pad high layers disposed on the power negative copper layer of the substrate.

[0031] The interconnect substrate includes interconnect copper layers, insulating ceramic sheets and signal shielding copper layers stacked in sequence. The interconnect copper layers are divided into a first part that covers all lower bridge emitter power interconnect pads and all lower bridge and DC negative interconnect pads, and a second part that covers all upper bridge emitter power interconnect pads and all upper and lower bridge power interconnect pads.

[0032] Optionally, the power path extends from the DC positive power electrode terminal through the upper bridge collector power copper layer on the substrate, the upper bridge chipset, the upper bridge emitter power interconnect pad layer, the second part of the interconnect substrate, the upper and lower bridge power interconnect pad layers, the lower bridge collector power copper layer on the substrate, the lower bridge chipset, the lower bridge emitter power interconnect pad layer, the first part of the lower bridge emitter power interconnect copper layer on the interconnect substrate, the lower bridge and DC negative interconnect pad layers, and the substrate power negative copper layer to the DC negative power electrode terminal.

[0033] Optionally, the upper bridge chipset includes two FRD power chips and two IGBT power chips, which are respectively crosswise disposed on the upper bridge collector power copper layer of the substrate;

[0034] The lower bridge chipset includes two FRD power chips and two IGBT power chips, which are respectively arranged crosswise on the power copper layer of the lower bridge collector on the substrate.

[0035] Optionally, the bridge gate signal copper layer, bridge emitter signal copper layer, and bridge collector power copper layer on the substrate are all disposed on one side of the substrate and extend along the length of the substrate.

[0036] The substrate lower bridge gate signal copper layer, substrate lower bridge emitter signal copper layer, and substrate lower bridge collector power copper layer are all disposed on the other side of the substrate and extend along the length direction of the substrate.

[0037] Secondly, the motor controller described in this invention employs the IGBT and FRD power semiconductor modules as described in this invention.

[0038] Thirdly, the automobile described in this invention employs a motor controller as described in this invention.

[0039] The beneficial effects of this invention are:

[0040] 1. This invention significantly reduces the inductance problem caused by excessively long power paths by optimizing the layout of components within the module, reducing cross-interference between signal and power busbars, and improving electrical stability. System inductance simulation results show that, compared to 7.6nH in existing four-parallel power modules, the inductance of this invention is reduced to 5.24nH, a reduction of 2.36nH. This helps improve the electromagnetic compatibility, switching efficiency, system stability, overall performance of the power module, and reduces power module losses, particularly demonstrating superior performance in hybrid electric vehicles, range-extended electric vehicles, and construction machinery.

[0041] 2. The drive paths of the upper and lower bridges in this invention adopt a 180° symmetrical design with the center as the origin, making the upper and lower drive paths basically consistent and reducing the difference in parasitic drive parameters. Regarding the parasitic inductance of the drive path: In existing solutions with four parallel power modules, due to the complexity of the upper and lower bridge circuits and the need for bonding wires for connection, the overall system has significant electromagnetic interference. Simulation of the drive path inductance of the upper and lower bridges at 1GHz shows that the parasitic drive inductances of the upper and lower bridges are 34.7nH and 54nH, respectively, with an inductance imbalance of 21.76%. Simulation of the parasitic inductance of the drive path of the upper and lower bridges in this invention at 1GHz shows that the parasitic inductances of the upper and lower bridges are 16nH and 13.5nH, respectively, with an inductance imbalance of only 8.47%, far lower than the 21.76% of the existing solutions. Regarding parasitic resistance in the drive path: Simulations of the parasitic resistance of the upper and lower bridges in the existing quad-parallel power module at 1Hz show resistances of 44.6mΩ and 77.7mΩ, respectively, with a gate resistance imbalance of 27.06%. Simulations of the drive path resistance of the upper and lower bridges in this invention at 1Hz show parasitic resistances of 5.7mΩ and 5.2mΩ, respectively, with a resistance imbalance of only 4.59%, significantly lower than the 27.06% of the existing solution. Compared to the existing quad-parallel power module, this invention offers a significant improvement in parasitic inductance in the drive path. After inductance optimization, the gate drive signal of the power module is more stable, resulting in better performance stability. There is also a significant improvement in loop resistance, which further reduces the impact of the power loop on the drive loop, greatly improving the system stability of the power module.

[0042] 3. In this invention, the drive path and power path have no spatial overlap, effectively reducing gate switching oscillations caused by mutual electromagnetic interference. Simulations of the mutual inductance between the gates and power paths of the upper and lower bridges at 1 GHz show that the mutual inductance between the upper bridge and the power path is only 1.25 nH, and the mutual inductance between the lower bridge and the power path is only 0.8 nH, with a mutual inductance imbalance of 21.95%. Compared to the existing four-parallel power module, which is more complex and has gate bonding lines crossing over the power loop, simulations of the mutual inductance between the gates and power loops of the upper and lower bridges at 1 GHz show mutual inductances of 1.92 nH and 10.2 nH, respectively, with a mutual inductance imbalance of 68.32%. These findings demonstrate that this invention effectively reduces the mutual inductance between the drive path and the power path, thus reducing the impact of the power path on the drive path and improving the system stability of the module. Simultaneously, the reduced impact on the drive loop helps reduce power module losses and significantly improves the overall efficiency of the power module.

[0043] 4. The power path converter circuit of the present invention is simpler, resulting in a faster converter speed.

[0044] 5. In the IGBT and FRD power semiconductor modules, the spatial structure formed by the interconnect pad layers and interconnect substrate allows current to flow in multiple directions. Specifically, when current in the power path passes through the interconnect pad layers, interconnect substrate, chip, and substrate, they form paths with the same current magnitude but flowing in opposite directions. The magnetic fields generated by these reverse current paths cancel each other out, thereby reducing stray inductance throughout the circuit, lowering switching losses, reducing turn-off spikes, and significantly improving the performance of the power module. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of an existing four-parallel power module;

[0046] Figure 2 This is a schematic diagram of the drive path and power path in an existing four-parallel power module;

[0047] Figure 3 This is a schematic diagram of the structure of the IGBT and FRD power semiconductor module described in the embodiments of this application;

[0048] Figure 4 This is a schematic diagram of the substrate structure in an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of the interconnect substrate structure in an embodiment of this application;

[0050] Figure 6 This is a schematic diagram of the interconnect copper layer structure in an embodiment of this application;

[0051] Figure 7 This is a schematic diagram showing the distribution of the upper bridge chipset and the lower bridge chipset in an embodiment of this application;

[0052] Figure 8 This is a schematic diagram of the structure of the IGBT and FRD power semiconductor module (excluding interconnect pads and interconnect substrate) described in the embodiments of this application;

[0053] Figure 9 This is a schematic diagram of the structure of the IGBT and FRD power semiconductor module (excluding the interconnect substrate) described in the embodiments of this application;

[0054] Figure 10 This is a schematic diagram of the driving path and the driving path in the embodiments of this application;

[0055] Figure 11 This is a schematic diagram of the IGBT and FRD power semiconductor module (with heat dissipation structure) described in the embodiments of this application;

[0056] In the diagram: 1. Temperature sensor; 2. Lower bridge arm gate signal terminal; 3. Lower bridge arm emitter signal terminal; 4. DC negative power electrode terminal; 5. DC positive power electrode terminal; 6. Substrate; 6-a1. Upper bridge gate signal copper layer on substrate; 6-a2. Lower bridge gate signal copper layer on substrate; 6-b1. Upper bridge emitter signal copper layer on substrate; 6-b2. Lower bridge emitter signal copper layer on substrate; 6-c. Upper bridge collector power copper layer on substrate; 6-d. Lower bridge collector power copper layer on substrate; 6-e. Power negative copper layer on substrate; 7. FRD power chip; 8. Signal connector; 8-a1. Upper bridge gate bonding wire; 8-a2. Lower bridge gate bonding wire; 8-b1. Upper bridge emitter bonding wire; 8-b2. Lower bridge emitter bonding wire; 9. IGBT power chip; 10. Interconnect pad layer; 10-a. Upper bridge emitter power interconnect pad layer; 10-b 10-c, Upper and lower bridge power interconnect layers; 10-d, Lower bridge emitter power interconnect layers; 11-Interconnect substrate; 11-a, Insulating ceramic sheet; 11-b, Interconnect copper layer; 11-b1, First part; 11-b2, Second part; 11-c, Signal shielding copper layer. 12. Upper bridge arm gate signal terminal; 13. Upper bridge arm emitter signal terminal; 14. Upper bridge arm collector signal terminal; 15. Output power electrode terminal; 16. Power chip area; 17. Power path; 18. Drive path; 19. Heat dissipation structure; 20-a. Upper bridge drain power copper layer on substrate; 20-b. Upper and lower bridge power interconnect copper layers on the first substrate; 20-c. Upper and lower bridge power interconnect copper layers on the second substrate; 20-d. Substrate power negative electrode copper layer; 21-a. Upper bridge source power interconnect copper busbar; 21-b. Upper and lower bridge interconnect copper busbar; 21-c. Lower bridge source power interconnect copper busbar.

[0057] The arrows in the diagram indicate the direction of current flow. Detailed Implementation

[0058] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0059] like Figure 3 As shown in the embodiment of this application, an IGBT and FRD power semiconductor module includes a substrate 6, and a plurality of power electrode terminals, a plurality of signal terminals, an upper bridge chipset, a lower bridge chipset, a signal connector 8, an interconnect pad layer 10, and an interconnect substrate 11 disposed on the substrate 6.

[0060] like Figure 3 As shown in the embodiment of this application, the substrate 6 is provided with an upper bridge chip group region, a substrate power negative electrode copper layer 6-e, and a lower bridge chip group region from one side to the other. The upper bridge chip group region includes a substrate upper bridge gate signal copper layer 6-a1, a substrate upper bridge emitter signal copper layer 6-b1, and a substrate upper bridge collector power copper layer. The lower bridge chip group region includes a substrate lower bridge gate signal copper layer 6-a2, a substrate lower bridge emitter signal copper layer 6-b2, and a substrate lower bridge collector power copper layer 6-d.

[0061] like Figure 3 As shown in the embodiments of this application, the plurality of power electrode terminals include a DC negative power electrode terminal 4, a DC positive power electrode terminal 5, and an output power electrode terminal 15, which are respectively connected to the substrate power negative electrode copper layer 6-e, the substrate upper bridge collector power copper layer and the substrate lower bridge collector power copper layer 6-d.

[0062] like Figure 3 As shown in the embodiment of this application, the plurality of signal terminals include an upper bridge arm gate signal terminal 12, an upper bridge arm emitter signal terminal 13, a lower bridge arm gate signal terminal 2, and a lower bridge arm emitter signal terminal 3, which are respectively connected to the upper bridge gate signal copper layer 6-a1, the upper bridge emitter signal copper layer 6-b1, the lower bridge gate signal copper layer 6-a2, and the lower bridge emitter signal copper layer 6-b2 on the substrate.

[0063] like Figure 3As shown in the embodiments of this application, the upper bridge chipset includes an FRD power chip 7 (e.g., a silicon-based FRD power chip) and an IGBT power chip 9 (e.g., a silicon-based IGBT power chip) respectively disposed on the power copper layer of the upper bridge collector on the substrate.

[0064] like Figure 3 As shown in the embodiment of this application, the lower bridge chipset includes an FRD power chip 7 and an IGBT power chip 9 respectively disposed on the power copper layer 6-d of the lower bridge collector of the substrate.

[0065] like Figure 3 As shown in the embodiment of this application, the signal connector 8 is used to connect the upper bridge gate signal copper layer 6-a1, the upper bridge emitter signal copper layer 6-b1, the lower bridge gate signal copper layer 6-a2, and the lower bridge emitter signal copper layer 6-b2 of the substrate to the driving area of ​​the corresponding IGBT power chip 9.

[0066] like Figure 3 As shown in the embodiment of this application, the interconnect pad layer 10 is disposed on the upper bridge chipset region, the lower bridge chipset region and the substrate power negative electrode copper layer 6-e.

[0067] like Figure 3 As shown in the embodiment of this application, the interconnect substrate 11 is disposed on the interconnect pad layer 10.

[0068] In this embodiment, the upper bridge arm gate signal terminal 12, the upper bridge arm emitter signal terminal 13, the lower bridge arm gate signal terminal 2, and the lower bridge arm emitter signal terminal 3 are respectively connected to the driving areas of the IGBT power chips 9 in the upper and lower bridge chipsets through corresponding signal connectors 8 to form a driving path; the DC positive power electrode terminal 5 is respectively connected to the DC negative power electrode terminal 4 through the power copper layer, chipset, interconnect pad layer 10, and interconnect substrate 11 on the substrate 6 to form a power path; and the driving path and the power path have no overlapping areas in space.

[0069] like Figure 4 As shown, in one possible embodiment, the upper bridge gate signal copper layer 6-a1, the upper bridge emitter signal copper layer 6-b1, and the upper bridge collector power copper layer are all disposed on the right side of the substrate 6 and extend along the length direction of the substrate 6. The lower bridge gate signal copper layer 6-a2, the lower bridge emitter signal copper layer 6-b2, and the lower bridge collector power copper layer 6-d are all disposed on the left side of the substrate 6 and extend along the length direction of the substrate 6. The substrate power negative copper layer 6-e is disposed in the region between the upper bridge collector power copper layer 6-c and the lower bridge collector power copper layer 6-d.

[0070] like Figure 3As shown, in one possible embodiment, the temperature sensor 1 is disposed at the lower left corner of the substrate 6.

[0071] like Figure 4 As shown, in one possible embodiment, one end of the lower bridge arm gate signal terminal 2 is connected to the lower bridge gate signal copper layer 6-a2 of the substrate. One end of the lower bridge arm emitter signal terminal 3 is connected to the lower bridge emitter signal copper layer 6-b2 of the substrate. One end of the DC negative power electrode terminal 4 is connected to the power negative copper layer 6-e of the substrate. One end of the DC positive power electrode terminal 5 is connected to the upper bridge collector power copper layer 6-c of the substrate. Furthermore, the lower bridge arm gate signal terminal 2, the lower bridge arm emitter signal terminal 3, the DC negative power electrode terminal 4, and the DC positive power electrode terminal 5 are all located at the first end of the substrate 6.

[0072] like Figure 8 As shown, in one possible embodiment, the upper bridge chipset includes two FRD power chips 7 and two IGBT power chips 9, which are respectively disposed crosswise on the upper bridge collector power copper layer 6-c of the substrate. The lower bridge chipset includes two FRD power chips 7 and two IGBT power chips 9, which are respectively disposed crosswise on the lower bridge collector power copper layer 6-d of the substrate.

[0073] like Figure 8 As shown, in one possible embodiment, the signal connector 8 includes an upper bridge gate bonding wire 8-a1 connecting the upper bridge gate signal copper layer 6-a1 of the substrate and the IGBT power chip 9, a lower bridge gate bonding wire 8-a2 connecting the lower bridge gate signal copper layer 6-a2 of the substrate and the lower bridge gate bonding wire 8-a2 connecting the upper bridge emitter signal copper layer 6-b1 of the substrate and the upper bridge emitter bonding wire 8-b1 connecting the upper bridge emitter signal copper layer 6-b2 of the substrate and the lower bridge emitter bonding wire 8-b2 connecting the lower bridge emitter signal copper layer 6-b2 of the substrate and the lower bridge emitter bonding wire 8-b2 connecting the lower bridge emitter signal copper layer 6-b2 of the substrate and the IGBT power chip 9.

[0074] like Figure 9 As shown, in one possible embodiment, the interconnect layer 10 includes upper bridge emitter power interconnect layer 10-a disposed on each upper bridge chip group, two upper and lower bridge power interconnect layers 10-b disposed on the lower bridge collector power copper layer 6-d of the substrate, lower bridge emitter power interconnect layers 10-c disposed on each lower bridge chip group, and four lower bridge and DC negative interconnect layers 10-d disposed on the power negative copper layer 6-e of the substrate.

[0075] like Figure 5 , Figure 6 and Figure 10As shown, in one possible embodiment, the interconnect substrate 11 includes an interconnect copper layer 11-b, an insulating ceramic sheet 11-a, and a signal shielding copper layer 11-c that are sequentially stacked. The interconnect copper layer 11-b includes a first portion 11-b1 and a second portion 11-b2. The first portion 11-b1 can cover all the lower bridge emitter power interconnect pad layers 10-c and all the lower bridge and DC negative interconnect pad layers 10-d. The second portion 11-b2 can cover all the upper bridge emitter power interconnect pad layers 10-a and all the upper and lower bridge power interconnect pad layers 10-b.

[0076] like Figure 4 As shown, in one possible embodiment, one end of the upper bridge arm gate signal terminal 12 is connected to the upper bridge gate signal copper layer 6-a1 on the substrate. One end of the upper bridge arm emitter signal terminal 13 is connected to the upper bridge emitter signal copper layer 6-b1 on the substrate. One end of the upper bridge arm collector signal terminal 14 is connected to the upper bridge collector power copper layer 6-c on the substrate. One end of the output power electrode terminal 15 is connected to the lower bridge collector power copper layer 6-d on the substrate. Furthermore, the upper bridge arm gate signal terminal 12, upper bridge arm emitter signal terminal 13, upper bridge arm collector signal terminal 14, and output power electrode terminal 15 are all located at the second end of the substrate 6.

[0077] like Figure 8 and Figure 10 As shown in the embodiments of this application, in the IGBT and FRD power semiconductor modules, the driving path 18 (the driving path is the chip control signal path, generally a small current) includes a gate path and an emitter path, wherein: the gate path includes an upper bridge gate path and a lower bridge gate path, which are symmetrically arranged at 180° with the center as the origin; the emitter path includes an upper bridge emitter path and a lower bridge emitter path, which are symmetrically arranged at 180° with the center as the origin. The specific details of each path are as follows:

[0078] Upper bridge gate path: from the upper bridge arm gate signal terminal 12 through the upper bridge gate signal copper layer 6-a1 on the substrate and the upper bridge gate bonding wire 8-a1 to the gate region of the IGBT power chip 9 in the upper bridge chipset;

[0079] Upper bridge emitter path: from the upper bridge arm emitter signal terminal 13 through the upper bridge emitter signal copper layer 6-b1 on the substrate and the upper bridge emitter bonding wire 8-b1 to the Kelvin emitter region of the IGBT power chip 9 in the upper bridge chipset;

[0080] Lower bridge gate path: from the lower bridge arm gate signal terminal 2 through the substrate lower bridge gate signal copper layer 6-a2 and the lower bridge gate bonding wire 8-a2 to the gate region of the IGBT power chip 9 in the lower bridge chipset;

[0081] Lower bridge emitter path: from emitter signal terminal 3 through the lower bridge emitter signal copper layer 6-b2 on the substrate and the lower bridge emitter bonding wire 8-b2 to the Kelvin emitter region of the IGBT power chip 9 in the lower bridge chipset.

[0082] like Figure 9 and 10 As shown in the embodiments of this application, the power path 17 (high current path) in the IGBT and FRD power semiconductor module is as follows:

[0083] From the DC positive power electrode terminal 5, through the upper bridge collector power copper layer 6-c, the upper bridge chipset, the upper bridge emitter power interconnect layer 10-a, the second part 11-b2 of the interconnect copper layer 11-b, the upper and lower bridge power interconnect layers 10-b (i.e., the lower bridge collector power interconnect layer), the lower bridge collector power copper layer 6-d, the lower bridge chipset, the lower bridge emitter power interconnect layer 10-c, the first part 11-b1 of the interconnect copper layer 11-b, the lower bridge and DC negative interconnect layer 10-d, and the substrate power negative copper layer 6-e, to the DC negative power electrode terminal 4.

[0084] In this embodiment of the application, the driving terminals of the upper and lower bridges are respectively arranged on the corresponding emitter terminals, so that the gate path and emitter path are basically the same, reducing the difference in driving parasitic parameters.

[0085] In this embodiment, the drive path and power path have no spatial overlap area, which greatly reduces gate switching oscillation caused by mutual electromagnetic interference.

[0086] In this embodiment, the commutation loop in the power path is significantly reduced compared to existing solutions. For example, the power paths at the chip drain or collector front end and the power interconnection paths between the upper and lower bridges are reduced, resulting in faster commutation. Simultaneously, when the upper and lower bridges are interconnected on the upper substrate, the current paths exhibit reverse cancellation (the number of "opposite current paths" increases throughout the power path, and the magnetic fields generated by opposite currents cancel each other out), thereby reducing loop inductance, lowering switching losses, reducing turn-off spikes, and significantly improving module performance.

[0087] In this embodiment, the FRD power chip 7, the IGBT power chip, and the substrate 6 are interconnected by soldering with soldering material. The temperature sensor 1, lower bridge arm gate signal terminal 2, lower bridge arm emitter signal terminal 3, DC negative power electrode terminal 4, DC positive power electrode terminal 5, upper bridge arm gate signal terminal 12, upper bridge arm emitter signal terminal 13, upper bridge arm collector signal terminal 14, and output power electrode terminal 15 are electrically interconnected with the substrate 6 by soldering with soldering material. The gate / emitter signals of the IGBT power chip 9 are interconnected with the gate / emitter terminals via gate / emitter signal bonding lines. The electrical interconnection between the upper and lower bridge arms of the IGBT power chip 9 is achieved through interconnect pad layers 10 and the interconnect substrate 11. The IGBT power chip 9 and the interconnect pad layers 10 are interconnected by soldering with soldering material. The interconnect pad layers 10 and the interconnect substrate 11 are interconnected by soldering with soldering material.

[0088] In one possible embodiment, the lower bridge arm gate signal terminal 2, the lower bridge arm emitter signal terminal 3, the DC negative power electrode terminal 4, the DC positive power electrode terminal 5, the upper bridge arm gate signal terminal 12, the upper bridge arm emitter signal terminal 13, the upper bridge arm collector signal terminal 14, and the output power electrode terminal 15 are distributed around the substrate 6 and satisfy a certain electrical clearance.

[0089] In one possible embodiment, when the interconnect pad high layer 10 is electrically connected to the interconnect substrate 11, it is connected to the interconnect copper layer 11-b of the interconnect substrate 11.

[0090] like Figure 7 As shown, in one possible embodiment, all components must meet electrical clearance and creepage distance requirements when interconnected. Signal connector 8 must meet electrical clearance requirements when bonded. Various portions of the power chip region 16 must meet electrical clearance and creepage distance requirements.

[0091] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A power semiconductor module using IGBTs and FRDs, characterized in that, include: The substrate (6) has an upper bridge chip group region, a substrate power negative electrode copper layer (6-e) and a lower bridge chip group region arranged sequentially from one side to the other. The upper bridge chip group region includes a substrate upper bridge gate signal copper layer (6-a1), a substrate upper bridge emitter signal copper layer (6-b1) and a substrate upper bridge collector power copper layer (6-c). The lower bridge chip group region includes a substrate lower bridge gate signal copper layer (6-a2), a substrate lower bridge emitter signal copper layer (6-b2) and a substrate lower bridge collector power copper layer (6-d). Multiple power electrode terminals, including a DC negative power electrode terminal (4), a DC positive power electrode terminal (5), and an output power electrode terminal (15) that are respectively connected to the substrate power negative electrode copper layer (6-e), the substrate upper bridge collector power copper layer (6-c), and the substrate lower bridge collector power copper layer (6-d). Multiple signal terminals, including an upper bridge arm gate signal terminal (12), an upper bridge arm emitter signal terminal (13), a lower bridge arm gate signal terminal (2), and a lower bridge arm emitter signal terminal (3) respectively connected to the upper bridge gate signal copper layer (6-a1), the upper bridge emitter signal copper layer (6-b1), the lower bridge gate signal copper layer (6-a2), and the lower bridge emitter signal copper layer (6-b2) on the substrate; The upper bridge chipset includes an FRD power chip (7) and an IGBT power chip (9) respectively disposed on the upper bridge collector power copper layer (6-c) of the substrate. The lower bridge chipset includes an FRD power chip (7) and an IGBT power chip (9) respectively disposed on the power copper layer (6-d) of the lower bridge collector of the substrate. Signal connector (8) is used to connect the upper bridge gate signal copper layer (6-a1), the upper bridge emitter signal copper layer (6-b1), the lower bridge gate signal copper layer (6-a2), and the lower bridge emitter signal copper layer (6-b2) of the substrate to the driving area of ​​the corresponding IGBT power chip (9). Interconnect pad layer (10) is disposed on the upper bridge chipset region, the lower bridge chipset region and the substrate power negative electrode copper layer (6-e); An interconnect substrate (11) is disposed on the interconnect pad layer (10); Among them, the upper bridge arm gate signal terminal (12), upper bridge arm emitter signal terminal (13), lower bridge arm gate signal terminal (2) and lower bridge arm emitter signal terminal (3) are respectively connected to the driving area of ​​the IGBT power chip (9) in the upper bridge chipset and the lower bridge chipset through the corresponding signal connector (8) to form a driving path; the DC positive power electrode terminal (5) is respectively connected to the DC negative power electrode terminal (4) through the power copper layer, chipset, interconnect pad layer (10) and interconnect substrate (11) on the substrate (6) to form a power path; and the driving path and the power path have no overlapping area in space.

2. The IGBT and FRD power semiconductor module according to claim 1, characterized in that, The signal connector (8) includes: The upper bridge gate bonding wire (8-a1) connects the upper bridge gate signal copper layer (6-a1) of the substrate and the IGBT power chip (9); The lower bridge gate bonding wire (8-a2) connects the lower bridge gate signal copper layer (6-a2) of the substrate and the IGBT power chip (9); The upper bridge emitter bonding wire (8-b1) connects the upper bridge emitter signal copper layer (6-b1) of the substrate and the IGBT power chip (9); The lower bridge emitter signal copper layer (6-b2) of the substrate connects the lower bridge emitter signal copper layer (6-b2) and the IGBT power chip (9) via a lower bridge emitter bonding wire (8-b2).

3. The IGBT and FRD power semiconductor module according to claim 2, characterized in that, The driving path includes a gate path, which includes an upper bridge gate path and a lower bridge gate path. The upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin. The upper bridge gate path extends from the upper bridge arm gate signal terminal (12) through the upper bridge gate signal copper layer (6-a1) on the substrate and the upper bridge gate bonding wire (8-a1) to the gate region of the IGBT power chip (9) in the upper bridge chipset; The lower bridge gate path extends from the lower bridge arm gate signal terminal (2) through the substrate lower bridge gate signal copper layer (6-a2) and the lower bridge gate bonding wire (8-a2) to the gate region of the IGBT power chip (9) in the lower bridge chipset.

4. The IGBT and FRD power semiconductor module according to claim 2, characterized in that, The drive path includes an emitter path, which includes an upper bridge emitter path and a lower bridge emitter path. The upper bridge emitter path and the lower bridge emitter path are symmetrically arranged at 180° with the center as the origin. The upper bridge emitter path runs from the upper bridge arm emitter signal terminal (13) through the upper bridge emitter signal copper layer (6-b1) on the substrate, the upper bridge emitter bonding wire (8-b1) to the Kelvin emitter region of the IGBT power chip (9) in the upper bridge chipset; The lower bridge emitter path runs from the lower bridge arm emitter signal terminal (3) through the lower bridge emitter signal copper layer (6-b2) on the substrate, the lower bridge emitter bonding wire (8-b2), to the Kelvin emitter region of the IGBT power chip (9) in the lower bridge chipset.

5. The IGBT and FRD power semiconductor module according to claim 1, characterized in that, The interconnect layer (10) includes an upper bridge emitter power interconnect layer (10-a) disposed on each upper bridge chip group, two upper and lower bridge power interconnect layers (10-b) disposed on the lower bridge collector power copper layer (6-d) of the substrate, lower bridge emitter power interconnect layers (10-c) disposed on each lower bridge chip group, and four lower bridge and DC negative interconnect layers (10-d) disposed on the power negative copper layer (6-e) of the substrate. The interconnect substrate (11) includes an interconnect copper layer (11-b), an insulating ceramic sheet (11-a), and a signal shielding copper layer (11-c) stacked sequentially. The interconnect copper layer (11-b) is divided into a first part (11-b1) that can cover all the lower bridge emitter power interconnect pads (10-c) and all the lower bridge and DC negative interconnect pads (10-d), and a second part (11-b2) that can cover all the upper bridge emitter power interconnect pads (10-a) and all the upper and lower bridge power interconnect pads (10-b).

6. The IGBT and FRD power semiconductor module according to claim 2, characterized in that, The power path runs from the DC positive power electrode terminal (5) through the upper bridge collector power copper layer (6-c), the upper bridge chipset, the upper bridge emitter power interconnect layer (10-a), the second part (11-b2) of the interconnect copper layer (11-b), the upper and lower bridge power interconnect layers (10-b), the lower bridge collector power copper layer (6-d), the lower bridge chipset, the lower bridge emitter power interconnect layer (10-c), the first part (11-b1) of the interconnect copper layer (11-b), the lower bridge and DC negative interconnect layer (10-d), and the substrate power negative copper layer (6-e) to the DC negative power electrode terminal (4).

7. The IGBT and FRD power semiconductor module according to claim 1, characterized in that, The upper bridge chipset includes two FRD power chips (7) and two IGBT power chips (9), which are respectively arranged crosswise on the upper bridge collector power copper layer (6-c) of the substrate; The lower bridge chipset includes two FRD power chips (7) and two IGBT power chips (9), which are respectively arranged crosswise on the lower bridge collector power copper layer (6-d) of the substrate.

8. The IGBT and FRD power semiconductor module according to claim 1, characterized in that, The board bridge gate signal copper layer (6-a1), board bridge emitter signal copper layer (6-b1), and board bridge collector power copper layer (6-c) are all disposed on one side of the board (6) and extend along the length direction of the board (6). The substrate lower bridge gate signal copper layer (6-a2), substrate lower bridge emitter signal copper layer (6-b2), and substrate lower bridge collector power copper layer (6-d) are all disposed on the other side of the substrate (6) and extend along the length direction of the substrate (6).

9. A motor controller, characterized in that: The IGBT and FRD power semiconductor module as described in any one of claims 1 to 8 is used.

10. A car, characterized in that: The motor controller as described in claim 9 is used.

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