A semiconductor light-emitting structure and a preparation method thereof

Abstract

The present invention provides a semiconductor light-emitting structure and a method for preparing the same. The semiconductor light-emitting structure includes: a semiconductor substrate layer; a lower confinement layer located on the semiconductor substrate layer; a lower waveguide layer, an active layer, an upper waveguide layer, and an upper confinement layer that are sequentially stacked on one side of the partial lower confinement layer facing away from the semiconductor substrate layer; an insulating epitaxial layer located on one side of the partial lower confinement layer facing away from the semiconductor substrate layer and on both sides of the lower waveguide layer, the active layer, the upper waveguide layer, and the upper confinement layer in the slow axis direction; a first isolation groove and a second isolation groove. Both the first isolation groove and the second isolation groove pass through the upper confinement layer from the insulating epitaxial layer on one side of the upper confinement layer in the slow axis direction along the slow axis direction and extend into the insulating epitaxial layer on the other side of the upper confinement layer in the slow axis direction. The first isolation groove is located on one side of the second isolation groove facing away from the rear cavity surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor light-emitting structure and a preparation method thereof. Background Art

[0002] A semiconductor light-emitting device is a device that generates stimulated emission using a certain semiconductor material as the working substance. Its working principle is: through a certain excitation method, population inversion of non-equilibrium carriers is achieved between the energy bands (conduction band and valence band) of the semiconductor material, or between the energy band of the semiconductor material and the energy levels of impurities (acceptors or donors). When a large number of electrons and holes in the population inversion state recombine, stimulated emission occurs. Due to its small size and high electro-optical conversion efficiency, semiconductor light-emitting devices are widely used.

[0003] A quantum cascade laser is an important semiconductor light-emitting device. Its spectral range covers the mid-infrared to far-infrared bands and can be used in various aspects such as trace gas detection and free-space optical communication, with broad market application prospects. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is how to improve the power and efficiency of the semiconductor light-emitting structure, and thus provide a semiconductor light-emitting structure and a preparation method thereof.

[0005] The present application provides a semiconductor light-emitting structure, including: a semiconductor substrate layer; a lower confinement layer located on the semiconductor substrate layer; a lower waveguide layer, an active layer, an upper waveguide layer, and an upper confinement layer sequentially stacked on one side of a part of the lower confinement layer facing away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer, and the upper confinement layer have a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction; an insulating epitaxial layer located on one side of a part of the lower confinement layer facing away from the semiconductor substrate layer and on both sides of the lower waveguide layer, the active layer, the upper waveguide layer, and the upper confinement layer in the slow axis direction; a first isolation groove and a second isolation groove, both the first isolation groove and the second isolation groove extend along the slow axis direction from the insulating epitaxial layer on one side of the upper confinement layer in the slow axis direction, pass through the upper confinement layer and extend into the insulating epitaxial layer on the other side of the upper confinement layer in the slow axis direction, and the first isolation groove is located on one side of the second isolation groove facing away from the rear cavity surface; in the cavity length direction, the distance from the first isolation groove to the front cavity surface is much smaller than the distance from the first isolation groove to the rear cavity surface, and the distance from the second isolation groove to the rear cavity surface is much smaller than the distance from the second isolation groove to the front cavity surface.

[0006] Optionally, it further includes: a first insulating filling layer and a second insulating filling layer; wherein, the first insulating filling layer is located in the first isolation groove, and the second insulating filling layer is located in the second isolation groove.

[0007] Optionally, the absolute value of the difference between the refractive index of the first insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.03; the absolute value of the difference between the refractive index of the second insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.03.

[0008] Optionally, the material of the upper limiting layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

[0009] Optionally, the first isolation groove extends in the fast axis direction into the upper confinement layer and does not extend into the upper waveguide layer; or, the first isolation groove extends in the fast axis direction into the upper confinement layer and the upper waveguide layer and does not extend into the active layer; wherein the second isolation groove extends in the fast axis direction into the upper confinement layer and does not extend into the upper waveguide layer; or, the second isolation groove extends in the fast axis direction into the upper confinement layer and the upper waveguide layer and does not extend into the active layer.

[0010] Optionally, the depth dimension of the first isolation groove in the fast axis direction is 1 μm to 6 μm; the depth dimension of the second isolation groove in the fast axis direction is 1 μm to 6 μm.

[0011] Optionally, the width of the first isolation groove in the cavity length direction is 10 μm to 20 μm; the width of the second isolation groove in the cavity length direction is 10 μm to 20 μm.

[0012] Optionally, the spacing distance between the first isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm; the spacing distance between the second isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm.

[0013] Optionally, it also includes: a front electrode layer, which is located on the side of the upper limiting layer, the first insulating filling layer and the second insulating filling layer away from the upper waveguide layer.

[0014] Optionally, it also includes: a first insulating dielectric layer, located between the front cavity surface and the first insulating filling layer and between the front electrode layer and the upper limiting layer; and a second insulating dielectric layer, located between the rear cavity surface and the second insulating filling layer and between the front electrode layer and the upper limiting layer.

[0015] Optionally, the active layer includes a first part and a second part, the first part is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second part is located between the rear cavity surface and the second isolation groove along the cavity length direction; wherein, the size of the first part at one end of the front cavity surface in the slow axis direction is larger than the size of the end of the first part away from the front cavity surface along the cavity length direction in the slow axis direction; the size of the second part at one end of the rear cavity surface in the slow axis direction is larger than the size of the end of the second part away from the rear cavity surface along the cavity length direction in the slow axis direction.

[0016] Optionally, the size of the first part along the slow axis increases from the first isolation groove to the front cavity surface along the cavity length direction; the size of the second part along the slow axis increases from the second isolation groove to the rear cavity surface along the cavity length direction.

[0017] Optionally, the size of the first part at one end of the front cavity surface in the slow axis direction is 15μm~25μm; the size of the first part at the end away from the front cavity surface along the cavity length direction in the slow axis direction is 8μm~12μm; the size of the second part at one end of the rear cavity surface in the slow axis direction is 15μm~25μm; the size of the second part at the end away from the rear cavity surface along the cavity length direction in the slow axis direction is 8μm~12μm.

[0018] The present application also provides a method for preparing a semiconductor light-emitting structure, comprising: providing a semiconductor substrate layer; forming a lower limiting layer on the semiconductor substrate layer; forming a lower waveguide layer, an active layer, an upper waveguide layer and an upper limiting layer stacked in sequence on a side of a portion of the lower limiting layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer have front cavity surfaces and rear cavity surfaces that are opposite in the cavity length direction; forming an insulating epitaxial layer, the insulating epitaxial layer being located on a side of a portion of the lower limiting layer away from the semiconductor substrate layer and being located on the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer. On both sides of the slow axis direction; a first isolation groove and a second isolation groove are formed, and the first isolation groove and the second isolation groove both extend along the slow axis direction from the upper restriction layer in the insulating epitaxial layer on one side of the slow axis direction, pass through the upper restriction layer and extend to the upper restriction layer in the insulating epitaxial layer on the other side of the slow axis direction, and the first isolation groove is located on the side of the second isolation groove away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation groove to the front cavity surface is much smaller than the spacing distance from the first isolation groove to the rear cavity surface, and the spacing distance from the second isolation groove to the rear cavity surface is much smaller than the spacing distance from the second isolation groove to the front cavity surface.

[0019] Optionally, the method further includes: forming a first insulating filling layer in the first isolation trench; and forming a second insulating filling layer in the second isolation trench.

[0020] Optionally, the material of the upper limiting layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

[0021] Optionally, it also includes: forming a first insulating dielectric layer on the side of the upper limiting layer between the front cavity surface and the first insulating filling layer facing away from the active layer, and forming a second insulating dielectric layer on the side of the upper limiting layer between the back cavity surface and the second insulating filling layer facing away from the active layer; forming a front electrode layer on the side of the upper limiting layer, the first insulating dielectric layer, the second insulating dielectric layer, the first insulating filling layer and the second insulating filling layer facing away from the upper waveguide layer.

[0022] Optionally, forming an active layer includes forming a first part and a second part, the first part is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second part is located between the rear cavity surface and the second isolation groove along the cavity length direction; wherein a size of the first part at one end of the front cavity surface in the slow axis direction is larger than a size of the first part at an end of the cavity length away from the front cavity surface in the slow axis direction; a size of the second part at one end of the rear cavity surface in the slow axis direction is larger than a size of the second part at an end of the cavity length away from the rear cavity surface in the slow axis direction.

[0023] The technical solution of the present invention has the following beneficial effects:

[0024] The semiconductor light-emitting structure provided by the technical solution of the present invention is provided with a first isolation groove and a second isolation groove, and the first isolation groove and the second isolation groove both penetrate the upper confinement layer along the slow axis direction. Even if the electron mobility of the upper confinement layer is high, due to the provision of the first isolation groove and the second isolation groove, when current is injected into the interior of the semiconductor light-emitting structure, it is difficult for the electrons to expand in the cavity length direction through the upper confinement layer, thereby reducing the injection current value of the semiconductor light-emitting structure near the front cavity surface and the rear cavity surface. The reduction in the injection current value can effectively suppress the electrical heating near the front cavity surface and the rear cavity surface, thereby reducing the temperature of the front cavity surface and the rear cavity surface, increasing the catastrophic optical damage threshold of the cavity surface, and thus improving the power and efficiency upper limit of the semiconductor light-emitting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 It is a schematic diagram of the three-dimensional structure of a quantum cascade laser in the related art;

[0027] Figure 2 for Figure 1 Schematic diagram of the cross section in the cavity surface direction x and the fast axis direction z;

[0028] Figure 3 A schematic diagram of the three-dimensional structure of a semiconductor light-emitting structure provided in one embodiment of the present application;

[0029] Figure 4 for Figure 3 Schematic diagram of the cross section in the cavity surface direction x and the fast axis direction z;

[0030] Figure 5 A top view of a partial structure of a semiconductor light emitting structure provided by another embodiment of the present application;

[0031] Figure 6 Schematic flow chart of a method for preparing a semiconductor light-emitting structure provided by an embodiment of the present application;

[0032] Figures 7 to 14 Schematic structural diagram of the preparation process of a semiconductor light-emitting structure provided by an embodiment of the present application. Detailed implementation manners

[0033] A quantum cascade laser such as Figure 1 and Figure 2 as shown. Figure 1 Schematic three-dimensional structure diagram of the quantum cascade laser, Figure 2 is Figure 1 Schematic cross-sectional view in the cavity length direction x and the fast axis direction z. The quantum cascade laser includes: a semiconductor substrate layer 100; a lower confinement layer 110 located on the semiconductor substrate layer 100; a lower waveguide layer 120, an active layer 130, an upper waveguide layer 140, and an upper confinement layer 150 that are sequentially stacked on one side of a part of the lower confinement layer 110 facing away from the semiconductor substrate layer 100; the lower waveguide layer 120, the active layer 130, the upper waveguide layer 140, and the upper confinement layer 150 have a front cavity surface and a rear cavity surface that are opposite in the cavity length direction x; an insulating epitaxial layer 160, located on one side of a part of the lower confinement layer 110 facing away from the semiconductor substrate layer 100 and on both sides of the lower waveguide layer 120, the active layer 130, the upper waveguide layer 140, and the upper confinement layer 150 in the slow axis direction y; an antireflection film 170 located on the front cavity surface; a reflection film 180 located on the rear cavity surface. Referring to Figure 2 , the reflection film 180 includes a first isolation film 180a, a main reflection film 180b, and a second isolation film 180c that are sequentially stacked in the cavity length direction. The semiconductor light-emitting structure further includes: a front electrode layer 190 located on one side of the upper confinement layer 150 facing away from the upper waveguide layer 140; a back electrode layer 200 located on one side of the semiconductor substrate layer 100 facing away from the lower confinement layer 110.

[0034] However, the current quantum cascade lasers can meet the basic performance requirements, but there are still many deficiencies.

[0035] On this basis, the embodiments of the present application provide a semiconductor light-emitting structure to improve the power and efficiency of the semiconductor light-emitting structure.

[0036] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0038] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0039] Referring Figure 3 , an embodiment of the present invention provides a semiconductor light-emitting structure, including:

[0040] A semiconductor substrate layer 1;

[0041] A lower confinement layer 2 located on the semiconductor substrate layer 1;

[0042] A lower waveguide layer 3, an active layer 4, an upper waveguide layer 5, and an upper confinement layer 6 that are sequentially stacked on one side of the partial lower confinement layer 2 facing away from the semiconductor substrate layer 1; the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, and the upper confinement layer 6 have a front cavity surface and a rear cavity surface that are opposite to each other in the cavity length direction x;

[0043] An insulating epitaxial layer 7, located on one side of the partial lower confinement layer 2 facing away from the semiconductor substrate layer 1 and on both sides of the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, and the upper confinement layer 6 in the slow axis direction y;

[0044] A first isolation groove 8a and a second isolation groove 8b, both the first isolation groove 8a and the second isolation groove 8b extend from the insulating epitaxial layer 7 on one side of the upper confinement layer 6 in the slow axis direction y along the slow axis direction y, pass through the upper confinement layer 6 and extend into the insulating epitaxial layer 7 on the other side of the upper confinement layer 6 in the slow axis direction y. The first isolation groove 8a is located on the side of the second isolation groove 8b facing away from the rear cavity surface; in the cavity length direction x, the distance from the first isolation groove 8a to the front cavity surface is much smaller than the distance from the first isolation groove 8a to the rear cavity surface, and the distance from the second isolation groove 8b to the rear cavity surface is much smaller than the distance from the second isolation groove 8b to the front cavity surface.

[0045] In the cavity length direction x, the distance from the first isolation groove 8a to the front cavity surface is much smaller than the distance from the first isolation groove 8a to the rear cavity surface, which also means that the first isolation groove 8a is close to the front cavity surface.

[0046] In the cavity length direction x, the spacing distance from the second isolation groove 8b to the rear cavity surface is much smaller than the spacing distance from the second isolation groove 8b to the front cavity surface, which also means that the second isolation groove 8b is close to the rear cavity surface.

[0047] In this embodiment, a first isolation groove 8a and a second isolation groove 8b are provided. Both the first isolation groove 8a and the second isolation groove 8b penetrate the upper confinement layer 6 along the slow axis direction. Even though the electron mobility of the upper confinement layer 6 is high, due to the provision of the first isolation groove 8a and the second isolation groove 8b, when current is injected into the interior of the semiconductor light-emitting structure, it is difficult for electrons to extend in the cavity length direction through the upper confinement layer 6, thereby reducing the injected current values near the front cavity surface and the rear cavity surface of the semiconductor light-emitting structure. The reduction of the injected current values can effectively suppress the electrical heating near the front cavity surface and the rear cavity surface, thereby reducing the temperatures of the front cavity surface and the rear cavity surface, increasing the catastrophic optical damage threshold of the cavity surface, and further raising the upper limits of the power and efficiency of the semiconductor light-emitting structure.

[0048] Figure 3 The lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, and the upper confinement layer 6 form a ridge structure. Figure 3 Taking the semiconductor light-emitting structure having a ridge structure as an example, it can be seen that both the first isolation groove 8a and the second isolation groove 8b penetrate the ridge structure along the slow axis direction y.

[0049] In other embodiments, the semiconductor light-emitting structure has multiple ridge structures along the slow axis direction y.

[0050] In this embodiment, the semiconductor light-emitting structure is taken as an edge-emitting semiconductor laser for illustration, such as a quantum cascade edge-emitting semiconductor laser, and the quantum cascade edge-emitting semiconductor laser includes a mid-infrared quantum cascade edge-emitting semiconductor laser. Further, in this embodiment, a mid-infrared quantum cascade edge-emitting semiconductor laser with a lasing wavelength of 9 μm is taken as an example. The quantum cascade edge-emitting semiconductor laser of this embodiment uses electrons as carriers, and the mobility of electrons is much higher than that of holes. Therefore, both the first isolation groove 8a and the second isolation groove 8b extend from the upper confinement layer 6 into the insulating epitaxial layer 7 on one side of the slow axis direction y along the slow axis direction y, penetrate through the upper confinement layer 6, and extend into the insulating epitaxial layer 7 on the other side of the slow axis direction y of the upper confinement layer 6, effectively blocking the extension of electrons in the cavity length direction.

[0051] In other embodiments, the semiconductor light-emitting structure may not be a quantum cascade edge-emitting semiconductor laser.

[0052] In this embodiment, the semiconductor substrate layer 1 is an InP substrate layer. It should be noted that in other embodiments, the semiconductor substrate layer may also be other materials.

[0053] In one embodiment, the material of the lower confinement layer 2 is InP doped with conductive ions. Based on the characteristics of the mid-infrared quantum cascade edge-emitting semiconductor laser, InP doped with conductive ions is used for the lower confinement layer 2. In a specific embodiment, the conductive ions doped in the lower confinement layer 2 are, for example, Si ions.

[0054] In a specific embodiment, the doping concentration of the conductive ions in the lower confinement layer 2 is 2×10 16 atom / cm 3 . In one embodiment, the thickness of the lower confinement layer 2 is 4 microns. This is only an example here.

[0055] In one embodiment, the material of the lower waveguide layer 3 is In p Ga (1-p) As, where p is greater than zero and less than 1. In a specific embodiment, the conductive ions doped in the lower waveguide layer 3 are, for example, Si ions.

[0056] In a specific embodiment, the doping concentration of the conductive ions in the lower waveguide layer 3 is 2×10 16 atom / cm 3 . In one embodiment, the thickness of the lower waveguide layer 3 is 0.1 micron. This is only an example here.

[0057] In one embodiment, the active layer 4 has a superlattice structure. The active layer 4 includes a plurality of stacked sub-active layer groups. The sub-active layer group includes a first sub-active layer unit to an Mth sub-active layer unit stacked in sequence from bottom to top. M is an integer greater than or equal to 2. Any mth sub-active layer unit includes an mth lower sub-active layer and an mth upper sub-active layer stacked in sequence from bottom to top. m is an integer greater than or equal to 1 and less than or equal to M. The material of the mth lower sub-active layer is In a Ga (1-a) As, and the material of the mth upper sub-active layer is In b Al (1-b) As.

[0058] In a specific embodiment, the thickness of the active layer 4 is 2 microns. This is only an example here.

[0059] In one embodiment, the material of the upper waveguide layer 5 is In p Ga (1-p) As. In one embodiment, the conductive ions doped in the upper waveguide layer 5 are, for example, Si ions.

[0060] In a specific embodiment, the doping concentration of the conductive ions in the upper waveguide layer 5 is 2×10 16 atom / cm 3。In one embodiment, the thickness of the upper waveguide layer 5 is 0.1 micrometer. This is only an example here. In one embodiment, the material of the upper confinement layer 6 is InP doped with conductive ions. In one embodiment, the conductive ions doped in the upper confinement layer 6 are, for example, Si ions.

[0061] In a specific embodiment, the doping concentration of the conductive ions in the upper confinement layer 6 is 2×10 16 atom / cm 3 。In one embodiment, the thickness of the upper confinement layer 6 is 5 micrometers. This is only an example here.

[0062] In one embodiment, the material of the insulating epitaxial layer 7 is InP doped with Fe. The insulating epitaxial layer 7 is non-conductive, and the carriers in the active layer 4 will not pass through the insulating epitaxial layer 7.

[0063] In one embodiment, the semiconductor light-emitting structure further includes: a contact layer (not shown) located on the surface of the upper confinement layer 6 facing away from the upper waveguide layer 5. In one embodiment, the contact layer is an InP contact layer, the contact layer is doped with conductive ions, and the doping concentration of the conductive ions in the contact layer is greater than that of the conductive ions in the upper confinement layer 6.

[0064] Reference Figure 4 , Figure 4 is Figure 3 a schematic cross-sectional view in the cavity length direction x and the fast axis direction z. The semiconductor light-emitting structure further includes: a first insulating filling layer 9a and a second insulating filling layer 9b; wherein, the first insulating filling layer 9a is located in the first isolation groove 8a, and the second insulating filling layer 9b is located in the second isolation groove 8b. Since the first isolation groove 8a and the second isolation groove 8b are filled with air when not filled, and the refractive index of air is very different from that of the upper confinement layer 6, the light field distribution at the positions of the first isolation groove 8a and the second isolation groove 8b is significantly different from the light field distribution at the positions in the upper confinement layer 6 far from the first isolation groove 8a and the second isolation groove 8b, thus affecting the optical transmission of the light field along the cavity length direction x. Based on this, in this embodiment, by filling the first insulating filling layer 9a in the first isolation groove 8a and filling the second insulating filling layer 9b in the second isolation groove 8b, the refractive index difference between the first insulating filling layer 9a and the upper confinement layer 6 is reduced, and the refractive index difference between the second insulating filling layer 9b and the upper confinement layer 6 is reduced, which can optimize the light field distribution, reduce the influence on the optical transmission of the light field along the cavity length direction x, improve the performance of the semiconductor light-emitting structure, and further improve the power and efficiency of the semiconductor light-emitting structure.

[0065] In one embodiment, the absolute value of the difference between the refractive index of the first insulating filling layer 9a and the refractive index of the upper confinement layer 6 is less than or equal to 0.03; the absolute value of the difference between the refractive index of the second insulating filling layer 9b and the refractive index of the upper confinement layer 6 is less than or equal to 0.03. The smaller the difference between the refractive index of the first insulating filling layer 9a and the refractive index of the upper confinement layer 6, and the smaller the difference between the refractive index of the second insulating filling layer 9b and the refractive index of the upper confinement layer 6, the stronger the effect of reducing the influence on the optical transmission of the optical field along the cavity length direction x.

[0066] In this embodiment, the material of the upper confinement layer 6 includes InP doped with Si; the material of the first insulating filling layer 9a includes InP doped with Fe; the material of the second insulating filling layer 9b includes InP doped with Fe. The first insulating filling layer 9a and the second insulating filling layer 9b have good electrical insulation characteristics and heat conduction characteristics, which can simultaneously ensure the heat dissipation ability and optical confinement effect of the semiconductor light-emitting structure; at the same time, since the difference between the refractive index of the first insulating filling layer 9a and the refractive index of the upper confinement layer 6 is very small, and the difference between the refractive index of the second insulating filling layer 9b and the refractive index of the upper confinement layer 6 is very small, the influence on the optical transmission of the optical field along the cavity length direction x is effectively reduced.

[0067] In this embodiment, the first isolation groove 8a extends in the fast axis direction z into the upper confinement layer 6 and does not extend into the upper waveguide layer 5. Specifically, the first isolation groove 8a is located in a part of the thickness of the upper confinement layer 6, or the first isolation groove 8a penetrates the upper confinement layer 6 and the bottom surface of the first isolation groove 8a is located at the interface between the upper confinement layer 6 and the upper waveguide layer 5.

[0068] In another embodiment, the first isolation groove 8a extends in the fast axis direction z into the upper confinement layer 6 and the upper waveguide layer 5 and does not extend into the active layer 4. Specifically, the first isolation groove 8a penetrates the upper confinement layer 6 and the bottom surface of the first isolation groove 8a is located in the upper waveguide layer 5, or the first isolation groove 8a penetrates the upper confinement layer 6 and the upper waveguide layer 5 and the bottom surface of the first isolation groove 8a is located at the interface between the upper waveguide layer 5 and the active layer 4.

[0069] When the first isolation groove 8a extends in the fast axis direction z into the upper confinement layer 6 and does not extend into the upper waveguide layer 5; or, when the first isolation groove 8a extends in the fast axis direction z into the upper confinement layer 6 and the upper waveguide layer 5 and does not extend into the active layer 4, since the first isolation groove 8a does not extend into the active layer 4, etching loss to the active layer 4 is avoided.

[0070] In this embodiment, the second isolation groove 8b extends in the fast axis direction z into the upper confinement layer 6 and does not extend into the upper waveguide layer 5. Specifically, the second isolation groove 8b is located in a part of the thickness of the upper confinement layer 6, or the second isolation groove 8b penetrates the upper confinement layer 6 and the bottom surface of the second isolation groove 8b is located at the interface between the upper confinement layer 6 and the upper waveguide layer 5.

[0071] In another embodiment, the second isolation groove 8b extends in the fast axis direction z into the upper confinement layer 6 and the upper waveguide layer 5 and does not extend into the active layer 4. Specifically, the second isolation groove 8b penetrates the upper confinement layer 6 and the bottom surface of the second isolation groove 8b is located in the upper waveguide layer 5, or the second isolation groove 8b penetrates the upper confinement layer 6 and the upper waveguide layer 5 and the bottom surface of the second isolation groove 8b is located at the interface between the upper waveguide layer 5 and the active layer 4.

[0072] When the second isolation groove 8b extends in the fast axis direction z into the upper confinement layer 6 and does not extend into the upper waveguide layer 5; or when the second isolation groove 8b extends in the fast axis direction z into the upper confinement layer 6 and the upper waveguide layer 5 and does not extend into the active layer 4, since the second isolation groove 8b does not extend into the active layer 4, this avoids etching loss to the active layer 4.

[0073] In one embodiment, the depth dimension of the first isolation groove 8a in the fast axis direction z is 1 μm to 6 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm or 6 μm. If the depth dimension of the first isolation groove 8a in the fast axis direction z is less than 1 μm, the limitation on the expansion of electrons in the upper confinement layer 6 along the cavity length direction has certain limitations, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small; if the depth dimension of the first isolation groove 8a in the fast axis direction z is greater than 6 μm, the probability that the first isolation groove 8a extends into the upper waveguide layer 5 and the active layer 4 is large, and the refractive index differences between the upper waveguide layer 5 and the active layer 4 and the first insulating filling layer 9a filled in the first isolation groove 8a are large, thus affecting the transmission of the optical field. Therefore, the depth dimension of the first isolation groove 8a in the fast axis direction z being 1 μm to 6 μm can take into account the above performances at the same time. In a specific embodiment, preferably, the depth dimension of the first isolation groove 8a in the fast axis direction z is 5.5 μm.

[0074] In one embodiment, the depth dimension of the second isolation groove 8b in the fast axis direction z is 1 μm to 6 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm or 6 μm. If the depth dimension of the second isolation groove 8b in the fast axis direction z is less than 1 μm, the limitation on the expansion of electrons in the upper confinement layer 6 along the cavity length direction has certain limitations, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small; if the depth dimension of the second isolation groove 8b in the fast axis direction z is greater than 6 μm, the probability that the second isolation groove 8b extends into the upper waveguide layer 5 and the active layer 4 is large, and the refractive index differences between the upper waveguide layer 5 and the active layer 4 and the second insulating filling layer 9b filled in the second isolation groove 8b are large, thus affecting the transmission of the optical field. Therefore, the depth dimension of the second isolation groove 8b in the fast axis direction z being 1 μm to 6 μm can take into account the above performances at the same time. Preferably, the depth dimension of the second isolation groove 8b in the fast axis direction z is 5.5 μm.

[0075] In one embodiment, the width dimension of the first isolation groove 8a in the cavity length direction x is 10 μm to 20 μm, such as 10 μm, 13 μm, 15 μm, 17 μm, or 20 μm. If the width dimension of the first isolation groove 8a in the cavity length direction x is less than 10 μm, there is a risk that the injected current bypasses the first isolation groove 8a in the cavity length direction x and reaches the cavity surface. There is a situation where the restriction of electrons expanding in the cavity length direction x at local positions is weak, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small. If the width dimension of the first isolation groove 8a in the cavity length direction x is greater than 20 μm, on the one hand, the process time required for etching the first isolation groove 8a and growing the first insulating filling layer 9a is long. On the other hand, it is not conducive to the increase in the length of the region where current is injected into the interior of the semiconductor light-emitting structure in the cavity length direction x, and the degree of increasing the power of the semiconductor light-emitting structure is limited. Therefore, the width dimension of the first isolation groove 8a in the cavity length direction x being 10 μm to 20 μm can take into account the above performances simultaneously.

[0076] In one embodiment, the width dimension of the second isolation groove 8b in the cavity length direction x is 10 μm to 20 μm, such as 10 μm, 13 μm, 15 μm, 17 μm, or 20 μm. If the width dimension of the second isolation groove 8b in the cavity length direction x is less than 10 μm, there is a risk that the injected current bypasses the second isolation groove 8b in the cavity length direction x and reaches the cavity surface. There is a situation where the restriction of electrons expanding in the cavity length direction x at local positions is weak, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small. If the width dimension of the second isolation groove 8b in the cavity length direction x is greater than 20 μm, on the one hand, the process time required for etching the second isolation groove 8b and growing the second insulating filling layer 9b is long. On the other hand, it is not conducive to the increase in the length of the region where current is injected into the interior of the semiconductor light-emitting structure in the cavity length direction x, and the degree of increasing the power of the semiconductor light-emitting structure is limited. Therefore, the width dimension of the second isolation groove 8b in the cavity length direction x being 10 μm to 20 μm can take into account the above performances simultaneously.

[0077] In one embodiment, the distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is 100 μm to 200 μm, for example, 100 μm, 130 μm, 150 μm, 180 μm or 200 μm. If the distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is less than 100 μm, the degree of improvement in the restriction of the expansion of electrons along the cavity length direction is small; if the distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is greater than 200 μm, it is not conducive to the increase in the length of the region for injecting current into the interior of the semiconductor light-emitting structure along the cavity length direction x, and the degree of increasing the power of the semiconductor light-emitting structure is limited. Therefore, the distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x being 100 μm to 200 μm can take into account the above performances simultaneously.

[0078] In one embodiment, the distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is 100 μm to 200 μm, for example, 100 μm, 130 μm, 150 μm, 180 μm or 200 μm. If the distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is less than 100 μm, the degree of improvement in the restriction of the expansion of electrons along the cavity length direction is small; if the distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is greater than 200 μm, it is not conducive to the increase in the length of the region for injecting current into the interior of the semiconductor light-emitting structure along the cavity length direction x, and the degree of increasing the power of the semiconductor light-emitting structure is limited. Therefore, the distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x being 100 μm to 200 μm can take into account the above performances simultaneously.

[0079] In this embodiment, the first isolation groove 8a and the second isolation groove 8b are symmetrically distributed along the cavity length direction x. That is, the depth dimensions of the first isolation groove 8a and the second isolation groove 8b in the fast axis direction z are the same, the width dimensions of the first isolation groove 8a and the second isolation groove 8b in the cavity length direction x are the same, and the distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is the same as the distance between the second isolation groove 8b and the rear cavity surface in the cavity length direction x. This is beneficial to simplifying the process.

[0080] In other embodiments, the first isolation groove 8a and the second isolation groove 8b may be asymmetrically designed along the cavity length direction x.

[0081] Reference Figure 4 , the semiconductor light-emitting structure further includes: a front electrode layer 10 located on the side of the upper confinement layer 6, the first insulating filling layer 9a and the second insulating filling layer 9b away from the upper waveguide layer 5; and a back electrode layer 11 located on the side of the semiconductor substrate layer 1 away from the lower confinement layer 2.

[0082] When the semiconductor light-emitting structure includes a contact layer, the first isolation groove 8a and the second isolation groove 8b also penetrate the contact layer along the fast axis direction, wherein the first insulating filling layer and the second insulating filling layer also penetrate the contact layer along the fast axis direction.

[0083] In this embodiment, the semiconductor light-emitting structure further includes: a first insulating dielectric layer 12a, located between the front cavity surface and the first insulating filling layer 9a and between the front electrode layer 10 and the upper confinement layer 6; and a second insulating dielectric layer 12b, located between the rear cavity surface and the second insulating filling layer 9b and between the front electrode layer 10 and the upper confinement layer 6. In this way, the current of the front electrode layer 10 will not be injected into the upper confinement layer 6 between the front cavity surface and the first insulating filling layer 9a and into the upper confinement layer 6 between the rear cavity surface and the second insulating filling layer 9b.

[0084] When the semiconductor light-emitting structure includes a contact layer, the first insulating dielectric layer 12a is located between the front cavity surface and the first insulating filling layer 9a and between the front electrode layer 10 and the contact layer, and the second insulating dielectric layer 12b is located between the rear cavity surface and the second insulating filling layer 9b and between the front electrode layer 10 and the contact layer.

[0085] In other embodiments, the first insulating dielectric layer and the second insulating dielectric layer may not be provided.

[0086] Continue to refer to Figure 4 , the semiconductor light-emitting structure further includes: an antireflection film 13 located on the front cavity surface; and a high-reflection film 14 located on the rear cavity surface.

[0087] In one embodiment, the material of the antireflection film 13 is Y2O3, Al2O3 or ZrO2. In this embodiment, the material of the antireflection film is Y2O3.

[0088] In one embodiment, the high-reflection film 14 includes a main reflection film 14a, a first isolation film 14b located on one side of the main reflection film 14a along the cavity length direction x, and a second isolation film 14c located on the other side of the main reflection film 14a along the cavity length direction x. In one embodiment, the material of the main reflection film 14a is Au; the material of the first isolation film 14b is Y2O3; the material of the second isolation film 14c is Y2O3.

[0089] In one embodiment, to improve the electrical isolation ability of the first isolation film 14b and the second isolation film 14c, the size of the first isolation film 14b along the cavity length direction x is greater than or equal to 200 nm, such as 200 nm or 250 nm, and the size of the second isolation film 14c along the cavity length direction x is greater than or equal to 200 nm, such as 200 nm or 250 nm.

[0090] Another embodiment of the present invention further provides a semiconductor light-emitting structure, which is different from the above embodiment in that: refer to Figure 5, the active layer 4 includes a first portion 4a and a second portion 4b. The first portion 4a is located between the front cavity surface and the first isolation groove 8a along the cavity length direction x, and the second portion 4b is located between the rear cavity surface and the second isolation groove 8b along the cavity length direction x. The active layer 4 further includes a third portion 4c, and the third portion 4c is located between the first isolation groove 8a and the second isolation groove 8b along the cavity length direction x.

[0091] The lower waveguide layer 3 includes a first lower waveguide portion, a second lower waveguide portion, and a third lower waveguide portion. The first lower waveguide portion is disposed opposite to the first portion 4a in the fast axis direction z, the second lower waveguide portion is disposed opposite to the second portion 4b in the fast axis direction z, and the third lower waveguide portion is disposed opposite to the third portion 4c in the fast axis direction z. The upper waveguide layer 5 includes a first upper waveguide portion, a second upper waveguide portion, and a third upper waveguide portion. The first upper waveguide portion is disposed opposite to the first portion 4a in the fast axis direction z, the second upper waveguide portion is disposed opposite to the second portion 4b in the fast axis direction z, and the third upper waveguide portion is disposed opposite to the third portion 4c in the fast axis direction z. The upper confinement layer 6 includes a first upper confinement portion, a second upper confinement portion, and a third upper confinement portion. The first upper confinement portion is disposed opposite to the first portion 4a in the fast axis direction z, the second upper confinement portion is disposed opposite to the second portion 4b in the fast axis direction z, and the third upper confinement portion is disposed opposite to the third portion 4c in the fast axis direction z.

[0092] In this embodiment, the dimension of one end of the first portion 4a on the front cavity surface in the slow axis direction y is greater than the dimension of the end of the first portion 4a along the cavity length direction x away from the front cavity surface in the slow axis direction y; the dimension of one end of the second portion 4b on the rear cavity surface in the slow axis direction y is greater than the dimension of the end of the second portion 4b along the cavity length direction x away from the rear cavity surface in the slow axis direction y. With such a design, on the premise that the output power of light on the front cavity surface of the semiconductor light-emitting structure is determined, since the dimension of one end of the first portion 4a on the front cavity surface in the slow axis direction y is relatively large, the optical power density on the front cavity surface will decrease, thereby reducing the optical power absorption density on the front cavity surface and suppressing the temperature rise phenomenon on the front cavity surface caused by optical power absorption. On the premise that the output power of light on the front cavity surface of the semiconductor light-emitting structure is determined, since the dimension of one end of the second portion 4b on the rear cavity surface in the slow axis direction y is relatively large, the optical power density on the rear cavity surface will decrease, thereby reducing the optical power absorption density on the rear cavity surface and suppressing the temperature rise phenomenon on the rear cavity surface caused by optical power absorption. Therefore, the catastrophic optical damage threshold of the cavity surface is further suppressed, thereby further improving the power and efficiency of the semiconductor light-emitting structure.

[0093] In one embodiment, the dimension of the third part 4c in the slow axis direction y remains unchanged along the cavity length direction. Exemplarily, the dimension of the third part 4c in the slow axis direction y is equal to the dimension of the end portion of the first part 4a departing from the front cavity surface in the slow axis direction y along the cavity length direction x, and the dimension of the third part 4c in the slow axis direction y is equal to the dimension of the end portion of the second part 4b departing from the rear cavity surface in the slow axis direction y along the cavity length direction x.

[0094] In this embodiment, the semiconductor light emitting structure further includes: an antireflection film 13 located on the front cavity surface; a high reflection film 14 located on the rear cavity surface. The descriptions of the antireflection film 13 and the high reflection film 14 refer to the foregoing embodiments. Although the thicknesses of both the first isolation film 14b and the second isolation film 14c are relatively large, the dimension setting of the second part 4b compensates for the influence of the thicknesses of the first isolation film 14b and the second isolation film 14c on the light power absorption of the rear cavity surface, reducing the probability of catastrophic optical damage occurring on the rear cavity surface. The dimension setting of the first part 4a compensates for the influence of the material of the antireflection film 13 on the light power absorption of the rear cavity surface, reducing the probability of catastrophic optical damage occurring on the front cavity surface.

[0095] Since in this embodiment, the probability of catastrophic optical damage occurring on the front cavity surface is reduced by the dimension setting of the first part 4a, there is no need to limit the dimension of the antireflection film 13 along the cavity length direction to reduce the probability of catastrophic optical damage occurring on the front cavity surface. Thus, the dimension range of the antireflection film 13 along the cavity length direction x can be selected within a relatively wide range, and the reflectivity of the front cavity surface can be effectively adjusted.

[0096] In one embodiment, along the cavity length direction x from the first isolation groove 8a to the front cavity surface, the dimension of the first part 4a in the slow axis direction y increases; along the cavity length direction x from the second isolation groove 8b to the rear cavity surface, the dimension of the second part 4b in the slow axis direction increases. The first part 4a smoothly transitions along the cavity length direction x from the first isolation groove 8a to the front cavity surface, and the second part 4b smoothly transitions along the cavity length direction x from the second isolation groove 8b to the rear cavity surface, which is beneficial to improving the stability of the cavity surface and the process operation is simple and convenient.

[0097] In one embodiment, the dimension of one end portion of the first part 4a on the front cavity surface in the slow axis direction y is 15 μm to 25 μm, for example, 15 μm, 20 μm or 25 μm; the dimension of the end portion of the first part 4a departing from the front cavity surface along the cavity length direction x in the slow axis direction y is 8 μm to 12 μm, for example, 8 μm, 10 μm or 12 μm. In this embodiment, preferably, the dimension of one end portion of the first part 4a on the front cavity surface in the slow axis direction y is 20 μm; the dimension of the end portion of the first part 4a departing from the front cavity surface along the cavity length direction x in the slow axis direction y is 10 μm.

[0098] In one embodiment, the size of one end of the second part 4b on the rear cavity surface in the slow axis direction y is 15 μm to 25 μm, such as 15 μm, 20 μm or 25 μm; the size of the end of the second part 4b along the cavity length direction x away from the rear cavity surface in the slow axis direction y is 8 μm to 12 μm, such as 8 μm, 10 μm or 12 μm. In this embodiment, preferably, the size of one end of the second part 4b on the rear cavity surface in the slow axis direction y is 20 μm; the size of the end of the second part 4b along the cavity length direction x away from the rear cavity surface in the slow axis direction y is 10 μm.

[0099] In one embodiment, the size of the third part 4c in the slow axis direction y is 8 μm to 12 μm, such as 8 μm, 10 μm or 12 μm. In this embodiment, preferably, the size of the third part 4c in the slow axis direction y is 10 μm.

[0100] For other same contents of this embodiment and the foregoing embodiments, they will not be elaborated herein.

[0101] The present invention further provides a semiconductor light-emitting structure, which is jointly constituted by all the features of the foregoing embodiments, that is, through the combination manner of the foregoing embodiments.

[0102] Another embodiment of the present invention further provides a preparation method of a semiconductor light-emitting structure, referring to Figure 6 , including:

[0103] S1: Provide a semiconductor substrate layer;

[0104] S2: Form a lower confinement layer on the semiconductor substrate layer;

[0105] S3: Form a lower waveguide layer, an active layer, an upper waveguide layer and an upper confinement layer which are sequentially stacked on one side of the partial lower confinement layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer have a front cavity surface and a rear cavity surface which are opposite in the cavity length direction;

[0106] S4: Form an insulating epitaxial layer, and the insulating epitaxial layer is located on one side of the partial lower confinement layer away from the semiconductor substrate layer and on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer in the slow axis direction;

[0107] S5: Form a first isolation groove and a second isolation groove. Both the first isolation groove and the second isolation groove extend from the insulating epitaxial layer on one side of the upper confinement layer in the slow axis direction along the slow axis direction, pass through the upper confinement layer and extend into the insulating epitaxial layer on the other side of the upper confinement layer in the slow axis direction. The first isolation groove is located on one side of the second isolation groove away from the rear cavity surface; in the cavity length direction, the interval distance from the first isolation groove to the front cavity surface is much smaller than the interval distance from the first isolation groove to the rear cavity surface, and the interval distance from the second isolation groove to the rear cavity surface is much smaller than the interval distance from the second isolation groove to the front cavity surface.

[0108] The method for preparing the semiconductor light-emitting structure further includes: forming a front electrode layer on the sides of the upper confinement layer, the first insulating filling layer, and the second insulating filling layer facing away from the upper waveguide layer; and forming a first insulating dielectric layer and a second insulating dielectric layer, where the first insulating dielectric layer is located between the front cavity surface and the first insulating filling layer and between the front electrode layer and the upper confinement layer; the second insulating dielectric layer is located between the rear cavity surface and the second insulating filling layer and between the front electrode layer and the upper confinement layer.

[0109] The following refers to Figures 7 to 14 to introduce in detail the preparation process of the semiconductor light-emitting structure in this embodiment.

[0110] Referring to Figure 7 , a semiconductor substrate layer 1 is provided; an initial lower confinement layer 2a is formed on the semiconductor substrate layer 1; a stacked initial lower waveguide layer 3a, an initial active layer 4a, an initial upper waveguide layer 5a, and an initial upper confinement layer 6a are sequentially formed on the side of the initial lower confinement layer 2a facing away from the semiconductor substrate layer 1.

[0111] In one embodiment, it further includes: forming an initial contact layer on the side of the initial upper confinement layer 6a facing away from the initial upper waveguide layer 5a.

[0112] Referring to Figure 8 , the initial upper confinement layer 6a, the initial upper waveguide layer 5a, the initial active layer 4a, the initial lower waveguide layer 3a, and a part of the initial lower confinement layer 2a are etched to form a lower waveguide layer 3 from the initial lower waveguide layer 3a, an active layer 4 from the initial active layer 4a, an upper waveguide layer 5 from the initial upper waveguide layer 5a, an upper confinement layer 6 from the initial upper confinement layer 6a, and a lower confinement layer 2 from the initial lower confinement layer 2a.

[0113] In some embodiments, it further includes: etching the initial contact layer to form a contact layer, and the contact layer is located on the side of the upper confinement layer 6 facing away from the upper waveguide layer 5.

[0114] For the material description, doping concentration description, and thickness description of the lower waveguide layer 3, the upper confinement layer 6, the lower confinement layer 2, the active layer 4, and the upper waveguide layer 5, refer to the description of the foregoing embodiments. For the description of the contact layer, refer to the description of the foregoing embodiments.

[0115] In this embodiment, the process of etching the initial upper confinement layer 6a, the initial upper waveguide layer 5a, the initial active layer 4a, the initial lower waveguide layer 3a, and a part of the initial lower confinement layer 2a includes a combination of one or both of a dry etching process and a wet etching process.

[0116] Figure 8 In the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, and the upper confinement layer 6 form a ridge structure. Figure 8In the figure, one ridge structure is provided along the slow axis direction y as an illustration. In other embodiments, the semiconductor light emitting structure has a plurality of ridge structures along the slow axis direction y.

[0117] In other embodiments, the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, the upper confinement layer 6 and the contact layer constitute a ridge structure.

[0118] Continue to refer Figure 8 , forming an insulating epitaxial layer 7, the insulating epitaxial layer 7 is located on the side of the lower confinement layer 2 away from the semiconductor substrate layer 1, and on both sides of the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5 and the upper confinement layer 6 in the slow axis direction y.

[0119] The process of forming the insulating epitaxial layer 7 is an epitaxial growth process.

[0120] In one embodiment, the material of the insulating epitaxial layer 7 includes InP doped with Fe. The insulating epitaxial layer 7 is non-conductive, and the carriers in the active layer 4 will not pass through the insulating epitaxial layer 7.

[0121] Combined with reference Figure 9 and Figure 10 , Figure 9 for Figure 8 Schematic diagram of the three-dimensional structure etched on the basis of Figure 10 for Figure 9 A schematic cross-sectional view along the cavity length direction x and the fast axis direction z. A first isolation groove 8a and a second isolation groove 8b are formed.

[0122] Both the first isolation groove 8a and the second isolation groove 8b extend along the slow axis direction y from the insulating epitaxial layer 7 on one side of the upper restriction layer 6 in the slow axis direction y, pass through the upper restriction layer 6 and extend to the insulating epitaxial layer 7 on the other side of the upper restriction layer 6 in the slow axis direction y. The first isolation groove 8a is located on the side of the second isolation groove 8b away from the rear cavity surface. In the cavity length direction x, the spacing distance from the first isolation groove 8a to the front cavity surface is much smaller than the spacing distance from the first isolation groove 8a to the rear cavity surface, and the spacing distance from the second isolation groove 8b to the rear cavity surface is much smaller than the spacing distance from the second isolation groove 8b to the front cavity surface.

[0123] In this embodiment, the process of forming the first isolation groove 8a and the second isolation groove 8b includes an etching process. Figure 9 and Figure 10 The steps of forming the first isolation groove 8a and the second isolation groove 8b include: forming a patterned mask layer 12 on the surface of the upper restriction layer 6 facing away from the semiconductor substrate layer 1; etching a portion of the upper restriction layer 6 using the patterned mask layer 12 as a mask to form the first isolation groove 8a and the second isolation groove 8b.

[0124] The material of the patterned mask layer 12 includes, but is not limited to, silicon dioxide.

[0125] In this embodiment, the first isolation groove 8a extends in the fast axis direction z into the upper confinement layer 6 and does not extend into the upper waveguide layer 5, and the second isolation groove 8b extends in the fast axis direction z into the upper confinement layer 6 and does not extend into the upper waveguide layer 5. In other embodiments, the first isolation groove extends in the fast axis direction into the upper confinement layer and the upper waveguide layer and does not extend into the active layer, and the second isolation groove extends in the fast axis direction into the upper confinement layer and the upper waveguide layer and does not extend into the active layer.

[0126] The arrangement description and size definition of the first isolation groove 8a and the second isolation groove 8b refer to the description of the foregoing embodiments.

[0127] When forming the contact layer, both the first isolation groove 8a and the second isolation groove 8b penetrate the contact layer along the fast axis direction.

[0128] Reference Figure 11 , a first insulating filling layer 9a is formed in the first isolation groove 8a; a second insulating filling layer 9b is formed in the second isolation groove 8b.

[0129] The second insulating filling layer 9b is formed during the process of forming the first insulating filling layer 9a, which simplifies the process.

[0130] When forming the contact layer, both the first insulating filling layer 9a and the second insulating filling layer 9b penetrate the contact layer along the fast axis direction.

[0131] The process for forming the first insulating filling layer 9a is metal organic chemical vapor deposition process or hydride vapor phase epitaxy process. The process for the second insulating filling layer 9b is metal organic chemical vapor deposition process or hydride vapor phase epitaxy process.

[0132] In one embodiment, the description of the relationship between the refractive indices of the first insulating filling layer 9a and the second insulating filling layer 9b and the upper confinement layer 6 refers to the description of the foregoing embodiments. The material description of the first insulating filling layer 9a and the second insulating filling layer 9b refers to the foregoing embodiments.

[0133] Reference Figure 12 , the patterned mask layer 12 is removed.

[0134] Reference Figure 12 , a first insulating dielectric layer 12a is formed on the side of the upper confinement layer 6 facing away from the active layer 4 between the front cavity surface and the first insulating filling layer 9a, and a second insulating dielectric layer, a second insulating dielectric layer 12b is formed on the side of the upper confinement layer 6 facing away from the active layer 4 between the rear cavity surface and the second insulating filling layer 9b.

[0135] The material of the first insulating dielectric layer 12a includes but is not limited to silicon dioxide; the material of the second insulating dielectric layer 12b includes but is not limited to silicon dioxide.

[0136] The positions of the first insulating dielectric layer 12a and the second insulating dielectric layer 12b are described with reference to the foregoing embodiments.

[0137] Reference Figure 13 , a front electrode layer 10 is formed on the sides of the upper confinement layer 6, the first insulating dielectric layer 12a, the second insulating dielectric layer 12b, the first insulating filling layer 9a, and the second insulating filling layer 9b that are away from the upper waveguide layer 5; and a back electrode layer 11 is formed on the side of the semiconductor substrate layer 1 away from the lower confinement layer 2.

[0138] The material of the front electrode layer 10 includes a metallic material, such as gold.

[0139] The material of the back electrode layer 11 includes a metallic material, such as gold.

[0140] Reference Figure 14 , the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, and the upper confinement layer 6 have a front cavity surface and a rear cavity surface that are opposite in the cavity length direction x; an antireflection film 13 is formed on the front cavity surface; and a high-reflection film 14 is formed on the rear cavity surface.

[0141] The description of the structure and material of the antireflection film 13, and the description of the structure and material of the high-reflection film 14 refer to the description of the foregoing embodiments.

[0142] Before forming the antireflection film 13 on the front cavity surface and the high-reflection film 14 on the rear cavity surface, the semiconductor light-emitting structure can be cleaved.

[0143] Another embodiment of the present invention further provides a method for manufacturing a semiconductor light-emitting structure, which is different from the foregoing embodiment in that: Reference Figure 5 , forming the active layer 4 includes: forming a first part 4a and a second part 4b, the first part 4a is located between the front cavity surface and the first isolation groove 8a along the cavity length direction x, and the second part 4b is located between the rear cavity surface and the second isolation groove 8b along the cavity length direction x. It further includes: forming a third part 4c, and the third part 4c is located between the first isolation groove 8a and the second isolation groove 8b along the cavity length direction x.

[0144] Wherein, the dimension of one end of the first part 4a on the front cavity surface in the slow axis direction y is greater than the dimension of the end of the first part 4a along the cavity length direction x away from the front cavity surface in the slow axis direction y; the dimension of one end of the second part 4b on the rear cavity surface in the slow axis direction y is greater than the dimension of the end of the second part 4b along the cavity length direction x away from the rear cavity surface in the slow axis direction y.

[0145] The dimension of the third part 4c in the slow axis direction y is equal to the dimension of the end of the first part 4a along the cavity length direction x away from the front cavity surface in the slow axis direction y, and is equal to the dimension of the end of the second part 4b along the cavity length direction x away from the rear cavity surface in the slow axis direction y.

[0146] Furthermore, in the direction of the cavity length x from the first isolation groove 8a to the front cavity surface, the dimension of the first part 4a in the slow axis direction y increases; in the direction of the cavity length x from the second isolation groove 8b to the rear cavity surface, the dimension of the second part 4b in the slow axis direction increases.

[0147] Regarding the dimension of one end of the first part 4a at the front cavity surface in the slow axis direction y, the dimension of the end of the first part 4a departing from the front cavity surface along the cavity length direction x in the slow axis direction y, the dimension of one end of the second part 4b at the rear cavity surface in the slow axis direction y, the dimension of the end of the second part 4b departing from the rear cavity surface along the cavity length direction x in the slow axis direction y, and the dimension of the third part 4c in the slow axis direction y, refer to the description of the foregoing embodiments.

[0148] Regarding other identical contents of this embodiment and the foregoing embodiments, they will not be elaborated herein.

[0149] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A semiconductor light emitting structure, characterized in that: include: Semiconductor substrate layer; a lower confinement layer located on the semiconductor substrate layer; A lower waveguide layer, an active layer, an upper waveguide layer and an upper limit layer are stacked in sequence on a side of the lower limit layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limit layer have a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction; an insulating epitaxial layer, located on a side of a portion of the lower confinement layer away from the semiconductor substrate layer, and located on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer in a slow axis direction; a first isolation trench and a second isolation trench, wherein the first isolation trench and the second isolation trench both extend along the slow axis direction from the insulating epitaxial layer on one side of the upper confinement layer in the slow axis direction, pass through the upper confinement layer and extend to the insulating epitaxial layer on the other side of the upper confinement layer in the slow axis direction, and the first isolation trench is located on the side of the second isolation trench away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation trench to the front cavity surface is much smaller than the spacing distance from the first isolation trench to the rear cavity surface, and the spacing distance from the second isolation trench to the rear cavity surface is much smaller than the spacing distance from the second isolation trench to the front cavity surface; A first insulating filling layer and a second insulating filling layer; wherein the first insulating filling layer is located in the first isolation trench, and the second insulating filling layer is located in the second isolation trench; The front electrode layer is located on a side of the upper limiting layer, the first insulating filling layer and the second insulating filling layer away from the upper waveguide layer.

2. The semiconductor light emitting structure according to claim 1, characterized in that: The absolute value of the difference between the refractive index of the first insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.03; the absolute value of the difference between the refractive index of the second insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.

03.

3. The semiconductor light emitting structure according to claim 1, characterized in that: The material of the upper confinement layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

4. The semiconductor light emitting structure according to claim 1, characterized in that: The first isolation groove extends into the upper confinement layer in the fast axis direction and does not extend into the upper waveguide layer; or, the first isolation groove extends into the upper confinement layer and the upper waveguide layer in the fast axis direction and does not extend into the active layer; The second isolation groove extends into the upper confinement layer in the fast axis direction but does not extend into the upper waveguide layer; or the second isolation groove extends into the upper confinement layer and the upper waveguide layer in the fast axis direction but does not extend into the active layer.

5. The semiconductor light emitting structure according to claim 1, characterized in that: The depth dimension of the first isolation groove in the fast axis direction is 1 μm to 6 μm; the depth dimension of the second isolation groove in the fast axis direction is 1 μm to 6 μm.

6. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the first isolation groove in the direction of the cavity length is 10 μm to 20 μm; the width of the second isolation groove in the direction of the cavity length is 10 μm to 20 μm.

7. The semiconductor light emitting structure according to claim 1, characterized in that: The spacing distance between the first isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm; the spacing distance between the second isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm.

8. The semiconductor light emitting structure according to claim 1, characterized in that: Also includes: A first insulating dielectric layer, located between the front cavity surface and the first insulating filling layer and between the front electrode layer and the upper limiting layer; and a second insulating dielectric layer, located between the rear cavity surface and the second insulating filling layer and between the front electrode layer and the upper limiting layer.

9. The semiconductor light emitting structure according to any one of claims 1 to 8, characterized in that: The active layer comprises a first portion and a second portion, the first portion is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second portion is located between the rear cavity surface and the second isolation groove along the cavity length direction; Among them, the size of the first part at one end of the front cavity surface in the slow axis direction is larger than the size of the first part at the end away from the front cavity surface along the cavity length direction in the slow axis direction; the size of the second part at one end of the rear cavity surface in the slow axis direction is larger than the size of the second part at the end away from the rear cavity surface along the cavity length direction in the slow axis direction.

10. The semiconductor light emitting structure according to claim 9, characterized in that: In the direction from the first isolation groove to the front cavity surface along the cavity length direction, the size of the first part along the slow axis direction increases gradually; In a direction from the second isolation trench to the rear cavity surface along the cavity length direction, a size of the second portion along the slow axis direction increases gradually.

11. The semiconductor light emitting structure according to claim 9, characterized in that: The size of the first part at one end of the front cavity surface in the slow axis direction is 15 μm to 25 μm; the size of the end of the first part away from the front cavity surface along the cavity length direction in the slow axis direction is 8 μm to 12 μm; The size of the second part at one end of the back cavity surface in the slow axis direction is 15 μm to 25 μm; the size of the second part at the end away from the back cavity surface along the cavity length direction in the slow axis direction is 8 μm to 12 μm.

12. A method for preparing a semiconductor light-emitting structure, characterized in that: include: providing a semiconductor substrate layer; forming a lower confinement layer on the semiconductor substrate layer; A lower waveguide layer, an active layer, an upper waveguide layer and an upper limit layer are sequentially stacked on a side of a portion of the lower limit layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limit layer have a front cavity surface and a rear cavity surface that are opposite to each other in the cavity length direction; forming an insulating epitaxial layer, wherein the insulating epitaxial layer is located on a side of the lower confinement layer away from the semiconductor substrate layer and on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer in a slow axis direction; A first isolation trench and a second isolation trench are formed, wherein the first isolation trench and the second isolation trench both extend along the slow axis direction from the insulating epitaxial layer on one side of the upper confinement layer in the slow axis direction, pass through the upper confinement layer and extend to the insulating epitaxial layer on the other side of the upper confinement layer in the slow axis direction, and the first isolation trench is located on the side of the second isolation trench away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation trench to the front cavity surface is much smaller than the spacing distance from the first isolation trench to the rear cavity surface, and the spacing distance from the second isolation trench to the rear cavity surface is much smaller than the spacing distance from the second isolation trench to the front cavity surface; forming a first insulating filling layer in the first isolation trench; forming a second insulating filling layer in the second isolation trench; A front electrode layer is formed on a side of the upper limiting layer, the first insulating filling layer, and the second insulating filling layer facing away from the upper waveguide layer.

13. The method for preparing a semiconductor light emitting structure according to claim 12, characterized in that: The material of the upper confinement layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

14. The method for preparing a semiconductor light emitting structure according to claim 12, characterized in that: Also includes: A first insulating dielectric layer is formed on a side of the upper limiting layer facing away from the active layer between the front cavity surface and the first insulating filling layer, and a second insulating dielectric layer is formed on a side of the upper limiting layer facing away from the active layer between the back cavity surface and the second insulating filling layer; The forming of the front electrode layer comprises: forming a front electrode layer on a side of the upper limiting layer, the first insulating dielectric layer, the second insulating dielectric layer, the first insulating filling layer and the second insulating filling layer away from the upper waveguide layer.

15. The method for preparing a semiconductor light emitting structure according to claim 12, characterized in that: Forming the active layer includes forming a first portion and a second portion, wherein the first portion is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second portion is located between the rear cavity surface and the second isolation groove along the cavity length direction; Among them, the size of the first part at one end of the front cavity surface in the slow axis direction is larger than the size of the first part at the end away from the front cavity surface along the cavity length direction in the slow axis direction; the size of the second part at one end of the rear cavity surface in the slow axis direction is larger than the size of the second part at the end away from the rear cavity surface along the cavity length direction in the slow axis direction.

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