Load power supply switching circuit

Abstract

The invention belongs to the field of electronic control circuits, and particularly relates to a load power supply switching circuit. According to the specific technical scheme, the circuit comprises an on-off threshold judgment stage, an on-delay stage, a level limiting stage, a buffer driving stage and a load switch M. The load switch M is used for switching on / off the output end of a high-voltage starting circuit and the power supply input end of a load, and an auxiliary power supply is responsible for replacing the high-voltage starting circuit to supply power to the load after the voltage is established; the on-off threshold judgment level generates a first switching signal according to the voltage of the output end of the high-voltage starting circuit; the turn-on delay stage is used for delaying a rising edge of the first switching signal output by the turn-on and turn-off threshold judgment stage so as to generate a second switching signal of a turn-on time sequence; when the voltage of the output end of the high-voltage starting circuit is higher than the set voltage, the level limiting stage transmits a second switching signal meeting the turn-on time sequence to the buffer driving stage; and the buffer driving stage converts the switching signal output by the level limiting stage into a driving signal for driving a load switch M. By combining the output voltage of the high-voltage starting circuit with a novel circuit structure and time sequence matching, the maximum stored energy of a given capacitor is used for supplying power to a load, and the loading capacity of the high-voltage starting circuit is effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of electronic control circuits, and in particular relates to a load power supply switch circuit. Background Art

[0002] In a switching power supply device, in addition to the main power stage responsible for current conversion, the electrical part also has an auxiliary power supply circuit that powers control functions such as controllers, drivers, and sampling circuits. In most application scenarios, the energy for the auxiliary power supply comes from the input side of the power supply. When the power supply system is more complex, the system generally uses a dedicated auxiliary power supply, such as a multi-winding flyback circuit to power the control part; when the device system is relatively simple and the main power stage can provide a stable power supply for the control part after operation, in order to save costs, the system generally uses a self-powered method.

[0003] For self-powered mode, when the voltage difference between the power input side voltage and the control voltage is large, Figure 1 A currently widely used self-powered method is given, that is, a solution using a high-voltage startup chip or a control chip with a high-voltage startup function. The high-voltage startup chip draws power from the high-voltage DC bus in the system to generate a controlled current source to charge the external capacitor. When the capacitor voltage is low, the current source works and the capacitor voltage rises. When the capacitor voltage reaches the set high threshold, the current source is turned off, and the system continues to work on the energy stored in the external capacitor, and the capacitor voltage decreases accordingly; when the capacitor voltage is lower than the set low threshold, the current source is turned on, and this is repeated until the system output is established and can provide the external capacitor with a voltage higher than the high-voltage startup output high threshold through its own output (such as an auxiliary winding) through a diode, and the circuit enters stable operation. The typical working waveform of the high-voltage startup circuit is as follows: Figure 2 The advantage of this method is that the high voltage startup function is turned off after the system works normally, which can reduce system losses.

[0004] However, in a typical 220V AC system, the voltage difference from the high-voltage DC bus to the high-voltage startup chip output is large, and the current source capacity of the chip cannot be set too large, usually around a few milliamperes, to prevent excessive losses and excessive heat accumulation. When the control part of the system has an increased load, such as using a microprocessor with a higher operating current or the main topology using multi-phase parallel connection, the external capacitor voltage cannot be established, or the charging time is too long, the high-voltage startup chip is shut down due to over-temperature protection, and the circuit output cannot be established. The typical capacitor voltage waveform is as follows: Figure 3 shown. Summary of the invention

[0005] In order to solve the above technical problems, an object of the present invention is to provide a load power supply switch circuit.

[0006] To achieve the above-mentioned purpose of the invention, the technical solution adopted by the present invention is: a load power supply switch circuit, including an on / off threshold judgment stage, an on delay stage, a level limiting stage, a buffer driving stage, and a load switch M, wherein the load switch M is used to turn on / off the output end of the high-voltage starting circuit and the load power supply input end, and the auxiliary power supply is responsible for replacing the high-voltage starting circuit to supply power to the load after its voltage is established; the on / off threshold judgment stage generates a first switching signal according to the voltage at the output end of the high-voltage starting circuit; the on delay stage delays the rising edge of the first switching signal output by the on / off threshold judgment stage to generate a second switching signal with an on timing; when the voltage at the output end of the high-voltage starting circuit is higher than the set voltage, the level limiting stage transmits the second switching signal that meets the on timing to the buffer driving stage; the buffer driving stage converts the switching signal output by the level limiting stage into a driving signal for driving the load switch M.

[0007] Preferably, the load switch M is a P-channel MOSFET, including a gate-source capacitor Cgs, a gate-drain capacitor Cgd, and a drain-source capacitor Cds, and the common-source input capacitor Ciss of the MOSFET is the sum of the gate-source capacitor Cgs and the gate-drain capacitor Cgd.

[0008] Preferably, the buffer driving stage is implemented by an N-channel MOSFET and a resistor, converting the high-level signal output by the level limiting stage into an on-signal of the load switch M, and converting the low-level signal output by the level limiting stage into an off-signal of the load switch M.

[0009] Preferably, the on / off threshold judgment stage works through an operational amplifier, or through a three-terminal precision adjustable regulator with an internally integrated reference voltage and a comparator.

[0010] Preferably, the opening delay stage is implemented by an operational amplifier, a logic gate, a diode, a resistor and a capacitor; or, the operation is completed by a MOSFET, a diode, a resistor and a capacitor;

[0011] Preferably, the level limiting stage works through an operational amplifier, a logic gate, a diode, a resistor and a capacitor; or, works through a MOSFET, a diode, a resistor and a capacitor.

[0012] Preferably, the on / off threshold judgment stage includes a first resistor R 1 , the second resistor R 2 、The first op amp U 1 , a first reference power supply Vref1, an output terminal of the high voltage startup circuit and a first resistor R 1 Connect the first resistor R 1 The other end is connected to the first op amp U 1 The positive terminal of the first reference power supply Vref1 is electrically connected to the first operational amplifier U1 The inverting input terminal is electrically connected to the negative terminal of the first reference power supply Vref1 and is grounded; the second resistor R 2 Connect to the first op amp U 1 Between the in-phase input and output terminals; the first op amp U 1 The output terminal is a first switch signal generated according to the voltage at the output terminal of the high-voltage starting circuit;

[0013] The turn-on delay stage includes a first diode D 1 , the second diode D 2 , the third resistor R 3 , the first inverter U 2 , the second inverter U 3 , the first capacitor C 1 , the first op amp U 1 The output terminal and the first diode D 1 Anode, second diode D 2 Cathode electrically connected to the first diode D 1 The cathode and the third resistor R 3 One end is electrically connected to the third resistor R 3 The other end is connected to the second diode D 2 Anode, first inverter U 2 Input terminal, first capacitor C 1 Electrical connection, the first capacitor C 1 The other end is grounded; the first inverter U 2 The output terminal is connected to the second inverter U 3 The input terminal is electrically connected to the second inverter U 3 The output end is a second switch signal that meets the turn-on timing;

[0014] The level limiting stage includes a first AND gate U 4 , the second reference power supply Vref2, the second operational amplifier U 5 The output terminal of the high voltage startup circuit is connected to the second operational amplifier U 5 The positive terminal of the second reference power supply Vref2 is electrically connected to the positive terminal of the second operational amplifier U 5 The inverting input terminal is electrically connected, and the negative terminal of the second reference power supply Vref2 is grounded; the second inverter U 3 The output terminal and the first AND gate U 4 An input terminal is electrically connected to the first AND gate U 4 The other input terminal is connected to the second op amp U 5 Output terminal electrical connection;

[0015] The buffer driver stage includes a fourth resistor R 4 , the fifth resistor R 5 , the first N-channel MOSFET Q 1 , the first AND gate U4 The output terminal is connected to the first N-channel MOSFET Q 1 Gate, fourth resistor R 4 One end is electrically connected to the first N-channel MOSFET Q 1 The source and the fourth resistor R 4 The other end is grounded; the first N-channel MOSFET Q 1 The drain is connected to the gate of the load switch M, and the drain of the load switch M is connected to the load power supply input terminal; the output terminal of the high-voltage startup circuit is connected to the source of the load switch M.

[0016] Preferably, the voltage values ​​at the output end of the high-voltage starting circuit corresponding to the on and off moments of the switch signal are respectively:

[0017]

[0018]

[0019] Where, VoH is the high level value corresponding to the output of the op amp; R 1 , R 2 are the resistance values ​​of the first and second resistors respectively; Vref1 is the voltage value of the first reference power supply; V TH is the voltage value of the output terminal of the high-voltage startup circuit corresponding to the moment when the first switch signal is turned on; V TL is the voltage value of the output end of the high-voltage starting circuit corresponding to the moment when the first switch signal is turned off.

[0020] Preferably, the on / off threshold judgment stage includes a first resistor R 1 , the second resistor R 2 , the third resistor R 3 , the fourth resistor R 4 , the first N-channel MOSFET Q 1 、The fifth N-channel MOSFET Q 5 , the first capacitor C 1 , the first three-terminal precision adjustable voltage regulator U 1 , the output end of the high voltage startup circuit is connected to the first resistor R 1 , the second resistor R 2 Electrical connection: First three-terminal precision adjustable voltage regulator U 1 The reference end and the first resistor R 1 The other end and the third resistor R 3 , the fourth resistor R 4 , the first capacitor C 1 One end is electrically connected; the third resistor R 3 The other end is connected to the fifth N-channel MOSFET Q 5 Drain connection, the fourth resistor R 4 The other end, the fifth N-channel MOSFET Q5 Source, first three-terminal precision adjustable voltage regulator U 1 Anode grounded, the first three-terminal precision adjustable regulator U 1 Cathode and second resistor R 2 and the first capacitor C 1 The other end, the fifth N-channel MOSFET Q 5 Gate, first N-channel MOSFET Q 1 Gate connection: First N-channel MOSFETQ 1 The source of the first N-channel MOSFET Q 1 The drain is a first switch signal generated according to the voltage at the output end of the high-voltage startup circuit;

[0021] The turn-on delay stage includes a fifth resistor R 5 , the second capacitor C 2 , the output end of the high voltage startup circuit and the fifth resistor R 5 One end is connected to the first N-channel MOSFET Q 1 The drain and the fifth resistor R 5 The other end, the second capacitor C 2 One end, the first voltage zener diode ZD 1 Cathode connection; second capacitor C 2 The other end is grounded;

[0022] The level limiting stage includes a sixth resistor R 6 , the seventh resistor R 7 , the eighth resistor R 8 , the first voltage zener diode ZD 1 , the second N-channel MOSFET Q 2 、The third N-channel MOSFET Q 3 , the seventh resistor R 7 , the eighth resistor R 8 One end is connected to the output end of the high voltage starting circuit; the first voltage stabilizing diode ZD 1 Anode and sixth resistor R 6 One end, the second N-channel MOSFET Q 2 Gate connection: Second N-channel MOSFET Q 2 The drain and the seventh resistor R 7 The other end, the third N-channel MOSFET Q 3 Gate connection: Third N-channel MOSFET Q 3 The drain and the eighth resistor R 8 The other end, the fourth N-channel MOSFET Q 4 Gate, ninth resistor R 9 One end is connected to the sixth resistor R 6The other end, the second N-channel MOSFET Q 2 Source, third N-channel MOSFET Q 3 The source is grounded;

[0023] The buffer driver stage includes a ninth resistor R 9 , the tenth resistor R 10 , the fourth N-channel MOSFET Q 4 , the output end of the high voltage startup circuit is connected to the source of the load switch M; the fourth N-channel MOSFET Q 4 The drain is connected to the gate of the load switch M; the ninth resistor R 9 The other end, the fourth N-channel MOSFET Q 4 The source is grounded; the tenth resistor R 10 It is connected between the gate and source of the load switch M, and the drain of the load switch M is connected to the load power supply input terminal.

[0024] Preferably, the voltage values ​​at the output end of the high-voltage starting circuit corresponding to the on and off moments of the first switch signal are respectively:

[0025]

[0026] Where VREF is the internal reference voltage value of the three-terminal precision adjustable regulator; R 1 , R 3 , R 4 are the resistance values ​​of the first, third and fourth resistors respectively; V TH is the voltage value of the output terminal of the high-voltage startup circuit corresponding to the moment when the first switch signal is turned on; V TL is the voltage value of the output end of the high-voltage starting circuit corresponding to the moment when the first switch signal is turned off.

[0027] The present invention has the following beneficial effects:

[0028] The present invention sets an on / off threshold judgment stage, an on / off delay stage, a level limiting stage, a buffer driving stage, and a load switch M. The load switch M is used to turn on and off the output end of the high-voltage startup circuit and the load power supply input end. The auxiliary power supply is responsible for replacing the high-voltage startup circuit to supply power to the load after its voltage is established. By combining the output voltage of the high-voltage startup circuit with the novel circuit structure and timing matching, the maximum energy storage of a given capacitor is used to supply power to the load, thereby effectively improving the load capacity of the high-voltage startup circuit. It has the characteristics of wide application range and strong load capacity; the discrete components used are general electronic component materials, which are convenient and flexible; low power consumption and small system standby loss; simple circuit structure and good economy; small size; insensitive to loop parasitic parameters and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1The conventional high voltage starting circuit described in the background technology;

[0030] Figure 2 The working waveform of the auxiliary power generated by the traditional high-voltage starting circuit and the main circuit of the system as recorded in the background technology;

[0031] Figure 3 It is a typical waveform of a traditional high-voltage starting circuit with a heavier load as described in the background technology;

[0032] Figure 4 This is a block diagram of the load power supply switch circuit of the present invention;

[0033] Figure 5 This is a buffer driver circuit diagram of the present invention;

[0034] Figure 6 This is a load power supply switch circuit diagram of embodiment 1 of the present invention;

[0035] Figure 7 This is the key signal waveform of the load power supply switch circuit in Example 1 of the present invention;

[0036] Figure 8 This is a load power supply switch circuit diagram of embodiment 2 of the present invention;

[0037] Fig. 9 This is a circuit diagram of a power switch system according to Embodiment 3 of the present invention.

[0038] Markings in the accompanying drawings: high-voltage starting circuit output terminal 401, on-off threshold judgment stage 402, first switch signal 403, on-delay stage 404, second switch signal 405, level limiting stage 406, buffer drive stage 407, drive signal 408, load switch M 409, load power supply input terminal 410, auxiliary power supply 411. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Unless otherwise specified, the technical means used in the embodiments are conventional means well known to those skilled in the art.

[0040] like Figure 4As shown, the present invention discloses a load power supply switch circuit, including an on / off threshold judgment stage 402, an on delay stage 404, a level limiting stage 406, a buffer driving stage 407, and a load switch M 409. The load switch M 409 is used to turn on / off the high-voltage startup circuit output terminal 401 and the load power supply input terminal 410, and the auxiliary power supply 411 is responsible for replacing the high-voltage startup circuit to supply power to the load after its voltage is established; the on / off threshold judgment stage 402 generates a first switch signal according to the voltage of the high-voltage startup circuit output terminal 401; the on delay stage 404 delays the rising edge of the first switch signal output by the on / off threshold judgment stage 402 to generate a second switch signal of the on timing; when the voltage of the high-voltage startup circuit output terminal 401 is higher than the set voltage, the level limiting stage 406 transmits the second switch signal that meets the on timing to the buffer driving stage 407; the buffer driving stage 407 further converts the switch signal output by the level limiting stage 406 into a drive signal 408 for driving the load switch M, thereby realizing reliable control of the load switch M 409.

[0041] The load switch M409 used in the present invention is a simplified model of a P-channel MOSFET. The specific MOSFET model also includes a gate-source capacitor Cgs, a gate-drain capacitor Cgd, and a drain-source capacitor Cds. The common-source input capacitor Ciss of the MOSFET is the sum of the gate-source capacitor Cgs and the gate-drain capacitor Cgd.

[0042] Furthermore, the buffer driver stage 407 is implemented by an N-channel MOSFET and a resistor, such as Figure 5 As shown, the high level signal output by the level limiting stage 406 is converted into an on signal of the load switch M409, and the low level signal output by the level limiting stage 406 is converted into an off signal of the load switch M409.

[0043] Furthermore, the on / off threshold determination stage 402 may be implemented by an operational amplifier, or by a three-terminal precision adjustable voltage regulator with an internally integrated reference voltage and a comparator.

[0044] Furthermore, the turn-on delay stage 404 may be implemented by an operational amplifier, a logic gate, a diode, a resistor and a capacitor, or may be implemented by a MOSFET, a diode, a resistor and a capacitor.

[0045] Furthermore, the level limiting stage 406 may be implemented by an operational amplifier, a logic gate, a diode, a resistor and a capacitor, or by a MOSFET, a diode, a resistor and a capacitor.

[0046] The working principle of a load power supply switch circuit disclosed in the present invention is as follows: the circuit includes an on-off threshold judgment circuit, a delay circuit, a level limiting circuit and a high-voltage side drive circuit. By combining the output voltage of the high-voltage starting circuit with a novel circuit structure and timing matching, the maximum energy storage of a given capacitor is used to power the load, thereby effectively improving the load-carrying capacity of the high-voltage starting circuit.

[0047] Example 1

[0048] like Figure 6 As shown, this embodiment discloses a specific implementation of a load power supply switch circuit, the on-off threshold judgment stage 402 includes a first resistor R 1 , the second resistor R 2 、The first op amp U 1 , a first reference power supply Vref1, the output terminal 401 of the high voltage startup circuit is connected to the first resistor R 1 Connect the first resistor R 1 The other end is connected to the first op amp U 1 The positive terminal of the first reference power supply Vref1 is electrically connected to the first operational amplifier U 1 The inverting input terminal is electrically connected to the negative terminal of the first reference power supply Vref1 and is grounded; the second resistor R 2 Connect to the first op amp U 1 Between the in-phase input and output terminals; the first op amp U 1 The output terminal is a first switch signal 403 generated according to the voltage of the output terminal 401 of the high-voltage startup circuit;

[0049] The turn-on delay stage 404 includes a first diode D 1 , the second diode D 2 , the third resistor R 3 , the first inverter U 2 , the second inverter U 3 , the first capacitor C 1 , the first op amp U 1 The output terminal and the first diode D 1 Anode, second diode D 2 Cathode electrically connected to the first diode D 1 The cathode and the third resistor R 3 One end is electrically connected to the third resistor R 3 The other end is connected to the second diode D 2 Anode, first inverter U 2 Input terminal, first capacitor C 1 Electrical connection, the first capacitor C 1 The other end is grounded; the first inverter U 2 The output terminal is connected to the second inverter U 3 The input terminal is electrically connected to the second inverter U3 The output end is a second switch signal 405 that meets the turn-on timing. The rising edge of the second switch signal 405 is delayed by a certain time compared with the rising edge of the first switch signal 403, while their falling edges remain synchronized.

[0050] The level limiting stage 406 includes a first AND gate U 4 , the second reference power supply Vref2, the second operational amplifier U 5 The high voltage startup circuit output terminal 401 is connected to the second operational amplifier U 5 The positive terminal of the second reference power supply Vref2 is electrically connected to the positive terminal of the second operational amplifier U 5 The inverting input terminal is electrically connected, and the negative terminal of the second reference power supply Vref2 is grounded; the second inverter U 3 The output terminal and the first AND gate U 4 An input terminal is electrically connected to the first AND gate U 4 The other input terminal is connected to the second op amp U 5 Output terminal electrical connection;

[0051] The buffer driver stage 407 includes a fourth resistor R 4 , the fifth resistor R 5 , the first N-channel MOSFET Q 1 , the first AND gate U 4 The output terminal is connected to the first N-channel MOSFET Q 1 Gate, fourth resistor R 4 One end is electrically connected to the first N-channel MOSFET Q 1 The source and the fourth resistor R 4 The other end is grounded; the first N-channel MOSFET Q 1 The drain is connected to the gate of the load switch M409 , and the drain of the load switch M409 is connected to the load power supply input terminal 410 ; the output terminal 401 of the high-voltage startup circuit is connected to the source of the load switch M409 .

[0052] Based on Figure 6 As shown in the circuit diagram, the voltage values ​​of the high-voltage startup circuit output terminal 401 corresponding to the on and off moments of the first switch signal 403 are respectively:

[0053]

[0054] Where, VoH is the high level value corresponding to the output of the op amp; R 1 , R 2 are the resistance values ​​of the first and second resistors respectively; Vref1 is the voltage value of the first reference power supply; V TH is the voltage value of the high-voltage startup circuit output terminal 401 corresponding to the first switch signal 403 when it is turned on; V TLis the voltage value of the high-voltage starting circuit output terminal 401 corresponding to the moment when the first switch signal 403 is turned off.

[0055] By reasonably designing the relevant parameters, V TH Set it slightly lower than the high voltage startup circuit output high limit, and set V TL The key signal waveforms of the proposed circuit are shown in Figure 4. Figure 7 As shown, it can ensure that the high voltage startup circuit works normally without over-temperature protection or failure to carry load.

[0056] Example 2

[0057] like Figure 8 As shown, this embodiment also discloses a specific implementation of a load power supply switch circuit, wherein the on-off threshold judgment stage 402 includes a first resistor R 1 , the second resistor R 2 , the third resistor R 3 , the fourth resistor R 4 , the first N-channel MOSFET Q 1 、The fifth N-channel MOSFET Q 5 , the first capacitor C 1 , the first three-terminal precision adjustable voltage regulator U 1 , the high voltage startup circuit output terminal 401 and the first resistor R 1 , the second resistor R 2 Electrical connection: First three-terminal precision adjustable voltage regulator U 1 The reference end and the first resistor R 1 The other end and the third resistor R 3 , the fourth resistor R 4 , the first capacitor C 1 One end is electrically connected; the third resistor R 3 The other end is connected to the fifth N-channel MOSFET Q 5 Drain connection, the fourth resistor R 4 The other end, the fifth N-channel MOSFET Q 5 Source, first three-terminal precision adjustable voltage regulator U 1 Anode grounded, the first three-terminal precision adjustable regulator U 1 Cathode and second resistor R 2 and the first capacitor C 1 The other end, the fifth N-channel MOSFET Q 5 Gate, first N-channel MOSFET Q 1 Gate connection: First N-channel MOSFET Q 1 The source of the first N-channel MOSFET Q 1The drain is a first switch signal 403 generated according to the voltage of the output terminal 401 of the high-voltage startup circuit;

[0058] The turn-on delay stage 404 includes a fifth resistor R 5 , the second capacitor C 2 , the high voltage startup circuit output terminal 401 and the fifth resistor R 5 One end is connected to the first N-channel MOSFET Q 1 The drain and the fifth resistor R 5 The other end, the second capacitor C 2 One end, the first voltage zener diode ZD 1 Cathode connection; second capacitor C 2 The other end is grounded;

[0059] The level limiting stage 406 includes a sixth resistor R 6 , the seventh resistor R 7 , the eighth resistor R 8 , the first voltage zener diode ZD 1 , the second N-channel MOSFET Q 2 、The third N-channel MOSFET Q 3 , the seventh resistor R 7 , the eighth resistor R 8 One end is connected to the output end 401 of the high voltage startup circuit; the first voltage stabilizing diode ZD 1 Anode and sixth resistor R 6 One end, the second N-channel MOSFET Q 2 Gate connection: Second N-channel MOSFET Q 2 The drain and the seventh resistor R 7 The other end, the third N-channel MOSFET Q 3 Gate connection: Third N-channel MOSFET Q 3 The drain and the eighth resistor R 8 The other end, the fourth N-channel MOSFET Q 4 Gate, ninth resistor R 9 One end is connected to the sixth resistor R 6 The other end, the second N-channel MOSFET Q 2 Source, third N-channel MOSFET Q 3 The source is grounded;

[0060] The buffer driver stage 407 includes a ninth resistor R 9 , the tenth resistor R 10 , the fourth N-channel MOSFET Q 4 , the high voltage startup circuit output terminal 401 is connected to the source of the load switch M; the fourth N-channel MOSFET Q 4The drain is connected to the gate of the load switch M 409; the ninth resistor R 9 The other end, the fourth N-channel MOSFET Q 4 The source is grounded; the tenth resistor R 10 The load switch M409 is connected between the gate and the source. The drain of the load switch M409 is connected to the load power supply input terminal 410 .

[0061] Based on Figure 8 As shown in the circuit diagram, the voltage values ​​of the high-voltage startup circuit output terminal 401 corresponding to the on and off moments of the first switch signal 403 are respectively:

[0062]

[0063] Where VREF is the internal reference voltage value of the three-terminal precision adjustable regulator; R 1 , R 3 , R 4 are the resistance values ​​of the first, third and fourth resistors respectively; V TH is the voltage value of the high-voltage startup circuit output terminal 401 corresponding to the first switch signal 403 when it is turned on; V TL is the voltage value of the high-voltage starting circuit output terminal 401 corresponding to the moment when the first switch signal 403 is turned off.

[0064] By reasonably designing the relevant parameters, V TH Set it slightly lower than the high voltage startup circuit output high limit, and set V TL Setting it slightly higher than the low output limit of the high voltage startup circuit can ensure reliable operation of the circuit.

[0065] Example 3

[0066] Based on Figure 8 The driving circuit shown in the embodiment discloses a specific application of the driving circuit, such as Fig. 9 The high-voltage DC bus in the system is connected to the high-voltage pin of the high-voltage startup chip or the control chip with the high-voltage startup function, so as to connect the current source inside the chip to start the high-voltage startup function; the positive end of the electrolytic capacitor is connected to the output end 401 of the high-voltage startup circuit, and the negative end is grounded to store the energy from the current source in the high-voltage startup circuit for use by the load; the output end 401 of the high-voltage startup circuit is externally connected to the auxiliary winding and its rectification structure to replace the high-voltage startup chip to supply power to the load, and one end of an auxiliary winding of the magnetic element in the system is connected to the second diode D 2 The cathode of the diode is connected to the third capacitor C 3 One end and the input end of the linear regulator LDO, the third capacitor C 3 The other end of the linear voltage regulator LDO is connected to the first diode D 1 The anode of the second diode D2 The cathode is connected to the high voltage start output terminal.

[0067] The connection method of other circuit parts is the same as Figure 8 The same is true, see the description of Example 2 for details, which will not be repeated here.

[0068] The embodiments described above are only descriptions of the preferred modes of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations, modifications, and substitutions made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A load power supply switch circuit, characterized in that: The invention comprises an on / off threshold judgment stage (402), an on delay stage (404), a level limiting stage (406), a buffer driving stage (407), and a load switch M (409). The load switch M (409) is used to turn on / off a high-voltage startup circuit output terminal (401) and a load power supply input terminal (410). The auxiliary power supply (411) is responsible for replacing the high-voltage startup circuit to supply power to the load after its voltage is established. The on / off threshold judgment stage (402) generates a first switch signal (403) according to the voltage of the high-voltage startup circuit output terminal (401). The on delay stage (404) generates a first switch signal (403) according to the voltage of the high-voltage startup circuit output terminal (401). The timing stage (404) delays the rising edge of the first switch signal (403) output by the on / off threshold judgment stage (402) to generate a second switch signal (405) of an on timing sequence; when the voltage at the output end (401) of the high-voltage startup circuit is higher than the set voltage, the level limiting stage (406) transmits the second switch signal (405) satisfying the on timing sequence to the buffer driving stage (407); the buffer driving stage (407) converts the switch signal output by the level limiting stage (406) into a drive signal (408) for driving a load switch M (409).

2. A load power supply switch circuit according to claim 1, characterized in that: The load switch M (409) is a P-channel MOSFET, including a gate-source capacitor Cgs, a gate-drain capacitor Cgd, and a drain-source capacitor Cds. The common-source input capacitor Ciss of the MOSFET is the sum of the gate-source capacitor Cgs and the gate-drain capacitor Cgd.

3. A load power supply switch circuit according to claim 1, characterized in that: The buffer driving stage (407) is implemented by an N-channel MOSFET and a resistor, converting a high-level signal output by the level limiting stage (406) into an on-signal of a load switch M (409), and converting a low-level signal output by the level limiting stage (406) into an off-signal of the load switch M (409).

4. A load power supply switch circuit according to claim 1, characterized in that: The on / off threshold judgment stage (402) completes its work through an operational amplifier or a three-terminal precision adjustable voltage regulator with an internal integrated reference voltage and a comparator.

5. A load power supply switch circuit according to claim 1, characterized in that: The turn-on delay stage (404) works through an operational amplifier, a logic gate, a diode, a resistor and a capacitor; or, works through a MOSFET, a diode, a resistor and a capacitor.

6. A load power supply switch circuit according to claim 1, characterized in that: The level limiting stage (406) works through an operational amplifier, a logic gate, a diode, a resistor and a capacitor; or, works through a MOSFET, a diode, a resistor and a capacitor.

7. A load power supply switch circuit according to claim 1, characterized in that: The on / off threshold judgment stage (402) comprises a first resistor R1, a second resistor R2, a first operational amplifier U1, and a first reference power supply Vref1; the output end (401) of the high-voltage startup circuit is connected to the first resistor R1, and the other end of the first resistor R1 is electrically connected to the non-inverting input end of the first operational amplifier U1; the positive end of the first reference power supply Vref1 is electrically connected to the inverting input end of the first operational amplifier U1, and the negative end of the first reference power supply Vref1 is grounded; the second resistor R2 is connected between the non-inverting input end and the output end of the first operational amplifier U1; the output end of the first operational amplifier U1 is a first switch signal (403) generated according to the voltage of the output end (401) of the high-voltage startup circuit; The opening delay stage (404) comprises a first diode D1, a second diode D2, a third resistor R3, a first inverter U2, a second inverter U3, and a first capacitor C1, wherein the output end of the first operational amplifier U1 is electrically connected to the anode of the first diode D1 and the cathode of the second diode D2; the cathode of the first diode D1 is electrically connected to one end of the third resistor R3, the other end of the third resistor R3 is electrically connected to the anode of the second diode D2, the input end of the first inverter U2, and the first capacitor C1, and the other end of the first capacitor C1 is grounded; the output end of the first inverter U2 is electrically connected to the input end of the second inverter U3; the output end of the second inverter U3 is the generated second switch signal (405) that satisfies the opening timing sequence; The level limiting stage (406) comprises a first AND gate U4, a second reference power supply Vref2, and a second operational amplifier U5; the output end (401) of the high voltage startup circuit is electrically connected to the in-phase input end of the second operational amplifier U5; the positive end of the second reference power supply Vref2 is electrically connected to the inverting input end of the second operational amplifier U5; the negative end of the second reference power supply Vref2 is grounded; the output end of the second inverter U3 is electrically connected to an input end of the first AND gate U4; the other input end of the first AND gate U4 is electrically connected to the output end of the second operational amplifier U5; The buffer driver stage (407) comprises a fourth resistor R4, a fifth resistor R5, and a first N-channel MOSFET Q1; the output end of the first AND gate U4 is electrically connected to the gate of the first N-channel MOSFET Q1 and one end of the fourth resistor R4; the source of the first N-channel MOSFET Q1 and the other end of the fourth resistor R4 are grounded; the drain of the first N-channel MOSFET Q1 is connected to the gate of a load switch M (409); the drain of the load switch M (409) is connected to the load power supply input end; the output end (401) of the high-voltage startup circuit is connected to the source of the load switch M (409).

8. A load power supply switch circuit according to claim 7, characterized in that: The voltage values ​​of the high-voltage startup circuit output terminal (409) corresponding to the on and off moments of the first switch signal (403) are respectively: Wherein, VoH is the high level value corresponding to the output of the operational amplifier; R1 and R2 are the resistance values ​​of the first and second resistors respectively; Vref1 is the voltage value of the first reference power supply; V TH is the voltage value of the high-voltage startup circuit output terminal (401) corresponding to the moment when the first switch signal (403) is turned on; V TL is the voltage value of the high-voltage startup circuit output terminal (401) corresponding to the moment when the first switch signal (403) is turned off.

9. A load power supply switch circuit according to claim 1, characterized in that: The on / off threshold judgment stage (402) comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first N-channel MOSFET Q1, a fifth N-channel MOSFET Q5, a first capacitor C1, and a first three-terminal precision adjustable voltage regulator U1. The output end (401) of the high-voltage startup circuit is electrically connected to the first resistor R1 and the second resistor R2; the reference end of the first three-terminal precision adjustable voltage regulator U1 is electrically connected to the other end of the first resistor R1 and the third resistor R3, the fourth resistor R4, and one end of the first capacitor C1; the other end of the third resistor R3 is connected to the drain of the fifth N-channel MOSFET Q5, the other end of the fourth resistor R4, the source of the fifth N-channel MOSFET Q5, and the anode of the first three-terminal precision adjustable voltage regulator U1 are grounded, and the cathode of the first three-terminal precision adjustable voltage regulator U1 is connected to the second resistor R2 and the other end of the first capacitor C1, the gate of the fifth N-channel MOSFET Q5, and the gate of the first N-channel MOSFET Q1; the source of the first N-channel MOSFET Q1 is grounded, and the first N-channel MOSFET Q5 is connected to the gate of the first N-channel MOSFET Q1. The drain of Q1 is a first switching signal (403) generated according to the voltage of the output terminal (401) of the high-voltage startup circuit; The opening delay stage (404) comprises a fifth resistor R5 and a second capacitor C2; the output end (401) of the high voltage startup circuit is connected to one end of the fifth resistor R5; the drain of the first N-channel MOSFET Q1 is connected to the other end of the fifth resistor R5, one end of the second capacitor C2, and the cathode of the first voltage stabilizing diode ZD1; and the other end of the second capacitor C2 is grounded; The level limiting stage (406) comprises a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first voltage stabilizing diode ZD1, a second N-channel MOSFET Q2, and a third N-channel MOSFET Q3; one end of the seventh resistor R7 and the eighth resistor R8 are connected to the output end (401) of the high-voltage startup circuit; the anode of the first voltage stabilizing diode ZD1 is connected to one end of the sixth resistor R6 and the gate of the second N-channel MOSFET Q2; the drain of the second N-channel MOSFET Q2 is connected to the other end of the seventh resistor R7 and the gate of the third N-channel MOSFET Q3; the drain of the third N-channel MOSFET Q3 is connected to the other end of the eighth resistor R8, the gate of the fourth N-channel MOSFET Q4, and one end of the ninth resistor R9; the other end of the sixth resistor R6, the source of the second N-channel MOSFET Q2, and the source of the third N-channel MOSFET Q3 are grounded; The buffer driver stage (407) includes a ninth resistor R9, a tenth resistor R 10 , a fourth N-channel MOSFET Q4, the high voltage startup circuit output terminal (401) is connected to the source of the load switch M (409); the drain of the fourth N-channel MOSFET Q4 is connected to the gate of the load switch M (409); the other end of the ninth resistor R9 and the source of the fourth N-channel MOSFET Q4 are grounded; the tenth resistor R 10 It is connected between the gate and source of the load switch M (409), and the drain of the load switch M (409) is connected to the load power supply input terminal (410).

10. A load power supply switch circuit according to claim 9, characterized in that: The voltage values ​​of the high-voltage startup circuit output terminal (401) corresponding to the on and off moments of the first switch signal (403) are respectively: Where VREF is the internal reference voltage value of the three-terminal precision adjustable regulator; R1, R3, R4 are the resistance values ​​of the first, third, and fourth resistors respectively; V TH is the voltage value of the high-voltage startup circuit output terminal (401) corresponding to the moment when the first switch signal (403) is turned on; V TL is the voltage value of the high-voltage startup circuit output terminal (401) corresponding to the moment when the first switch signal (403) is turned off.

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