Pulse width modulation signal regulator, voltage conversion circuit, and DC power supply

Abstract

An embodiment of the present application provides a pulse width modulation signal regulator for controlling a voltage converter in a DC power supply, the DC power supply comprising a multi-phase voltage converter, the pulse width modulation signal regulator comprising: a current sensor, a feedback circuit configured to be electrically connected to the voltage converter to generate a feedback signal corresponding to an output current of the voltage converter; a duty cycle adjustment signal generation unit configured to receive the feedback signal and a reference signal to generate a duty cycle adjustment signal based on the feedback signal and the reference signal, the reference signal corresponding to the output current of each phase voltage converter in the multi-phase voltage converter reaching an equalized current; and the pulse width modulation signal adjusting unit is configured to receive an initial pulse width modulation signal and the duty ratio adjusting signal so as to adjust the duty ratio of the initial pulse width modulation signal according to the duty ratio adjusting signal, so that a corrected pulse width modulation signal for driving the voltage converter is obtained.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a pulse width modulation signal regulator for controlling a voltage converter, a voltage conversion circuit including the pulse width modulation signal regulator, and a direct current power supply. Background Art

[0002] In order to support the high performance and intelligence of electronic devices, electronic devices usually include functional electronic components with a high degree of integration. These functional electronic components are usually in the form of integrated circuit chips, such as GPU (graphics processing unit). Some functional electronic components in electronic devices (for example, processors for image processing or artificial intelligence calculations) require a large operating current, and the amplitude of the operating current may reach hundreds of amperes or even thousands of amperes. Moreover, the amplitude requirements of the drive current of the new generation of processors are still increasing. A single voltage converter usually cannot provide such a large current. In order to provide a sufficiently large drive current to the load, a feasible solution is to make the DC power supply that supplies power to the load include a multi-phase voltage converter, and connect the output ends of these voltage converters in parallel, thereby obtaining an increased output current. Summary of the invention

[0003] An embodiment of the present application provides a pulse width modulation signal regulator for controlling a voltage converter in a direct current power supply, wherein the direct current power supply includes a multi-phase voltage converter, and the pulse width modulation signal regulator includes: a current sensor, configured to be electrically connected to the voltage converter to generate a feedback signal corresponding to the output current of the voltage converter; a duty cycle adjustment signal generating unit, configured to receive the feedback signal and a reference signal, so as to generate a duty cycle adjustment signal based on the feedback signal and the reference signal, wherein the reference signal corresponds to a balanced current at which the output currents of the voltage converters of each phase in the multi-phase voltage converter reach a balanced state; and a pulse width modulation signal adjusting unit, configured to receive an initial pulse width modulation signal and the duty cycle adjustment signal, so as to adjust the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal, thereby obtaining a corrected pulse width modulation signal for driving the voltage converter.

[0004] According to some embodiments of the present application, the feedback signal is a voltage signal corresponding to the output current of the voltage converter, and the duty cycle adjustment signal generating unit includes: a comparator including a first input terminal, a second input terminal, and an output terminal electrically connected to the pulse width modulation signal adjusting unit, the first input terminal being electrically connected to the output terminal of the current sensor to receive the feedback signal, and the second input terminal being configured to receive the reference signal; a buffer circuit, the input terminal of the buffer circuit being electrically connected to the current sensor to receive the feedback signal and output a buffer signal from the output terminal of the buffer circuit, and the output terminal of the buffer circuit being electrically connected to the second input terminal of the comparator. The comparator generates the duty cycle adjustment signal based on one of the buffer signal or the reference signal and the feedback signal, and the pulse width modulation signal adjusting unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the feedback signal and the reference signal or the buffer signal.

[0005] According to some embodiments of the present application, the buffer circuit includes an operational amplifier and a transistor, the output of the operational amplifier is electrically connected to the control end of the transistor, the first input of the operational amplifier is electrically connected to the first input of the comparator, the second input of the operational amplifier is electrically connected to the second input of the comparator, the first end of the transistor is used to receive a power supply voltage, and the second end of the transistor is electrically connected to the second input of the comparator.

[0006] According to some embodiments of the present application, the buffer circuit includes a first diode, an anode of the first diode is electrically connected to the output terminal of the current sensor, and a cathode of the first diode is electrically connected to the second input terminal of the comparator. The duty cycle adjustment signal generating unit also includes a second diode, an anode and a cathode of the second diode are electrically connected to the output terminal of the current sensor and the first input terminal of the comparator, respectively, wherein the parameters of the first diode and the second diode are the same.

[0007] According to some embodiments of the present application, the feedback signal is a current signal corresponding to the output current of the voltage converter, and the duty cycle adjustment signal generating unit includes: a comparator, which includes a first input terminal, a second input terminal and an output terminal electrically connected to the pulse width modulation signal adjustment unit, and the second input terminal of the comparator is configured to receive the reference signal; a mirror current source, the mirror current source includes a reference current branch and a mirror current branch, the reference current branch is electrically connected to the output terminal of the current sensor and the first input terminal of the comparator, and the mirror current branch is electrically connected to the output terminal of the current sensor and the second input terminal of the comparator; and a first resistor, which is electrically connected between the first input terminal and the reference voltage terminal of the comparator to convert the feedback signal into an intermediate voltage signal, wherein the comparator generates the duty cycle adjustment signal based on the reference signal and the intermediate voltage signal, and the pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the reference signal and the intermediate voltage signal.

[0008] According to some embodiments of the present application, the duty cycle adjustment signal generating unit further includes a connection resistor electrically connected between the second input terminal of the comparator and a reference voltage terminal.

[0009] According to some embodiments of the present application, the correction pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, the duty cycle of the first pulse width modulation signal is greater than the duty cycle of the initial pulse width modulation signal, and the duty cycle of the second pulse width modulation signal is less than the duty cycle of the initial pulse width modulation signal, wherein the pulse width modulation signal adjustment unit includes: a pulse width modulation signal delay circuit, configured to be electrically connected to the output end of the comparator and receive the initial pulse width modulation signal, so as to delay the rising edge or falling edge of the effective level of the initial pulse width modulation signal under the control of the duty cycle adjustment signal, thereby generating the first pulse width modulation signal or the second pulse width modulation signal; and a selector, configured to be electrically connected to the output end of the comparator, so as to select the first pulse width modulation signal or the second pulse width modulation signal as the correction pulse width modulation signal according to the duty cycle adjustment signal.

[0010] According to some embodiments of the present application, the pulse width modulation signal delay circuit includes an RC delay circuit, an AND gate and an OR gate, the RC delay circuit includes a variable resistor and a capacitor connected in series, the output end of the comparator is electrically connected to the variable resistor to adjust the resistance of the variable resistor under the control of the duty cycle adjustment signal, the RC delay circuit generates a delay signal according to the initial pulse width modulation signal and the duty cycle adjustment signal, wherein the AND gate is configured to receive the delay signal and the initial pulse width modulation signal to generate the first pulse width modulation signal, and the OR gate is configured to receive the delay signal and the initial pulse width modulation signal to generate the second pulse width modulation signal.

[0011] According to some embodiments of the present application, the selector is configured to: in response to the amplitude of the duty cycle adjustment signal being greater than a threshold, select the first pulse width modulation signal as the correction pulse width modulation signal; and in response to the amplitude of the duty cycle adjustment signal being less than the threshold, select the second pulse width modulation signal as the correction pulse width modulation signal.

[0012] According to some embodiments of the present application, the duty cycle adjustment signal generating unit further includes a filter electrically connected to an output end of the comparator, and the filter filters the output signal of the comparator to obtain the duty cycle adjustment signal.

[0013] Another embodiment of the present application provides a voltage conversion circuit, which includes a voltage converter and a pulse width modulation signal adjuster according to any of the aforementioned embodiments, wherein the pulse width modulation signal adjuster is electrically connected to the voltage converter to drive the voltage converter based on the correction pulse width modulation signal.

[0014] Another embodiment of the present application provides a DC power supply, which includes: N voltage conversion circuits according to the aforementioned embodiments, the output ends of the respective voltage converters of the N voltage conversion circuits are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2.

[0015] Another embodiment of the present application provides a DC power supply, which includes: an N-phase voltage converter and N pulse width modulation signal regulators according to any one of the aforementioned embodiments, each pulse width modulation signal regulator is electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, the output ends of the N-phase voltage converters are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2, wherein the second input ends of each comparator of the N pulse width modulation signal regulators are electrically connected to a common node to receive the reference voltage, and the DC power supply also includes a connection resistor electrically connected between the common node and the reference voltage end.

[0016] Yet another embodiment of the present application provides a DC power supply, comprising: an N-phase voltage converter and N pulse width modulation signal regulators according to the aforementioned embodiments, each pulse width modulation signal regulator being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, the output ends of the N-phase voltage converters being connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2, the second input ends of each comparator of the N pulse width modulation signal regulators being electrically connected to a common node to receive the reference voltage, and the DC power supply further comprising a connection resistor electrically connected between the common node and the reference voltage end, the resistance value of the first resistor being n times the resistance value of the connection resistor.

[0017] According to some embodiments of the present application, the reference signal corresponds to an average value, a maximum value or a minimum value of each of the feedback signals generated by the N-phase voltage converter.

[0018] According to some embodiments of the present application, the DC power supply also includes an initial pulse width modulation signal generator, which is electrically connected to the output node and each pulse width modulation signal adjuster in the N-phase voltage converter, wherein the initial pulse width modulation signal generator is configured to provide a corresponding initial pulse width modulation signal to each pulse width modulation signal adjustment unit in each pulse width modulation signal adjuster according to the DC voltage at the output node.

[0019] Some embodiments of the present application are summarized above, and other different embodiments can be obtained based on the combination of some embodiments and the combination of features in different embodiments, and these different embodiments also belong to the protection scope of the present application. According to the embodiments described below, these and other advantages of the present application will become clear, and these and other advantages of the present application will be explained with reference to the embodiments described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Embodiments of the present application will now be described in more detail and with reference to the accompanying drawings, in which:

[0021] Figure 1 A topology of a DC power supply including a multi-phase voltage converter is illustrated;

[0022] Figure 2 The figure shows a circuit schematic diagram of a DC-DC voltage converter;

[0023] Figure 3 The figure shows a structural block diagram of a pulse width modulation signal regulator for a voltage converter VC provided according to an embodiment of the present application;

[0024] Figure 4 FIG. 1 illustrates a structural block diagram of a pulse width modulation signal regulator for a voltage converter VC provided according to another embodiment of the present application;

[0025] Figure 5 FIG. 1 illustrates a structural block diagram of each pulse width modulation signal regulator for a multi-phase voltage converter provided according to another embodiment of the present application;

[0026] Figure 6 FIG. 1 illustrates a structural block diagram of each pulse width modulation signal regulator for a multi-phase voltage converter provided according to another embodiment of the present application;

[0027] Figure 7 FIG. 1 illustrates a structural block diagram of each pulse width modulation signal regulator for a multi-phase voltage converter provided according to another embodiment of the present application;

[0028] Figure 8 FIG. 1 illustrates a structural block diagram of a pulse width modulation signal regulator for a voltage converter provided according to another embodiment of the present application;

[0029] Fig. 9 and Fig.10 They are used to illustrate how the duty cycle of a PWM signal is changed by delaying a falling edge or a rising edge of an effective level of the PWM signal;

[0030] Fig.11 An exemplary circuit schematic diagram for illustrating a pulse width modulation signal adjustment unit in a pulse width modulation signal adjuster according to another embodiment of the present application;

[0031] Fig.12 The diagram illustrates a topological structure provided by a DC power supply according to another embodiment of the present application. DETAILED DESCRIPTION

[0032] The following description provides the specific details of various embodiments of the present application so that those skilled in the art can fully understand and implement the various embodiments of the present application. In some cases, the present application does not illustrate or describe in detail some structures or functions well known in the art to avoid these unnecessary descriptions from obscuring the description of the embodiments of the present application. The technical solution of the present application can be embodied in many different forms and purposes, and should not be limited to the embodiments described herein. These embodiments are provided to make the technical solution of the present application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0033] Here, some of the terms involved in the embodiments of the present application are first explained to facilitate understanding by those skilled in the art. The "voltage converter" mentioned herein refers to a circuit that converts a DC voltage into another DC voltage, or converts an AC voltage into a DC voltage. Examples of voltage converters include rectifiers or DC-DC converters, etc. The voltage converter may include a rectifier and a DC-DC converter electrically connected to the rectifier. The "DC power supply" mentioned herein refers to a power supply that provides a DC voltage to a load.

[0034] The inventor of the present application realizes that due to the limitation of the switch tube and the inductor current, the average current that a single voltage converter (e.g., a DC-DC buck circuit) can provide is relatively limited, generally not higher than 30 A. However, the current required in actual applications is often as high as hundreds or even thousands of amperes, especially for loads such as image processors (GPUs) used for artificial intelligence and image processing, the demand for current is still increasing, which requires the use of a DC power supply including multi-phase voltage converters connected in parallel to power the load. Figure 1 The figure shows a topological structure of a DC power supply including a multi-phase voltage converter. The DC power supply includes N-phase voltage converters, each of which includes a switch main circuit VC1, VC2... or VCn, an inductor, a capacitor, etc. A pulse width modulation (PWM) signal generator 100 provides corresponding pulse width modulation signals PWM1, PWM2... PWMn to each phase voltage converter in a time-sharing manner. The DC output terminals of each voltage converter are connected to the output terminal of the DC power supply and generate an output voltage Vout. In order to achieve a balance in the output current between the phase voltage converters, each voltage converter provides a corresponding feedback current signal I1, I2... In to the pulse width modulation signal generator 100 to adjust the duty cycle of the pulse width modulation signals PWM1, PWM2... PWMn, so that the output current of each phase voltage converter tends to be balanced.

[0035] Figure 2 An example of a schematic diagram of a voltage converter is shown in FIG. Figure 2 As shown, the voltage converter includes an input capacitor CIN , a first transistor K1, a second transistor K2, an output inductor L and an output capacitor C OUT . Figure 2 The voltage converter shown is a classic DC-DC step-down circuit. The first transistor K1 and the second transistor K2 are alternately turned on and off under the control of the PWM signal to convert the DC input voltage V IN Converts to a lower DC output voltage V OUT .exist Figure 1 The DC power supply shown in the figure adopts Figure 2 In the case of the voltage converter shown, Figure 1 The switching main circuits VC1, VC2, ... VCn of each voltage converter in the circuit mainly include Figure 2 The first transistor K1 and the second transistor K2 are shown in FIG.

[0036] The present application provides a pulse width modulation (PWM) signal regulator for controlling a voltage converter in a DC power supply, wherein the DC power supply includes a multi-phase voltage converter, such as Figure 3 As shown, the pulse width modulation signal regulator includes: a current sensor 310, which is configured to be electrically connected to a voltage converter VC to generate a feedback signal fi corresponding to the output current Iout of the voltage converter VC; a duty cycle adjustment signal generating unit 320, which is configured to receive the feedback signal fi and a reference signal Vr, so as to generate a duty cycle adjustment signal di based on the feedback signal fi and the reference signal Vr, wherein the reference signal Vr corresponds to a balanced current at which the output currents of the voltage converters of each phase in the multi-phase voltage converter are balanced; and a pulse width modulation signal adjusting unit 330, which is configured to receive an initial pulse width modulation signal PWMi and the duty cycle adjustment signal di, so as to adjust the duty cycle of the initial pulse width modulation signal PWMi according to the duty cycle adjustment signal di, thereby obtaining a correction pulse width modulation signal PWMo for driving the voltage converter. The current sensor 310 here can collect the output current Iout of the voltage converter VC and generate a feedback signal fi. Depending on the type of the current sensor, the specific form of the feedback signal fi can be a voltage signal or a current signal, but both correspond to the magnitude of the output current Iout. In some embodiments, the feedback signal fi is a voltage signal or a current signal proportional to the output current Iout. For example, the feedback signal fi may be 5mv / A, that is, when the output current Iout is 1A, the feedback signal fi is a voltage signal of 5mv, or the feedback signal fi may be 5ua / A, that is, when the output current Iout is 1A, the feedback signal fi is a current signal of 5uA.

[0037] The duty cycle adjustment signal generating unit 320 can generate a duty cycle adjustment signal di based on the feedback signal fi output by the current sensor and the reference signal Vr. On this basis, the pulse width modulation signal adjusting unit 330 can increase or decrease the duty cycle of the initial pulse width modulation signal PWMi according to the duty cycle adjustment signal di, thereby obtaining a correction pulse width modulation signal PWMo for driving the voltage converter VC. The pulse width modulation signal adjuster proposed in the embodiment of the present application can be applied to Figure 1 . Specifically, the DC power supply may include N-phase voltage converters and N pulse width modulation signal regulators for controlling the N-phase voltage converters respectively. Each pulse width modulation signal regulator may readjust the duty cycle of the pulse width modulation signal PWM1, PWM2, ..., PWMn provided to the corresponding voltage converter according to the feedback signal fi output by the current sensor and the reference signal Vr. The output current of each voltage converter may be balanced without requiring the voltage converter to provide the corresponding feedback current signal to the pulse width modulation signal generator 100, that is, the Figure 1 The current transmission lines shown in the figure are used to transmit feedback current signals I1, I2, ... In, which will also be further described below in conjunction with specific application scenarios discussed in different examples.

[0038] In some embodiments, the feedback signal output by the current sensor is a voltage signal corresponding to the output current of the voltage converter, such as Figure 4As shown, the duty cycle adjustment signal generating unit 320 includes: a comparator CM, which includes a first input terminal a, a second input terminal b, and an output terminal c electrically connected to the pulse width modulation signal adjusting unit 330, the first input terminal a is electrically connected to the output terminal of the current sensor 310 to receive the feedback signal fi, and the second input terminal b is configured to receive the reference signal Vr; a buffer circuit B, the input terminal of the buffer circuit B is electrically connected to the output terminal of the current sensor 310 to receive the feedback signal fi and output the buffer signal bi from the output terminal of the buffer circuit, and the output terminal of the buffer circuit B is electrically connected to the second input terminal b of the comparator CM. The comparator CM generates a duty cycle adjustment signal di based on one of the buffer signal bi or the reference signal Vr and the feedback signal fi, and the pulse width modulation signal adjusting unit 330 adjusts the duty cycle of the initial pulse width modulation signal PWMi according to the duty cycle adjustment signal di to reduce the difference between the feedback signal fi and the reference signal Vr or the buffer signal bi. In some embodiments, the buffer signal bi can be a voltage signal slightly lower than the feedback signal fi, and the comparator CM can generate the duty cycle adjustment signal di according to the buffer signal bi and the feedback signal fi. When the reference signal Vr exceeds the feedback signal fi, the buffer circuit may be in a failure state. At this time, the potential of the second input terminal b of the comparator CM is determined by the reference signal Vr, and the comparator CM generates a duty cycle adjustment signal di according to the reference signal and the feedback signal fi.

[0039] Figure 5 The structure block diagram of the PWM signal regulator for controlling the voltage converters VC1 and VC2 in the DC power supply according to one embodiment of the present application is illustrated, wherein a specific example of the empty ratio adjustment signal generating unit is illustrated. The buffer circuit includes an operational amplifier op and a transistor T, the output end of the operational amplifier op is electrically connected to the control end of the transistor T, the first input end of the operational amplifier op is electrically connected to the first input end a of the comparator CM, the second input end of the operational amplifier op is electrically connected to the second input end b of the comparator CM, the first end of the transistor T is used to receive the power supply voltage VDD, and the second end of the transistor T is electrically connected to the second input end b of the comparator CM. The control end of the transistor mentioned here refers to the gate of the transistor for receiving the control signal, the first end and the second end of the transistor refer to the electrodes other than the gate, and the first end and the second end of the transistor may include a source or a drain, respectively. In this example, the transistor T is a P-channel metal-oxide semiconductor field effect transistor.

[0040] The following is based on Figure 5 The example shown specifically illustrates the working process of the pulse width modulation signal regulator provided by the embodiment of the present application being applied to a DC power supply including a multi-phase voltage converter. Figure 5As shown, the DC power supply may include a multi-phase voltage converter VC1...VCn and n pulse width modulation signal regulators for controlling the voltage converters VC1...VCn, respectively, each pulse width modulation signal regulator receives a corresponding initial pulse width modulation signal PWMi1...PWMin, and the output end of the buffer circuit in each pulse width modulation signal regulator (i.e., the second input end of the comparator) is connected to a common node N, and the common node N is electrically connected to the reference voltage terminal through a connecting resistor Rc. When the voltage signal at the second input end b of the comparator CM in the pulse width modulation signal regulator of a certain phase voltage converter gradually increases and is higher than the feedback signal fi, the operational amplifier op will output a high level signal, the transistor T is in a disconnected state, the buffer circuit is in a failed state, and the buffer signal bi is not output. The voltage at the second input end b of the comparator CM (i.e., the voltage at the common node N) will depend on the maximum value of the buffer signals bi output by the buffer circuits in the pulse width modulation signal regulators for other phase voltage converters that are still in normal working state, and the maximum value also means that the output current of the corresponding voltage converter is larger than the output current of other voltage converters and has the maximum output current. That is to say, at this time, the aforementioned reference signal Vr is the buffer signal output by the buffer circuit in the pulse width modulation signal regulator corresponding to the voltage converter with the maximum output current, that is, the reference signal Vr corresponds to the maximum output current. The pulse width modulation signal regulator corresponding to the remaining voltage converters will increase the duty cycle of the initial PWM signal according to the reference signal and the corresponding feedback signal fi, thereby obtaining a correction PWM signal with a large duty cycle, so that the output current of the remaining voltage converters gradually increases toward the maximum output current. Correspondingly, the feedback signal fi of the current sensor 510 of each phase voltage converter also increases toward the maximum value of each buffer signal bi, and is close to or equal to the maximum value. When the voltage signal at the second input terminal b of the comparator CM in the pulse width modulation signal regulator of a certain phase voltage converter is less than the feedback signal fi, the operational amplifier op outputs a low level signal, the transistor T is in the on state, and the voltage signal at the second input terminal b of the comparator CM gradually increases until it is equal to the feedback signal fi. The PWM signal regulator of each voltage converter can adjust the duty cycle of its own initial PWM signal PWMin according to the feedback signal fi and the reference signal Vr, so that the feedback signal fi is equal to the reference signal. In this way, the output currents of various voltage converters can be made consistent (within an error range), thus achieving the purpose of current balancing. Figure 5 The connection resistor Rc in the buffer circuit can provide the minimum current required for the buffer circuit during operation.

[0041] Figure 6The figure shows a block diagram of a pulse width modulation signal regulator for controlling voltage converters VC1 and VC2 in a DC power supply according to another embodiment of the present application, wherein a specific example of a duty cycle adjustment signal generating unit is shown. Figure 6As shown, the duty cycle adjustment signal generating unit includes a comparator CM and a buffer circuit, the buffer circuit includes a first diode D1, the anode of the first diode D1 is electrically connected to the output end of the current sensor 610, the cathode of the anode of the first diode D1 is electrically connected to the second input end b of the comparator CM, the duty cycle adjustment signal generating unit also includes a second diode D2, the anode and cathode of the second diode D2 are electrically connected to the output end of the current sensor 610 and the first input end a of the comparator CM, respectively, and the parameters of the first diode D1 and the second diode D2 are the same. The same parameters of the first diode and the second diode mean that the temperature characteristics and PN junction voltage drop characteristics of the two diodes are highly consistent. Due to the unidirectional conductivity of the diode, when the feedback signal fi output by the current sensor 610 is less than the voltage at the second input terminal b of the comparator CM, the first diode D1 is in the cut-off state, and the voltage at the second input terminal b of the comparator CM (i.e., the voltage at the common node N) will depend on the maximum value of the voltages at the cathodes of the first diodes D1 that are still in the on state in the pulse width modulation signal regulators for other phase voltage converters, which also means that the output current of the corresponding voltage converter is larger than the output currents of other voltage converters and has the maximum output current. That is to say, at this time, the aforementioned reference signal Vr is the voltage signal at the cathode of the first diode D1 in the pulse width modulation signal regulator corresponding to the voltage converter with the maximum output current, and the reference signal corresponds to the above-mentioned maximum output current. The comparator CM in the pulse width modulation signal regulator corresponding to each of the remaining voltage converters will increase the duty cycle of the initial PWM signal according to the reference signal and the corresponding feedback signal fi, thereby obtaining a correction PWM signal with a larger duty cycle, so that the output current of each of the remaining voltage converters gradually increases toward the above-mentioned maximum output current. Correspondingly, the feedback signal fi of the current sensor 610 of each phase voltage converter also increases toward the maximum value of the voltage at the cathode of each first diode D1, and approaches or is equal to the maximum value. When the feedback signal fi output by the current sensor 610 is greater than the voltage at the second input terminal b of the comparator CM, the first diode is in a conducting state, and the voltage at the second input terminal b of the comparator CM will also be clamped at a voltage having a value of the difference between the feedback signal fi and the voltage drop of the first diode. The PWM signal regulator of each voltage converter can adjust the duty cycle of the respective initial PWM signal PWMin according to the voltage signal at the cathode of the second diode D2 (the feedback signal fi minus the voltage drop of the second diode) and the reference signal Vr, so that the voltage at the first input terminal a of the comparator CM (the feedback signal fi minus the voltage drop of the second diode D2) is equal to the reference signal Vr. In this way, the output current of each voltage converter can be consistent (within the error range), and the purpose of current balancing can be achieved. Figure 6The connection resistor Rc in can provide the required minimum current when the first diode D1 is turned on.

[0042] In some embodiments, the feedback signal output by the current sensor is a current signal corresponding to the output current of the voltage converter. Figure 7 The figure shows a block diagram of a pulse width modulation signal regulator for controlling voltage converters VC1 and VC2 in a DC power supply according to another embodiment of the present application, wherein a specific example of a duty cycle adjustment signal generating unit is shown. Figure 7As shown, the duty cycle adjustment signal generating unit includes: a comparator CM, which includes a first input terminal a, a second input terminal b and an output terminal electrically connected to the PWM signal adjustment unit 730, and the second input terminal b of the comparator CM is configured to receive the reference signal Vr; a mirror current source, the mirror current source includes a reference current branch Im1 and a mirror current branch Im2, the reference current branch Im1 is electrically connected to the output terminal of the current sensor 710 and the first input terminal a of the comparator CM, and the mirror current branch Im2 is electrically connected to the output terminal of the current sensor 710 and the second input terminal b of the comparator CM; and a first resistor R1, which is electrically connected between the first input terminal a of the comparator CM and the reference voltage terminal to convert the feedback signal into an intermediate voltage signal. The comparator CM generates a duty cycle adjustment signal based on the reference signal Vr and the intermediate voltage signal, and the PWM signal adjustment unit 730 adjusts the duty cycle of the initial PWM signal PWMin according to the duty cycle adjustment signal to reduce the difference between the reference signal Vr and the intermediate voltage signal. In this embodiment, the mirror current source forms the same current signal in the reference current branch Im1 and the mirror current branch Im2 based on the feedback signal of the current sensor 710. The current signal on the reference current branch Im1 forms an intermediate voltage signal through the first resistor R1 and is provided to the first input terminal a of the comparator CM, and the current signal on the mirror current branch Im2 flows to the common node N. The second input terminal b of the comparator CM receives the reference signal Vr at the common node N. When the PWM signal regulators of each phase voltage converter are connected to the common node N, the currents on the mirror current branch Im2 in each PWM signal regulator converge to the common node N. At this time, the reference signal Vr at the common node N is (Im21+Im22+…Im2n)*R0, Im21, Im22, Im2n are the currents on the mirror current branch Im2 in the PWM signal regulators in the first phase power converter, the second phase voltage converter and the Nth phase voltage converter, respectively, and R0 is the resistance value of the connection resistor Rc between the common node N and the reference voltage terminal. Therefore, in this embodiment, the reference signal Vr at the common node N can provide a unified reference signal for the comparator CM of the PWM signal regulator in each phase voltage converter, so that the PWM signal adjustment unit 730 can adjust the duty cycle of the initial PWM signal to make the output current of each phase voltage converter tend to be consistent (within the error range). In some embodiments, the resistance value of the first resistor R1 is N times the resistance value R0 of the connecting resistor Rc. In this case, the reference signal Vr is (Im21+Im22+…Im2n)*R1 / N, that is, the reference signal Vr is the average value of the intermediate voltage signal in the PWM signal regulator of each phase voltage converter, and therefore, the reference signal Vr can correspond to the average value of the output current of each phase voltage converter.Therefore, through this embodiment, the output currents of various voltage converters can also be made consistent (within an error range), thereby achieving the purpose of current balancing.

[0043] In some embodiments, the duty cycle adjustment signal generating unit further includes a connection resistor electrically connected between the second input terminal of the comparator and a reference voltage terminal. Figure 5 , Figure 6 or Figure 7 As shown in FIG. 1 , in some embodiments, the connection resistor Rc can be used as a component of a PWM signal regulator for a voltage converter of a certain phase, and can be shared by PWM signal regulators of voltage converters of other phases.

[0044] The present application does not impose any specific limitation on the value of the reference signal Vr. The above discusses an example in which the reference signal Vr corresponds to the average value or maximum value of the output current of each phase voltage converter. In other embodiments, the reference signal Vr may correspond to the minimum value of the output current of each phase voltage converter.

[0045] In some embodiments, the correction PWM signal PWMo includes a first pulse width modulation signal and a second pulse width modulation signal, wherein the duty cycle of the first pulse width modulation signal is greater than the duty cycle of the initial PWM signal, and the duty cycle of the second pulse width modulation signal is less than the duty cycle of the initial PWM signal. Figure 8 As shown, the PWM signal adjustment unit 830 includes: a pulse width modulation signal delay circuit DL, which is configured to be electrically connected to the output end of the comparator CM and receive the initial PWM signal PWMi, so as to delay the rising edge or falling edge of the effective level of the initial PWM signal under the control of the duty cycle adjustment signal di, thereby generating the first pulse width modulation signal or the second pulse width modulation signal; and a selector SW, which is configured to be electrically connected to the output end of the comparator CM, so as to select the first pulse width modulation signal or the second pulse width modulation signal as the correction pulse width modulation signal PWMo according to the duty cycle adjustment signal di. The pulse width modulation signal delay circuit DL can delay the rising edge or falling edge of the effective level of the initial PWM signal under the control of the duty cycle adjustment signal di, thereby obtaining the correction PWM signal PWMo with increased duty cycle or reduced duty cycle. Fig. 9 and Fig.10 1 and 2 respectively illustrate exemplary schematic diagrams of a first pulse width modulation signal PWMo1 and a second pulse width modulation signal PWMo2 generated according to an initial PWM signal PWMi. The effective level of the initial PWM signal is a high level, such as Fig. 9 As shown, by delaying the falling edge of the effective level of the initial PWM signal, a first pulse width modulation signal PWMo1 with a larger duty cycle can be obtained. Fig.10 As shown, by delaying the rising and falling edge of the effective level of the initial PWM signal, a second pulse width modulation signal PWMo2 with a smaller duty cycle can be obtained. Fig. 9 and Fig.10 In the example of FIG. 1 , the effective level of the initial PWM signal is a high level. In other embodiments, the effective level of the initial PWM signal may also be a low level.

[0046] Fig.11 An exemplary schematic diagram of a pulse width modulation signal delay circuit DL and a selector SW is given. Fig.11 As shown, the pulse width modulation signal delay circuit includes an RC delay circuit, an AND gate A1 and an OR gate O1. The RC delay circuit includes a variable resistor Ra and a capacitor C1 connected in series. The output end of the comparator CM is electrically connected to the variable resistor Ra to adjust the resistance of the variable resistor Ra under the control of the duty cycle adjustment signal. The RC delay circuit generates a delay signal according to the initial PWM signal and the duty cycle adjustment signal. The AND gate A1 is configured to receive the delay signal and the initial PWM signal to generate a first pulse width modulation signal. The OR gate O1 is configured to receive the delay signal and the initial PWM signal to generate a second pulse width modulation signal. Fig.11 The signal at the node between the capacitor C1 and the variable resistor Ra is the above-mentioned delayed signal, which is provided to one input end of the AND gate A1 and the OR gate O1 respectively, and the other input end of the AND gate A1 and the OR gate O1 receives the initial PWM signal PWMi. The selector SW may include a switching switch, which may adjust the signal according to the duty cycle. In this embodiment, the second pulse width modulation signal PWMo2 with a reduced duty cycle may be output from the AND gate A1, and the first pulse width modulation signal PWMo1 with an increased duty cycle may be output from the OR gate O1.

[0047] In some embodiments, Fig.11As shown, the duty cycle adjustment signal generating unit further includes a filter F1 electrically connected to the output terminal of the comparator CM, and the filter F1 filters the output signal of the comparator CM to obtain the duty cycle adjustment signal. In some embodiments, the selector SW is configured to: in response to the amplitude of the duty cycle adjustment signal being greater than a threshold, select the first pulse width modulation signal as the correction pulse width modulation signal; and in response to the amplitude of the duty cycle adjustment signal being less than the threshold, select the second pulse width modulation signal as the correction pulse width modulation signal. The threshold can be set, for example, according to the average value or median value of the output signal of the comparator CM. If the amplitude of the power supply voltage received by the comparator CM is VDD, then the amplitude of the output signal of the comparator CM usually does not exceed VDD, and the output signal of the comparator CM can be considered to vary between 0 and VDD, and its average value or median value is VDD / 2. If the input signal of the positive phase input terminal (e.g., the second input terminal b) of the comparator is greater than the input signal of the negative phase input terminal (e.g., the first input terminal a), that is, the reference signal Vr is greater than the feedback signal fi, and it also means that the output signal of the comparator (duty cycle adjustment signal) is greater than the threshold VDD / 2. At this time, the switching switch in the selector SW can connect the output end of the PWM signal adjustment unit to the output end of the AND gate O1, and output the first pulse width modulation signal PWMo1 with a larger duty cycle, that is, increase the PWM signal used to drive the voltage converter to reduce the difference between the reference signal Vr and the feedback signal fi. When the output signal of the comparator (duty cycle adjustment signal) is less than the threshold VDD / 2, it means that the feedback signal fi is too large, and the selector SW can connect the output end of the PWM signal adjustment unit to the output end of the AND gate, and output the second pulse width modulation signal PWMo2 with a smaller duty cycle, that is, reduce the PWM signal used to drive the voltage converter to reduce the difference between the reference signal Vr and the feedback signal fi.

[0048] exist Fig.11 In the example, the degree to which the duty cycle of the first pulse width modulation signal PWMo1 or the second pulse width modulation signal PWMo2 increases or decreases relative to the duty cycle of the initial PWM signal PWMi depends on the signal delay degree of the RC delay circuit, that is, depends on the resistance value of the variable resistor Ra. The change in the resistance value of the variable resistor Ra can be controlled by the duty cycle adjustment signal output by the comparator CM. In some embodiments, the resistance value of the variable resistor Ra can be designed to be K*|di-1 / 2*VDD|, where K is a coefficient, that is, the resistance value of the variable resistor Ra is proportional to the absolute value of the difference between the duty cycle adjustment signal and the above threshold. When the value of the duty cycle adjustment signal is equal to the above threshold, the RC delay circuit is similar to not generating a valid delay signal, and the duty cycle of the pulse width modulation signal output from the OR gate O1 or the AND gate A1 is approximately the same as the duty cycle of the initial PWM signal PWMi.

[0049] Fig.11 The structure of the PWM signal adjustment unit is only described by way of example, rather than limiting the specific implementation of the PWM signal adjustment unit. The pulse width modulation signal delay circuit and selector in the PWM signal adjustment unit may have other implementations different from the above examples, and the present application does not limit this.

[0050] The pulse width modulation signal regulator proposed in the embodiment of the present application can be applied to each voltage converter in a DC power supply. Based on the pulse width modulation signal regulator, each voltage converter can readjust the duty cycle of the pulse width modulation signal provided to the corresponding voltage converter according to the reference signal and the feedback signal output by the current sensor, so that the output current of each voltage converter can be balanced without requiring each voltage converter to provide a corresponding feedback current signal to an external pulse width modulation signal generator. In addition, this can avoid setting multiple feedback current signal transmission lines from each voltage converter to an external pulse width modulation signal generator on the circuit board, simplifying the routing design of the circuit board of the DC power supply and saving the wiring space of the circuit board.

[0051] Another embodiment of the present application provides a voltage conversion circuit, which includes a voltage converter and a pulse width modulation (PWM) signal regulator according to any of the aforementioned embodiments, wherein the pulse width modulation signal regulator is electrically connected to the voltage converter to drive the voltage converter based on the correction pulse width modulation signal.

[0052] Another embodiment of the present application provides a DC power supply, which includes N voltage conversion circuits as described in the above embodiments, and the output ends of the respective voltage converters of the N voltage conversion circuits are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2.

[0053] Yet another embodiment of the present application provides a DC power supply, comprising: an N-phase voltage converter and N pulse width modulation signal regulators according to the aforementioned embodiments, each pulse width modulation signal regulator being electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, the output terminals of the N-phase voltage converters being connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2, the second input terminals of each comparator of the N pulse width modulation signal regulators being electrically connected to a common node to receive the reference voltage, and the DC power supply also comprising a connection resistor electrically connected between the common node and the reference voltage terminal. Fig.12An example of the topological structure of the DC power supply is illustrated. The DC power supply includes: an N-phase voltage converter and N pulse width modulation signal regulators J1, J2...Jn according to the aforementioned embodiments, each pulse width modulation signal regulator is electrically connected to a corresponding voltage converter to drive the voltage converter based on the correction pulse width modulation signal, and each voltage converter includes a corresponding main switch circuit VC1, VC2...or VCn and an inductor LC1, LC2...or LCn. The output ends of the N-phase voltage converters are connected in parallel to an output node to provide a DC voltage Vout at the output node, wherein N is an integer greater than 2, and the second input ends of each comparator of the N pulse width modulation signal regulators are electrically connected to a common node to receive the reference voltage, and the DC power supply also includes a connection resistor Rc electrically connected between the common node and the reference voltage terminal.

[0054] The DC power supply includes Figure 7 In the case of the pulse width modulation signal adjuster shown, that is, the duty cycle adjustment signal generating unit includes a comparator CM, a mirror current source and a first resistor R1, and the resistance value of the first resistor may be n times the resistance value of the connecting resistor Rc.

[0055] In some embodiments, Fig.12 As shown, the DC power supply also includes an initial PWM signal generator 100a, which is electrically connected to the above-mentioned output node and each PWM signal regulator J1, J2...Jn in the N-phase voltage converter. The initial PWM signal regulator 100a is configured to provide a corresponding initial PWM signal to each PWM signal adjustment unit in the each PWM signal regulator J1, J2...Jn according to the DC voltage at the output node.

[0056] Some embodiments of the present application are described above, but the scope of protection of the present application is not limited to the specific forms of the embodiments described herein, and the scope of the present application is defined by the appended claims. Although the terms first, second, etc. may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms, and only represent the distinction in terms of name. In addition, the "electrical connection" mentioned herein includes "direct connection" or "indirect connection".

Claims

1. A pulse width modulation signal regulator for controlling a voltage converter in a DC power supply, the DC power supply comprising a multi-phase voltage converter, characterized in that: The pulse width modulation signal adjuster comprises: a current sensor configured to be electrically connected to the voltage converter to generate a feedback signal corresponding to an output current of the voltage converter; a duty cycle adjustment signal generating unit configured to receive the feedback signal and a reference signal to generate a duty cycle adjustment signal based on the feedback signal and the reference signal, wherein the reference signal corresponds to a balanced current at which the output currents of the respective phase voltage converters in the multi-phase voltage converter reach a balanced state; The PWM signal adjustment unit is configured to receive an initial PWM signal and the duty cycle adjustment signal to adjust the duty cycle of the initial PWM signal according to the duty cycle adjustment signal, thereby obtaining a corrected PWM signal for driving the voltage converter.

2. The pulse width modulation signal regulator according to claim 1, characterized in that: The feedback signal is a voltage signal corresponding to the output current of the voltage converter, and the duty cycle adjustment signal generating unit includes: a comparator comprising a first input terminal, a second input terminal and an output terminal electrically connected to the pulse width modulation signal adjustment unit, the first input terminal being electrically connected to the output terminal of the current sensor to receive the feedback signal, and the second input terminal being configured to receive the reference signal; a buffer circuit, wherein an input terminal of the buffer circuit is electrically connected to the current sensor to receive the feedback signal and output a buffer signal from an output terminal of the buffer circuit, and an output terminal of the buffer circuit is electrically connected to a second input terminal of the comparator; The comparator generates the duty cycle adjustment signal based on the buffered signal or one of the reference signals and the feedback signal, and the pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the feedback signal and the reference signal or the buffered signal.

3. The pulse width modulation signal regulator according to claim 2, characterized in that: The buffer circuit includes an operational amplifier and a transistor, the output end of the operational amplifier is electrically connected to the control end of the transistor, the first input end of the operational amplifier is electrically connected to the first input end of the comparator, the second input end of the operational amplifier is electrically connected to the second input end of the comparator, the first end of the transistor is used to receive a power supply voltage, and the second end of the transistor is electrically connected to the second input end of the comparator.

4. The pulse width modulation signal regulator according to claim 2, characterized in that: The buffer circuit includes a first diode, an anode of the first diode is electrically connected to the output end of the current sensor, and a cathode of the first diode is electrically connected to the second input end of the comparator, wherein the duty cycle adjustment signal generating unit also includes a second diode, an anode and a cathode of the second diode are electrically connected to the output end of the current sensor and the first input end of the comparator, respectively, wherein the parameters of the first diode and the second diode are the same.

5. The pulse width modulation signal regulator according to claim 1, characterized in that: The feedback signal is a current signal corresponding to the output current of the voltage converter, and the duty cycle adjustment signal generating unit includes: a comparator comprising a first input terminal, a second input terminal and an output terminal electrically connected to the pulse width modulation signal adjustment unit, the second input terminal of the comparator being configured to receive the reference signal; a mirror current source, the mirror current source comprising a reference current branch and a mirror current branch, the reference current branch being electrically connected to the output end of the current sensor and the first input end of the comparator, the mirror current branch being electrically connected to the output end of the current sensor and the second input end of the comparator; and a first resistor, electrically connected between the first input terminal of the comparator and a reference voltage terminal, to convert the feedback signal into an intermediate voltage signal, The comparator generates the duty cycle adjustment signal based on the reference signal and the intermediate voltage signal, and the pulse width modulation signal adjustment unit adjusts the duty cycle of the initial pulse width modulation signal according to the duty cycle adjustment signal to reduce the difference between the reference signal and the intermediate voltage signal.

6. The pulse width modulation signal regulator according to any one of claims 2 to 5, characterized in that: The duty cycle adjustment signal generating unit further includes a connection resistor electrically connected between the second input terminal of the comparator and a reference voltage terminal.

7. The pulse width modulation signal regulator according to any one of claims 2 to 5, characterized in that: The correction pulse width modulation signal includes a first pulse width modulation signal and a second pulse width modulation signal, the duty cycle of the first pulse width modulation signal is greater than the duty cycle of the initial pulse width modulation signal, and the duty cycle of the second pulse width modulation signal is less than the duty cycle of the initial pulse width modulation signal, wherein the pulse width modulation signal adjustment unit includes: a pulse width modulation signal delay circuit, configured to be electrically connected to the output terminal of the comparator and receive the initial pulse width modulation signal, to delay a rising edge or a falling edge of an effective level of the initial pulse width modulation signal under the control of the duty cycle adjustment signal, thereby generating the first pulse width modulation signal or the second pulse width modulation signal; and The selector is configured to be electrically connected to the output terminal of the comparator to select the first pulse width modulation signal or the second pulse width modulation signal as the correction pulse width modulation signal according to the duty cycle adjustment signal.

8. The pulse width modulation signal regulator according to claim 7, characterized in that: The pulse width modulation signal delay circuit includes an RC delay circuit, an AND gate and an OR gate, the RC delay circuit includes a variable resistor and a capacitor connected in series, the output end of the comparator is electrically connected to the variable resistor to adjust the resistance of the variable resistor under the control of the duty cycle adjustment signal, and the RC delay circuit generates a delay signal according to the initial pulse width modulation signal and the duty cycle adjustment signal, wherein the AND gate is configured to receive the delay signal and the initial pulse width modulation signal to generate the first pulse width modulation signal, and the OR gate is configured to receive the delay signal and the initial pulse width modulation signal to generate the second pulse width modulation signal.

9. The pulse width modulation signal regulator according to claim 7, characterized in that: The selector is configured to: In response to the magnitude of the duty cycle adjustment signal being greater than a threshold, selecting the first pulse width modulation signal as the correction pulse width modulation signal; and In response to the magnitude of the duty cycle adjustment signal being less than the threshold, the second pulse width modulation signal is selected as the correction pulse width modulation signal.

10. The pulse width modulation signal regulator according to claim 2, characterized in that: The duty cycle adjustment signal generating unit further includes a filter electrically connected to an output terminal of the comparator, and the filter filters an output signal of the comparator to obtain the duty cycle adjustment signal.

11. A voltage conversion circuit, characterized in that: The voltage conversion circuit includes a voltage converter, and a pulse width modulation signal regulator according to any one of claims 1 to 10, wherein the pulse width modulation signal regulator is electrically connected to the voltage converter to drive the voltage converter based on the correction pulse width modulation signal.

12. A DC power supply, characterized in that: The DC power supply includes: According to claim 11, output ends of the respective voltage converters of the N voltage conversion circuits are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2.

13. A DC power supply, characterized in that: The DC power supply includes: N-phase voltage converters and N pulse width modulation signal regulators according to any one of claims 2-5, 7-10, each pulse width modulation signal regulator is electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, and the output ends of the N-phase voltage converters are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2, The second input terminals of the respective comparators of the N pulse width modulation signal regulators are electrically connected to a common node to receive the reference voltage, and the DC power supply further includes a connection resistor electrically connected between the common node and the reference voltage terminal.

14. A DC power supply, characterized in that: The DC power supply includes: N-phase voltage converters and N pulse width modulation signal regulators according to claim 5, each pulse width modulation signal regulator is electrically connected to a corresponding voltage converter to drive the voltage converter based on the corrected pulse width modulation signal, and output terminals of the N-phase voltage converters are connected in parallel to an output node to provide a DC voltage at the output node, wherein N is an integer greater than 2, The second input terminals of the respective comparators of the N pulse width modulation signal regulators are electrically connected to a common node to receive the reference voltage, and the DC power supply also includes a connection resistor electrically connected between the common node and the reference voltage terminal, and the resistance value of the first resistor is n times the resistance value of the connection resistor.

15. The DC power supply according to claim 13, characterized in that: The reference signal corresponds to an average value, a maximum value, or a minimum value of each of the feedback signals generated by the N-phase voltage converter.

16. The DC power supply according to any one of claims 12 to 15, characterized in that: The DC power supply also includes an initial pulse width modulation signal generator, which is electrically connected to the output node and each pulse width modulation signal regulator in the N-phase voltage converter. The initial pulse width modulation signal generator is configured to provide a corresponding initial pulse width modulation signal to each pulse width modulation signal adjustment unit in each pulse width modulation signal adjuster according to the DC voltage at the output node.

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