Fault-tolerant control method for open-circuit fault of power semiconductor of resonant dual-active bridge converter

Abstract

The invention belongs to the field of circuit fault control, particularly relates to a fault-tolerant control method for an open-circuit fault of a power semiconductor of a resonant dual-active-bridge converter, and aims to solve the problems that in a DAB converter with a small direct-current capacitor, the open-circuit fault of the power semiconductor causes current asymmetry, and effective fault-tolerant operation is difficult to realize. The method comprises the following steps: when any one of the devices from S5 to S8 fails, locking the devices and recalculating the switching frequency and the time sequence; if S1 or S3 has a fault, respectively keeping S7 on / S8 off or S5 on / S6 off, and adjusting the switching period according to the negative half wave of the high-frequency current; and when the S2 or S4 fails, the S8 or the S6 is correspondingly kept on, the S7 or the S5 is turned off, and the switching period is also adjusted based on the high-frequency current positive half wave. By adjusting the switching frequency and the time sequence, on the basis that the hardware cost is not increased, the system reliability is improved, the method is particularly suitable for small direct current side capacitor application, and efficient and stable operation can be maintained and a device can be protected even under the condition of open-circuit fault of a power semiconductor.

Description

Technical Field

[0001] The invention belongs to the field of circuit fault control, and in particular relates to a fault-tolerant control method for open-circuit faults of power semiconductors of a resonant dual-active bridge converter. Background Art

[0002] The resonant dual-active bridge converter can realize soft switching of all power semiconductor devices without closed-loop control. It has outstanding advantages such as high operating efficiency and high power density. It is the core component of intelligent electrical equipment such as power electronic transformers. It is widely used in AC / DC hybrid distribution networks, renewable energy grid-connected power generation, and electrified rail transit. In recent years, State Grid Corporation of China and Zhuzhou CRRC Times Electric Co., Ltd. have respectively presided over the implementation of power electronic transformer research and development and demonstration projects for AC / DC hybrid distribution networks and high-speed train traction power supply systems, both of which use dual-active bridge converters as core components for high-frequency isolation and power conversion.

[0003] Most existing resonant dual-active bridge converters have large DC side capacitors. During operation, the DC capacitor voltage remains basically unchanged. Its switching frequency is determined by the resonant frequency of the high-frequency circuit composed of the high-frequency transformer leakage inductance and the resonant capacitor. In addition, the switching frequency of the power semiconductor devices of the resonant dual-active bridge converter is high, the current stress is large, and the power semiconductor device is prone to open-circuit failure. The open-circuit failure of any power semiconductor device does not affect the resonant frequency of the high-frequency link, and open-circuit fault-tolerant operation can be achieved only by topological reconstruction. "A Fault-Tolerant Series-Resonant DC–DC Converter" published in "IEEE Transactions on Power Electronics" Vol. 32 No. 2 proposes to achieve fault-tolerant operation of resonant dual-active bridge converters under open-circuit faults by topological reconstruction. The article "Open-Circuit Fault Diagnosis and Fault-Tolerant Strategies for Full-Bridge DC–DC Converters" published in Volume 27, Issue 5 of IEEE Transactions on Power Electronics proposes to achieve open-circuit fault-tolerant operation of power semiconductor devices by changing the ratio of high-frequency transformers, but this method requires additional hardware and is costly. The article "Composite Fault-Tolerant Control Method for SR-DAB Interface Converter in DC Distribution System" published in Volume 42, Issue 20 of Automation of Electric Power Systems proposes to achieve fault-tolerant operation of resonant dual active bridge converters by topology reconstruction + asymmetric duty cycle, but this method requires some power semiconductor devices to bear hard switching, resulting in high losses.

[0004] However, the energy storage components of the dual active bridge converter with large DC side capacitance are large in size, which seriously restricts the improvement of its power density. However, as the DC side capacitance of the resonant dual active bridge converter decreases, especially when the DC side capacitance is basically equivalent to the resonant capacitance, its switching frequency is not only related to the resonant frequency of the high-frequency link, but also to the DC side capacitance. The relationship between the switching frequency and the resonant frequency is relatively complex. In this case, when an open-circuit fault occurs in the power semiconductor device of the resonant dual active bridge converter, its positive and negative half-wave currents will be seriously asymmetric. The traditional topology reconstruction method is difficult to achieve open-circuit fault-tolerant operation. Existing literature rarely involves the open-circuit fault-tolerant operation control of the power semiconductor of the resonant dual active bridge converter with small DC capacitance. Summary of the invention

[0005] In order to solve the above-mentioned problems in the prior art, namely, in a DAB converter with a small DC capacitor, a power semiconductor open-circuit fault causes current asymmetry, and the traditional topology reconstruction method is difficult to achieve effective fault-tolerant operation, the present invention provides a resonant dual active bridge converter power semiconductor open-circuit fault fault-tolerant control method, which is applied to a resonant dual active bridge converter, wherein the resonant dual active bridge converter comprises a high-voltage side DC capacitor C1, a low-voltage side DC capacitor C2, and a high-voltage side resonant capacitor C rp , low voltage side resonant capacitor C rs , high frequency transformer leakage inductance L r , a first power semiconductor device S1, a second power semiconductor device S2, a third power semiconductor device S3, a fourth power semiconductor device S4, a fifth power semiconductor device S5, a sixth power semiconductor device S6, a seventh power semiconductor device S7, and an eighth power semiconductor device S8, the method comprising:

[0006] Step A1, determine the position of the power semiconductor having an open circuit fault. If the power semiconductor having an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, jump to step A2;

[0007] If the power semiconductor device having an open circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, jump to step A3; if the power semiconductor device having an open circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, jump to step A4;

[0008] Step A2, locking the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, calculating the switching frequency according to the initial phase of the high-frequency current, and allocating the switching timing of the power semiconductor devices based on the switching frequency;

[0009] Step A3: if the first power semiconductor device S1 has an open circuit fault, the seventh power semiconductor device S7 is always in the on state, and the eighth power semiconductor device S8 is always in the off state.

[0010] If an open circuit fault occurs in the third power semiconductor device S3, the fifth power semiconductor device S5 is always in the on state, and the sixth power semiconductor device S6 is always in the off state;

[0011] The switching period is calculated according to the negative half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period;

[0012] Step A4, if the second power semiconductor device S2 has an open circuit fault, the eighth power semiconductor device S8 is always in the on state, and the seventh power semiconductor device S7 is always in the off state; if the fourth power semiconductor device S4 has an open circuit fault, the sixth power semiconductor device S6 is always in the on state, and the fifth power semiconductor device S5 is always in the off state;

[0013] The switching period is calculated according to the positive half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0014] Preferably, in step A2, the initial phase of the high-frequency current The calculation method is:

[0015]

[0016] Among them, λ F is the ratio of the resonant capacitor to the DC side capacitor of the resonant dual active bridge converter, and n is the transformation ratio of the high frequency transformer;

[0017] λ F The calculation method is:

[0018]

[0019] Preferably, in step A2, the switching frequency is calculated as follows:

[0020]

[0021] Among them, f rF1 is the resonant frequency of the resonant dual active bridge converter.

[0022] Preferably, in step A2, the switching timing of the power semiconductor device is allocated based on the switching frequency, and the method is:

[0023] When k / 2f s ≤t<(k+1) / 2f sWhen , the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned on, and the second power semiconductor device S2 and the third power semiconductor device S3 are turned off;

[0024] When (k+1) / 2f s ≤t<(k+2) / 2f s When , the second power semiconductor device S2 and the third power semiconductor device S3 are turned on, and the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off;

[0025] Among them, k is an integer and t is a time variable.

[0026] Preferably, in step A3, the high-frequency current negative half-wave amplitude and the high-frequency current negative half-wave initial phase are calculated by:

[0027]

[0028] Among them, I rn is the negative half-wave amplitude of the high-frequency current, θ n is the initial phase of the negative half-wave of the high-frequency current, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k n is the negative half cycle capacitance ratio coefficient, ω rn is the negative half-cycle resonant angular frequency;

[0029] k n and ω rn , which is calculated as:

[0030]

[0031] Preferably, in step A3, the switching period includes a positive half-wave switching period and a negative half-wave switching period, and the calculation method thereof is:

[0032]

[0033] Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the negative half-cycle current, and its calculation method is:

[0034]

[0035] Preferably, in step A3, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is:

[0036] When the first power semiconductor device S1 is open, kt p +kt n ≤t<(k+1)tp +kt n , the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off;

[0037] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off;

[0038] When the third power semiconductor device S3 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 , the fourth power semiconductor device S4 , and the eighth power semiconductor device S8 are turned on, and the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned off;

[0039] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned on; the first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned off;

[0040] Among them, k is an integer and t is a time variable.

[0041] Preferably, in step A4, the high-frequency current positive half-wave amplitude and initial phase are calculated as follows:

[0042]

[0043] Among them, I rp is the positive half-wave amplitude of the high-frequency current, θ p is the initial phase of the high-frequency current positive half-wave, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k p is the positive half-cycle capacitance ratio coefficient, ω rp is the positive half-cycle resonant angular frequency;

[0044] k p and ω rp , the calculation method is:

[0045]

[0046] Preferably, in step A4, the switching period includes a positive half-wave switching period and a negative half-wave switching period, and the calculation method thereof is:

[0047]

[0048] Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the negative half-cycle current, and its calculation method is:

[0049]

[0050] Preferably, in step A4, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is:

[0051] When the second power semiconductor device S2 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 , the fourth power semiconductor device S4 , and the fifth power semiconductor device S5 are turned on, and the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned off;

[0052] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned on, and the first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned off;

[0053] When the fourth power semiconductor device S4 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned off;

[0054] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n, the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned on, and the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned off;

[0055] Among them, k is an integer and t is a time variable.

[0056] Beneficial effects of the present invention:

[0057] Improve system reliability: Through specific switching frequency and timing control strategies, the system can maintain stable operation in the event of an open circuit failure in the power semiconductor device, avoiding the risk of failure of the entire power electronic transformer due to a single device failure.

[0058] No additional hardware is required: Compared with some methods that require the addition of additional hardware to achieve fault-tolerant operation, the present invention only relies on software algorithm adjustment and does not require additional hardware investment, which reduces costs and simplifies system design.

[0059] Adapt to small DC side capacitor applications: It is particularly suitable for situations where the DC side capacitor is small, which helps to reduce the volume of energy storage components and further improve the power density of the converter, making the converter more suitable for applications with limited space but high requirements for efficiency and power density.

[0060] Enhanced flexibility: Different control strategies are adopted according to the open circuit faults in different locations, which improves the control system's responsiveness and adaptability to different types of faults and enhances the overall flexibility of the system.

[0061] Improved efficiency: By accurately calculating and distributing the switching cycles, unnecessary energy losses can be minimized, ensuring that the converter can operate efficiently even in fault-tolerant mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0063] Figure 1 It is a resonant dual active bridge converter circuit topology;

[0064] Figure 2 It is a flow chart of the power semiconductor open-circuit fault tolerance control method of the resonant dual active bridge converter of the present invention;

[0065] Figure 3 The high-frequency voltage and current waveforms of the fifth power semiconductor device S5 of the resonant dual active bridge converter under an open circuit fault;

[0066] Figure 4The high-frequency voltage and current waveforms are shown in the figure when the first power semiconductor device S1 of the resonant dual active bridge converter is open-circuited. DETAILED DESCRIPTION

[0067] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0068] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0069] The present invention provides a resonant dual active bridge converter power semiconductor open circuit fault tolerance control method, which is applied to a resonant dual active bridge converter in the prior art. The resonant dual active bridge converter comprises a high voltage side DC capacitor C1, a low voltage side DC capacitor C2, and a high voltage side resonant capacitor C rp , low voltage side resonant capacitor C rs , high frequency transformer leakage inductance L r , a first power semiconductor device S1, a second power semiconductor device S2, a third power semiconductor device S3, a fourth power semiconductor device S4, a fifth power semiconductor device S5, a sixth power semiconductor device S6, a seventh power semiconductor device S7, and an eighth power semiconductor device S8, the method comprising:

[0070] Step A1, determine the position of the power semiconductor having an open circuit fault. If the power semiconductor having an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, jump to step A2;

[0071] If the power semiconductor device having an open circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, jump to step A3; if the power semiconductor device having an open circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, jump to step A4;

[0072] Step A2, locking the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, calculating the switching frequency according to the initial phase of the high-frequency current, and allocating the switching timing of the power semiconductor devices based on the switching frequency;

[0073] Step A3: if the first power semiconductor device S1 has an open circuit fault, the seventh power semiconductor device S7 is always in the on state, and the eighth power semiconductor device S8 is always in the off state.

[0074] If an open circuit fault occurs in the third power semiconductor device S3, the fifth power semiconductor device S5 is always in the on state, and the sixth power semiconductor device S6 is always in the off state;

[0075] The switching period is calculated according to the negative half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period;

[0076] Step A4, if the second power semiconductor device S2 has an open circuit fault, the eighth power semiconductor device S8 is always in the on state, and the seventh power semiconductor device S7 is always in the off state; if the fourth power semiconductor device S4 has an open circuit fault, the sixth power semiconductor device S6 is always in the on state, and the fifth power semiconductor device S5 is always in the off state;

[0077] The switching period is calculated according to the positive half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0078] In order to more clearly explain the power semiconductor open-circuit fault tolerance control method of the resonant dual active bridge converter of the present invention, the following is combined with Figure 1 and Figure 2 Each step in the embodiment of the present invention is described in detail as follows:

[0079] Step A1, determine the position of the power semiconductor having an open circuit fault. If the power semiconductor having an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, jump to step A2;

[0080] Step A2, locking the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, the switching frequency of the resonant dual active bridge converter is consistent with that when there is no fault, the switching frequency is calculated according to the initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching frequency;

[0081] In step A2, the initial phase of the high-frequency current The calculation method is:

[0082]

[0083] Among them, λ Fis the ratio of the resonant capacitor to the DC side capacitor of the resonant dual active bridge converter, and n is the transformation ratio of the high frequency transformer;

[0084] λ F The calculation method is:

[0085]

[0086] In step A2 of the present invention, the switching frequency is calculated as follows:

[0087]

[0088] Among them, f rF1 is the resonant frequency of the resonant dual active bridge converter.

[0089] In step A2 of the present invention, the switching timing of the power semiconductor device is allocated based on the switching frequency, and the method is as follows:

[0090] When k / 2f s ≤t<(k+1) / 2f s When , the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned on, and the second power semiconductor device S2 and the third power semiconductor device S3 are turned off;

[0091] When (k+1) / 2f s ≤t<(k+2) / 2f s When , the second power semiconductor device S2 and the third power semiconductor device S3 are turned on, and the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off;

[0092] Wherein, k is an integer used to divide the time interval to ensure that different semiconductor devices are turned on or off in a predetermined order in different time intervals, thereby realizing power distribution and control. t is a time variable used to determine which semiconductor devices should be turned on or off in a specific time interval, thereby realizing power distribution and control.

[0093] If the power semiconductor device having an open circuit failure is the first power semiconductor device S1 or the third power semiconductor device S3, jump to step A3;

[0094] Step A3: if the first power semiconductor device S1 has an open circuit fault, the seventh power semiconductor device S7 is always in the on state, and the eighth power semiconductor device S8 is always in the off state.

[0095] If an open circuit fault occurs in the third power semiconductor device S3, the fifth power semiconductor device S5 is always in the on state, and the sixth power semiconductor device S6 is always in the off state;

[0096] The switching period is calculated according to the negative half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period;

[0097] In step A3, the high-frequency current negative half-wave amplitude and the high-frequency current negative half-wave initial phase are calculated as follows:

[0098]

[0099] Among them, I rn is the negative half-wave amplitude of the high-frequency current, θ n is the initial phase of the negative half-wave of the high-frequency current, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k n is the negative half cycle capacitance ratio coefficient, ω rn is the negative half-cycle resonant angular frequency;

[0100] k n and ω rn , which is calculated as:

[0101]

[0102] In step A3, the switching period includes a positive half-wave switching period and a negative half-wave switching period, and the calculation method is:

[0103]

[0104] Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the negative half-cycle current, and its calculation method is:

[0105]

[0106] In step A3, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows:

[0107] When the first power semiconductor device S1 is open, kt p +kt n ≤t<(k+1)t p +kt n , the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off;

[0108] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n, the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off;

[0109] When the third power semiconductor device S3 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 , the fourth power semiconductor device S4 , and the eighth power semiconductor device S8 are turned on, and the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned off;

[0110] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned on; the first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned off;

[0111] Among them, k is an integer and t is a time variable.

[0112] If the power semiconductor device having an open circuit failure is the second power semiconductor device S2 or the fourth power semiconductor device S4, jump to step A4;

[0113] Step A4, if the second power semiconductor device S2 has an open circuit fault, the eighth power semiconductor device S8 is always in the on state, and the seventh power semiconductor device S7 is always in the off state; if the fourth power semiconductor device S4 has an open circuit fault, the sixth power semiconductor device S6 is always in the on state, and the fifth power semiconductor device S5 is always in the off state;

[0114] The switching period is calculated according to the positive half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period.

[0115] In step A4, the high-frequency current positive half-wave amplitude and initial phase are calculated as follows:

[0116]

[0117] Among them, I rp is the positive half-wave amplitude of the high-frequency current, θ p is the initial phase of the high-frequency current positive half-wave, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k p is the positive half-cycle capacitance ratio coefficient, ω rp is the positive half-cycle resonant angular frequency;

[0118] k p and ω rp , the calculation method is:

[0119]

[0120] In step A4, the switching period includes a positive half-wave switching period and a negative half-wave switching period, and the calculation method is:

[0121]

[0122] Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the negative half-cycle current, and its calculation method is:

[0123]

[0124] In step A4, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows:

[0125] When the second power semiconductor device S2 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 , the fourth power semiconductor device S4 , and the fifth power semiconductor device S5 are turned on, and the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned off;

[0126] (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned on, and the first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned off;

[0127] When the fourth power semiconductor device S4 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned off;

[0128] (k+1)t p +kt n≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned on, and the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned off;

[0129] Among them, k is an integer and t is a time variable.

[0130] An embodiment of the present invention is as follows:

[0131] In this embodiment, the main circuit parameters of the resonant dual active bridge converter are shown in the following table:

[0132] The fault-tolerant control method is described by taking the open-circuit failure of the fifth power semiconductor device S5 and the first power semiconductor device S1 as an example.

[0133] When an open circuit fault occurs in the fifth power semiconductor device S5, the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7 and the eighth power semiconductor device S8 are locked. The switching frequency of the resonant dual active bridge converter is consistent with that when there is no fault, and the switching frequency calculation method includes the following steps:

[0134] (1) Calculate the initial phase of high-frequency current

[0135] The initial phase of the high-frequency current of the resonant dual active bridge converter satisfies the following equation:

[0136]

[0137] Among them, λ F is the ratio of the resonant capacitor to the DC side capacitor of the resonant dual active bridge converter, and n is the transformation ratio of the high frequency transformer.

[0138]

[0139] (2) Calculate the switching frequency

[0140] The switching frequency is calculated based on the initial phase of the high-frequency current calculated in (1), as follows:

[0141]

[0142] Among them, f rF1 is the resonant frequency of the resonant dual active bridge converter.

[0143] (3) Allocating the switching timing of power semiconductor devices

[0144] When k / 2f s≤t<(k+1) / 2f s When (k is an integer, f s =25kHz), the first power semiconductor device S1 and the fourth power semiconductor device S4 of the resonant dual active bridge converter are turned on, and the second power semiconductor device S2 and the third power semiconductor device S3 are turned off; when (k+1) / 2f s ≤t<(k+2) / 2f s When , the second power semiconductor device S2 and the third power semiconductor device S3 of the resonant dual active bridge converter are turned on; the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off.

[0145] When an open circuit fault occurs in the first power semiconductor device S1, the seventh power semiconductor device S7 is always in the on state, and the eighth power semiconductor device S8 is always in the off state; the switching frequency calculation method includes the following steps:

[0146] (1) Calculate the negative half-wave amplitude and initial phase of high-frequency current

[0147] The negative half-wave amplitude and initial phase of the high-frequency current of the resonant dual active bridge converter satisfy the following equations:

[0148]

[0149] Among them, I rn is the negative half-wave amplitude of the high-frequency current, θ n is the initial phase of the negative half-wave of the high-frequency current, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k n and ω rn The expression is as follows

[0150]

[0151] (2) Calculate the switching cycle

[0152] According to the negative half-wave amplitude and initial phase of the high-frequency current calculated in (1), the positive half-wave and negative half-wave switching periods of the resonant dual active bridge converter are calculated as follows:

[0153]

[0154] Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the current adjacent to the negative half cycle calculated according to the following formula:

[0155]

[0156] (3) Allocating the switching timing of power semiconductor devices

[0157] When the first power semiconductor device S1 is open, kt p +kt n ≤t<(k+1)t p +kt n (k is an integer), the fourth power semiconductor device S4 and the fifth power semiconductor device S5 of the resonant dual active bridge converter are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off; (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 of the resonant dual active bridge converter are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off.

[0158] Figure 3 The high-frequency voltage and current waveforms of the resonant dual active bridge converter when the fifth power semiconductor device S5 has an open circuit fault. After the fifth power semiconductor device S5 has an open circuit fault, the resonant dual active bridge converter can still be soft-switched by adopting the proposed fault-tolerant control method.

[0159] Figure 4 The high-frequency voltage and current waveforms under the open-circuit fault of the first power semiconductor device S1 of the resonant dual active bridge converter. It can be seen from the simulation waveform that after the first power semiconductor device S1 has an open-circuit fault, the positive and negative half-waves of the high-frequency current of the resonant dual active bridge converter become asymmetric. After adopting the proposed fault-tolerant control method, soft switching of all power semiconductor devices can be achieved. Therefore, the control method of the present invention can achieve fault-tolerant operation under the open-circuit fault of the power semiconductor device of the resonant dual active bridge converter.

[0160] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0161] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0162] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0163] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A resonant dual active bridge converter power semiconductor open circuit fault tolerance control method, applied to a resonant dual active bridge converter, characterized in that: The method includes: Step A1, determine the position of the power semiconductor having an open circuit fault. If the power semiconductor having an open circuit fault is any one of the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, jump to step A2; If the power semiconductor device having an open circuit fault is the first power semiconductor device S1 or the third power semiconductor device S3, jump to step A3; if the power semiconductor device having an open circuit fault is the second power semiconductor device S2 or the fourth power semiconductor device S4, jump to step A4; Step A2, locking the fifth power semiconductor device S5, the sixth power semiconductor device S6, the seventh power semiconductor device S7, and the eighth power semiconductor device S8, calculating the switching frequency according to the initial phase of the high-frequency current, and allocating the switching timing of the power semiconductor devices based on the switching frequency; Step A3: if the first power semiconductor device S1 has an open circuit fault, the seventh power semiconductor device S7 is always in the on state, and the eighth power semiconductor device S8 is always in the off state. If an open circuit fault occurs in the third power semiconductor device S3, the fifth power semiconductor device S5 is always in the on state, and the sixth power semiconductor device S6 is always in the off state; The switching period is calculated according to the negative half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period; Step A4, if the second power semiconductor device S2 has an open circuit fault, the eighth power semiconductor device S8 is always in the on state, and the seventh power semiconductor device S7 is always in the off state; if the fourth power semiconductor device S4 has an open circuit fault, the sixth power semiconductor device S6 is always in the on state, and the fifth power semiconductor device S5 is always in the off state; The switching period is calculated according to the positive half-wave amplitude and initial phase of the high-frequency current, and the switching timing of the power semiconductor device is allocated based on the switching period.

2. The method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 1, characterized in that: In step A2, the initial phase of the high-frequency current The calculation method is: Among them, λ F is the ratio of the resonant capacitor to the DC side capacitor of the resonant dual active bridge converter, and n is the transformation ratio of the high frequency transformer; λ F The calculation method is:

3. A method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 2, characterized in that: In step A2, the switching frequency is calculated as follows: Among them, f rF1 is the resonant frequency of the resonant dual active bridge converter.

4. A method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 3, characterized in that: In step A2, the switching timing of the power semiconductor device is allocated based on the switching frequency, and the method is as follows: When k / 2f s ≤t<(k+1) / 2f s When , the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned on, and the second power semiconductor device S2 and the third power semiconductor device S3 are turned off; When (k+1) / 2f s ≤t<(k+2) / 2f s When , the second power semiconductor device S2 and the third power semiconductor device S3 are turned on, and the first power semiconductor device S1 and the fourth power semiconductor device S4 are turned off; Among them, k is an integer and t is a time variable.

5. The method for controlling power semiconductor open-circuit fault tolerance of a resonant dual active bridge converter according to claim 1, characterized in that: In step A3, the high-frequency current negative half-wave amplitude and the high-frequency current negative half-wave initial phase are calculated as follows: Among them, I rn is the negative half-wave amplitude of the high-frequency current, θ n is the initial phase of the negative half-wave of the high-frequency current, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k n is the negative half cycle capacitance ratio coefficient, ω rn is the negative half-cycle resonant angular frequency; k n and ω rn , which is calculated as:

6. A method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 5, characterized in that: In step A3, the switching period includes a positive half-wave switching period and a negative half-wave switching period, and the calculation method is: Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the negative half-cycle current, and its calculation method is:

7. A method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 6, characterized in that: In step A3, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows: When the first power semiconductor device S1 is open, kt p +kt n ≤t<(k+1)t p +kt n , the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned off; (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2, the third power semiconductor device S3, and the sixth power semiconductor device S6 are turned on; the fourth power semiconductor device S4 and the fifth power semiconductor device S5 are turned off; When the third power semiconductor device S3 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 , the fourth power semiconductor device S4 , and the eighth power semiconductor device S8 are turned on, and the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned off; (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2 and the seventh power semiconductor device S7 are turned on; the first power semiconductor device S1, the fourth power semiconductor device S4, and the eighth power semiconductor device S8 are turned off; Among them, k is an integer and t is a time variable.

8. The method for controlling power semiconductor open-circuit fault tolerance of a resonant dual active bridge converter according to claim 1, characterized in that: In step A4, the high-frequency current positive half-wave amplitude and initial phase are calculated as follows: Among them, I rp is the positive half-wave amplitude of the high-frequency current, θ p is the initial phase of the high-frequency current positive half-wave, i1 is the input current on the high-voltage side of the resonant dual active bridge converter, k p is the positive half-cycle capacitance ratio coefficient, ω rp is the positive half-cycle resonant angular frequency; k p and ω rp , the calculation method is:

9. A method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 8, characterized in that: In step A4, the switching period includes a positive half-wave switching period and a negative half-wave switching period, and the calculation method is: Among them, t p is the positive half-wave switching period, t n is the negative half-wave switching period, t z1 and t z2 It is the zero-crossing moment of the negative half-cycle current, and its calculation method is:

10. A method for controlling power semiconductor open-circuit faults of a resonant dual active bridge converter according to claim 9, characterized in that: In step A4, the switching timing of the power semiconductor device is allocated based on the switching cycle, and the method is as follows: When the second power semiconductor device S2 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 , the fourth power semiconductor device S4 , and the fifth power semiconductor device S5 are turned on, and the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned off; (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the third power semiconductor device S3 and the sixth power semiconductor device S6 are turned on, and the first power semiconductor device S1, the fourth power semiconductor device S4, and the fifth power semiconductor device S5 are turned off; When the fourth power semiconductor device S4 is open, kt p +kt n ≤t<(k+1)t p +kt n , the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned on, and the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned off; (k+1)t p +kt n ≤t<(k+1)t p +(k+1)t n , the second power semiconductor device S2, the third power semiconductor device S3, and the seventh power semiconductor device S7 are turned on, and the first power semiconductor device S1 and the eighth power semiconductor device S8 are turned off; Among them, k is an integer and t is a time variable.

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