Apparatus and method for protecting power amplifier

Abstract

The invention relates to a device and a method for protecting a power amplifier. An example apparatus includes: a first interpolation circuitry (202); a second interpolation circuitry (204); first band envelope determination circuitry (206), the first band envelope determination circuitry having an input coupled to the first interpolation circuitry (202), and having an output; second band envelope determination circuitry (208) having an input coupled to the second interpolation circuitry (204), and having an output; a combiner circuitry (210) having a first input coupled to the output of the first band envelope determination circuitry (206), having a second input coupled to the output of the second band envelope determination circuitry (208), and having an output; and signal monitor circuitry (212) having an input terminal coupled to the output terminal of the combiner circuitry (210).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit and priority of Indian Provisional Patent Application No. 202341076646 filed on November 9, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description relates generally to circuits and, more particularly, to apparatus and methods for protecting power amplifiers. Background Art

[0004] In communication applications, a power amplifier (PA) is used to amplify the transmitted signal so that the transmitted signal has enough power to reach the destination. The signal input to the power amplifier can have different power levels before such amplification. Summary of the invention

[0005] For methods, apparatus, systems, and articles of manufacture for protecting a power amplifier, an example apparatus includes: a first interpolation circuit system; a second interpolation circuit system; a first frequency band envelope determination circuit system, the first frequency band envelope determination circuit system having an input coupled to the first interpolation circuit system and having an output; a second frequency band envelope determination circuit system, the second frequency band envelope determination circuit system having an input coupled to the second interpolation circuit system and having an output; a combiner circuit system, the combiner circuit system having a first input coupled to the output of the first frequency band envelope determination circuit system, having a second input coupled to the output of the second frequency band envelope determination circuit system, and having an output; and a signal monitor circuit system, the signal monitor circuit system having an input coupled to the output of the combiner circuit system. Other examples are described.

[0006] For methods, devices, systems and articles of manufacture for protecting a power amplifier, an example device includes: a power amplifier circuit system, the power amplifier circuit system having an input terminal; a digital-to-analog converter circuit system, the digital-to-analog converter circuit system having an output terminal coupled to the input terminal of the power amplifier circuit system and having an input terminal; a multiplier circuit system, the multiplier circuit system having an output terminal coupled to the input terminal of the digital-to-analog converter circuit system and having a first input terminal and a second input terminal; a first combiner circuit system, the first combiner circuit system having an output terminal coupled to the first input terminal of the multiplier circuit system and having a first input terminal and a second input terminal; a first mixer circuit system, the first mixer circuit system having an output terminal coupled to the first input terminal of the first combiner circuit system and having an input terminal; a second mixer circuit system, the second mixer circuit system having an output terminal coupled to the second input terminal of the first combiner circuit system and having an input terminal; a first internal interpolation circuitry, the first interpolation circuitry having an output coupled to the input of the first mixer circuitry and having an input; a second interpolation circuitry, the second interpolation circuitry having an output coupled to the input of the second mixer circuitry and having an input; a first frequency band envelope determination circuitry, the first frequency band envelope determination circuitry having an input coupled to the first interpolation circuitry and having an output; a second frequency band envelope determination circuitry, the second frequency band envelope determination circuitry having an input coupled to the second interpolation circuitry and having an output; a second combiner circuitry, the second combiner circuitry having a first input coupled to the output of the first frequency band envelope determination circuitry and a second input coupled to the output of the second frequency band envelope determination circuitry and having an output; and a signal monitor circuitry, the signal monitor circuitry having an input coupled to the output of the second combiner circuitry. Other examples are described.

[0007] For methods, devices, systems and articles of manufacture for protecting a power amplifier, an example device includes: a frequency band envelope determination circuit system, the frequency band envelope determination circuit system is configured to determine an envelope corresponding to a first frequency band signal and has an output terminal; a combiner circuit system, the combiner circuit system has an input terminal coupled to the output terminal of the frequency band envelope determination circuit system and is configured to generate a combined envelope signal by combining the envelope corresponding to the first frequency band signal and the envelope corresponding to the second frequency band signal, and has an output terminal; a signal monitor circuit system, the signal monitor circuit system is A power amplifier is configured to determine that the combined envelope signal meets a damage criterion for a power amplifier and has an output; a controller circuit system having an input coupled to the output of the signal monitor circuit system and configured to generate a power reduction value and has an output; and a multiplier circuit system having a first input coupled to the output of the controller circuit system, the multiplier circuit system configured to reduce the power of a combined radio frequency (RF) signal based on the power reduction value, the combined RF signal corresponding to the combined envelope signal. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example communication system environment is depicted in which the power amplifier protection (PAP) circuitry described herein may be implemented.

[0009] Figure 2A-2C Shows include Figure 1 An example transmitter circuit system of a PAP circuit system to protect a power amplifier.

[0010] Figure 3 Yes Figure 1 An example transmitter circuit system of another embodiment of the PAP circuit system of FIG. 5 is provided in which the input of the frequency band envelope determination circuit system is connected to the output of the interpolation circuit system.

[0011] Figure 4 Yes Figure 1 An example transmitter circuit system of yet another embodiment of the PAP circuit system of FIG. 1 is provided in which an input of the band envelope determination circuit system is coupled to the interpolation circuit system between the interpolation circuit system stages.

[0012] Figure 5 It is shown by Figure 1-4 An example signal diagram of a corrupted candidate portion detected by the PAP circuit system in the frequency band envelope.

[0013] Figure 6 Is implemented Figure 1-4Flow diagram of example operations of a PAP circuit system to protect a power amplifier from damaging effects of a portion of a combined RF signal that exceeds a power threshold. DETAILED DESCRIPTION

[0014] Generally, the same reference numerals will be used throughout the drawings and the accompanying written description to refer to the same or similar parts. The drawings are not necessarily drawn to scale. Instead, the thickness of a layer or region may be exaggerated in the drawings. Although the drawings show layers and regions with clean lines and boundaries, some or all of these lines or boundaries may be idealized. In reality, boundaries or lines may be unobservable, blended, or irregular.

[0015] Power amplifiers (PAs) are used in wireless communications to amplify signals before transmission. PAs are sensitive to input signal power due to electrical characteristics, such as rated power or maximum rated voltage. Therefore, the PA may be highly sensitive to various parameters of the input signal, such as the power of the signal being too high for an extended period of time. Examples described herein include a power amplifier protection (PAP) circuit system that calculates the envelope of an input frequency band signal obtained before a mixer circuit system of a transmission circuit and determines a combined envelope of the frequency band signals. In some examples, the mixer circuit system operates in parallel with the PAP circuit system to generate a radio frequency (RF) signal based on the input frequency band signal. In this way, information in the input frequency band signal can be transmitted via the RF signal. The combined envelope generated by the PAP circuit system is monitored by a signal monitor to detect portions of the combined envelope that indicate corresponding portions of the RF signal that may damage the power amplifier (PA). When a portion of the RF signal that may damage the PA is detected, the signal monitor sends an alarm / warning to the PAP controller. The alarm / warning triggers the PAP controller to implement a power reduction scheme to reduce the power of the RF signal portion before it reaches the PA. This in turn prevents damage to the PA by preventing excessive power RF signals from entering the PA.

[0016] The examples described herein can be used to adapt to different PAs. For example, a signal power threshold that defines the excess power of the PA can be selected based on the electrical characteristics of the PA. The signal power threshold can be programmed into the PAP circuit system based on the PA to be used for a specific circuit design.

[0017] Figure 1 A cellular communication system 102 and a satellite communication system 104 are depicted that may implement the example power amplifier protection (PAP) circuit system 106 described herein. Each of the cellular communication system 102 and the satellite communication system 104 includes a corresponding transceiver, such as an example Figure 1. The transceiver 108 includes a transmitter circuit system 112 and a receiver circuit system 114. The transmitter circuit system 112 receives one or more transmit (Tx) band signals (e.g., communication logic from the communication system 102, 104, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a baseband processor, a programmable circuit system, etc.), and generates a Tx RF signal including the Tx band signal. The transmitter circuit system 112 then transmits the Tx band signal via the TxRF signal.

[0018] The receiver circuit system 114 receives the receive (Rx) RF signal via a transmission medium (e.g., conductive wire, optical fiber, radio electromagnetic waves, etc.) and recovers one or more Rx band signals from the Rx RF signal. The receiver circuit system 114 then provides the one or more Rx band signals to the communication logic of the communication system 102, 104.

[0019] In the example Figure 1 , PAP circuitry 106 is implemented in transmitter circuitry 112. PAP circuitry 106 protects a PA (not shown) of transmitter circuitry 112 from damage that may be caused by a portion of a Tx RF signal having too much power. For example, a signal power level that exceeds the PA rated power may be too powerful. Cellular communication system 102 and satellite communication system 104 may be implemented using any type of communication circuitry, including a 5G wireless base station for a 5G based communication system. Although Figure 1 Only the cellular communication system 102 and the satellite communication system 104 are shown, and the PAP circuit system 106 can be implemented in any other communication system, such as an automobile communication system, a mobile communication device (e.g., a mobile phone, a tablet device, a laptop computer, etc.), a desktop computer, an Internet device, a smart wearable device, etc.

[0020] Figure 2A Yes Figure 1 1. Example transmitter circuitry 200 of the PAP circuitry 106. Figure 2A The transmitter circuit system 200 may be used to implement Figure 1The transmitter circuit system 200 is implemented as a dual-band mode transmitter in which two separate input baseband signals (referred to herein as band signals, such as "Band-1 Tx Data" and "Band-2 Tx Data") are interpolated and up-converted to radio frequency (RF) signals having different center frequencies. The example dual-band mode of the transmitter circuit system 200 allows the same data or different data to be transmitted on two different frequencies to support multiple band frequencies using the same device. Similarly or alternatively, the transmitter circuit system 200 can be implemented to process signals of more than two bands.

[0021] The input baseband signal is referred to as a band signal to indicate that after the first band signal and the second band signal (e.g., baseband signal) are converted into RF signals, they will occupy different center frequency bands. Therefore, the first band signal (e.g., first baseband signal) occupies a first frequency band (e.g., first center frequency), and the second band signal (e.g., second baseband signal) occupies a second frequency band different from the first frequency band (e.g., second center frequency). In the examples described herein, the interval between the center frequencies is small enough that the two RF signals can be combined, and a single power amplifier (PA) can be used to amplify the two band signals.

[0022] In the example Figure 2A In the embodiment of the present invention, the input frequency band signals (e.g., "baseband-1Tx data" and "baseband-2Tx data") can be provided by communication logic, such as FPGA, ASIC, baseband processor, programmable circuit system. In some examples, the baseband processor is coupled to the FPGA or ASIC to generate the input frequency band signals. For example, the FPGA or ASIC can encode or modulate (e.g., orthogonal frequency division multiplexing (OFDM)) the data provided by the baseband processor to generate the input frequency band signals so that the data can be transmitted by the transmitter circuit system 200.

[0023] Transmitter circuitry 200 includes first interpolation circuitry 202, second interpolation circuitry 204, first frequency band envelope determination circuitry 206, second frequency band envelope determination circuitry 208, first combiner circuitry 210, signal monitor circuitry 212, and PAP controller circuitry 214. Figure 2A In FIG. 1 , band envelope determination circuitry 206, band envelope determination circuitry 208, combiner circuitry 210, and signal monitor circuitry 212 are included in PAP detector circuitry 215. PAP detector circuitry 215 and PAP controller circuitry 214 are included in PAP circuitry 106.

[0024] Band envelope determination circuitry 206 has an input coupled to interpolation circuitry 202. Band envelope determination circuitry 206 also has an output. Band envelope determination circuitry 208 has an input coupled to interpolation circuitry 204. Band envelope determination circuitry 208 also has an output. Inputs of band envelope determination circuitry 206, 208 and interpolation circuitry 202, 204 receive input band signals. For example, band envelope determination circuitry 206 and interpolation circuitry 202 receive Figure 2A In addition, the band envelope determination circuit system 208 and the interpolation circuit system 204 receive the first input band signal shown as "Band-1 Tx Data". Figure 2A 1 is a second input band signal shown as “Band-2Tx Data” in FIG. 1. As used herein, a band signal is a signal that includes information and is based on a single center frequency.

[0025] In the examples described herein, the frequency band signal is up-converted to a frequency for transmitting the resulting signal by a mixer circuit system (e.g., mixer circuit systems 222, 224). However, the examples described herein may also be implemented in a transmit circuit that generates an intermediate frequency (IF) signal. For example, a mixer circuit system may be used to up-convert an IF signal to an intermediate frequency lower than the RF frequency at which the signal transmission occurs to generate an IF signal. The IF signal may then be up-converted to an RF frequency by a second mixer circuit system to generate an RF signal to be transmitted.

[0026] Combiner circuitry 210 has a first input coupled to the output of frequency band envelope determination circuitry 206. Combiner circuitry 210 also has a second input coupled to the output of frequency band envelope determination circuitry 208. Combiner circuitry 210 also has an output. Signal monitor circuitry 212 has an input coupled to the output of combiner circuitry 210. Signal monitor circuitry 212 also has an output. Controller circuitry 214 has an input coupled to the output of signal monitor circuitry 212.

[0027] Transmitter circuitry 200 also includes multiplier circuitry 216, digital-to-analog converter (DAC) circuitry 218, and PA circuitry 220. Multiplier circuitry 216 has a first input coupled to the output of controller circuitry 214. Multiplier circuitry 216 also has an output. DAC circuitry 218 has an input coupled to the output of multiplier circuitry 216. DAC circuitry 218 also has an output. Power amplifier circuitry 220 has an input coupled to the output of DAC circuitry 218.

[0028] Transmitter circuitry 200 also includes first mixer circuitry 222, second mixer circuitry 224, and second combiner circuitry 226. Mixer circuitry 222 has an input coupled to the output of interpolation circuitry 202. Mixer circuitry 222 also has an output. Mixer circuitry 224 has an input coupled to the output of interpolation circuitry 204. Mixer circuitry 224 also has an output. Combiner circuitry 226 has a first input coupled to the output of mixer circuitry 222, and a second input coupled to the output of mixer circuitry 224. Combiner circuitry 226 also has an output coupled to a second input of multiplier circuitry 216.

[0029] Alternatively, if Figure 2B As shown, multiplier circuitry 216 may be replaced by first multiplier circuitry 232 and second multiplier circuitry 234 coupled to respective outputs of interpolation circuitry 202, 204, rather than multiplier circuitry 216 being positioned after combiner circuitry 226. Figure 2B 204, a first input of multiplier circuitry 232 is coupled to the output of interpolation circuitry 202, and an output of multiplier circuitry 232 is coupled to an input of mixer circuitry 222. Additionally, a first input of multiplier circuitry 234 is coupled to the output of interpolation circuitry 204, and an output of multiplier circuitry 234 is coupled to an input of mixer circuitry 224. In such an example, an output of PAP controller circuitry 214 is coupled to a second input of multiplier circuitry 232 and a second input of multiplier circuitry 234.

[0030] In yet another alternative embodiment, Figure 2C As shown, multiplier circuit system 216 may be replaced by first multiplier circuit system 236 and second multiplier circuit system 238 coupled to respective output terminals of mixer circuit systems 222, 224. Figure 2C 224, and an output of multiplier circuitry 236 is coupled to a first input of combiner circuitry 226. Additionally, a first input of multiplier circuitry 238 is coupled to an output of mixer circuitry 224, and an output of multiplier circuitry 238 is coupled to a second input of combiner circuitry 226. In such an example, an output of PAP controller circuitry 214 is coupled to a second input of multiplier circuitry 236 and a second input of multiplier circuitry 238.

[0031] In the examples described herein, the input band signals (e.g., "Band-1 Tx Data" and "Band-2 Tx Data") provided to the transmitter circuit system 200 are digital signals in the digital domain. As such, the input band signals include digital samples that encode the information carried by the band signals. To prepare the input band signals for transmission by the transmitter circuit system 200, the interpolation circuit system 202 and the interpolation circuit system 204 interpolate the corresponding band signals of the input band signals by generating interpolated digital samples based on the original digital samples in these band signals. For example, the original digital samples in the input band signals have a sampling rate resolution such that the original digital samples appear at a specific rate within the duration of the input band signals. To increase the sampling resolution of the input band signals, the interpolation circuit systems 202, 204 use the original digital samples to generate and add interpolated digital samples between the original digital samples. Thus, an example input sampling rate for the input band signal may be 500 Msps, and the interpolated sampling rate for the input band signal may be 12 Gsps to match the higher sampling rate of the DAC circuitry 218 .

[0032] In the example Figure 2A In the example, a single-stage RF mixing process is performed on the interpolated frequency band signal (e.g., the higher resolution frequency band signal) by the corresponding circuit systems in the mixer circuit system 222 and the mixer circuit system 224 to up-convert the interpolated frequency band signal to an RF frequency. For example, the mixer circuit system 222 mixes the interpolated frequency band signal from the interpolation circuit system 202 with a first frequency (f1) (e.g., the first center frequency (f1)), and the mixer circuit system 224 mixes the interpolated frequency band signal from the interpolation circuit system 204 with a second frequency (f2) (e.g., the second center frequency (f2)). In the example Figure 2A , the interpolated band signal provided by the interpolation circuit system 202, 204 is a complex signal because it includes both the imaginary and real parts of the signal. In this way, the mixer circuit system 222, 224 generates the up-converted band signal as a complex signal. In an example where only one of the real or imaginary parts of the complex signal is used for additional processing, it is not necessary to generate and process logic for one of the real and imaginary parts that is not used for additional processing. The interpolated and up-converted band signal is provided by the mixer circuit system 222, 224 to the combiner circuit system 226.

[0033] Combiner circuit system 226 generates a combined RF signal based on the interpolated and up-converted signal of the first frequency band signal and the second frequency band signal. The combined RF signal is a digital signal (e.g., in the digital domain), the final form of which will be provided to DAC circuit system 218. DAC circuit system 218 converts the combined RF signal from the digital domain to an analog combined RF signal in the analog domain. Before transmitting the analog combined RF signal, PA circuit system 220 amplifies the power of the analog combined RF signal to a suitable level for transmission. However, some portions of one or more windows of the digital combined RF signal may have characteristics that may cause damage to PA circuit system 220. As such, PAP circuit system 106 monitors such characteristics and adjusts the digital combined RF signal at any portion that may damage PA circuit system 220 before DAC circuit system 218 converts the digital combined RF signal to the analog combined RF signal.

[0034] Turning now to the PAP circuitry 106, the band envelope determination circuitry 206, 208 determines envelope A based on digital samples of corresponding ones of the input band signals (eg, "Band-1 Tx Data" and "Band-2 Tx Data"). i (t) (e.g., frequency band envelope). In the examples described herein, the input frequency band signal is a complex signal including a real part and an imaginary part. As such, the frequency band envelope determination circuitry 206, 208 determines the envelope A based on the complex input frequency band signal. i (t). If the complex signal can be expressed as x(t) = x I (t)+jx Q (t), where x I (t) and x Q (t) are the real and imaginary parts of the signal, then the envelope of the signal can be calculated using Equation 1 below.

[0035]

[0036] For envelope A i (t), index "i" is an indicator of the i-th input frequency band signal. For example, the band envelope determination circuit system 206 determines or calculates a first envelope A1(t) (e.g., index i=1) based on a first input frequency band signal (e.g., "Band-1 Tx Data"), and the band envelope determination circuit system 208 determines or calculates a second envelope A2(t) (e.g., index i=2) based on a second input frequency band signal (e.g., "Band-2 Tx Data"). The combiner circuit system 210 generates a combined envelope signal A(t) by combining the envelopes determined by the band envelope determination circuit systems 206 and 208 based on the input frequency band signals. For example, the combiner circuit system 210 combines the envelopes A1(t) and A2(t) according to Equation 2 below.

[0037] A(t)=A1(t)+A2(t) (Equation 2)

[0038] The signal monitor circuitry 212 monitors the combined envelope signal A(t) generated by the combiner circuitry 210. During such monitoring, the signal monitor circuitry 212 monitors a signal pattern or signal characteristic of the combined envelope signal A(t) to determine whether any portion (e.g., a window) of the combined envelope signal A(t) indicates that a corresponding portion of the combined RF signal generated by the combiner circuitry 226 may damage the PA 220. In the examples described herein, determining possible damage to the PA circuitry 220 is based on whether the combined envelope signal A(t) satisfies one or more damage criteria of the PA circuitry 220. For example, the damage criteria may be established based on one or more of a power threshold, a duration threshold, a power level change rate threshold, or any other suitable characteristic of the PA circuitry 220. The characteristics of the PA circuitry 220 may be obtained from an operating specification (e.g., in a specification table) or design parameters of the PA circuitry 220.

[0039] For example, the power threshold may be based on the electrical power operating range of the PA circuit system 220. Thus, the power threshold may be set to the maximum input operating power that the PA circuit system 220 is rated for. The duration threshold may be set to the maximum time that the PA circuit system 220 is rated to withstand a signal that meets (e.g., reaches or exceeds) the maximum operating power of the PA circuit system 220. The power level change rate threshold may be set to the amount of power level change per time (e.g., per microsecond, per millisecond, etc.) that the PA circuit system 220 is rated to withstand. For example, a sudden change in power in the signal (e.g., a power spike) may cause material failure in the PA circuit system 220. Thus, after the combined envelope signal A(t) meets at least one of the power threshold, the duration threshold, the power level change rate threshold, or any other operating characteristic threshold of the PA circuit system 220, the signal monitor circuit system 212 determines that the combined envelope signal A(t) meets one or more damage criteria in the PA circuit system 220.

[0040] When the signal monitor circuit system 212 determines to reduce the data signal power of the combined RF signal, the signal monitor circuit system 212 provides an alarm or warning to the PAP controller circuit system 214 to trigger a power reduction scheme at the PAP controller circuit system 214. In this power reduction scheme, the PAP controller circuit system 214 initiates a power ramp-down process to reduce the data signal power of the combined RF signal. In some examples, in response to the combined envelope signal A(t) failing to meet one or more damage criteria (e.g., the portion of the combined RF signal that may damage the PA is not detected), the alarm / warning terminal from the signal monitor circuit system 212 can output a logic value of zero ('0') to indicate that there is no alarm / warning. In response to the combined envelope signal A(t) meeting one or more damage criteria (e.g., the portion of the combined RF signal that may damage the PA is not detected), the signal monitor circuit system 212 can output a logic value of one ('1') to indicate an active alarm / warning to be processed by the PAP controller circuit system 214.

[0041] The PAP controller circuitry 214 generates one or more power reduction (PR) values ​​in response to a warning or alarm from the signal monitor circuitry 212 indicating a request to reduce the data signal power of the combined RF signal. For example, the PAP controller circuitry 214 generates one or more consecutive power reduction values ​​to gradually reduce the power in a window of the combined RF signal over time. An example format for representing such a window is T=[n:m], where T is the window time period or duration, 'n' is the start time of the portion of the combined RF signal that may damage the PA, and 'm' is the stop time of the portion of the combined RF signal that may damage the PA. As used herein, a power reduction value is a value that can be used to process a signal to reduce the data signal power of the signal. For example, the power reduction value can be a multiplier value by which the signal is multiplied, can be a subtrahend to be subtracted from the signal, or can be a negative addend to be added to the signal. In Figure 2A, the power reduction value is a multiplier value by which the multiplier circuit system 216 can multiply the combined RF signal to reduce the data signal power of the combined RF signal. For example, a power reduction value of one (PR=1) does not reduce the power, but instead maintains the power at its original level. However, a power reduction value of 0.9 (PR=0.9) reduces the power of the combined RF signal to 90% of its original power. Similarly, a power reduction value of 0.5 (PR=0.5) reduces the power of the combined RF signal to 50% of its original power. In this way, the array of consecutive power reduction values ​​generated by the PAP controller circuit system 214 may include PR[4:0]=0.9, 0.7, 0.5, 0.3, 0.1 to gradually ramp down the power over time in the window. In such an example, multiplier circuitry 216 may multiply successive portions of the combined RF signal in the window by the following successive power reduction values: PR[4]=0.9 at the first signal portion, PR[3]=0.7 at the second signal portion, PR[2]=0.5 at the third signal portion, PR[1]=0.3 at the fourth signal portion, and PR[0]=0.1 at the fifth signal portion. Thereafter, if the affected signal portions are to be zeroed, multiplier circuitry 216 may multiply the combined RF signal by zero.

[0042] In the example Figure 2B , the power reduction value is the multiplier value by which the multiplier circuitry 232, 234 can multiply the interpolated frequency band signals from the interpolation circuitry 202, 204 to reduce the data signal power of the interpolated frequency band signals. This in turn prevents the data signal power of the combined RF signal generated by the combiner circuitry 226 from damaging the PA circuitry 220. In the example Figure 2C In FIG. 2 , the power reduction value is the multiplier value by which the multiplier circuit systems 236, 238 multiply the IF signals from the mixer circuit systems 222, 224 to reduce the data signal power of the IF signals. This in turn prevents the data signal power of the combined RF signal generated by the combiner circuit system 226 from damaging the PA circuit system 220. Figure 2A Similar to the description, Figure 2B The multiplier circuit systems 232, 234 and Figure 2C The multiplier circuitry 236, 238 may use the continuous array of power reduction values ​​generated by the PAP controller circuitry 214 to gradually ramp down the data signal power over time in the window.

[0043] In some instances, power reduction values, such as the example values ​​described above, are generated to ramp down the power of the portions of the combined RF signal that may damage the PA, zeroing out the data for those signal portions. In other instances, power reduction values ​​are generated to ramp down the power of the portions of the combined RF signal that may damage the PA to a power value that does not zero out the data but brings the power level of those signal portions below the damage criteria of the PA circuit system 220. In either case, since the data at the portions of the combined RF signal that are subject to power reduction may not be recovered from those signal portions, the PAP controller circuit system 214 generates an error signal for those signal portions. The PAP controller circuit system 214 may provide the error signal as feedback to a user or communication logic (e.g., FPGA, ASIC, baseband processor, etc.). In this way, the user or communication logic may take corrective measures, such as modifying one or more of the input frequency band signals to prevent damage to the PA circuit system 220, and providing the modified input frequency band signals to the transmitter circuit system 200 for retransmission.

[0044] The portion of the combined RF signal that is subjected to the power reduction corresponds to the portion of the combined envelope signal A(t) that meets the damage criteria of the PA circuit system 220. This gradual reduction in the power of the data signal prevents the DAC circuit system 218 and the PA circuit system 220 from being affected by sudden changes in power that could damage the DAC circuit system 218 or the PA circuit system 220. The gradual reduction in the power of the data signal can also prevent unstable conditions from being generated in the DAC circuit system 218 or the PA circuit system 220 based on sudden power changes. The number of consecutive power reduction values ​​or the amount of reduction between consecutive power reduction values ​​generated by the PAP controller circuit system 214 can be based on the amount of power that needs to be reduced, the electrical operating characteristics of the DAC circuit system 218 or the PA circuit system 220, or the sensitivity of the transmit application to sudden changes in power. For example, if the amount of power that needs to be reduced in the combined RF signal is large, the amount of the consecutive power reduction values ​​may be greater than if less power is to be reduced in the combined RF signal. In some instances, if DAC circuitry 218, PA circuitry 220, or the transmit application is more sensitive to power level variations, the amount of reduction between consecutive power reduction values ​​may be less than if DAC circuitry 218, PA circuitry 220, or the transmit application is less sensitive to power level variations.

[0045] exist Figure 2A, during the power reduction process performed by the PAP controller circuit system 214 and the multiplier circuit system 216, the signal monitor circuit system 212 continues to monitor other portions of the incoming combined envelope signal A(t) to determine whether such portions of the combined envelope signal A(t) meet the one or more corruption criteria. In this way, the signal monitor circuit system 212 can determine whether to continue to reduce the data signal power of subsequent portions of the combined RF signal or to stop reducing the power. When the signal monitor circuit system 212 determines to stop the power reduction of the combined RF signal, the signal monitor circuit system 212 stops providing an alarm or warning to the PAP controller circuit system 214. Similarly or alternatively, any suitable external signal separate from the signal monitor circuit system 212 can be provided to remove the alarm or warning and thereby start the ramp up of the signal power. In any case, there is no alarm or warning indicating that the PAP controller circuit system 214 will initiate the power ramp up scheme of the combined RF signal. In this manner, subsequent portions of the combined RF signal propagate through multiplier circuitry 216 and to DAC circuitry 218 and PA circuitry 220 at their original power levels.

[0046] exist Figure 2A, during the power ramp-up process, PAP controller circuitry 214 provides successive power reduction values ​​(e.g., PR[4:0]=0.9, 0.7, 0.5, 0.3, 0.1) previously generated by PAP controller circuitry 214 to multiplier circuitry 216 in reverse order (e.g., PR[4:0]=0.1, 0.3, 0.5, 0.7, 0.9). Multiplier circuitry 216 ramps up the data signal power of the combined RF signal by multiplying subsequent portions of the combined RF signal with the successive power reduction values ​​in reverse order to gradually ramp up the power of the combined RF signal over time. For example, multiplier circuitry 216 may multiply successive portions of the combined RF signal with the following opposite successive power reduction values: PR[4]=0.1 at the first signal portion, PR[3]=0.3 at the second signal portion, PR[2]=0.5 at the third signal portion, PR[1]=0.7 at the fourth signal portion, and PR[0]=0.9 at the fifth signal portion. Thereafter, multiplier circuitry 216 applies a multiplier value of one (e.g., PR=1) to the combined RF signal to maintain the original power of subsequent portions of the combined RF signal without reducing any power. Similar to reducing the data signal power, gradually increasing the data signal power in this manner prevents DAC circuitry 218, PA circuitry 220, or a transmit application from being affected by a sudden change in power that could damage DAC circuitry 218 or PA circuitry 220. In some instances, such a gradual increase in power also prevents unstable conditions from being generated in DAC circuitry 218 or PA circuitry 220 based on a sudden power change.

[0047] Briefly go to Figure 2BDuring the power reduction process performed by the PAP controller circuitry 214 and the multiplier circuitry 232, 234 on the interpolated frequency band signals from the interpolation circuitry 202, 204, the signal monitor circuitry 212 continues to monitor other portions of the incoming combined envelope signal A(t) to determine whether such portions of the combined envelope signal A(t) meet the one or more impairment criteria. In this manner, the signal monitor circuitry 212 can determine whether to continue reducing the data signal power of subsequent portions of the interpolated frequency band signals or to stop reducing the power. When the signal monitor circuitry 212 determines to stop reducing the power of the interpolated frequency band signals, the signal monitor circuitry 212 stops providing an alarm or warning to the PAP controller circuitry 214. Similarly or alternatively, any suitable external signal separate from the signal monitor circuitry 212 can be provided to remove the alarm or warning to begin ramping up the signal power. In any case, there is no alarm or warning that the PAP controller circuitry 214 will initiate a power ramp-up scheme for the interpolated frequency band signal. In this manner, subsequent portions of the interpolated frequency band signal are propagated to the mixer circuitry 222, 224 at their original power levels.

[0048] exist Figure 2B , during the power ramp-up process, the PAP controller circuitry 214 provides the successive power reduction values ​​(e.g., PR[4:0]=0.9, 0.7, 0.5, 0.3, 0.1) previously generated by the PAP controller circuitry 214 to the multiplier circuitry 232, 234 in reverse order (e.g., PR[4:0]=0.1, 0.3, 0.5, 0.7, 0.9). The multiplier circuitry 232, 234 ramps up the data signal power of the interpolated frequency band signal by multiplying subsequent portions of the interpolated frequency band signal with the successive power reduction values ​​in reverse order to gradually ramp up the power of the interpolated frequency band signal over time. For example, the multiplier circuitry 232, 234 may multiply successive portions of the interpolated frequency band signal with the following opposite successive power reduction values: PR[4]=0.1 at the first signal portion, PR[3]=0.3 at the second signal portion, PR[2]=0.5 at the third signal portion, PR[1]=0.7 at the fourth signal portion, and PR[0]=0.9 at the fifth signal portion. Thereafter, the multiplier circuitry 232, 234 applies a multiplier value of one (e.g., PR=1) to the corresponding frequency band signal of the interpolated frequency band signal to maintain the original power of the subsequent portion of the interpolated frequency band signal without reducing the power.

[0049] Briefly go to Figure 2C, during the power reduction process performed by the PAP controller circuitry 214 and the multiplier circuitry 236, 238 on the up-converted frequency band signals from the mixer circuitry 222, 224, the signal monitor circuitry 212 continues to monitor other portions of the incoming combined envelope signal A(t) to determine whether such portions of the combined envelope signal A(t) meet the one or more corruption criteria. In this manner, the signal monitor circuitry 212 can determine whether to continue reducing the data signal power of subsequent portions of the up-converted frequency band signals or to stop reducing the power. When the signal monitor circuitry 212 determines to stop reducing the power of the up-converted frequency band signals, the signal monitor circuitry 212 stops providing an alarm or warning to the PAP controller circuitry 214. Similarly or alternatively, any suitable external signal separate from the signal monitor circuitry 212 can be provided to remove the alarm or warning to begin ramping up the signal power. In any case, there is no alarm or warning indicating that the PAP controller circuitry 214 will initiate a power ramp-up scheme for the up-converted frequency band signal. In this manner, subsequent portions of the up-converted frequency band signal are propagated to the combiner circuitry 226 at their original power levels.

[0050] exist Figure 2C , during the power ramp-up process, the PAP controller circuitry 214 provides the successive power reduction values ​​(e.g., PR[4:0]=0.9, 0.7, 0.5, 0.3, 0.1) previously generated by the PAP controller circuitry 214 to the multiplier circuitry 236, 238 in reverse order (e.g., PR[4:0]=0.1, 0.3, 0.5, 0.7, 0.9). The multiplier circuitry 236, 238 ramps up the data signal power of the up-converted frequency band signal by multiplying subsequent portions of the up-converted frequency band signal with the successive power reduction values ​​in reverse order to gradually ramp up the power of the up-converted frequency band signal over time. For example, the multiplier circuitry 236, 238 may multiply successive portions of the up-converted frequency band signal with the following opposite successive power reduction values: PR[4]=0.1 at the first signal portion, PR[3]=0.3 at the second signal portion, PR[2]=0.5 at the third signal portion, PR[1]=0.7 at the fourth signal portion, and PR[0]=0.9 at the fifth signal portion. Thereafter, the multiplier circuitry 236, 238 applies a multiplier value of one (e.g., PR=1) to the corresponding frequency band signal of the up-converted frequency band signal to maintain the original power of subsequent portions of the up-converted frequency band signal without reducing the power.

[0051] Return to example Figure 2A, an input of band envelope determination circuitry 206 is coupled to an input of interpolation circuitry 202, and an input of band envelope determination circuitry 208 is coupled to an input of interpolation circuitry 204. However, in other examples, an input of band envelope determination circuitry 206 and an input of band envelope determination circuitry 208 may be coupled to any other suitable point between the input and output of corresponding ones of interpolation circuitry 202 and interpolation circuitry 204. Figure 3 and 4 Example alternative connection configurations are shown by way of example in FIG.

[0052] Figure 3 Yes Figure 1 An example transmitter circuit system 300 of another embodiment of the PAP circuit system 106 is shown. Figure 3 In FIG. 2 , an input of the band envelope determination circuitry 206 is coupled to an output of the interpolation circuitry 202 , and an input of the band envelope determination circuitry 208 is coupled to an output of the interpolation circuitry 204 . Figure 4 Yes Figure 1 An example transmitter circuit system 400 of yet another embodiment of the PAP circuit system 106 of the present invention is shown. Figure 4 In FIG. 2 , an input of band envelope determination circuitry 206 is coupled to an output of first interpolation circuitry stage 1 202a (eg, a first stage of interpolation circuitry 202) and an input of first interpolation circuitry stage 2 202b (eg, a second stage of interpolation circuitry 202). Figure 4 , an input of band envelope determination circuitry 208 is coupled to an output of second interpolation circuitry stage 1 204a (eg, a first stage of interpolation circuitry 204) and an input of second interpolation circuitry stage 2 204b (eg, a second stage of interpolation circuitry 204).

[0053] Selecting the circumstances under which the inputs of the frequency band envelope determination circuitry 206, 208 are coupled relative to the inputs and outputs of the interpolation circuitry 202, 204 allows different numbers of digital samples to be provided to the frequency band envelope determination circuitry 206, 208. For example, since the interpolation circuitry 202, 204 generates (e.g., interpolates) interpolated digital samples based on digital samples of the input frequency band signal, the inputs of the frequency band envelope determination circuitry 206, 208 are coupled to the inputs of the interpolation circuitry 202, 204, as shown in FIG. Figure 2AAs shown, only the original samples of the input band signal are provided to the band envelope determination circuit systems 206, 208. In addition, such a configuration allows the interpolation circuit systems 202, 204 to generate interpolated digital samples for the input band signal while the band envelope determination circuit systems 206, 208 determine the envelope of the original digital samples of the input band signal. An advantage of this parallel configuration is that since the interpolation circuit systems 202, 204 and the band envelope determination circuit systems 206, 208 process the same portion of the signal at different times, there is no need to provide the interpolation circuit systems 202, 204 with the same portion of the signal. Figure 2A The digital logic area is reduced by adding delay logic to the transmitter circuit system 200. Another advantage of the parallel configuration includes reducing digital dynamic power by not needing to power additional delay logic. Yet another advantage of the parallel configuration is that the band envelope determination circuit systems 206, 208 process the input band signals at their original sample frequencies rather than at the higher sample frequencies at the outputs of the interpolation circuit systems 202, 204. This allows for the use of a plurality of transmitters that do not need to be connected to the transmitter circuit system 200. Figure 2A The transmitter circuitry 200 may run a higher clock frequency for higher sampling rates to process higher resolution versions of the input frequency band signals generated by the interpolation circuitry 202, 204 to reduce power.

[0054] like Figure 3 As shown, the inputs of the band envelope determination circuit systems 206, 208 are coupled to the outputs of the interpolation circuit systems 202, 204, resulting in the original samples of the input band signal and the interpolated samples (e.g., all interpolated samples generated by the interpolation circuit systems 202 and 204) being provided to the band envelope determination circuit systems 206, 208. Figure 4 As shown, the input ends of the frequency band envelope determination circuit systems 206, 208 are coupled to the input ends and output ends of successive stages of the interpolation circuit systems 202, 204, resulting in the original samples of the input frequency band signal and some interpolated samples (for example, less than all the interpolated samples generated by the interpolation circuit systems 202 and 204) being provided to the frequency band envelope determination circuit systems 206, 208.

[0055] like Figure 2AAs shown, coupling the inputs of the band envelope determination circuit systems 206, 208 to the inputs of the interpolation circuit systems 202, 204 allows for a reduction in the digital logic semiconductor area and digital dynamic power used to implement the band envelope determination circuit systems 206, 208. For example, by providing fewer samples (e.g., original samples) of the input band signal (e.g., a low-resolution representation of the input band signal) to the band envelope determination circuit systems 206, 208, the PAP circuit system 106 can operate at a lower sampling rate. Using a lower sampling rate reduces the complexity and amount of circuitry of the PAP circuit system 106. This reduces the digital logic area used to manufacture the transmitter circuit system 200, and thereby reduces the digital dynamic power used by the transmitter circuit system 200. Additionally, operating the PAP circuit system 106 at a lower sampling rate further reduces the digital dynamic power consumed by the PAP circuit system 106 compared to operating at a higher sampling rate. As shown in FIG. Figure 2A As shown, coupling the inputs of band envelope determination circuitry 206, 208 to the inputs of interpolation circuitry 202, 204 also allows band envelope determination circuitry 206, 208 to operate in parallel on the same portion of the input band signal being processed by interpolation circuitry 202 and 204.

[0056] In an alternative embodiment where the inputs of the band envelope determination circuitry 206, 208 are coupled to the outputs of the interpolation circuitry 202, 204, delay circuitry 302 may be added to the transmitter circuitry 200 between the combiner circuitry 226 and the multiplier circuitry 216. Such delay circuitry prevents portions of the combined RF signal from reaching the multiplier circuitry 216 before the PAP circuitry 106 can process and monitor the envelopes corresponding to those portions. In this manner, one advantage of coupling the inputs of the band envelope determination circuitry 206, 208 to the inputs of the interpolation circuitry 202, 204 includes parallel processing of the band envelope determination circuitry 206, 208 and the interpolation circuitry 202, 204. Another advantage includes reducing digital logic area by not requiring the addition of delay logic to the transmitter circuitry 200. Yet another advantage includes reducing digital dynamic power by not powering additional delay logic and not needing to run higher clock frequencies for higher sampling rates to process higher resolution versions of the input band signals generated by the interpolation circuitry 202, 204.

[0057] Moving the input of the band envelope determination circuitry 206, 208 to the output of the interpolation circuitry 202, 204 to adjust the number of digital samples of each input band signal available to the band envelope determination circuitry 206, 208 allows the performance of the band envelope determination circuitry 206, 208 to be adjusted. For example, more digital samples of the input band signal per unit time produces a higher resolution representation of the input band signal (e.g., a higher time resolution). For example, adding additional digital samples to a time period of the signal produces a representation of the signal in the time period with a higher sample resolution relative to the sample resolution before the additional digital samples were added. This can improve the accuracy performance of the band envelope determination circuitry 206, 208 because the band envelope determination circuitry 206, 208 can determine a more accurate envelope representation based on the higher sample resolution.

[0058] However, as described above, the trade-off for this higher sample resolution is that the band envelope determination circuitry 206, 208 must operate at a higher sampling rate to detect a greater number of digital samples. Operating at a higher sampling rate in turn consumes more power and may require more expensive circuitry to implement the band envelope determination circuitry 206, 208 or to implement other portions of the transmitter circuitry 200. Thus, as shown in FIGS. 2-4, the flexibility of selecting different coupling points of the inputs of the band envelope determination circuitry 206, 208 to the interpolation circuitry 202, 204 allows for an adjustment of the trade-offs between frequency envelope accuracy, sampling rate, digital logic area, and digital dynamic power of the transmitter circuitry 200.

[0059] Although the transmitter circuit systems 200, 300, 400 of FIGS. 2-4 are shown as receiving two input frequency band signals (e.g., "Band-1 Tx Data" and "Band-2 Tx Data"), the examples described herein are readily extended to implementations with any number of input frequency band signals. Thus, by adding additional circuit systems in parallel with the circuit systems shown in FIGS. 2-4, the transmitter circuit systems 200, 300, 400 may be scaled up with relatively little or no impact on signal propagation timing. For example, the transmitter circuit systems 200, 300, 400 may be scaled up by including one or more interpolation circuits (e.g., substantially similar or identical to the interpolation circuit systems 202, 204), one or more mixer circuits (e.g., substantially similar or identical to the mixer circuit systems 222, 224), and one or more band envelope determination circuits (e.g., substantially similar or identical to the band envelope determination circuit systems 206, 208). In such an example, the third frequency band envelope determination circuitry has an input coupled to the third interpolation circuitry to receive a third frequency band signal (e.g., "Band-3Tx Data"). The third frequency band envelope determination circuitry also has an output coupled to a third input of the combiner circuitry 210 and determines an envelope of the third frequency band signal. The combiner circuitry 210 generates a combined envelope signal by combining the envelopes of the first frequency band signal, the second frequency band signal, and the third frequency band signal.

[0060] To generate a combined RF signal based on the first frequency band signal, the second frequency band signal, and the third frequency band signal, a third mixer circuit system (e.g., substantially similar or identical to mixer circuit systems 222, 224) has an input coupled to the output of the third interpolation circuit system to receive the interpolated frequency band signal and generate a third interpolated and up-converted frequency band signal. The output of the third mixer circuit system is connected to the input of combiner circuit system 226, so that combiner circuit system 226 can generate a combined RF signal based on the interpolated and up-converted frequency band signals from mixer circuit system 222, mixer circuit system 224, and the third mixer circuit system.

[0061] Figure 5 It is shown by ( Figure 1-4 ) is an example signal diagram of a corrupted candidate portion detected by the PAP circuitry 106 in an envelope 500 of an input signal (e.g., "Band-1 Tx Data" or "Band-2 Tx Data"). In the examples described herein, the corrupted candidate portion of the envelope 500 corresponds to a portion of the combined RF signal that may be corrupting to the PA circuitry 220 (FIGS. 2-4). Figure 5 , an example damaged candidate portion 502 of the envelope 500 is shown as satisfying (e.g., exceeding) a power threshold. Figure 5, the power threshold is shown as an amplitude value of 0.8, which may correspond to an electrical power value. When the signal monitor circuitry 212 (FIGS. 2-4) detects the damage candidate portion 502, the signal monitor circuitry 212 generates a warning or alarm for the PAP controller circuitry 214 (FIGS. 2 to 4) to reduce the data signal power of the corresponding portion of the combined RF signal. However, other portions of the envelope 500 that are unlikely to cause damage to the PA circuitry 220 do not meet the power threshold. As such, the signal monitor circuitry 212 stops issuing warnings or alarms to the PAP controller circuitry 214 regarding such non-damage candidate portions of the combined RF signal. Although the damage candidate portion 502 is based on the power threshold, other damage candidate portions may be detected by the signal monitor circuitry 212 based on one or more other damage criteria instead of or in addition to the power threshold.

[0062] Figure 6 Is implemented Figure 1-4 2-4 to protect a power amplifier (eg, power amplifier circuitry 220 of FIGS. 2-4) from being damaged by a portion of a combined RF signal that exceeds a power threshold. Figure 6 The flowchart of FIG. 1 represents a series of operations performed by the PA circuit system 106 on a specific window of the input frequency band signal. As the input frequency band signal continues to flow into the transmitter circuit system 200, 300, 400, the PA circuit system 106 performs the following operations in parallel: Figure 6 The operation is to continuously monitor subsequent incoming windows of the input frequency band signal.

[0063] Figure 6 Operation of begins at block 602 where the band envelope determination circuitry 206, 208 receives an input band signal. The band envelope determination circuitry 206, 208 determines the envelope of the input band signal (block 604). The combiner circuitry 210 generates a combined envelope signal by combining the envelopes of the band signals (block 606).

[0064] The signal monitor circuitry 212 monitors the combined envelope signal (block 608). The signal monitor circuitry 212 determines whether to reduce the power of the combined RF signal corresponding to the combined envelope signal (block 610). For example, if the signal monitor circuitry 212 determines that the window of the combined envelope signal meets the damage criteria of the PA circuitry 220 (e.g., the corresponding combined RF signal may damage the PA circuitry 220) (block 610: yes), the signal monitor circuitry 212 issues an alarm / warning to the PAP controller circuitry 214 to reduce the power of one or more corresponding portions of the combined RF signal (block 612). In such cases, the PAP controller circuitry 214 generates one or more power reduction values ​​(block 614). For example, in response to the alarm / warning, the PAP controller circuitry 214 implements a power reduction scheme by generating one or more consecutive power reduction values ​​to gradually reduce the power of a portion of the combined RF signal over time. The portion of the combined RF signal that experiences this power reduction corresponds to a window of the combined envelope signal that meets the impairment criteria of PA circuitry 220 .

[0065] The multiplier circuitry 216 ramps down the data signal power of the combined RF signal based on the one or more power reduction values ​​(block 616). For example, the multiplier circuitry 216 may apply the one or more power reduction values ​​of block 614 to portions of the combined RF signal to gradually ramp down the power of the combined RF signal. To do so, the multiplier circuitry 216 multiplies successive portions of the combined RF signal by successive power reduction values ​​of the power reduction value. The signal monitor circuitry 212 continues to monitor the combined envelope signal provided by the combiner circuitry 210 (block 618).

[0066] The signal monitor circuitry 212 determines whether to stop reducing the power of the combined RF signal (block 620). If the signal monitor circuitry 212 determines to stop reducing the power of the combined RF signal (block 620: yes), the signal monitor circuitry 212 stops issuing the alarm / alert to the PAP controller circuitry 214 (block 622). The multiplier circuitry 216 ramps up the data signal power of the combined RF signal (block 624). For example, the PAP controller circuitry 214 provides the one or more power reduction values ​​of block 614 to the multiplier circuitry 216 in reverse order. The multiplier then applies the one or more power reduction values ​​of block 614 to the combined RF signal in reverse order. For example, the multiplier circuitry 216 multiplies successive portions of the combined RF signal by increasing one of the power reduction values ​​to gradually ramp up the combined RF signal over time.

[0067] The signal monitor circuit system 212 determines whether to stop monitoring the envelope from the frequency band envelope determination circuit system 206, 208 (box 626). For example, when the input signal is not present, the signal monitor circuit system 212 can determine to stop monitoring. Similarly or alternatively, the signal monitor circuit system 212 can determine to stop monitoring in response to an external signal that enables or disables the monitoring activity of the signal monitor circuit system 212. Such an external signal can be provided by a controller, a processor, or any other suitable circuit system (e.g., communication logic such as an FPGA, an ASIC, a baseband processor, a programmable circuit system, etc.). If the signal monitor circuit system 212 determines not to stop monitoring (box 626: No), control returns to box 608. However, if the signal monitor circuit system 212 determines to stop monitoring (box 626: Yes), the process ends. Figure 6 Operation 600.

[0068] From the foregoing, it will be appreciated that example systems, devices, articles, and methods for protecting power amplifiers have been described. The described systems, devices, articles, and methods improve the operation of transmitter circuits by reducing or eliminating the probability of damage to the power amplifier caused by data signal power levels. Thus, the described systems, devices, articles, and methods relate to one or more improvements in the operation of a machine such as a computer or other electronic or mechanical device.

[0069] Descriptors such as "first," "second," and "third" are used herein when identifying multiple elements or components that can be referenced individually. Unless otherwise specified or implied based on the context of their use, such descriptors do not confer any meaning of priority, physical order, or arrangement in a list or chronological order, but are merely used as labels to individually reference multiple elements or components to facilitate understanding of the described examples. In some instances, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor, such as "second" or "third," in the claims. In such cases, such descriptors are used only to facilitate reference to multiple elements or components.

[0070] As used herein, unless otherwise specified, connection references (e.g., attachment, coupling, connection, and engagement) may include intermediate members between the elements to which the connection refers and / or relative movement between these elements. Thus, connection references do not necessarily imply that two elements are directly connected and / or fixed to each other.

[0071] In the specification and claims, unless otherwise stated, the terms "including" and "having" and variations thereof shall be included in a manner similar to the term "comprising". Unless otherwise stated, "about", "approximately" or "substantially" before a value means + / -10% of the stated value. In another example, "about", "approximately" or "substantially" before a value means + / -5% of the stated value. In another example, "about", "approximately" or "substantially" before a value means + / -1% of the stated value.

[0072] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0073] As used herein, "programmable circuitry" is defined as including (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmed with instructions to perform specific functions and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include a programmable microprocessor, such as a central processing unit (CPU), which can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction to configure and / or structure the FPGA to implement one or more operations and / or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations and / or functions; and / or an integrated circuit, such as an application specific integrated circuit (ASIC). For example, the XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc. and / or any combination thereof), and coordination technology (e.g., an application programming interface (API)) that can distribute computing tasks to any of the multiple types of programmable circuit systems that are suitable and available to perform the computing tasks.

[0074] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuit system, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0075] In this specification, the term "and / or" (when used in the form of A, B and / or C) refers to any combination or subset of A, B, C, such as (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Moreover, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments including any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0076] As used herein, the terms "couple", "coupled", and "couples" and variations thereof may encompass connections, communications, or signal paths that achieve a functional relationship consistent with the present description. For example, if device A generates a signal to control device B to perform an action, in a first instance, device A is coupled to device B, or in a second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, device A is coupled to device B through an intermediate component C such that device B is controlled by device A through a control signal generated by device A. In addition, the terms "couple", "coupled", and "couples" or variations thereof include indirect or direct electrical or mechanical connections.

[0077] Although not separately marked in the figure, the components or elements of the systems and circuits shown therein have one or more conductors or terminals that allow signals to enter the components or elements and / or leave them. Conductors or terminals (or parts thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), input terminals, output terminals, nodes, and interconnects. As used herein, the terms "terminal", "node", "interconnect", "pin", "pad", and "lead" are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or their terminals between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0078] As used herein, a "terminal" of a component, device, system, circuit, integrated circuit or other electronic or semiconductor component is generally a conductor, such as a wire, trace, pin, pad or other connector or interconnect, which enables the component, device and system, etc. to be electrically connected and / or mechanically connected to another component, device or system, etc. The terminal can be used, for example, to receive or provide an analog or digital electrical signal (or a simple signal), or to be electrically connected to a common or ground reference. Therefore, an input terminal or input end is used to receive a signal from another component, device, system, etc. The output terminal or output end is used to provide a signal to another component, device or system, etc. Other terminals can be used to connect to a common, ground or voltage reference, such as a reference terminal or a ground terminal. The terminal of an integrated circuit (IC) or a printed circuit board (PCB) may also be referred to as a pin (vertical conductor) or a pad (planar conductor). A node refers to a connection point or interconnection point of two or more terminals. An example number of terminals and nodes can be shown. However, depending on a specific circuit or system topology, there may be more or fewer terminals and nodes.

[0079] Circuits or devices described herein as including certain components may instead be adapted to be coupled to those components to be included in the described circuit system or device. For example, a device described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to be included in the described structure during or after manufacturing, such as by an end user and / or a third party.

[0080] The circuit described herein is reconfigurable to include replaced components, thereby providing functions that are at least partially similar to those available before component replacement. Unless otherwise specified, the components shown as resistors generally represent any one or more elements coupled in series and / or in parallel, to provide the impedance represented by the resistors shown. For example, the resistors or capacitors shown and described as a single component herein can be multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, the resistors or capacitors shown and described as a single component herein can be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively. Although some elements of the described examples are included in the integrated circuit, and other elements are outside the integrated circuit, in other examples, additional or fewer features can be incorporated into the integrated circuit. In addition, some or all features shown as outside the integrated circuit can be included in the integrated circuit, and / or some features shown as inside the integrated circuit can be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0081] Use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0082] The following claims are hereby incorporated by reference into this detailed description. Although certain example systems, devices, articles, and methods have been described herein, the coverage of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent. The described examples may be modified within the scope of the claims, and other examples are possible.

Claims

1. A device comprising: a first interpolation circuit system; a second interpolation circuit system; first frequency band envelope determination circuitry having an input coupled to the first interpolation circuitry and having an output; second frequency band envelope determination circuitry having an input coupled to the second interpolation circuitry and having an output; combiner circuitry having a first input coupled to the output of the first frequency band envelope determination circuitry, having a second input coupled to the output of the second frequency band envelope determination circuitry, and having an output; as well as Signal monitor circuitry has an input coupled to the output of the combiner circuitry.

2. The device according to claim 1, comprising: controller circuitry having an input coupled to the output of the signal monitor circuitry and having an output; a multiplier circuitry having a first input coupled to the output of the controller circuitry and having an output; digital-to-analog converter circuitry having an input coupled to the output of the multiplier circuitry and having an output; as well as A power amplifier circuitry has an input coupled to the output of the digital-to-analog converter circuitry.

3. The apparatus according to claim 2, comprising: first mixer circuitry having an input coupled to the first interpolation circuitry and having an output; second mixer circuitry having an input coupled to the second interpolation circuitry and having an output; as well as A second combiner circuit system has a first input coupled to the output of the first mixer circuit system, a second input coupled to the output of the second mixer circuit system, and an output coupled to the second input of the multiplier circuit system.

4. The apparatus according to claim 1, wherein: The input of the first frequency band envelope determination circuitry is coupled to an input of the first interpolation circuitry, and The input of the second frequency band envelope determination circuitry is coupled to an input of the second interpolation circuitry.

5. The apparatus of claim 1, wherein: The input of the first frequency band envelope determination circuitry is coupled to the output of the first interpolation circuitry; and The input of the second frequency band envelope determination circuitry is coupled to the output of the second interpolation circuitry.

6. The apparatus of claim 1, wherein the input of the first frequency band envelope determination circuitry is coupled to an output of a first stage of the first interpolation circuitry and to an input of a second stage of the first interpolation circuitry.

7. The apparatus according to claim 1, comprising: controller circuitry having an input coupled to the output of the signal monitor circuitry and having an output; first multiplier circuitry having a first input coupled to the first interpolation circuitry, having a second input coupled to the output of the controller circuitry, and having an output; a second multiplier circuitry having a first input coupled to the second interpolation circuitry and having a second input coupled to the output of the controller circuitry and having an output; first mixer circuitry having an input coupled to the output of the first multiplier circuitry; second mixer circuitry having an input coupled to the output of the second multiplier circuitry; as well as A second combiner circuitry has a first input coupled to the output of the first mixer circuitry and a second input coupled to the output of the second mixer circuitry.

8. The apparatus according to claim 1, comprising: controller circuitry having an input coupled to the output of the signal monitor circuitry and having an output; first mixer circuitry having an input coupled to the first interpolation circuitry and having an output; second mixer circuitry having an input coupled to the second interpolation circuitry and having an output; a first multiplier circuitry having a first input coupled to the output of the first mixer circuitry, having a second input coupled to the output of the controller circuitry, and having an output; a second multiplier circuitry having a first input coupled to the output of the second mixer circuitry, having a second input coupled to the output of the controller circuitry, and having an output; as well as A second combiner circuitry has a first input coupled to the output of the first multiplier circuitry and has a second input coupled to the output of the second multiplier circuitry.

9. An apparatus comprising: a power amplifier circuit system having an input terminal; a digital-to-analog converter circuitry having an output coupled to the input of the power amplifier circuitry and having an input; a multiplier circuitry having an output coupled to the input of the digital-to-analog converter circuitry and having a first input and a second input; first combiner circuitry having an output coupled to the first input of the multiplier circuitry and having a first input and a second input; first mixer circuitry having an output coupled to the first input of the first combiner circuitry and having an input; second mixer circuitry having an output coupled to the second input of the first combiner circuitry and having an input; first interpolation circuitry having an output coupled to the input of the first mixer circuitry and having an input; second interpolation circuitry having an output coupled to the input of the second mixer circuitry and having an input; first frequency band envelope determination circuitry having an input coupled to the first interpolation circuitry and having an output; second frequency band envelope determination circuitry having an input coupled to the second interpolation circuitry and having an output; a second combiner circuitry having a first input coupled to the output of the first frequency band envelope determination circuitry and a second input coupled to the output of the second frequency band envelope determination circuitry and having an output; as well as Signal monitor circuitry has an input coupled to the output of the second combiner circuitry.

10. The apparatus of claim 9, wherein: The input of the first frequency band envelope determination circuitry is coupled to an input of the first interpolation circuitry, and The input of the second frequency band envelope determination circuitry is coupled to an input of the second interpolation circuitry.

11. The apparatus of claim 9, wherein: The input of the first frequency band envelope determination circuitry is coupled to the output of the first interpolation circuitry; and The input of the second frequency band envelope determination circuitry is coupled to the output of the second interpolation circuitry.

12. The apparatus of claim 9, wherein the input of the first frequency band envelope determination circuitry is coupled to an output of a first stage of the first interpolation circuitry and to an input of a second stage of the first interpolation circuitry.

13. The apparatus of claim 9, comprising controller circuitry having an input coupled to the output of the signal monitor circuitry and having an output coupled to the second input of the multiplier circuitry.

14. An apparatus comprising: frequency band envelope determination circuitry configured to determine an envelope corresponding to the first frequency band signal and having an output; combiner circuitry having an input coupled to the output of the frequency band envelope determination circuitry and configured to generate a combined envelope signal by combining the envelope corresponding to the first frequency band signal and an envelope corresponding to a second frequency band signal, and having an output; signal monitor circuitry configured to determine that the combined envelope signal meets a damage criterion for a power amplifier and having an output; a controller circuitry having an input coupled to the output of the signal monitor circuitry and configured to generate a power reduction value and having an output; as well as a multiplier circuit system having a first input terminal coupled to the output terminal of the controller circuit system, the multiplier circuit system being configured to reduce the power of a combined radio frequency (RF) signal based on the power reduction value, the combined RF signal corresponding to the combined envelope signal.

15. The apparatus of claim 14, wherein the first frequency band signal comprises a first digital sample, the apparatus comprising an interpolation circuit system configured to generate a second digital sample of the first frequency band signal while the frequency band envelope determination circuit system determines the envelope of the first digital sample of the first frequency band signal.

16. The apparatus of claim 14, wherein the first frequency band signal, the second frequency band signal, and the combined RF signal are in the digital domain.

17. The apparatus of claim 14, comprising a second combiner circuit system having an output connected to a second input of the multiplier circuit system and configured to generate the combined RF signal based on an interpolated and up-converted signal of the first frequency band signal and the second frequency band signal.

18. The apparatus of claim 14, comprising a digital-to-analog converter having an input coupled to an output of the multiplier circuitry and configured to convert the RF signal from a digital domain to an analog domain.

19. The apparatus of claim 18, comprising the power amplifier having an input coupled to the output of the digital-to-analog converter and configured to amplify the RF signal before transmitting the RF signal.

20. The apparatus of claim 14, wherein the signal monitor circuitry is configured to determine that the combined envelope signal satisfies the damage criterion for the power amplifier after the combined envelope signal satisfies at least one of a power threshold or a duration threshold.

21. The apparatus of claim 14, wherein the damage criterion for the power amplifier is based on an electrical power operating range of the power amplifier.

22. The apparatus of claim 14, comprising: second frequency band envelope determination circuitry having an output coupled to a second input of the combiner circuitry and configured to determine the envelope corresponding to the second frequency band signal; as well as a third frequency band envelope determination circuit system having an output terminal coupled to the third input terminal of the combiner circuit system and configured to determine an envelope corresponding to a third frequency band signal, the combiner circuit system being configured to generate the combined envelope signal by combining the envelopes corresponding to the first frequency band signal, the second frequency band signal and the third frequency band signal.

23. The apparatus of claim 14, wherein the controller circuitry and the multiplier circuitry reduce the power of the combined RF signal by ramping down the power over time.

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