Radio frequency power amplifier chip, radio frequency front end module and electronic device

Abstract

According to the radio frequency power amplifier chip, the radio frequency front-end module and the electronic device provided by the invention, transistor arrays (a first transistor array, a second transistor array, a third transistor array and a fourth transistor array) and corresponding power synthesis units (a first power synthesis unit and a second power synthesis unit) are reasonably arranged; and the integration level of the radio frequency power amplifier chip is well improved.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a radio frequency power amplifier chip, a radio frequency front-end module and an electronic device. Background Art

[0002] The rapid development of communication technology is constantly driving the progress of the electronic equipment industry. For mobile devices, portability and ease of use are very important requirements for users, which requires electronic devices to have higher performance and smaller size. Therefore, the requirements for the integration of various modules in mobile devices are becoming higher and higher. Taking the RF front-end module as an example, with the gradual popularization of the fifth-generation mobile communication technology (5G), the number of frequency bands that communication equipment needs to support has increased significantly, which poses a greater challenge to the design of the RF front-end. In order to meet this challenge, the requirements for the integration of each module are an extremely important aspect. Summary of the invention

[0003] The present application provides a radio frequency power amplifier chip, a radio frequency front-end module and an electronic device, which can improve the overall integration.

[0004] In a first aspect of the present application, a radio frequency power amplifier chip is provided, comprising:

[0005] A first transistor array is arranged on a first side in a first direction;

[0006] A second transistor array is arranged on a first side in a second direction, wherein the first direction intersects with the second direction;

[0007] A first power synthesis unit, disposed on the second side in the first direction and the second side in the second direction, and configured to perform power synthesis on output signals of the first transistor array and the second transistor array;

[0008] A third transistor array is arranged on the second side in the first direction;

[0009] A fourth transistor array is arranged on the second side in the second direction;

[0010] A second power synthesis unit is disposed on the first side in the second direction and the first side in the first direction, and is configured to perform power synthesis on output signals of the third transistor array and the fourth transistor array.

[0011] Further, a portion of the first transistor array disposed on the first side in the first direction relative to the second power synthesis unit is closer to a second side in the first direction, and a portion of the second transistor array disposed on the first side in the second direction relative to the second power synthesis unit is closer to a second side in the second direction;

[0012] and / or,

[0013] The third transistor array is closer to the first side in the first direction relative to a portion of the first power synthesis unit disposed on the second side in the first direction, and the fourth transistor array is closer to the first side in the second direction relative to a portion of the first power synthesis unit disposed on the second side in the second direction.

[0014] Furthermore, the first direction is perpendicular to the second direction.

[0015] Furthermore, the first power synthesis unit and the second power synthesis unit are arranged outside the RF power amplifier chip.

[0016] Further, the portion of the second power synthesis unit disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array, the portion of the second power synthesis unit disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array, the portion of the third transistor array disposed on the second side in the first direction is closer to the first side in the first direction relative to the portion of the first power synthesis unit disposed on the second side in the first direction, and the portion of the fourth transistor array disposed on the second side in the second direction is closer to the first side in the second direction relative to the portion of the first power synthesis unit disposed on the second side in the second direction;

[0017] or,

[0018] The portion of the first power synthesis unit arranged on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array, the portion of the first power synthesis unit arranged on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array, the first transistor array is closer to the second side in the first direction relative to the portion of the second power synthesis unit arranged on the first side in the first direction, and the second transistor array is closer to the second side in the second direction relative to the portion of the second power synthesis unit arranged on the first side in the second direction.

[0019] Further, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first primary sub-coil and a second primary sub-coil, and the first secondary coil includes a first secondary sub-coil and a second secondary sub-coil; the first primary sub-coil and the first secondary sub-coil are coupled to each other and are arranged on the second side in the first direction; the second primary sub-coil and the second secondary sub-coil are coupled to each other and are arranged on the second side in the second direction;

[0020] The second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a third primary sub-coil and a fourth primary sub-coil, the second secondary coil includes a third secondary sub-coil and a fourth secondary sub-coil; the third primary sub-coil and the third secondary sub-coil are coupled to each other and are arranged on the first side in the first direction; the fourth primary sub-coil and the fourth secondary sub-coil are coupled to each other and are arranged on the first side in the second direction.

[0021] Further, the first secondary sub-coil is closer to the first side in the first direction relative to the first primary sub-coil, the second secondary sub-coil is closer to the first side in the second direction relative to the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction relative to the third secondary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction relative to the fourth secondary sub-coil;

[0022] or,

[0023] The first primary sub-coil is closer to the first side in the first direction relative to the first secondary sub-coil, the second primary sub-coil is closer to the first side in the second direction relative to the second secondary sub-coil, the third secondary sub-coil is closer to the second side in the first direction relative to the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction relative to the fourth primary sub-coil.

[0024] Further, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first outer primary coil and a first inner primary coil, the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a second outer primary coil and a second inner primary coil, the first secondary coil includes a first partial secondary coil arranged between the first outer primary coil and the first inner primary coil, and a second partial secondary coil arranged between the second outer primary coil and the second inner primary coil, the first partial secondary coil and the second partial secondary coil are connected in series.

[0025] Furthermore, the first secondary coil also includes a third partial secondary coil arranged inside the first primary coil, and the second secondary coil also includes a fourth partial secondary coil arranged inside the second primary coil, and the first partial secondary coil, the third partial secondary coil, the second partial secondary coil and the fourth partial secondary coil are connected in series in sequence.

[0026] Further, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, and the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other;

[0027] The first secondary coil includes a first portion of the secondary coil arranged on the first metal layer of the RF power amplifier chip and a second portion of the secondary coil arranged on the second metal layer of the RF power amplifier chip, and the second secondary coil includes a third portion of the secondary coil arranged on the first metal layer of the RF power amplifier chip and a fourth portion of the secondary coil arranged on the second metal layer of the RF power amplifier chip;

[0028] One end of the first secondary coil is configured to be connected to the signal output terminal, one end of the third secondary coil is configured to be grounded, and the first secondary coil is connected in series with the third secondary coil; one end of the second secondary coil is configured to be connected to the signal output terminal, one end of the fourth secondary coil is configured to be grounded, and the second secondary coil is connected in series with the fourth secondary coil;

[0029] The coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer; or, the coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the first manner is a clockwise manner or a counterclockwise manner.

[0030] Further, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, and the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other;

[0031] The first primary coil includes a first portion of the primary coil disposed on a first metal layer of the RF power amplifier chip and a second portion of the primary coil disposed on a second metal layer of the RF power amplifier chip, wherein the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled;

[0032] The second primary coil includes a third primary coil arranged on the first metal layer of the RF power amplifier chip and a fourth primary coil arranged on the second metal layer of the RF power amplifier chip, and the third primary coil and the fourth primary coil are longitudinally coupled.

[0033] Furthermore, it also includes a pre-stage driving circuit, which is arranged in a region surrounded by the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0034] Furthermore, it also includes a passive component network, which is arranged in an area surrounded by the first power synthesis unit and the second power synthesis unit.

[0035] Furthermore, the passive component network includes a first passive component unit and a second passive component unit, the first passive component unit is arranged in a region between the first transistor array, the second transistor array and the second power synthesis unit, and the second passive component unit is arranged in a region between the third transistor array, the fourth transistor array and the first power synthesis unit.

[0036] Further, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, a first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array;

[0037] The second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, a first end of the second primary coil is connected to the third transistor array, and a second end of the second primary coil is connected to the fourth transistor array.

[0038] Further, the first end of the first secondary coil is configured to be connected to the signal output end, the second end of the first secondary coil is connected to the first end of the second secondary coil, and the second end of the second secondary coil is configured to be grounded;

[0039] or,

[0040] The first end of the first secondary coil and the second end of the second secondary coil are configured to be connected to a signal output terminal, and the second end of the first secondary coil and the first end of the second secondary coil are configured to be grounded.

[0041] Further, the first transistor array, the second transistor array and the first power synthesis unit are configured to achieve power amplification of differential RF signals, and the third transistor array, the fourth transistor array and the second power synthesis unit are configured to achieve power amplification of differential RF signals.

[0042] Further, the first power synthesis unit and the second power synthesis unit are at least partially arranged in a contact metal layer of the chip, and the contact metal layer is arranged adjacent to a substrate of the chip.

[0043] In a second aspect of the present application, a radio frequency power amplifier chip is provided, comprising:

[0044] The first transistor array, the second transistor array, the third transistor array and the fourth transistor array are distributed in four regions: a first side in the first direction, a second side in the first direction, a first side in the second direction and a second side in the second direction, and the first direction and the second direction intersect;

[0045] A first power synthesis unit, disposed on the second side in the first direction and the second side in the second direction, configured to perform power synthesis on two transistor arrays among the first transistor array, the second transistor array, the third transistor array and the fourth transistor array;

[0046] A second power synthesis unit, which is arranged on the first side in the second direction and the first side in the first direction is arranged on the outside of the chip, is configured to perform power synthesis on the other two transistor arrays of the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0047] Further, the first power synthesis unit is configured to perform power synthesis on the output signals of the first transistor array and the second transistor array, and the second power synthesis unit is configured to perform power synthesis on the output signals of the third transistor array and the fourth transistor array; the first transistor array, the second transistor array and the first power synthesis unit are configured to amplify the radio frequency signal of the first frequency band, and the third transistor array, the fourth transistor array and the second power synthesis unit are configured to amplify the radio frequency signal of the second frequency band.

[0048] In a third aspect of the present application, a radio frequency power amplifier chip is provided, comprising:

[0049] A first transistor array is arranged on a first side of a first virtual rectangular region in a first direction;

[0050] A second transistor array is arranged at a first side of the first virtual rectangular area in a second direction, wherein the first direction intersects with the second direction;

[0051] A first transformer structure is arranged on a second side of the first virtual rectangular area in the first direction and on a second side of the first virtual rectangular area in the second direction, and includes a first primary coil and a first secondary coil coupled to each other, a first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array.

[0052] Furthermore, it also includes:

[0053] A third transistor array is arranged on the second side in the first direction;

[0054] A fourth transistor array is arranged at a second side of the first virtual rectangular area in the second direction;

[0055] The second transformer structure is arranged on the first side of the first virtual rectangular area in the second direction and the first side of the first virtual rectangular area in the first direction, and includes a second primary coil and a second secondary coil coupled to each other, a first end of the second primary coil is connected to the third transistor array, and a second end of the second primary coil is connected to the fourth transistor array.

[0056] In a fourth aspect of the present application, a radio frequency front-end module is provided, comprising the above-mentioned radio frequency power amplifier chip.

[0057] In a fifth aspect of the present application, an electronic device is provided, comprising the above-mentioned RF front-end module.

[0058] In the RF power amplifier chip, RF front-end module and electronic device provided in the embodiments of the present application, the integration of the RF power amplifier chip is greatly improved through the reasonable layout of the transistor arrays (first transistor array, second transistor array, third transistor array and fourth transistor array) and the corresponding power synthesis units (first power synthesis unit and second power synthesis unit). BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a schematic diagram of a radio frequency power amplifier chip provided in an embodiment of the present application;

[0060] Figure 2 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0061] Figure 3 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0062] Figure 4 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0063] Figure 5 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0064] Figure 6 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0065] Figure 7 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0066] Figure 8 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0067] Fig. 9 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0068] Fig.10 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0069] Fig.11 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0070] Fig.12 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0071] Fig.13 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0072] Fig.14 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0073] Fig.15 is another schematic diagram of a radio frequency power amplifier chip provided by an embodiment of the present application;

[0074] Fig.16 This is another schematic diagram of the RF power amplifier chip provided in one embodiment of the present application. DETAILED DESCRIPTION

[0075] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0076] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0077] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, connected to, connected to, or coupled to other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0078] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0079] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an" and " / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0080] In order to thoroughly understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0081] At least one embodiment of the present application provides a radio frequency power amplifier chip, including:

[0082] A first transistor array is arranged on a first side in a first direction;

[0083] A second transistor array is arranged on a first side in a second direction, wherein the first direction intersects with the second direction;

[0084] A first power synthesis unit, disposed on the second side in the first direction and the second side in the second direction, and configured to perform power synthesis on output signals of the first transistor array and the second transistor array;

[0085] A third transistor array is arranged on a second side in the second direction;

[0086] A fourth transistor array is arranged on the second side in the first direction;

[0087] A second power synthesis unit is disposed on the first side in the second direction and the first side in the first direction, and is configured to perform power synthesis on output signals of the third transistor array and the fourth transistor array.

[0088] The RF power amplifier chip provided in this embodiment includes a first transistor array and a second transistor array. Figure 1 As shown, the first transistor array 11 is arranged on the first side in the first direction. The second transistor array 12 is arranged on the first side in the second direction. The third transistor array 21 is arranged on the second side in the first direction. The fourth transistor array 22 is arranged on the second side in the second direction. The first direction and the second direction intersect. It can be understood that Figure 1The first direction and the second direction in the example are close to being perpendicular to each other, but this should not be understood as a limitation to this embodiment. In this embodiment, it suffices as long as the first direction and the second direction intersect (ie, two non-parallel directions).

[0089] Among them, the transistor array (the first transistor array, the second transistor array, the third transistor array and the fourth transistor array) can be formed by connecting two or more transistors in series or in parallel, or adopt other conventional implementation methods in the art, which are not limited here. In at least one embodiment, the transistors constituting any of the above transistor arrays can be bipolar junction transistors (BJTs), or field effect transistors (FETs), etc. In at least one embodiment, the transistor is a heterojunction transistor (HBT). Exemplarily, the transistor is a heterojunction transistor implemented using a GaAs process. In at least one implementation, the transistor is an NPN transistor, that is, the first transistor array, the second transistor array, the third transistor array and the fourth transistor array are all NPN transistors. It can be understood that in some embodiments, different transistor arrays can be different types of transistors. Exemplarily, the first transistor array is a PNP transistor, the second transistor array is an NPN transistor, the third transistor array is a PNP transistor, and the fourth transistor array is an NPN transistor. The arrangement of each transistor array can be arranged in a staggered manner such as one column, two or more columns, and multiple columns, which are not specifically limited here.

[0090] In at least one embodiment, the RF power amplifier chip is implemented using a BJT process, or the RF power amplifier chip is implemented using a CMOS process, or the RF power amplifier chip is implemented using a gallium arsenide process.

[0091] like Figure 1 As shown, the first transistor array 11 is arranged on the first side in the first direction, and the third transistor array 21 is arranged on the second side in the first direction. The second transistor array 12 is arranged on the first side in the second direction, and the fourth transistor array 22 is arranged on the second side in the second direction.

[0092] It can be understood that the first side and the second side in this embodiment are only limitations on relative positions. Figure 1 For example, the first transistor array and the third transistor array are distributed in the first direction, the first transistor array is arranged closer to the lower side relative to the third transistor array, and the third transistor array is arranged closer to the upper side relative to the first transistor array, the second transistor array and the fourth transistor array are distributed in the second direction, the second transistor array is arranged closer to the right side relative to the fourth transistor array, and the fourth transistor array is arranged closer to the left side relative to the second transistor array.

[0093] The first power synthesis unit is arranged on the second side in the first direction and the second side in the second direction, and is configured to perform power synthesis on the output signals of the first transistor array and the second transistor array. Figure 1 As shown, the first power synthesis unit 30 is arranged on the second side in the first direction and the second side in the second direction. Specifically, the first power synthesis unit 30 can be divided into two parts, one part is arranged on the second side in the first direction, and the other part is arranged on the second side in the second direction. In at least one embodiment, the first power synthesis unit is a transformer structure, including a first primary coil and a first secondary coil, and the two ends of the first primary coil are respectively connected to the first transistor array and the second transistor array. Optionally, one end of the first secondary coil is connected to the output signal end, and the other end is configured to be grounded or connected to the second power synthesis unit. In at least one embodiment, the first primary coil and the first secondary coil can realize same-layer coupling in the same metal layer in the chip, or the first primary coil and the first secondary coil can realize longitudinal (stacked) coupling in different metal layers in the chip, or the first primary coil and the first secondary coil can realize both same-layer coupling and longitudinal coupling.

[0094] The second power synthesis unit is arranged on the first side in the second direction and the first side in the first direction, and is configured to perform power synthesis on the output signals of the third transistor array and the fourth transistor array. Figure 1 As shown, the second power synthesis unit 40 is arranged on the first side in the second direction and the first side in the first direction. Specifically, the second power synthesis unit 40 can be divided into two parts, one part is arranged on the first side in the second direction, and the other part is arranged on the first side in the first direction. In at least one embodiment, the second power synthesis unit is a transformer structure, including a second primary coil and a second secondary coil, and the two ends of the second primary coil are respectively connected to the third transistor array and the fourth transistor array. One end of the second secondary coil is connected to the output signal end, and the other end is configured to be grounded, or one end of the second secondary coil is configured to be grounded, and the other end is connected to the first power synthesis unit. In at least one embodiment, the second primary coil and the second secondary coil can realize same-layer coupling in the same metal layer in the chip, or the second primary coil and the second secondary coil can realize longitudinal (stacked) coupling in different metal layers in the chip, or the second primary coil and the second secondary coil can realize both same-layer coupling and longitudinal coupling.

[0095] In at least one embodiment, the first primary coil and the first secondary coil can be longitudinally coupled (stacked) in different metal layers in the chip, and the second primary coil and the second secondary coil can be longitudinally coupled (stacked) in different metal layers in the chip. Specifically, the first primary coil and the second primary coil are arranged in the first metal layer of the chip, the first secondary coil and the second secondary coil are arranged in the second metal layer of the chip, the first primary coil and the first secondary coil are longitudinally coupled, and the second primary coil and the second secondary coil are longitudinally coupled.

[0096] In at least one embodiment, Figure 1 As shown, the first power synthesis unit and the second power synthesis unit are arranged together around the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0097] In at least one embodiment, the first transistor array, the second transistor array and the corresponding first power synthesis unit may constitute a first power amplification unit, and the third transistor array, the fourth transistor array and the corresponding second power synthesis unit may constitute a second power amplification unit. The first power amplification unit and the second power amplification unit may amplify different RF signals, for example, RF signals of different frequency bands. The different frequency bands may be different frequency bands under the same communication standard (for example, N41, N77, N79, etc.), or different frequency bands under different communication standards (for example, 3G frequency band, 4G frequency band, 5G frequency band, etc.). Alternatively, the first power amplification unit and the second power amplification unit may respectively support amplification of RF signals under different power modes.

[0098] It can be understood that the relative positions in this embodiment can be defined by projection in the thickness direction of the chip, that is, different devices / elements can be arranged in different layers of the chip.

[0099] In this embodiment, the first transistor array is arranged on the first side in the first direction; the second transistor array is arranged on the first side in the second direction, and the first direction and the second direction intersect; the first power synthesis unit is arranged on the second side in the first direction and the second side in the second direction, and is configured to perform power synthesis on the output signals of the first transistor array and the second transistor array; the third transistor array is arranged on the second side in the first direction; the fourth transistor array is arranged on the second side in the second direction; the second power synthesis unit is arranged on the first side in the second direction and the first side in the first direction, and is configured to perform power synthesis on the output signals of the third transistor array and the fourth transistor array. By rationally arranging the transistor array and the corresponding power synthesis unit, the integration of the RF power amplifier chip is improved. Moreover, under the premise of achieving high power, the overall thermal resistance of the chip is reduced, and the reliability of the chip is also guaranteed.

[0100] In at least one embodiment, the first transistor array is closer to the second side in the first direction relative to the portion of the second power synthesis unit disposed on the first side in the first direction, and the second transistor array is closer to the second side in the second direction relative to the portion of the second power synthesis unit disposed on the first side in the second direction;

[0101] and / or,

[0102] The third transistor array is closer to the first side in the first direction relative to a portion of the first power synthesis unit disposed on the second side in the first direction, and the fourth transistor array is closer to the first side in the second direction relative to a portion of the first power synthesis unit disposed on the second side in the second direction.

[0103] For example, in Figure 1 In the embodiment, the first transistor array 11 is closer to the second side in the first direction relative to the second power synthesis unit 40. Specifically, the first transistor array 11 is closer to the second side in the first direction than the portion of the second power synthesis unit 40 disposed on the first side in the first direction.

[0104] The second transistor array 12 is closer to the second side in the second direction relative to the second power synthesis unit. Specifically, the second transistor array 12 is closer to the second side in the second direction than the second power synthesis unit 40 is disposed on the first side in the second direction.

[0105] The third transistor array 21 is closer to the first side in the first direction relative to the first power synthesis unit 30 . Specifically, the third transistor array 21 is closer to the first side in the first direction than the portion of the first power synthesis unit 30 disposed on the second side in the first direction.

[0106] The fourth transistor array 22 is closer to the first side in the second direction relative to the first power synthesis unit 30 . Specifically, the fourth transistor array 22 is closer to the first side in the second direction than the portion of the first power synthesis unit 30 disposed on the second side in the second direction.

[0107] In this embodiment, by arranging the transistor array closer to the inside of the chip relative to the power synthesis unit, routing can be facilitated and excessive cross-wires can be avoided, thereby further ensuring the chip integration and avoiding performance degradation caused by excessive cross-wires.

[0108] In at least one embodiment, the first direction is perpendicular to the second direction. By setting the first direction and the second direction perpendicular, the overall layout can be made more square, which fits the appearance of the chip and makes the overall layout compact. It can be understood that the verticality in this embodiment is not limited to an absolute 90 degree. As long as the first direction and the second direction deviate by a certain angle (for example, plus or minus 5 degrees or plus or minus 10 degrees, etc.) within the range of 90 degrees, it should be considered to be in accordance with this embodiment.

[0109] In at least one embodiment, the first power synthesis unit and the second power synthesis unit are arranged outside the RF power amplifier chip. Figure 1 As shown, by arranging the first power synthesis unit 30 and the second power synthesis unit 40 on the outside of the RF power amplifier chip, the circuit routing is facilitated while making better use of the internal space of the chip, taking into account both the integration and the chip performance.

[0110] Furthermore, the first power synthesis unit and the second power synthesis unit are arranged on the outside of the RF power amplifier chip and can serve as at least a partial sealing ring (Sealring) of the RF power amplifier chip, which can reduce the additional space consumption of the chip (otherwise an additional sealing ring needs to be arranged on the outside of the chip) and improve the overall integration of the chip.

[0111] In at least one embodiment, the first power synthesis unit and the second power synthesis unit are at least partially disposed in a contact metal layer of the chip, and the contact metal layer is disposed adjacent to a substrate of the chip.

[0112] It can be understood that the first power synthesis unit and the second power synthesis unit can be partially set in the first metal layer of the chip and partially set in the contact metal layer. Alternatively, the first power synthesis unit and the second power synthesis unit can be partially set in the first metal layer and the second metal layer of the chip and partially set in the contact metal layer.

[0113] In at least one embodiment, Fig.16 As shown, the contact metal layer 202 is disposed on the substrate 201, and the first metal layer 204 is disposed above the contact metal layer 202, wherein the first metal layer 204 and the contact metal layer 202 may be connected through a first via 203. The second metal layer 206 is disposed above the first metal layer 204, wherein the second metal layer 206 and the first metal layer 204 may be connected through a second via 204.

[0114] In at least one embodiment, the first power synthesis unit and the second power synthesis unit are disposed in the first metal layer 204 and the contact metal layer 202 , and a pattern disposed in the first metal layer and a pattern disposed in the contact metal layer 202 are connected through a first via 203 .

[0115] In at least one embodiment, the first power synthesis unit and the second power synthesis unit are arranged in the second metal layer 206, the first metal layer 204 and the contact metal layer 202, and the pattern arranged in the first metal layer and the pattern arranged in the contact metal layer 202 are connected through a first via 203, and the pattern arranged in the first metal layer and the pattern arranged in the second metal layer 206 are connected through a second via 205.

[0116] In this embodiment, the first power synthesis unit and the second power synthesis unit are at least partially disposed in the contact metal layer of the chip to realize the function of the chip sealing ring, thereby better improving the integration of the chip.

[0117] In at least one embodiment, a portion of the second power synthesis unit 40 disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array.

[0118] In at least one embodiment, a portion of the second power synthesis unit 40 disposed on the first side in the second direction is closer to the second side in the second direction than the second transistor array 12 .

[0119] In at least one embodiment, the portion of the first power synthesis unit 30 disposed on the second side in the first direction is closer to the first side in the first direction than the third transistor array 21 .

[0120] In at least one embodiment, the portion of the first power synthesis unit 30 disposed on the second side in the second direction is closer to the first side in the second direction than the fourth transistor array 22 .

[0121] In at least one embodiment, the RF power amplifier chip meets at least one of the following requirements:

[0122] The portion of the second power synthesis unit 40 disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array;

[0123] The portion of the second power synthesis unit 40 disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array 12;

[0124] The portion of the first power synthesis unit 30 disposed on the second side in the first direction is closer to the first side in the first direction than the third transistor array 21;

[0125] The portion of the first power synthesis unit 30 disposed on the second side in the second direction is closer to the first side in the second direction than the fourth transistor array 22 .

[0126] In at least one embodiment, a portion of the second power synthesis unit 40 disposed on the first side in the first direction is closer to a second side in the first direction relative to the first transistor array, and a portion of the second power synthesis unit 40 disposed on the first side in the second direction is closer to a second side in the second direction relative to the second transistor array 12;

[0127] and / or,

[0128] The portion of the first power synthesis unit 30 disposed on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array 21 , and the portion of the first power synthesis unit 30 disposed on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array 22 .

[0129] In this embodiment, by flexibly setting the power synthesis unit and the corresponding transistor array, it is possible to better ensure adaptation to different application scenarios (different frequency modes, different power modes or reconfigurable modes, etc.), and to ensure better functions and performance in different scenarios.

[0130] In at least one embodiment, a portion of the second power synthesis unit 40 disposed on the first side in the first direction is closer to a second side in the first direction relative to the first transistor array, and a portion of the second power synthesis unit 40 disposed on the first side in the second direction is closer to a second side in the second direction relative to the second transistor array 12;

[0131] The third transistor array is closer to the first side in the first direction relative to a portion of the first power synthesis unit disposed on the second side in the first direction, and the fourth transistor array is closer to the first side in the second direction relative to a portion of the first power synthesis unit disposed on the second side in the second direction.

[0132] In this embodiment, by flexibly adjusting the relative positions of the transistor array and the corresponding power synthesis unit, the layout can be performed more flexibly.

[0133] In at least one embodiment, the portion of the first power synthesis unit 30 disposed on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array 21, and the portion of the first power synthesis unit 30 disposed on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array 22;

[0134] The first transistor array is closer to the second side in the first direction relative to a portion of the second power synthesis unit disposed on the first side in the first direction, and the second transistor array is closer to the second side in the second direction relative to a portion of the second power synthesis unit disposed on the first side in the second direction.

[0135] In this embodiment, by flexibly adjusting the relative positions of the transistor array and the corresponding power synthesis unit, the layout can be performed more flexibly.

[0136] In at least one embodiment, the first secondary sub-coil is closer to the first side in the first direction relative to the first primary sub-coil, the second secondary sub-coil is closer to the first side in the second direction relative to the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction relative to the third secondary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction relative to the fourth secondary sub-coil;

[0137] or,

[0138] The first primary sub-coil is closer to the first side in the first direction relative to the first secondary sub-coil, the second primary sub-coil is closer to the first side in the second direction relative to the second secondary sub-coil, the third secondary sub-coil is closer to the second side in the first direction relative to the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction relative to the fourth primary sub-coil.

[0139] In at least one embodiment, Figure 1 As shown, the first secondary sub-coil 33 is closer to the first side in the first direction relative to the first primary sub-coil 31, the second secondary sub-coil 34 is closer to the first side in the second direction relative to the second primary sub-coil 32, the third primary sub-coil 41 is closer to the second side in the first direction relative to the third secondary sub-coil 43, and the fourth primary sub-coil 42 is closer to the second side in the second direction relative to the fourth secondary sub-coil 44.

[0140] In at least one embodiment, Figure 3 As shown, the first primary sub-coil 31 is closer to the first side in the first direction relative to the first secondary sub-coil 33, the second primary sub-coil 32 is closer to the first side in the second direction relative to the second secondary sub-coil 34, the third secondary sub-coil 43 is closer to the second side in the first direction relative to the third primary sub-coil 41, and the fourth secondary sub-coil 44 is closer to the second side in the second direction relative to the fourth primary sub-coil 42.

[0141] In at least one embodiment, one end of the first primary sub-coil 31 is connected to the output end of the second transistor array 12, the other end of the first primary sub-coil 31 is connected to one end of the second primary sub-coil 32, and the other end of the second primary sub-coil 32 is connected to the output end of the first transistor array 11. In at least one implementation, the other end of the first primary sub-coil 31 and one end of the second primary sub-coil 32 are configured to be connected to a first power supply terminal.

[0142] In at least one embodiment, one end of the third primary sub-coil 41 is connected to the output end of the fourth transistor array 22, the other end of the third primary sub-coil 41 is connected to one end of the fourth primary sub-coil 42, and the other end of the fourth primary sub-coil 42 is connected to the output end of the third transistor array 21. In at least one implementation, the other end of the third primary sub-coil 41 and one end of the fourth primary sub-coil 42 are configured to be connected to a second power supply terminal.

[0143] It can be understood that the first power supply terminal and the second power supply terminal can be configured to receive the same power supply voltage or different power supply voltages.

[0144] In at least one embodiment, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first primary sub-coil 31 and a second primary sub-coil 32, and the first secondary coil includes a first secondary sub-coil 33 and a second secondary sub-coil 34; the first primary sub-coil 31 and the first secondary sub-coil 33 are coupled to each other and are arranged on the second side in the first direction; the second primary sub-coil 32 and the second secondary sub-coil 34 are coupled to each other and are arranged on the second side in the second direction;

[0145] The second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a third primary sub-coil 41 and a fourth primary sub-coil 42, the second secondary coil includes a third secondary sub-coil 43 and a fourth secondary sub-coil 44; the third primary sub-coil 41 and the third secondary sub-coil 43 are coupled to each other and are arranged on the first side in the first direction; the fourth primary sub-coil 42 and the fourth secondary sub-coil 44 are coupled to each other and are arranged on the first side in the second direction.

[0146] Among them, the number of the first primary sub-coil 31 can be at least one, the number of the second primary sub-coil 32 can be at least one, the number of the first secondary sub-coil 33 can be at least one, and the number of the second secondary sub-coil 34 can be at least one. Optionally, the number of the first primary sub-coil 31 can be two, and exemplarily, the two first primary sub-coils 31 are connected in parallel on the second side in the first direction. The number of the second primary sub-coil 32 can be two, and exemplarily, the two second primary sub-coils 32 are connected in parallel on the second side in the second direction. Optionally, the number of the first secondary sub-coil 34 can be two, and exemplarily, the two first secondary sub-coils 34 are connected in parallel on the second side in the first direction. The number of the second secondary sub-coil 34 can be two, and exemplarily, the two second secondary sub-coils 34 are connected in parallel on the second side in the second direction. Further, the number of primary sub-coils (the first primary sub-coil 31 and the second primary sub-coil 32) and secondary sub-coils (the first secondary sub-coil 33 and the second secondary sub-coil 34) can be the same or different, and there is no limitation here.

[0147] Among them, the number of the third primary sub-coil 41 can be at least one, the number of the fourth primary sub-coil 42 can be at least one, the number of the third secondary sub-coil 41 can be at least one, and the number of the fourth secondary sub-coil 44 can be at least one. Optionally, the number of the third primary sub-coil 41 can be two, and exemplarily, the two third primary sub-coils 41 are connected in parallel on the second side in the first direction. The number of the fourth primary sub-coil 42 can be two, and exemplarily, the two fourth primary sub-coils 42 are connected in parallel on the second side in the second direction. Optionally, the number of the third secondary sub-coil 41 can be two, and exemplarily, the two third secondary sub-coils 41 are connected in parallel on the second side in the first direction. The number of the fourth secondary sub-coil 44 can be two, and exemplarily, the two fourth secondary sub-coils 44 are connected in parallel on the second side in the second direction. Further, the number of primary sub-coils (the third primary sub-coil 41 and the fourth primary sub-coil 42) and secondary sub-coils (the third secondary sub-coil 41 and the fourth secondary sub-coil 44) can be the same or different, and there is no limitation here.

[0148] In at least one embodiment, the first secondary sub-coil is closer to the first side in the first direction relative to the first primary sub-coil, the second secondary sub-coil is closer to the first side in the second direction relative to the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction relative to the third secondary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction relative to the fourth secondary sub-coil;

[0149] or,

[0150] The first primary sub-coil is closer to the first side in the first direction relative to the first secondary sub-coil, the second primary sub-coil is closer to the first side in the second direction relative to the second secondary sub-coil, the third secondary sub-coil is closer to the second side in the first direction relative to the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction relative to the fourth primary sub-coil.

[0151] like Figure 1 As shown, in at least one embodiment, the first secondary sub-coil 33 is closer to the first side in the first direction relative to the first primary sub-coil 31, the second secondary sub-coil 34 is closer to the first side in the second direction relative to the second primary sub-coil 32, the third primary sub-coil 41 is closer to the second side in the first direction relative to the third secondary sub-coil 43, and the fourth primary sub-coil 42 is closer to the second side in the second direction relative to the fourth secondary sub-coil 44.

[0152] like Figure 3 As shown, in at least one embodiment, the first primary sub-coil 31 is closer to the first side in the first direction relative to the first secondary sub-coil 33, the second primary sub-coil 32 is closer to the first side in the second direction relative to the second secondary sub-coil 34, the third secondary sub-coil 43 is closer to the second side in the first direction relative to the third primary sub-coil 41, and the fourth secondary sub-coil 44 is closer to the second side in the second direction relative to the fourth primary sub-coil 42.

[0153] In at least one embodiment, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first outer primary coil and a first inner primary coil, the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a second outer primary coil and a second inner primary coil, the first secondary coil includes a first partial secondary coil arranged between the first outer primary coil and the first inner primary coil, and a second partial secondary coil arranged between the second outer primary coil and the second inner primary coil, the first partial secondary coil and the second partial secondary coil are connected in series.

[0154] like Figure 4 As shown, the first power synthesis unit 30 includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first outer primary coil 35 and a first inner primary coil 36; the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a second outer primary coil 45 and a second inner primary coil 46, the first secondary coil includes a first partial secondary coil 37 arranged between the first outer primary coil 35 and the first inner primary coil 36, and a second partial secondary coil 47 arranged between the second outer primary coil 45 and the second inner primary coil 46, the first partial secondary coil 37 and the second partial secondary coil 47 are connected in series.

[0155] In at least one embodiment, one end of the first partial secondary coil 37 is configured to be connected to the signal output terminal, the other end of the first partial secondary coil 37 is connected to one end of the second partial secondary coil 47, and the other end of the second partial secondary coil 47 is configured to be grounded. In at least one embodiment, one end of the first partial secondary coil 37 is configured to be grounded, the other end of the first partial secondary coil 37 is connected to one end of the second partial secondary coil 47, and the other end of the second partial secondary coil 47 is configured to be connected to the signal output terminal.

[0156] In this embodiment, the first primary coil includes a first outer primary coil 35 and a first inner primary coil 36, and the corresponding first partial secondary coil 37 is arranged between the first outer primary coil 35 and the first inner primary coil 36. The second primary coil includes a second outer primary coil 45 and a second inner primary coil 46, and the corresponding first partial secondary coil 37 is arranged between the first outer primary coil 35 and the first inner primary coil 36, which ensures better coupling and further improves the performance of the power amplifier.

[0157] In at least one embodiment, the first secondary coil also includes a third partial secondary coil arranged inside the first primary coil, and the second secondary coil also includes a fourth partial secondary coil arranged inside the second primary coil, and the first partial secondary coil, the third partial secondary coil, the second partial secondary coil and the fourth partial secondary coil are connected in series in sequence.

[0158] like Figure 5 As shown, the first secondary coil further includes a third partial secondary coil 38 disposed inside the first primary coil, and the second secondary coil further includes a fourth partial secondary coil 48 disposed inside the second primary coil. Figure 5 , the third partial secondary coil 38 is arranged inside the first primary coil, specifically, the third partial secondary coil 38 is arranged inside the first outer primary coil 35 and also inside the first inner primary coil 36. The fourth partial secondary coil 48 is arranged inside the second primary coil, specifically, the fourth partial secondary coil 48 is arranged inside the second outer primary coil 45 and also inside the second inner primary coil 46. The first partial secondary coil 37, the third partial secondary coil 47, the second partial secondary coil 38 and the fourth partial secondary coil 48 are connected in series in sequence. Specifically, one end of the first partial secondary coil 37 is configured to be connected to the signal output end, the other end of the first partial secondary coil 37 is connected to one end of the second partial secondary coil 47, the other end of the second partial secondary coil 47 is connected to one end of the third partial secondary coil 38, the other end of the third partial secondary coil 38 is connected to one end of the fourth partial secondary coil 48, and the other end of the fourth partial secondary coil 48 is configured to be grounded. Alternatively, one end of the first partial secondary coil 37 is configured to be grounded, the other end of the first partial secondary coil 37 is connected to one end of the second partial secondary coil 47, the other end of the second partial secondary coil 47 is connected to one end of the third partial secondary coil 38, the other end of the third partial secondary coil 38 is connected to one end of the fourth partial secondary coil 48, and the other end of the fourth partial secondary coil 48 is configured to be connected to the signal output end.

[0159] In this embodiment, by winding the secondary coil in multiple layers, the power amplifier can be matched to a lower impedance in coordination with the primary coil.

[0160] In at least one embodiment, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, and the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other;

[0161] The first secondary coil includes a first portion of the secondary coil arranged on the first metal layer of the RF power amplifier chip and a second portion of the secondary coil arranged on the second metal layer of the RF power amplifier chip, and the second secondary coil includes a third portion of the secondary coil arranged on the first metal layer of the RF power amplifier chip and a fourth portion of the secondary coil arranged on the second metal layer of the RF power amplifier chip;

[0162] One end of the first secondary coil is configured to be connected to the signal output terminal, one end of the third secondary coil is configured to be grounded, and the first secondary coil is connected in series with the third secondary coil; one end of the second secondary coil is configured to be connected to the signal output terminal, one end of the fourth secondary coil is configured to be grounded, and the second secondary coil is connected in series with the fourth secondary coil;

[0163] The coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer; or, the coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the first manner is a clockwise manner or a counterclockwise manner.

[0164] like Figure 6 As shown, the first secondary coil includes a first portion of the secondary coil 391 disposed on the first metal layer of the RF power amplifier chip and a second portion of the secondary coil 392 disposed on the second metal layer of the RF power amplifier chip, and the second secondary coil includes a third portion of the secondary coil 491 disposed on the first metal layer of the RF power amplifier chip and a fourth portion of the secondary coil 492 disposed on the second metal layer of the RF power amplifier chip. It can be understood that Figure 6The first secondary coil 391, the second secondary coil 392, the third secondary coil 491 and the fourth secondary coil 492 all include two parts (an L-shaped coil segment arranged relatively outside and an L-shaped coil segment arranged relatively inside), but it should not be interpreted as a limitation on the quantity and shape of any of the above secondary coils. It is only used as an example here.

[0165] Understandably, Figure 6 The first partial secondary coil 391 and the third partial secondary coil 491 arranged in the first metal layer and the second partial secondary coil 392 and the fourth partial secondary coil 492 arranged in the second metal layer are illustrated side by side only for a more intuitive description, but in fact the first metal layer and the second metal layer belong to different layers in the thickness direction of the chip. In at least one embodiment, the first metal layer is located above the second metal layer. In at least one embodiment, the first metal layer is located below the second metal layer. In at least one embodiment, the first metal layer and the second metal layer are two adjacent metal layers.

[0166] In at least one embodiment, the first metal layer and the second metal layer are two non-adjacent metal layers. Exemplarily, the RF power amplifier chip further includes a third metal layer, the first primary coil and the second primary coil may be disposed on the third metal layer, and the third metal layer is disposed between the first metal layer and the second metal layer.

[0167] One end of the first part secondary coil 391 is configured to be connected to the signal output terminal, one end of the third part secondary coil 491 is configured to be grounded, and the first part secondary coil 391 is connected in series with the third part secondary coil 491; one end of the second part secondary coil 392 is configured to be connected to the signal output terminal, one end of the fourth part secondary coil 492 is configured to be grounded, and the second part secondary coil 392 is connected in series with the fourth part secondary coil 492.

[0168] by Figure 6 For example, the first part of the secondary coil 391 includes a first part of the outer coil and a first part of the inner coil, and the third part of the secondary coil 491 includes a third part of the outer coil and a third part of the inner coil. The first end of the first part of the outer coil is configured to be connected to the signal output end, the other end of the first part of the outer coil is connected to the first end of the third part of the outer coil, the other end of the third part of the outer coil is connected to the first end of the first part of the inner coil, the other end of the first part of the inner coil is connected to the first end of the third part of the inner coil, and the other end of the third part of the inner coil is configured to be grounded.

[0169] The second secondary coil 392 includes a second outer coil and a second inner coil, and the fourth secondary coil 492 includes a fourth outer coil and a fourth inner coil. The first end of the second inner coil is configured to be connected to the signal output end, the other end of the second inner coil is connected to the first end of the fourth inner coil, the other end of the fourth inner coil is connected to the first end of the second outer coil, the other end of the second outer coil is connected to the first end of the fourth outer coil, and the other end of the fourth outer coil is configured to be grounded.

[0170] In at least one embodiment, the coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer, and the first manner is a clockwise manner or a counterclockwise manner.

[0171] by Figure 6 For example, the first part of the secondary coil 391 includes a first part of the outer coil and a first part of the inner coil, and the third part of the secondary coil 491 includes a third part of the outer coil and a third part of the inner coil. The first end of the first part of the outer coil is configured to be connected to the signal output end, the other end of the first part of the outer coil is connected to the first end of the third part of the outer coil, the other end of the third part of the outer coil is connected to the first end of the first part of the inner coil, the other end of the first part of the inner coil is connected to the first end of the third part of the inner coil, and the other end of the third part of the inner coil is configured to be grounded.

[0172] The second secondary coil 392 includes a second outer coil and a second inner coil, and the fourth secondary coil 492 includes a fourth outer coil and a fourth inner coil. The first end of the second inner coil is configured to be connected to the signal output end, the other end of the second inner coil is connected to the first end of the fourth inner coil, the other end of the fourth inner coil is connected to the first end of the second outer coil, the other end of the second outer coil is connected to the first end of the fourth outer coil, and the other end of the fourth outer coil is configured to be grounded.

[0173] In at least one embodiment, the coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound from the inner layer to the outer layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound from the outer layer to the inner layer.

[0174] The first secondary coil includes a first outer coil and a first inner coil, and the third secondary coil includes a third outer coil and a third inner coil. The first end of the first inner coil is configured to be connected to the signal output end, the other end of the first inner coil is connected to the first end of the third inner coil, the other end of the third inner coil is connected to the first end of the second outer coil, the other end of the first outer coil is connected to the first end of the third outer coil, and the other end of the third outer coil is configured to be grounded.

[0175] The second secondary coil includes a second outer coil and a second inner coil, and the fourth secondary coil includes a fourth outer coil and a fourth inner coil. The first end of the second outer coil is configured to be connected to the signal output end, the other end of the second outer coil is connected to the first end of the fourth outer coil, the other end of the fourth outer coil is connected to the first end of the second inner coil, the other end of the second inner coil is connected to the first end of the fourth inner coil, and the other end of the fourth inner coil is configured to be grounded.

[0176] In this embodiment, in at least one implementation, the first primary coil and the second primary coil may be disposed only on the first metal layer.

[0177] In at least one embodiment, the first primary coil is partially disposed on the first metal layer and the other part is disposed on the second metal layer, and the second primary coil is partially disposed on the first metal layer and the other part is disposed on the second metal layer. Figure 5 The first primary coil and the second primary coil may be arranged on the second metal layer in the manner described above. Figure 5 The method settings in .

[0178] In this embodiment, the first secondary coil and the second secondary coil are arranged in different metal layers in a relatively complementary manner, thereby better ensuring the balance of the radio frequency power amplifier.

[0179] In at least one embodiment, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, and the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other;

[0180] The first primary coil includes a first portion of the primary coil disposed on a first metal layer of the RF power amplifier chip and a second portion of the primary coil disposed on a second metal layer of the RF power amplifier chip, wherein the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled;

[0181] The second primary coil includes a third primary coil arranged on the first metal layer of the RF power amplifier chip and a fourth primary coil arranged on the second metal layer of the RF power amplifier chip, and the third primary coil and the fourth primary coil are longitudinally coupled.

[0182] In this embodiment, the first primary coil includes a first portion of the primary coil disposed on the first metal layer and a second portion of the primary coil disposed on the second metal layer, and the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled. The second primary coil includes a third portion of the primary coil disposed on the first metal layer of the RF power amplifier chip and a fourth portion of the primary coil disposed on the second metal layer of the RF power amplifier chip, and the third portion of the primary coil and the fourth portion of the primary coil are longitudinally coupled. In at least one embodiment, the secondary coil disposed on the two metal layers can cooperate with each other to better ensure the performance of the power amplifier.

[0183] In at least one embodiment, the RF power amplifier chip further includes a pre-stage driving circuit, and the pre-stage driving circuit is arranged in an area surrounded by the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0184] like Figure 7 As shown, the pre-stage driving circuit 90 is arranged in the area surrounded by the first transistor array, the second transistor array, the third transistor array and the fourth transistor array. The pre-stage driving circuit 90 is a radio frequency signal conversion circuit, for example, converting an unbalanced radio frequency signal into a balanced radio frequency signal, converting a single-ended signal into a differential signal, etc. Alternatively, the pre-stage driving circuit can be at least one stage of amplification circuit.

[0185] Figure 8 The circuit schematic shown corresponds to Figure 1 A structure in which one end of the first secondary coil is connected to the output signal end, and the other end is connected to one end of the second secondary coil, and the other end of the second secondary coil is configured to be grounded.

[0186] Fig. 9 The circuit schematic shown corresponds to Figure 2 A structure in which one end of the first secondary coil is configured to be grounded, the other end is connected to one end of the second secondary coil and configured to be connected to the output signal end, and the other end of the second secondary coil is configured to be grounded.

[0187] In at least one embodiment, Fig.10As shown, the pre-stage driving circuit includes a first input transformer 50 and a second input transformer 60. The first end of the secondary coil of the first input transformer 50 is connected to the first transistor array 11, and the second end of the secondary coil of the first input transformer 50 is connected to the second transistor array 12. The first end of the secondary coil of the second input transformer 60 is connected to the third transistor array 21, and the second end of the secondary coil of the second input transformer 60 is connected to the fourth transistor array 22. Taking the transistor array as an NPN transistor composition as an example, the first end of the secondary coil of the first input transformer 50 is connected to the base of the first transistor array 11, and the second end of the secondary coil of the first input transformer 50 is connected to the base of the second transistor array 12. The first end of the secondary coil of the second input transformer 60 is connected to the base of the third transistor array 21, and the second end of the secondary coil of the second input transformer 60 is connected to the base of the fourth transistor array 22. The emitter of the first transistor array 11, the emitter of the second transistor array 12, the emitter of the third transistor array 21, and the emitter of the fourth transistor array 21 are all configured to be grounded. The collectors of the first transistor array 11 and the second transistor array 12 are connected to both ends of the first primary coil of the first power synthesis unit, respectively. The collectors of the third transistor array 21 and the fourth transistor array 22 are connected to both ends of the second primary coil of the second power synthesis unit, respectively.

[0188] In at least one embodiment, the first end of the primary coil of the first input transformer 50 receives the input RF signal, the second end of the primary coil of the first input transformer 50 is connected to the first end of the second input transformer 60, and the second end of the second input transformer 60 is configured to be grounded. Optionally, a preamplifier circuit is further included, the input end of the preamplifier circuit is configured to receive the input RF signal, and the output end is connected to the first end of the primary coil of the first input transformer 50.

[0189] In at least one embodiment, Fig.11 As shown, the first end of the primary coil of the first input transformer 50 is configured to be grounded, the second end of the primary coil of the first input transformer 50 receives the input RF signal, the first end of the second input transformer 60 receives the input RF signal, and the second end of the second input transformer 60 is configured to be grounded. Optionally, a preamplifier circuit is further included, the input end of the preamplifier circuit is configured to receive the input RF signal, and the output end is connected to the second end of the primary coil of the first input transformer 50 and the first end of the second input transformer 60.

[0190] In at least one embodiment, Fig.12As shown, the first end of the primary coil of the first input transformer 50 is configured to be grounded, and the second end of the primary coil of the first input transformer 50 is connected to the output end of one pre-amplifier circuit. The first end of the second input transformer 60 is connected to the output end of another pre-amplifier circuit, and the second end of the second input transformer 60 is configured to be grounded.

[0191] In at least one embodiment, Fig.13 As shown, both ends of the secondary coil of the first input transformer 50 are respectively connected to the fifth transistor array 71 and the sixth transistor array 72. Both ends of the secondary coil of the second input transformer 60 are respectively connected to the seventh transistor array 81 and the eighth transistor array 82. It can be understood that the composition of the fifth transistor array 71, the sixth transistor array 72, the seventh transistor array 81 and the eighth transistor array 82 can be the same as that of the first transistor array, and will not be repeated here.

[0192] It can be understood that in the above implementation, other circuit modules such as a bias circuit, a matching circuit, and a power supply circuit may also be included, which will not be elaborated here.

[0193] In at least one embodiment, the RF power amplifier chip further includes a passive component network disposed in an area surrounded by the first power synthesis unit and the second power synthesis unit.

[0194] The passive component network is a network composed of at least one passive component, illustratively, a network composed of at least one of a resistor, a capacitor, or an inductor. In at least one embodiment, the passive component network is a network composed of at least one capacitor and at least one inductor. The passive component network is arranged in an area surrounded by the first power synthesis unit and the second power synthesis unit.

[0195] Optionally, the passive component network may be disposed in a space between a power synthesis unit and a corresponding transistor array. Exemplarily, the passive component network may be disposed in a region between the first transistor array, the second transistor array, and the second power synthesis unit. Alternatively, the passive component network may be disposed in a region between the third transistor array, the fourth transistor array, and the first power synthesis unit.

[0196] Optionally, the passive component network may be arranged in the space between two transistor arrays. Exemplarily, it is arranged between the first transistor array and the second transistor array, or, it is arranged between the third transistor array and the fourth transistor array. Or, it is arranged between the second transistor array and the third transistor array. Or, it is arranged between the first transistor array and the fourth transistor array.

[0197] Optionally, the passive component network may be arranged inside the transistor array.

[0198] In at least one embodiment, the passive component network includes a first passive component unit and a second passive component unit, the first passive component unit is arranged in an area between the first transistor array, the second transistor array and the second power synthesis unit, and the second passive component unit is arranged in an area between the third transistor array, the fourth transistor array and the first power synthesis unit.

[0199] like Fig.14 As shown, the passive component network includes a first passive component unit 110 and a second passive component unit 120. The first passive component unit 110 is disposed in a region between the first transistor array, the second transistor array, and the second power synthesis unit. The second passive component unit 120 is disposed in a region between the third transistor array, the fourth transistor array, and the first power synthesis unit.

[0200] In at least one embodiment, the first passive component unit 110 includes a first capacitor, a second capacitor, and a first inductor. One end of the first capacitor is connected to the output end of the first transistor array, the second end of the first capacitor is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the output end of the second transistor array, the first end of the first inductor is connected to the second end of the first capacitor and the first end of the second capacitor, and the second end of the first inductor is configured to be grounded.

[0201] In at least one embodiment, the second passive unit 120 includes a third capacitor, a fourth capacitor, and a second inductor. One end of the third capacitor is connected to the output end of the first transistor array, the second end of the third capacitor is connected to the first end of the second capacitor, the second end of the fourth capacitor is connected to the output end of the second transistor array, the first end of the second inductor is connected to the second end of the first capacitor and the first end of the fourth capacitor, and the second end of the second inductor is configured to be grounded.

[0202] In at least one embodiment, the passive component network includes a third passive unit, a fourth passive unit, a fifth passive unit and a sixth passive unit, the third passive unit is arranged between the first transistor array and the second transistor array, the fourth passive unit is arranged between the second transistor array and the third transistor array, the fifth passive unit is arranged between the third transistor array and the fourth transistor array, and the sixth passive unit is arranged between the fourth transistor array and the first transistor array.

[0203] Wherein, each of the above passive units can be connected to one of the transistor arrays to achieve a network matching function. In at least one embodiment, the third passive unit is connected to the first transistor array, the fourth passive unit is connected to the second transistor array, the fifth passive unit is connected to the third transistor array, and the sixth passive unit is connected to the fourth transistor array.

[0204] Further, one end of the third passive unit is connected to the output end of the first transistor array, and the other end is configured to be grounded. One end of the fourth passive unit is connected to the output end of the second transistor array, and the other end is configured to be grounded. One end of the fifth passive unit is connected to the output end of the third transistor array, and the other end is configured to be grounded. One end of the sixth passive unit is connected to the output end of the fourth transistor array, and the other end is configured to be grounded. In at least one embodiment, the third passive unit, the fourth passive unit, the fifth passive unit, and the sixth passive unit all include an inductor and a capacitor connected in series. In at least one embodiment, the third passive unit, the fourth passive unit, the fifth passive unit, and the sixth passive unit all include an inductor and a capacitor connected in series. One end of the capacitor is connected to the corresponding transistor array, and the second end of the capacitor is connected to the ground terminal through a bonding wire.

[0205] In at least one embodiment, the first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, a first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array;

[0206] The second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, a first end of the second primary coil is connected to the third transistor array, and a second end of the second primary coil is connected to the fourth transistor array.

[0207] In at least one embodiment, the first end of the first secondary coil is configured to be connected to a signal output terminal, the second end of the first secondary coil is connected to the first end of the second secondary coil, and the second end of the second secondary coil is configured to be grounded;

[0208] or,

[0209] The first end of the first secondary coil and the second end of the second secondary coil are configured to be connected to a signal output terminal, and the second end of the first secondary coil and the first end of the second secondary coil are configured to be grounded.

[0210] In at least one embodiment, the first transistor array, the second transistor array and the first power synthesis unit are configured to achieve power amplification of differential RF signals, and the third transistor array, the fourth transistor array and the second power synthesis unit are configured to achieve power amplification of differential RF signals.

[0211] At least one embodiment of the present invention provides a radio frequency power amplifier chip, including:

[0212] A first power synthesis amplifier circuit comprises a first amplifier branch and a second amplifier branch;

[0213] The second power synthesis amplifying circuit comprises a third amplifying branch and a fourth amplifying branch;

[0214] An output transformer network is configured to receive the radio frequency signals output by the first amplifying branch, the second amplifying branch, the third amplifying branch and the fourth amplifying branch and output them after combining. The output transformer network is arranged on the outside of the chip and surrounds the first power synthesis amplifying circuit and the second power synthesis amplifying circuit.

[0215] Wherein, the first amplifying branch may include a first transistor array, the second amplifying branch may include a second transistor array, the third amplifying branch may include a third transistor array, and the fourth amplifying branch may include a fourth transistor array. The output transformer network includes a first output transformer and a second output transformer, one end of the primary coil of the first output transformer is connected to the output end of the first transistor array, and the other end of the primary coil of the first output transformer is connected to the output end of the second transistor array. One end of the primary coil of the second output transformer is connected to the output end of the third transistor array, and the other end of the primary coil of the second output transformer is connected to the output end of the fourth transistor array. Optionally, one end of the secondary coil of the first output transformer is configured to be connected to the output signal end, the other end of the secondary coil of the first output transformer is connected to one end of the secondary coil of the second output transformer, and the other end of the secondary coil of the second output transformer is configured to be grounded. Optionally, one end of the secondary coil of the first output transformer is configured to be grounded, the other end of the secondary coil of the first output transformer is connected to one end of the secondary coil of the second output transformer, and is configured to be connected to the output signal end, and the other end of the secondary coil of the second output transformer is configured to be grounded.

[0216] It can be understood that the above-mentioned output transformer network can be implemented by the first power synthesis unit and the second power synthesis unit in any of the above-mentioned embodiments, which will not be described in detail here.

[0217] At least one embodiment of the present invention provides a radio frequency power amplifier chip, including:

[0218] The first transistor array, the second transistor array, the third transistor array and the fourth transistor array are distributed in four regions: a first side in the first direction, a second side in the first direction, a first side in the second direction and a second side in the second direction, and the first direction and the second direction intersect;

[0219] A first power synthesis unit, disposed on the second side in the first direction and the second side in the second direction, configured to perform power synthesis on two transistor arrays among the first transistor array, the second transistor array, the third transistor array and the fourth transistor array;

[0220] A second power synthesis unit, which is arranged on the first side in the second direction and the first side in the first direction is arranged on the outside of the chip, is configured to perform power synthesis on the other two transistor arrays of the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0221] Among them, the first transistor array, the second transistor array, the third transistor array and the fourth transistor array each select an area in four areas (the first side in the first direction, the second side in the first direction, the first side in the second direction and the second side in the second direction) for setting.

[0222] Exemplarily, the first transistor array is arranged on the first side in the first direction, the second transistor array is arranged on the first side in the second direction, the third transistor array is arranged on the second side in the first direction, and the fourth transistor array is arranged on the second side in the second direction. Alternatively, the first transistor array is arranged on the first side in the first direction, the second transistor array is arranged on the second side in the first direction, the third transistor array is arranged on the first side in the second direction, and the fourth transistor array is arranged on the second side in the second direction. Alternatively, the first transistor array is arranged on the second side in the first direction, the second transistor array is arranged on the second side in the second direction, the third transistor array is arranged on the first side in the first direction, and the fourth transistor array is arranged on the first side in the second direction.

[0223] A first power synthesis unit is arranged on the second side in the first direction and the second side in the second direction, and is configured to perform power synthesis on two transistor arrays among the first transistor array, the second transistor array, the third transistor array and the fourth transistor array; a second power synthesis unit is arranged on the first side in the second direction and the first side in the first direction is arranged on the outside of the chip, and is configured to perform power synthesis on the other two transistor arrays among the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0224] Exemplarily, if the first power synthesis unit is configured to perform power synthesis on the first transistor array and the second transistor array, the second power synthesis unit is configured to perform power synthesis on the third transistor array and the fourth transistor array. If the first power synthesis unit is configured to perform power synthesis on the first transistor array and the third transistor array, the second power synthesis unit is configured to perform power synthesis on the second transistor array and the fourth transistor array. If the first power synthesis unit is configured to perform power synthesis on the second transistor array and the third transistor array, the second power synthesis unit is configured to perform power synthesis on the first transistor array and the fourth transistor array.

[0225] It can be understood that the first transistor array, the second transistor array, the third transistor array and the fourth transistor array can be implemented by the first transistor array, the second transistor array, the third transistor array and the fourth transistor array in any of the above embodiments / implementations, which will not be described in detail here. The first power synthesis unit and the second power synthesis unit can be implemented by the first power synthesis unit and the second power synthesis unit in any of the above embodiments / implementations, which will not be described in detail here.

[0226] In this embodiment, through the reasonable layout of the transistor arrays and the corresponding power synthesis units, the four transistor arrays are distributed and arranged, thereby reducing the thermal resistance of the entire chip and ensuring the reliability of the chip.

[0227] In at least one embodiment, a first transistor array is arranged on a first side in a first direction, a second transistor array is arranged on a second side in the first direction, and a first power synthesis unit is configured to perform power synthesis on output signals of the first transistor array and the second transistor array; a third transistor array is arranged on a first side in the second direction, a fourth transistor array is arranged on a second side in the second direction, and a second power synthesis unit is configured to perform power synthesis on output signals of the third transistor array and the fourth transistor array.

[0228] Optionally, the first power synthesis unit can be set in at least one of the above-mentioned four areas (the first side in the first direction, the second side in the first direction, the first side in the second direction, and the second side in the second direction), and the second power synthesis unit can be set in at least one of the above-mentioned four areas (the first side in the first direction, the second side in the first direction, the first side in the second direction, and the second side in the second direction).

[0229] In at least one embodiment, the first power synthesis unit may be arranged in two of the four areas, and the second power synthesis unit may be arranged in the other two of the four areas.

[0230] In at least one embodiment, the first power synthesis unit is configured to perform power synthesis on the output signals of the first transistor array and the second transistor array, and the second power synthesis unit is configured to perform power synthesis on the output signals of the third transistor array and the fourth transistor array;

[0231] The first transistor array, the second transistor array and the first power synthesis unit are configured to amplify radio frequency signals of a first frequency band, and the third transistor array, the fourth transistor array and the second power synthesis unit are configured to amplify radio frequency signals of a second frequency band.

[0232] Among them, the first frequency band and the second frequency band can be different frequency bands under the same communication standard (for example, N41, N77, N79, etc.), or they can be different frequency bands under different communication standards (for example, 3G, 4G, 5G, etc.).

[0233] In at least one embodiment, the first transistor array, the second transistor array, the third transistor array, the fourth transistor array, the first power synthesis unit and the second power synthesis unit are configured to operate in a first operating mode, and the first transistor array, the second transistor array and the first power synthesis unit are configured to operate in a second operating mode. The first operating mode may be an operating mode with higher power than the second operating mode.

[0234] At least one embodiment of the present invention provides a radio frequency power amplifier chip, including:

[0235] A first transistor array is arranged on a first side of a first virtual rectangular region in a first direction;

[0236] A second transistor array is arranged at a first side of the first virtual rectangular area in a second direction, wherein the first direction intersects with the second direction;

[0237] A first transformer structure is arranged on a second side of the first virtual rectangular area in the first direction and on a second side of the first virtual rectangular area in the second direction, and includes a first primary coil and a first secondary coil coupled to each other, a first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array.

[0238] like Fig.15As shown, the first transistor array 11 is arranged at a first side in a first direction of the first virtual rectangular area 100. The second transistor array 12 is arranged at a first side in a second direction of the first virtual rectangular area 100, and the first direction and the second direction intersect.

[0239] The first transformer structure is arranged on the second side of the first virtual rectangular area in the first direction and the second side of the first virtual rectangular area in the second direction. It includes a first primary coil and a first secondary coil coupled to each other, the first end of the first primary coil is connected to the first transistor array, and the second end of the first primary coil is connected to the second transistor array. It can be understood that the first transformer structure can be implemented by the first power synthesis unit 30 in any of the above embodiments, which will not be repeated here. Among them, the first virtual rectangular area 100 can be any roughly rectangular area in the chip.

[0240] In this embodiment, the chip space is better utilized through the reasonable arrangement and layout of the first transistor array 11, the second transistor array 12 and the first transformer structure. In the scenario where the transistor arrays are close and the transformer structure requires a larger inductance value, it is possible to avoid the transformer structure being separately wound and occupying additional space, thereby improving the overall integration of the chip.

[0241] In at least one embodiment, the RF power amplifier chip further includes a third transistor array, which is arranged on the second side in the first direction;

[0242] A fourth transistor array is arranged at a second side of the first virtual rectangular area in the second direction;

[0243] The second transformer structure is arranged on the first side of the first virtual rectangular area in the second direction and the first side of the first virtual rectangular area in the first direction, and includes a second primary coil and a second secondary coil coupled to each other, a first end of the second primary coil is connected to the third transistor array, and a second end of the second primary coil is connected to the fourth transistor array.

[0244] It can be understood that the second transformer structure can be implemented by the second power synthesis unit 40 in any of the above embodiments, which will not be described in detail here.

[0245] At least one embodiment of the present invention provides a radio frequency front-end module, including a radio frequency power amplifier chip as described in any of the above embodiments / implementations.

[0246] At least one embodiment of the present invention provides a radio frequency front-end module, comprising a substrate and a radio frequency power amplifier chip arranged on the substrate, wherein the radio frequency power amplifier chip comprises a first transistor array, a second transistor array, a third transistor array, and a fourth transistor array, which are distributed in four areas, namely, a first side of the radio frequency power amplifier chip in a first direction, a second side of the radio frequency power amplifier chip in the first direction, a first side of the radio frequency power amplifier chip in the second direction, and a second side of the radio frequency power amplifier chip in the second direction, wherein the first direction intersects with the second direction;

[0247] The RF front-end module also includes a first transformer structure and a second transformer structure arranged on a substrate, and the first transformer structure and the second transformer structure are arranged around the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0248] It can be understood that the specific composition of the first transformer structure in this embodiment can be implemented by the first synthesis unit in any of the above embodiments / implementations, except that the first transformer structure is arranged on a substrate. The specific composition of the second transformer structure in this embodiment can be implemented by the second synthesis unit in any of the above embodiments / implementations, except that the second transformer structure is arranged on a substrate.

[0249] At least one embodiment of the present invention provides an electronic device, including a radio frequency front-end module as described in any of the above embodiments / implementations.

[0250] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present application. These improvements and substitutions should also be regarded as the scope of protection of the present application.

Claims

1. A radio frequency power amplifier chip, characterized in that: include: A first transistor array is arranged on a first side in a first direction; A second transistor array is arranged on a first side in a second direction, wherein the first direction intersects with the second direction; A first power synthesis unit, disposed on the second side in the first direction and the second side in the second direction, and configured to perform power synthesis on output signals of the first transistor array and the second transistor array; A third transistor array is arranged on the second side in the first direction; A fourth transistor array is arranged on the second side in the second direction; A second power synthesis unit is disposed on the first side in the second direction and the first side in the first direction, and is configured to perform power synthesis on output signals of the third transistor array and the fourth transistor array.

2. The RF power amplifier chip according to claim 1, characterized in that: The first transistor array is closer to the second side in the first direction than the second power synthesis unit is arranged on the first side in the first direction, and the second transistor array is closer to the second side in the second direction than the second power synthesis unit is arranged on the first side in the second direction; and / or, The third transistor array is closer to the first side in the first direction relative to a portion of the first power synthesis unit disposed on the second side in the first direction, and the fourth transistor array is closer to the first side in the second direction relative to a portion of the first power synthesis unit disposed on the second side in the second direction.

3. The RF power amplifier chip according to claim 1, characterized in that: The first direction is perpendicular to the second direction.

4. The radio frequency power amplifier chip according to claim 1, characterized in that: The first power synthesis unit and the second power synthesis unit are arranged outside the radio frequency power amplifier chip.

5. The radio frequency power amplifier chip according to claim 1, characterized in that: The portion of the second power synthesis unit disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array, the portion of the second power synthesis unit disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array, the third transistor array is closer to the first side in the first direction relative to the portion of the first power synthesis unit disposed on the second side in the first direction, and the fourth transistor array is closer to the first side in the second direction relative to the portion of the first power synthesis unit disposed on the second side in the second direction; or, The portion of the first power synthesis unit arranged on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array, the portion of the first power synthesis unit arranged on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array, the first transistor array is closer to the second side in the first direction relative to the portion of the second power synthesis unit arranged on the first side in the first direction, and the second transistor array is closer to the second side in the second direction relative to the portion of the second power synthesis unit arranged on the first side in the second direction.

6. The radio frequency power amplifier chip according to claim 1, characterized in that: The first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first primary sub-coil and a second primary sub-coil, and the first secondary coil includes a first secondary sub-coil and a second secondary sub-coil; the first primary sub-coil and the first secondary sub-coil are coupled to each other and are arranged on the second side in the first direction; the second primary sub-coil and the second secondary sub-coil are coupled to each other and are arranged on the second side in the second direction; The second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a third primary sub-coil and a fourth primary sub-coil, the second secondary coil includes a third secondary sub-coil and a fourth secondary sub-coil; the third primary sub-coil and the third secondary sub-coil are coupled to each other and are arranged on the first side in the first direction; the fourth primary sub-coil and the fourth secondary sub-coil are coupled to each other and are arranged on the first side in the second direction.

7. The radio frequency power amplifier chip according to claim 6, characterized in that: The first secondary sub-coil is closer to the first side in the first direction relative to the first primary sub-coil, the second secondary sub-coil is closer to the first side in the second direction relative to the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction relative to the third secondary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction relative to the fourth secondary sub-coil; or, The first primary sub-coil is closer to the first side in the first direction relative to the first secondary sub-coil, the second primary sub-coil is closer to the first side in the second direction relative to the second secondary sub-coil, the third secondary sub-coil is closer to the second side in the first direction relative to the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction relative to the fourth primary sub-coil.

8. The radio frequency power amplifier chip according to claim 1, characterized in that: The first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil includes a first outer primary coil and a first inner primary coil, the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil includes a second outer primary coil and a second inner primary coil, the first secondary coil includes a first partial secondary coil arranged between the first outer primary coil and the first inner primary coil, and a second partial secondary coil arranged between the second outer primary coil and the second inner primary coil, the first partial secondary coil and the second partial secondary coil are connected in series.

9. The radio frequency power amplifier chip according to claim 8, characterized in that: The first secondary coil also includes a third partial secondary coil arranged inside the first primary coil, and the second secondary coil also includes a fourth partial secondary coil arranged inside the second primary coil. The first partial secondary coil, the third partial secondary coil, the second partial secondary coil and the fourth partial secondary coil are connected in series in sequence.

10. The radio frequency power amplifier chip according to claim 1, characterized in that: The first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, and the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other; The first secondary coil includes a first portion of the secondary coil arranged on the first metal layer of the RF power amplifier chip and a second portion of the secondary coil arranged on the second metal layer of the RF power amplifier chip, and the second secondary coil includes a third portion of the secondary coil arranged on the first metal layer of the RF power amplifier chip and a fourth portion of the secondary coil arranged on the second metal layer of the RF power amplifier chip; One end of the first secondary coil is configured to be connected to the signal output terminal, one end of the third secondary coil is configured to be grounded, and the first secondary coil is connected in series with the third secondary coil; one end of the second secondary coil is configured to be connected to the signal output terminal, one end of the fourth secondary coil is configured to be grounded, and the second secondary coil is connected in series with the fourth secondary coil; The coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer; or, the coil from one end of the first part of the secondary coil connected to the signal output terminal to one end of the third part of the secondary coil configured as grounded is wound in a first manner from the inner layer to the outer layer, and the coil from one end of the second part of the secondary coil connected to the signal output terminal to one end of the fourth part of the secondary coil configured as grounded is wound in a first manner from the outer layer to the inner layer, and the first manner is a clockwise manner or a counterclockwise manner.

11. The radio frequency power amplifier chip according to claim 1, characterized in that: The first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, and the second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other; The first primary coil includes a first portion of the primary coil disposed on a first metal layer of the RF power amplifier chip and a second portion of the primary coil disposed on a second metal layer of the RF power amplifier chip, wherein the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled; The second primary coil includes a third primary coil arranged on the first metal layer of the RF power amplifier chip and a fourth primary coil arranged on the second metal layer of the RF power amplifier chip, and the third primary coil and the fourth primary coil are longitudinally coupled.

12. The radio frequency power amplifier chip according to claim 1, characterized in that: It also includes a front-stage driving circuit, which is arranged in a region surrounded by the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

13. The radio frequency power amplifier chip according to claim 1, characterized in that: It also includes a passive component network, which is arranged in an area surrounded by the first power synthesis unit and the second power synthesis unit.

14. The radio frequency power amplifier chip according to claim 13, characterized in that: The passive component network includes a first passive component unit and a second passive component unit. The first passive component unit is arranged in a region between the first transistor array, the second transistor array and the second power synthesis unit. The second passive component unit is arranged in a region between the third transistor array, the fourth transistor array and the first power synthesis unit.

15. The radio frequency power amplifier chip according to claim 1, characterized in that: The first power synthesis unit includes a first primary coil and a first secondary coil coupled to each other, a first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array; The second power synthesis unit includes a second primary coil and a second secondary coil coupled to each other, a first end of the second primary coil is connected to the third transistor array, and a second end of the second primary coil is connected to the fourth transistor array.

16. The radio frequency power amplifier chip according to claim 1, characterized in that: The first end of the first secondary coil is configured to be connected to the signal output end, the second end of the first secondary coil is connected to the first end of the second secondary coil, and the second end of the second secondary coil is configured to be grounded; or, The first end of the first secondary coil and the second end of the second secondary coil are configured to be connected to a signal output terminal, and the second end of the first secondary coil and the first end of the second secondary coil are configured to be grounded.

17. The radio frequency power amplifier chip according to claim 1, characterized in that: The first transistor array, the second transistor array and the first power synthesis unit are configured to achieve power amplification of differential radio frequency signals, and the third transistor array, the fourth transistor array and the second power synthesis unit are configured to achieve power amplification of differential radio frequency signals.

18. The radio frequency power amplifier chip according to claim 4, characterized in that: The first power synthesis unit and the second power synthesis unit are at least partially disposed in a contact metal layer of the chip, and the contact metal layer is disposed adjacent to a substrate of the chip.

19. A radio frequency power amplifier chip, characterized in that: include: The first transistor array, the second transistor array, the third transistor array and the fourth transistor array are distributed in four regions: a first side in the first direction, a second side in the first direction, a first side in the second direction and a second side in the second direction, and the first direction and the second direction intersect; A first power synthesis unit, disposed on the second side in the first direction and the second side in the second direction, configured to perform power synthesis on two transistor arrays among the first transistor array, the second transistor array, the third transistor array and the fourth transistor array; A second power synthesis unit, which is arranged on the first side in the second direction and the first side in the first direction is arranged on the outside of the chip, is configured to perform power synthesis on the other two transistor arrays of the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

20. The radio frequency power amplifier chip according to claim 19, characterized in that: The first power synthesis unit is configured to perform power synthesis on the output signals of the first transistor array and the second transistor array, and the second power synthesis unit is configured to perform power synthesis on the output signals of the third transistor array and the fourth transistor array; The first transistor array, the second transistor array and the first power synthesis unit are configured to amplify radio frequency signals of a first frequency band, and the third transistor array, the fourth transistor array and the second power synthesis unit are configured to amplify radio frequency signals of a second frequency band.

21. A radio frequency power amplifier chip, characterized in that: include: A first transistor array is arranged on a first side of a first virtual rectangular region in a first direction; A second transistor array is arranged at a first side of the first virtual rectangular area in a second direction, wherein the first direction intersects with the second direction; A first transformer structure is arranged on a second side of the first virtual rectangular area in the first direction and on a second side of the first virtual rectangular area in the second direction, and includes a first primary coil and a first secondary coil coupled to each other, a first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array.

22. The radio frequency power amplifier chip according to claim 21, characterized in that: Also includes: A third transistor array is arranged on the second side in the first direction; A fourth transistor array is arranged at a second side of the first virtual rectangular area in the second direction; The second transformer structure is arranged on the first side of the first virtual rectangular area in the second direction and the first side of the first virtual rectangular area in the first direction, and includes a second primary coil and a second secondary coil coupled to each other, a first end of the second primary coil is connected to the third transistor array, and a second end of the second primary coil is connected to the fourth transistor array.

23. A radio frequency front-end module, characterized in that: Comprising a radio frequency power amplifier chip as described in any one of claims 1-22.

24. An electronic device, characterized in that: Comprising the RF front-end module as described in claim 23.

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