High-precision grid voltage bootstrapped switch
By adding auxiliary capacitor branches to the gate voltage bootstrap switching circuit of the analog circuit and quickly charging the gate of the MOS tube, the problems of slow signal establishment speed and low sampling accuracy of traditional circuits are solved, and higher signal establishment speed and sampling accuracy are achieved.
Patent Information
- Application Number
- CN202510097609.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-09
AI Technical Summary
In analog circuit design, traditional gate voltage bootstrap switching circuits have slow signal establishment speed and low sampling accuracy due to the influence of parasitic capacitance.
By adding an auxiliary capacitor branch to a traditional gate voltage bootstrap switching circuit, it is used to quickly charge the gate of the MOS tube, reducing the equivalent capacitance at the gate node, thereby increasing the signal establishment speed.
It improves the signal establishment speed and sampling accuracy of the circuit, and reduces the capacitance parasitic effects and noise of the circuit.
Smart Images
Figure CN119966392A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of analog switch circuits and relates to a high-precision gate voltage bootstrap switch. Background Art
[0002] In analog circuit design, the sample-and-hold circuit is often located at the forefront of the overall circuit and is used to sample the input signal of the circuit. It is widely used in signal chain circuit design and analog-to-digital converter circuit design. A single MOS tube can also be used as the simplest sampling switch, but both PMOS and NMOS have a unique voltage operating range, which causes the on-resistance to change when transmitting signals of different voltage values, which greatly affects the performance and accuracy of the switching circuit. In order to solve the above problems, high-precision circuit design often uses a gate voltage bootstrap switch as a switching circuit. The gate voltage bootstrap switch uses a capacitor to keep the voltage difference between the gate and source of the MOS tube unchanged during the entire sampling phase, thereby effectively optimizing the linearity of the circuit.
[0003] In a conventional gate voltage bootstrap switch circuit, the gate node of the switch tube is connected to other branches and the substrate of other MOS tubes, and its gate will be affected by the parasitic capacitance from other branches and the substrate of other MOS tubes, causing the gate and source of the switch tube to produce a changing voltage difference during the sampling phase, reducing the linearity of the circuit when transmitting signals. In addition, the charging speed of the circuit node will also affect the speed of opening and closing the switch tube, thereby affecting the response speed of the overall circuit and the sampling capability of the input signal change, and further affecting the accuracy of the overall circuit.
[0004] In summary, in order to improve the signal establishment speed and sampling accuracy of the gate voltage bootstrap switch, a certain degree of improvement must be made. By improving the circuit structure, the accuracy and signal establishment speed of the gate voltage bootstrap switch can be improved. Summary of the invention
[0005] The object of the present invention is to provide a high-precision gate voltage bootstrap switch, which has the characteristics of fast signal establishment speed and high sampling accuracy.
[0006] The technical solution adopted by the present invention is to include a first charging module and a second charging module, wherein one end of the first charging module is connected to a power source and the other end is grounded, the first charging module is connected to a signal transmission module, the signal transmission module is connected to a switch tube, and the switch tube is an N-type MOS tube, a branch at one end of the first charging module connected to the power source is connected to a first discharge module, and the signal transmission module is connected to a control module; One end of the second charging module is connected to the power supply and the other end is grounded. A second discharge module is connected to the branch at one end of the first charging module connected to the power supply. The second charging module is connected to an auxiliary module, which is respectively connected to the signal transmission module and the control module.
[0007] The present invention is also characterized in that: The first charging module includes a fourth MOS tube, a capacitor and a third MOS tube connected in series from the power supply to the ground end, the source of the fourth MOS tube is connected to the power supply, the drain is connected to the capacitor, and the gate is connected to the first discharging module, the source of the third MOS tube is grounded, the drain is connected to the capacitor, and the gate is connected to the reverse clock signal circuit; The second charging module includes a twelfth MOS tube, a capacitor group and a tenth MOS tube connected in series from the power supply to the ground end, the source of the twelfth MOS tube is connected to the power supply, the drain is connected to the capacitor group, and the gate is connected to the second discharging module, the source of the tenth MOS tube is grounded, the drain is connected to the capacitor group, and the gate is connected to the reverse clock signal circuit; The node between the tenth MOS tube and the capacitor group is connected to the node between the capacitor and the third MOS tube; The twelfth MOS tube and the fourth MOS tube are P-type MOS tubes, and the tenth MOS tube and the third MOS tube are N-type MOS tubes.
[0008] The first discharge module includes a fifth MOS tube and a sixth MOS tube connected to the gate of the fourth MOS tube in sequence, the drain of the fifth MOS tube is connected to the gate of the fourth MOS tube, the source of the fifth MOS tube is connected to the drain of the sixth MOS tube, and the source of the sixth MOS tube is grounded, the gate of the fifth MOS tube is connected to the power supply, and the gate of the sixth MOS tube is connected to the reverse clock signal circuit; The second discharge module includes a thirteenth MOS tube and a fourteenth MOS tube connected to the gate of the twelfth MOS tube in sequence, the drain of the thirteenth MOS tube is connected to the gate of the twelfth MOS tube, the source of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube, and the source of the fourteenth MOS tube is grounded, the gate of the thirteenth MOS tube is connected to the power supply, and the gate of the fourteenth MOS tube is connected to the reverse clock signal circuit; The fifth MOS tube, the sixth MOS tube, the fourteenth MOS tube and the thirteenth MOS tube are all N-type MOS tubes.
[0009] The signal transmission module includes a seventh MOS tube connected to a branch between the fourth MOS tube and the capacitor, and the source of the seventh MOS tube is connected to the branch, the drain of the seventh MOS tube is connected to the gate of the switch tube, and the connection line is connected to the branch between the fourth MOS tube and the fifth MOS tube through the branch, and the gate of the seventh MOS tube is connected to the control module, the node between the capacitor and the third MOS tube is also connected to the second MOS tube, and the source of the second MOS tube is connected to the node, the drain of the second MOS tube is connected to the source of the switch tube, and the gate of the second MOS tube is connected to the auxiliary module; The auxiliary module includes an eleventh MOS tube connected to a branch between the twelfth MOS tube and the capacitor group, and the source of the eleventh MOS tube is connected to the branch, the drain of the eleventh MOS tube is connected to the gate of the second MOS tube, and the connection line is connected to the branch between the thirteenth MOS tube and the twelfth MOS tube through the branch, and the gate of the eleventh MOS tube is connected to the control module; The second MOS tube is an N-type MOS tube, and the seventh MOS tube and the eleventh MOS tube are both P-type MOS tubes.
[0010] The control module includes a ninth MOS tube and an eighth MOS tube which are sequentially connected to a branch between the capacitor and the third MOS tube, the drain of the ninth MOS tube is connected to the drain of the eighth MOS tube, and the gates of the eleventh MOS tube and the seventh MOS tube are respectively connected to the line through a branch, the source of the eighth MOS tube is connected to a power supply, and the gates of the ninth MOS tube and the eighth MOS tube are both connected to a clock signal circuit; The ninth MOS tube is an N-type MOS tube, and the eighth MOS tube is a P-type MOS tube.
[0011] The substrates of the fourth MOS tube, the seventh MOS tube, the eleventh MOS tube and the twelfth MOS tube are connected to each other, and the connecting line is connected to the line between the twelfth MOS tube and the capacitor group.
[0012] One side of the switch tube close to the second MOS tube is connected to the input interface in the circuit, and the other end is connected to the output interface.
[0013] The capacitor bank is composed of several capacitors connected in parallel.
[0014] The beneficial effects of the present invention are: The present invention adds an auxiliary capacitor branch on the basis of the traditional gate voltage bootstrap switch, which is used to quickly charge the gate of the MOS tube. The added auxiliary branch connects other branches at the gate node of the switch tube of the gate voltage bootstrap switch to the auxiliary capacitor branch, so that the equivalent capacitance at the gate node of the switch tube of the gate voltage bootstrap switch is reduced, thereby improving the signal establishment speed of the circuit. By introducing additional capacitors to quickly charge the key nodes of the circuit, the signal establishment speed of the circuit is improved. By connecting the substrate of individual MOS tubes on the main signal path to the auxiliary capacitor branch, the capacitance parasitic effect of the substrate of the MOS tube on the main signal path of the circuit is reduced, and the capacitance parasitic effect and noise of the circuit are reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a schematic diagram of the module structure of the high-precision gate voltage bootstrap switch of the present invention; Figure 2 It is a schematic diagram of the circuit structure of the high-precision gate voltage bootstrap switch of the present invention.
[0016] In the figure: 1. switch tube; 2. second MOS tube; 3. third MOS tube; 4. fourth MOS tube; 5. fifth MOS tube; 6. sixth MOS tube; 7. seventh MOS tube; 8. eighth MOS tube; 9. ninth MOS tube; 10. tenth MOS tube; 11. eleventh MOS tube; 12. twelfth MOS tube; 13. thirteenth MOS tube; 14. fourteenth MOS tube; 15. capacitor; 16. capacitor group; 17. first charging module; 18. second charging module; 19. signal transmission module; 20. first discharge module; 21. control module; 22. second discharge module; 23. auxiliary module. DETAILED DESCRIPTION
[0017] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
[0018] Embodiment 1: like Figure 1 As shown, it includes a first charging module 17 and a second charging module 18. One end of the first charging module 17 is connected to the power supply and the other end is grounded. The first charging module 17 is connected to the signal transmission module 19. The signal transmission module 19 is connected to a switch tube 1. The switch tube 1 is an N-type MOS tube. A first discharge module 20 is connected to the branch at one end of the first charging module 17 connected to the power supply. The signal transmission module 19 is connected to a control module 21. One end of the second charging module 18 is connected to the power supply and the other end is grounded. The second discharging module 22 is connected to the branch at one end of the first charging module 17 connected to the power supply. The second charging module 18 is connected to the auxiliary module 23, and the auxiliary module 23 is respectively connected to the signal transmission module 19 and the control module 21.
[0019] The operation of the signal transmission module 19 is adjusted by the second charging module 18 and the control module 21 so as to control the operation of the switch tube 1 in the holding stage and the sampling stage to complete the signal sampling work.
[0020] Embodiment 2: Based on Example 1: like Figure 1 and Figure 2 As shown, the first charging module 17 includes a fourth MOS tube 4, a capacitor 15 and a third MOS tube 3 connected in series from the power supply to the ground end, the source of the fourth MOS tube 4 is connected to the power supply, the drain is connected to the capacitor 15, and the gate is connected to the first discharge module 20, the source of the third MOS tube 3 is grounded, the drain is connected to the capacitor 15, and the gate is connected to the reverse clock signal circuit; The second charging module 18 includes a twelfth MOS transistor 12, a capacitor group 16 and a tenth MOS transistor 10 connected in series from the power supply to the ground end. The source of the twelfth MOS transistor 12 is connected to the power supply, the drain is connected to the capacitor group 16, and the gate is connected to the second discharging module 22. The source of the tenth MOS transistor 10 is grounded, the drain is connected to the capacitor group 16, and the gate is connected to the reverse clock signal circuit. The node between the tenth MOS transistor 10 and the capacitor group 16 is connected to the node between the capacitor 15 and the third MOS transistor 3; The twelfth MOS transistor 12 and the fourth MOS transistor 4 are P-type MOS transistors, and the tenth MOS transistor 10 and the third MOS transistor 3 are N-type MOS transistors.
[0021] In the first charging module 17 , the fourth MOS transistor 4 and the third MOS transistor 3 respectively control the connection between the two ends of the capacitor 15 and the power supply and the ground terminal through their own conduction, so as to realize the charging and discharging of the capacitor 15 .
[0022] In the second charging module 18 , the twelfth MOS transistor 12 and the tenth MOS transistor 10 respectively control the connection between the two ends of the capacitor group 16 and the power supply and the ground terminal through their own conduction, so as to realize the charging and discharging of the capacitor group 16 .
[0023] The twelfth MOS tube 12 and the fourth MOS tube 4 are controlled to be turned on by the second discharge module 22 and the first discharge module 20 respectively, and the gates of the third MOS tube 3 and the tenth MOS tube 10 are connected to the reverse clock circuit in the circuit to periodically control the opening and closing of the two MOS tubes.
[0024] The signal of the clock circuit CLK is high in the sampling phase and low in the holding phase. The reverse clock circuit is the opposite, with the signal being low in the sampling phase and high in the holding phase.
[0025] Embodiment three: Based on the second embodiment: like Figure 1 and Figure 2 As shown, the first discharge module 20 includes a fifth MOS tube 5 and a sixth MOS tube 6 which are sequentially connected to the gate of the fourth MOS tube 4, the drain of the fifth MOS tube 5 is connected to the gate of the fourth MOS tube 4, the source of the fifth MOS tube 5 is connected to the drain of the sixth MOS tube 6, and the source of the sixth MOS tube 6 is grounded, the gate of the fifth MOS tube 5 is connected to the power supply, and the gate of the sixth MOS tube 6 is connected to the reverse clock signal circuit; The second discharge module 22 includes a thirteenth MOS tube 13 and a fourteenth MOS tube 14 which are sequentially connected to the gate of the twelfth MOS tube 12, the drain of the thirteenth MOS tube 13 is connected to the gate of the twelfth MOS tube 12, the source of the thirteenth MOS tube 13 is connected to the drain of the fourteenth MOS tube 14, and the source of the fourteenth MOS tube 14 is grounded, the gate of the thirteenth MOS tube 13 is connected to the power supply, and the gate of the fourteenth MOS tube 14 is connected to the reverse clock signal circuit; The fifth MOS transistor 5 , the sixth MOS transistor 6 , the fourteenth MOS transistor 14 and the thirteenth MOS transistor 13 are all N-type MOS transistors.
[0026] The gates of the sixth MOS tube 6 and the fourteenth MOS tube 14 are both connected to a clock signal circuit. Contrary to the reverse clock signal circuit cycle, the opening and closing of the twelfth MOS tube 12 and the fourth MOS tube 4 are controlled by adjusting the opening and closing of the sixth MOS tube 6 and the fourteenth MOS tube 14. The gates of the thirteenth MOS tube 13 and the fifth MOS tube 5 are both connected to the power supply and maintained in a normally open state, thereby protecting the sixth MOS tube 6 and the fourteenth MOS tube 14 from being broken down by the source-drain voltage.
[0027] Embodiment 4: Based on Example 3: like Figure 1 and Figure 2 As shown, the signal transmission module 19 includes a seventh MOS tube 7 connected to the branch between the fourth MOS tube 4 and the capacitor 15, and the source of the seventh MOS tube 7 is connected to the branch, the drain of the seventh MOS tube 7 is connected to the gate of the switch tube 1, and the connection line is connected to the branch between the fourth MOS tube 4 and the fifth MOS tube 5 through the branch, and the gate of the seventh MOS tube 7 is connected to the control module 21, the node between the capacitor 15 and the third MOS tube 3 is also connected to the second MOS tube 2, and the source of the second MOS tube 2 is connected to the node, the drain of the second MOS tube 2 is connected to the source of the switch tube 1, and the gate of the second MOS tube 2 is connected to the auxiliary module 23; The auxiliary module 23 includes an eleventh MOS transistor 11 connected to a branch between the twelfth MOS transistor 12 and the capacitor group 16, and the source of the eleventh MOS transistor 11 is connected to the branch, the drain of the eleventh MOS transistor 11 is connected to the gate of the second MOS transistor 2, and the connection line is connected to the branch between the thirteenth MOS transistor 13 and the twelfth MOS transistor 12 through the branch, and the gate of the eleventh MOS transistor 11 is connected to the control module 21; The second MOS transistor 2 is an N-type MOS transistor, and the seventh MOS transistor 7 and the eleventh MOS transistor 11 are both P-type MOS transistors.
[0028] The operation of the seventh MOS tube 7 and the eleventh MOS tube 11 are controlled by the control module 21, and they are turned off in the holding stage and turned on in the sampling stage. When the two MOS tubes are turned on, the seventh MOS tube 7 transmits the signal of the upper plate of the capacitor 15 to the switch tube 1 to control its conduction. When the switch tube 1 is turned on, the signal is transmitted from VIN to VOUT to achieve signal sampling. When the switch tube 1 is turned off, the VOUT signal remains as the VIN signal at the moment before the switch tube 1 is turned off, so as to achieve signal retention. The eleventh MOS tube 11 transmits the signal of the upper plate of the capacitor group 16 to the gate of the second MOS tube 2 to control its conduction.
[0029] In the sampling stage, the second MOS tube 2 transmits the VIN signal to the lower plate of the capacitor 15 and the capacitor group 16, increasing the voltage of the lower plate. Due to the principle of charge conservation, the voltage of the upper plate of the capacitor 15 and the capacitor group 16 increases accordingly, making the gate and source voltage difference of the first MOS tube a constant value.
[0030] Since the other branches at the gate node of the switch tube 1 are connected to the auxiliary branch, the parasitic capacitance originally equivalent to its gate is equivalent to the auxiliary branch, so that the equivalent capacitance at the gate node of the switch tube 1 is reduced, thereby improving the signal establishment speed of the circuit.
[0031] Embodiment five: Based on the fourth embodiment: like Figure 1 and Figure 2 As shown, the control module 21 includes a ninth MOS tube 9 and an eighth MOS tube 8 which are sequentially connected to the branch between the capacitor 15 and the third MOS tube 3, the drain of the ninth MOS tube 9 is connected to the drain of the eighth MOS tube 8, and the line is respectively connected to the gates of the eleventh MOS tube 11 and the seventh MOS tube 7 through branches, the source of the eighth MOS tube 8 is connected to the power supply, and the gates of the ninth MOS tube 9 and the eighth MOS tube 8 are both connected to the clock signal circuit; The ninth MOS tube 9 is an N-type MOS tube, and the eighth MOS tube 8 is a P-type MOS tube.
[0032] In the sampling stage, the signal of the clock signal CLK is low, the eighth MOS tube 8 is turned on, the ninth MOS tube 9 is turned off, and the voltage of the power supply is transmitted to the eleventh MOS tube 11 and the seventh MOS tube 7 through the eighth MOS tube 8, so that they remain in the off state. In the holding stage, the signal of the clock signal CLK is high, the eighth MOS tube 8 is turned off, the ninth MOS tube 9 is turned on, and the gate voltages of the eleventh MOS tube 11 and the seventh MOS tube 7 are reduced and switched to the on state.
[0033] Embodiment six: Based on Example 5: like Figure 1 and Figure 2As shown, the substrates of the fourth MOS transistor 4 , the seventh MOS transistor 7 , the eleventh MOS transistor 11 and the twelfth MOS transistor 12 are connected to each other, and the connection line is connected to the line between the twelfth MOS transistor 12 and the capacitor group 16 .
[0034] One side of the switch tube 1 close to the second MOS tube 2 is connected to the input interface in the circuit, and the other end is connected to the output interface.
[0035] The capacitor group 16 is composed of a plurality of capacitors connected in parallel.
[0036] Since there are parasitic capacitors at the substrate end of the MOS tube, when charging the circuit node, the parasitic capacitors at the substrate end will also be charged, which interferes with the gate voltage of the switch tube 1, thereby causing the voltage difference between the source and the gate of the switch tube 1 to be unstable, causing non-ideal effects and noise in the circuit. By connecting the substrates of multiple MOS tubes to the auxiliary capacitor branch, the parasitic influence of the substrate of the MOS tube on the main path of the circuit signal is reduced, and the capacitance parasitic effect and noise of the circuit are reduced.
[0037] The present invention quickly charges the key nodes of the traditional gate voltage bootstrap switch circuit by setting up an auxiliary circuit, thereby improving the signal establishment speed of the circuit. At the same time, by connecting the substrate of the MOS tube to the auxiliary branch, the parasitic influence of the MOS tube substrate on the main path of the circuit signal is avoided, the capacitance parasitic effect and noise of the circuit are reduced, and higher sampling accuracy and signal establishment speed are achieved.
[0038] Working principle: Holding phase: The clock signal CLK is low, and the reverse clock signal CLKB is high. Under the action of the reverse clock signal CLKB, the third MOS transistor 3, the sixth MOS transistor 6, the tenth MOS transistor 10 and the fourteenth MOS transistor 14 are in a connected state, and under the action of the clock signal CLK, the eighth MOS transistor 8 is in a connected state, and the ninth MOS transistor 9 is in a disconnected state.
[0039] At this time, since the fifth MOS tube 5 and the thirteenth MOS tube 13 are normally open, the gates of the fourth MOS tube 4 and the twelfth MOS tube 12 are grounded, and the voltage is low, which is a connected state. The upper and lower plates of the capacitor 15 and the capacitor group 16 are respectively connected to the power supply VDD and the ground terminal, and the potential difference is VDD and remains constant. The eighth MOS tube 8 transmits the voltage of the power supply to the eleventh MOS tube 11 and the seventh MOS tube 7, so that they remain in a disconnected state. At this time, since the eleventh MOS tube 11 and the seventh MOS tube 7 are disconnected, the gates of the second MOS tube 2 and the switch tube 1 have no input voltage and remain in a disconnected state.
[0040] Sampling phase: The clock signal CLK is high, and the reverse clock signal CLKB is low. Under the action of the reverse clock signal CLKB, the third MOS transistor 3, the sixth MOS transistor 6, the tenth MOS transistor 10 and the fourteenth MOS transistor 14 are in a disconnected state, and under the action of the clock signal CLK, the eighth MOS transistor 8 is in a disconnected state, and the ninth MOS transistor 9 is in a connected state.
[0041] At this time, the ninth MOS tube 9 connects the lower plate of the capacitor 15 with the eleventh MOS tube 11 and the seventh MOS tube 7, so that they are changed to a connected state. The capacitor group 16 charges the node B in the circuit through the eleventh MOS tube 11, the second MOS tube 2 is connected, and the current closes the twelfth MOS tube 12 through the branch; the capacitor 15 charges the node A in the circuit through the seventh MOS tube 7, the switch tube 1 is connected, and the current closes the twelfth MOS tube 12 through the branch. At this time, the lower plates of the capacitor 15 and the capacitor group 16 are connected to VIN through the second MOS tube 2, and the lower plates are charged to the VIN potential. According to the charge conservation principle, the potential difference between the upper plate and the lower plate is always VDD, so the potential of the upper plate is increased to VIN+VDD, and the circuit nodes A and circuit nodes B are charged to the VIN+VDD potential. At this time, the voltage difference between the gate and the source of the switch tube 1 is VDD and remains constant, so that the switch tube 1 maintains a constant conduction potential during signal transmission.
Claims
1. High-precision gate voltage bootstrap switch, characterized in that: The device comprises a first charging module (17) and a second charging module (18), wherein one end of the first charging module (17) is connected to a power source and the other end is grounded, the first charging module (17) is connected to a signal transmission module (19), the signal transmission module (19) is connected to a switch tube (1), the switch tube (1) is an N-type MOS tube, a first discharge module (20) is connected to a branch at one end of the first charging module (17) connected to the power source, and the signal transmission module (19) is connected to a control module (21); One end of the second charging module (18) is connected to a power source, and the other end is grounded; a second discharge module (22) is connected to a branch at one end of the first charging module (17) connected to the power source; the second charging module (18) is connected to an auxiliary module (23); and the auxiliary module (23) is respectively connected to the signal transmission module (19) and the control module (21).
2. The high-precision gate voltage bootstrap switch according to claim 1, characterized in that: The first charging module (17) comprises a fourth MOS tube (4), a capacitor (15) and a third MOS tube (3) which are connected in series in sequence from the power supply to the ground end, the source of the fourth MOS tube (4) being connected to the power supply, the drain being connected to the capacitor (15), and the gate being connected to the first discharging module (20), the source of the third MOS tube (3) being connected to the ground, the drain being connected to the capacitor (15), and the gate being connected to a reverse clock signal circuit; The second charging module (18) comprises a twelfth MOS tube (12), a capacitor group (16) and a tenth MOS tube (10) which are connected in series in sequence from the power supply to the ground end, the source of the twelfth MOS tube (12) being connected to the power supply, the drain being connected to the capacitor group (16), and the gate being connected to the second discharging module (22), the source of the tenth MOS tube (10) being connected to the ground, the drain being connected to the capacitor group (16), and the gate being connected to a reverse clock signal circuit; The node between the tenth MOS tube (10) and the capacitor group (16) is connected to the node between the capacitor (15) and the third MOS tube (3); The twelfth MOS tube (12) and the fourth MOS tube (4) are P-type MOS tubes, and the tenth MOS tube (10) and the third MOS tube (3) are N-type MOS tubes.
3. The high-precision gate voltage bootstrap switch according to claim 2, characterized in that: The first discharge module (20) comprises a fifth MOS tube (5) and a sixth MOS tube (6) which are sequentially connected to the gate of the fourth MOS tube (4); the drain of the fifth MOS tube (5) is connected to the gate of the fourth MOS tube (4); the source of the fifth MOS tube (5) is connected to the drain of the sixth MOS tube (6); the source of the sixth MOS tube (6) is grounded; the gate of the fifth MOS tube (5) is connected to a power supply; and the gate of the sixth MOS tube (6) is connected to a reverse clock signal circuit; The second discharge module (22) comprises a thirteenth MOS tube (13) and a fourteenth MOS tube (14) connected in sequence to the gate of the twelfth MOS tube (12); the drain of the thirteenth MOS tube (13) is connected to the gate of the twelfth MOS tube (12); the source of the thirteenth MOS tube (13) is connected to the drain of the fourteenth MOS tube (14); the source of the fourteenth MOS tube (14) is grounded; the gate of the thirteenth MOS tube (13) is connected to a power supply; and the gate of the fourteenth MOS tube (14) is connected to a reverse clock signal circuit; The fifth MOS tube (5), the sixth MOS tube (6), the fourteenth MOS tube (14) and the thirteenth MOS tube (13) are all N-type MOS tubes.
4. The high-precision gate voltage bootstrap switch according to claim 3, characterized in that: The signal transmission module (19) comprises a seventh MOS tube (7) connected to a branch between the fourth MOS tube (4) and the capacitor (15), and the source of the seventh MOS tube (7) is connected to the branch, the drain of the seventh MOS tube (7) is connected to the gate of the switch tube (1), and the connection line is connected to the branch between the fourth MOS tube (4) and the fifth MOS tube (5) through the branch, and the gate of the seventh MOS tube (7) is connected to the control module (21), the node between the capacitor (15) and the third MOS tube (3) is also connected to the second MOS tube (2), and the source of the second MOS tube (2) is connected to the node, the drain of the second MOS tube (2) is connected to the source of the switch tube (1), and the gate of the second MOS tube (2) is connected to the auxiliary module (23); The auxiliary module (23) comprises an eleventh MOS tube (11) connected to a branch between the twelfth MOS tube (12) and the capacitor group (16), the source of the eleventh MOS tube (11) being connected to the branch, the drain of the eleventh MOS tube (11) being connected to the gate of the second MOS tube (2), and the connecting line being connected to a branch between the thirteenth MOS tube (13) and the twelfth MOS tube (12) through a branch, and the gate of the eleventh MOS tube (11) being connected to the control module (21); The second MOS tube (2) is an N-type MOS tube, and the seventh MOS tube (7) and the eleventh MOS tube (11) are both P-type MOS tubes.
5. The high-precision gate voltage bootstrap switch according to claim 4, characterized in that: The control module (21) comprises a ninth MOS tube (9) and an eighth MOS tube (8) connected in sequence on a branch line between the capacitor (15) and the third MOS tube (3); the drain of the ninth MOS tube (9) is connected to the drain of the eighth MOS tube (8); the line is respectively connected to the gates of the eleventh MOS tube (11) and the seventh MOS tube (7) through a branch line; the source of the eighth MOS tube (8) is connected to a power supply; and the gates of the ninth MOS tube (9) and the eighth MOS tube (8) are both connected to a clock signal circuit; The ninth MOS tube (9) is an N-type MOS tube, and the eighth MOS tube (8) is a P-type MOS tube.
6. The high-precision gate voltage bootstrap switch according to claim 5, characterized in that: The substrates of the fourth MOS tube (4), the seventh MOS tube (7), the eleventh MOS tube (11) and the twelfth MOS tube (12) are connected to each other, and the connection line is connected to the line between the twelfth MOS tube (12) and the capacitor group (16).
7. The high-precision gate voltage bootstrap switch according to claim 6, characterized in that: The side of the switch tube (1) close to the second MOS tube (2) is connected to the input interface in the circuit, and the other end is connected to the output interface.
8. The high-precision gate voltage bootstrap switch according to claim 7, characterized in that: The capacitor group (16) is composed of a plurality of capacitors connected in parallel.