Multiplexer Switch Circuit of a Battery Management Chip

Abstract

The present invention relates to the technical field of battery management systems, and specifically provides a multiplexer switch circuit, a current mirror module, a control module one, a freewheeling module, and a control module two for a battery management chip. The current mirror module is used to mirror and copy the currents on the second PMOS transistor and the fourth PMOS transistor to the first PMOS transistor and the third PMOS transistor; the control module one is used to control the second control signal to turn on or off the second NMOS transistor; the freewheeling module is used to control the on / off states of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor by receiving the current inputs on the first PMOS transistor and the third PMOS transistor; the control module two is used to control the first control signal to quickly turn off the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor, and to clear the residual charges of the above MOS transistors; the switch module is used to turn on or off the path between the input voltage and the output voltage, including an input module and an output module. By utilizing the electrical characteristics of different MOS transistors, the present invention reduces the overall conduction loss while ensuring the current transmission efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management systems, and particularly to a multiplexer switch circuit of a battery management chip with low power consumption and high reliability. Background Art

[0002] With the increasing global emphasis on clean energy and sustainable development, electric vehicles (EVs), as an important alternative to traditional fuel vehicles, are experiencing rapid growth in market size and technological level. As one of the core components of electric vehicles, the battery management system (BMS) is directly related to the performance, safety, endurance, and service life of the battery pack. In the BMS, accurate measurement of the battery cell voltage is the basis for estimating the state of charge (SOC) and state of health (SOH) of the battery, and is also the key to realizing the battery equalization function.

[0003] However, in practical applications, measuring the battery cell voltage faces multiple technical challenges. Firstly, a large amount of electromagnetic interference is generated during the operation of electric vehicles, especially the high-frequency noise of the DC motor and inverter switching current. These interferences may be coupled into the measurement circuit through conduction or radiation, resulting in a decrease in voltage measurement accuracy. Secondly, the battery pack is usually composed of dozens or even hundreds of battery cells connected in series, and its total voltage can be as high as hundreds of volts, which poses extremely high requirements for the voltage withstand capacity and isolation performance of the measurement circuit. In addition, during the battery equalization process, the measurement circuit needs to frequently switch between different battery cells. Traditional switch circuits may cause measurement errors or even safety hazards due to residual charge or leakage current during switching.

[0004] Currently, multiplexer switch circuits on the market mainly use relays or solid-state switches (such as MOSFETs) to achieve channel switching. Although relays have a high voltage withstand capacity, they are large in size, slow in response speed, and have mechanical wear problems. While traditional MOSFET switch circuits have advantages in terms of speed and size, they are prone to performance degradation due to insufficient gate drive or leakage current problems in high-voltage environments. In addition, existing solutions also have deficiencies in anti-interference ability and redundant design, and are difficult to meet the high-reliability requirements under complex operating conditions of electric vehicles.

[0005] Therefore, there is an urgent need for a new type of multiplexer switch circuit that can achieve low-power, high-reliability channel switching in a high-voltage environment, and at the same time has fast response and anti-interference capabilities to improve the overall performance of the electric vehicle battery management system. Summary of the Invention

[0006] The present invention provides a multiplexer switch circuit for a battery management chip, which realizes low power consumption and high reliability of battery voltage shielding and transmission.

[0007] To achieve the object of the present invention, the present invention provides the following technical solution: A multiplexer switch circuit of a battery management chip, comprising,

[0008] A current mirror module for mirroring and copying the currents on the second PMOS transistor PM2 and the fourth PMOS transistor PM4 to the first PMOS transistor PM1 and the third PMOS transistor PM3;

[0009] A first control module for controlling the second control signal Sn to turn on or off the second NMOS transistor NM2, so as to control whether there is a current path on the second PMOS transistor PM2 and the fourth PMOS transistor PM4;

[0010] A freewheeling module for receiving the current inputs on the first PMOS transistor PM1 and the third PMOS transistor PM3, establishing a voltage across the first resistor R1, and controlling the on / off states of the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6;

[0011] A second control module for controlling the first control signal S’n to quickly turn off the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6, and to clear the residual charges of the above MOS transistors;

[0012] A switch module for turning on or off the path between the input voltage VCn and the output voltage Vo, and comprising an input module and an output module.

[0013] As a preferred technical solution of a multiplexer switch circuit of a battery management chip, the current mirror module and the freewheeling module include a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor PM4. The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to the total voltage VCP. The gate of the first PMOS transistor PM1 is connected to the gate of the second MOS transistor. The drain of the first PMOS transistor PM1 is connected to the source of the third PMOS transistor PM3. The drain of the second PMOS transistor PM2 is connected to its own gate and the source of the fourth PMOS transistor PM4 respectively. The gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4. The drain of the third PMOS transistor PM3 is connected to the source of the fifth PMOS transistor PM5 through the first resistor R1. The drain of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2.

[0014] As a preferred technical solution for the multiplexer switch circuit of a battery management chip, control module 2 includes a first NMOS tube NM1, a gate of the first NMOS tube NM1 is connected to a first control signal S'n, a drain of the first NMOS tube NM1 is connected to a gate of a third NMOS tube NM3, and a source of the first NMOS tube NM1 is connected to a source of the third NMOS tube NM3.

[0015] As a preferred technical solution for the multiplexer switch circuit of a battery management chip, the control module 1 includes a second NMOS tube NM2, a ninth NMOS tube NM9 and an eighth NMOS tube NM8, the gate of the second NMOS tube NM2 is connected to the second control signal Sn, the source of the second NMOS tube NM2 is connected to the drain of the ninth NMOS tube NM9; the drain of the eighth NMOS tube NM8 is connected to the drain of the third PMOS tube PM3, and the gate of the eighth NMOS tube NM8 is respectively connected to the control level V CTRL and the gate of the ninth NMOS tube NM9, the source of the eighth NMOS tube NM8 is connected to the ground, the drain of the ninth NMOS tube NM9 is connected to the second NMOS tube NM2, and the source of the ninth NMOS tube NM9 is connected to the ground.

[0016] As a preferred technical solution for the multiplexer switch circuit of a battery management chip, the input module includes a third NMOS tube NM3, a first TVS diode D1, a fifth NMOS tube NM5, a second capacitor C2, and a first capacitor C1. The drain of the third NMOS tube NM3 is connected to the input voltage VCn and is connected to the ground through the first TVS diode D1 and the first capacitor C1, respectively. The gate of the third NMOS tube NM3 is connected to the drain of the third PMOS tube PM3 and the gate of the fifth NMOS tube NM5. The source of the third NMOS tube NM3 is connected to the ground through the second capacitor C2 and the second resistor R2 and is connected to the source of the fourth NMOS tube NM4.

[0017] As a preferred technical solution for a multiplexer switch circuit of a battery management chip, the output module includes a fourth NMOS tube NM4 and a sixth NMOS tube NM6, the gate of the fourth NMOS tube NM4 is respectively connected to the drain of the third PMOS tube PM3 and the gate of the sixth NMOS tube NM6, the drain of the fourth NMOS tube NM4 is connected to the output voltage Vo, the drain of the fifth NMOS tube NM5 is connected to the drain of the third NMOS tube NM3, the source of the fifth NMOS tube NM5 is connected to the source of the third NMOS tube NM3, the source of the sixth NMOS tube NM6 is connected to the source of the fourth NMOS tube NM4, the drain of the sixth NMOS tube NM6 is connected to the drain of the fourth NMOS tube NM4, the gate of the fifth PMOS tube PM5 is connected to the source of the fourth NMOS tube NM4, and the drain of the fifth PMOS tube PM5 is connected to ground.

[0018] As an optimal technical solution for the multiplexer switch circuit of a battery management chip, the input voltage VCn is the input voltage of the circuit, which is the single cell voltage of any string of batteries, and the output voltage Vo is the output voltage of the circuit, which is the input of the subsequent level conversion module.

[0019] As a preferred technical solution for the multiplexer switch circuit of a battery management chip, the first control signal S'n and the second control signal Sn come from the same control signal and present opposite levels. When the first control signal S'n is at a high level, the second control signal Sn is at a low level, and when the first control signal S'n is at a low level, the second control signal Sn is at a high level, which is used to control the opening and closing of the first NMOS tube NM1 and the second NMOS tube NM2.

[0020] As an optimal technical solution for the multiplexer switch circuit of a battery management chip, the total voltage VCP is a voltage higher than the total voltage of the battery pack output after the battery management monitoring chip processes the total voltage of the battery pack.

[0021] As a preferred technical solution for the multiplexer switch circuit of a battery management chip, the control level V CTRL The control level signal provided for the battery management monitoring chip provides a gate voltage for turning on the eighth NMOS tube NM8 and the ninth NMOS tube NM9.

[0022] Beneficial effects of the present invention: The present invention uses two pairs of NMOS connection modes with common gate and common source connections (the third NMOS tube NM3 and the fourth NMOS tube NM4 are one pair, and the fifth NMOS tube M5 and the sixth NMOS tube NM6 are another pair) to isolate the input signal and the output signal of the circuit from each other in the closed working state, thereby increasing the anti-interference ability between the voltages when switching the measurement object, and at the same time increasing redundancy, thereby improving the reliability and safety of the circuit.

[0023] The present invention realizes the on and off of the circuit through two opposite control signals (S'n and Sn), wherein the first NMOS tube NM1 and the control signal S'n replace the original diode solution, thereby reducing the residual voltage.

[0024] The present invention utilizes the electrical characteristics of different MOS tubes (low on-resistance of low-voltage MOS and withstand voltage capability of high-voltage MOS) to reduce overall conduction loss while ensuring current transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0026] Figure 1 It is a principle block diagram of the application of the present invention to the system;

[0027] Figure 2 It is a circuit schematic diagram of the present invention. DETAILED DESCRIPTION

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0030] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0031] Secondly, the present invention is described in detail with reference to the schematic diagram. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0032] Example 1

[0033] Reference Figures 1 to 2 This embodiment provides a multiplexer switch circuit of a battery management chip, including:

[0034] A current mirror module, used for mirror-copying the current on the second PMOS tube PM2 and the fourth PMOS tube PM4 to the first PMOS tube PM1 and the third PMOS tube PM3;

[0035] A control module 1 is used to control the second control signal Sn to turn on or off the second NMOS transistor NM2, so as to control whether there is a current path on the second PMOS transistor PM2 and the fourth PMOS transistor PM4;

[0036] The freewheeling module is used to establish a voltage on the first resistor R1 by receiving the current input on the first PMOS tube PM1 and the third PMOS tube PM3 to control the on and off of the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the sixth NMOS tube NM6;

[0037] The control module 2 is used to control the first control signal S'n to quickly turn off the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the sixth NMOS tube NM6, and clear the residual charges of the above MOS tubes;

[0038] The switch module is used to open or close the path between the input voltage VCn and the output voltage Vo, and includes an input module and an output module.

[0039] Further, such as Figure 1As shown, the present invention discloses a multiplexer switch circuit of a battery management chip, comprising a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a fifth PMOS tube PM5, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a first resistor R1, a second resistor R2, a first TVS diode D1, a first capacitor C1, and a second capacitor C2, wherein the source of the first PMOS tube PM1 and the source of the second PMOS tube PM2 are connected to a total voltage VCP , the gate of the first PMOS tube PM1 is connected to the gate of the second MOS tube, the drain of the first PMOS tube PM1 is connected to the source of the third PMOS tube PM3, the drain of the second PMOS tube PM2 is respectively connected to its own gate and the source of the fourth PMOS tube PM4, the gate of the third PMOS tube PM3 is connected to the gate of the fourth PMOS tube PM4, the drain of the third PMOS tube PM3 is connected to the source of the fifth PMOS tube PM5 through the first resistor R1, the drain of the fourth PMOS tube PM4 is connected to the drain of the second NMOS tube NM2, the gate of the first NMOS tube NM1 is connected to the first control signal S'n, the drain of the first NMOS tube NM1 is connected to the gate of the third NMOS tube NM3, the first The source of the NMOS transistor NM1 is connected to the source of the third NMOS transistor NM3, the gate of the second NMOS transistor NM2 is connected to the second control signal Sn, the source of the second NMOS transistor NM2 is connected to the drain of the ninth NMOS transistor NM9, the drain of the third NMOS transistor NM3 is connected to the input voltage VCn and is connected to the ground through the first TVS diode D1 and to the ground through the first capacitor C1, the gate of the third NMOS transistor NM3 is connected to the drain of the third PMOS transistor PM3 and the gate of the fifth NMOS transistor NM5, the source of the third NMOS transistor NM3 is connected to the ground and the source of the fourth NMOS transistor NM4 through the second capacitor C2 and the second resistor R2, and the gate of the fourth NMOS transistor NM4 is connected to the ground through the second capacitor C2 and the second resistor R2, respectively. The gate of the fifth NMOS tube PM5 is connected to the drain of the fourth NMOS tube NM4, the drain of the fourth NMOS tube NM4 is connected to the output voltage Vo, the drain of the fifth NMOS tube NM5 is connected to the drain of the third NMOS tube NM3, the source of the fifth NMOS tube NM5 is connected to the source of the third NMOS tube NM3, the source of the sixth NMOS tube NM6 is connected to the source of the fourth NMOS tube NM4, the drain of the sixth NMOS tube NM6 is connected to the drain of the fourth NMOS tube NM4, the gate of the fifth PMOS tube PM5 is connected to the source of the fourth NMOS tube NM4, the drain of the fifth PMOS tube PM5 is connected to the ground, the drain of the eighth NMOS tube NM8 is connected to the drain of the third PMOS tube PM3,The gates of the eighth NMOS tube NM8 are respectively connected to the control level V, CTRL and the gate of the ninth NMOS tube NM9, the source of the eighth NMOS tube NM8 is connected to the ground, the drain of the ninth NMOS tube NM9 is connected to the second NMOS tube NM2, and the source of the ninth NMOS tube NM9 is connected to the ground.

[0040] The circuit has two working states, a conducting state, when the second control signal Sn is at a high level and the first control signal S'n is at a low level, the first NMOS tube NM1 is turned off (not conducting), and the second NMOS tube NM2 is turned on (conducting), and the total voltage VCP forms a current path to the ground through the first PMOS tube PM1, the third PMOS tube PM3, the first resistor R1 and the fifth PMOS tube PM5, and a stable voltage is established on the first resistor R1 so that the third NMOS tube NM3 and the fourth NMOS tube NM4 can be stably turned on, so that the input voltage VCn voltage can be transmitted to the output voltage Vo, and a closed state, when the second control signal Sn is at a low level and the first control signal S'n is at a high level, the first NMOS tube NM1 is turned on, and the second NMOS tube NM2 is turned off. At this time, the first NMOS tube NM1 forms a current path to the ground through the eighth NMOS tube NM8, and the gate voltages of the third NMOS tube NM3 and the fourth NMOS tube NM4 are clamped at a low level to ensure stable shutdown, so that the input voltage VCn voltage cannot be transmitted to the output voltage Vo. The battery management monitoring chip can realize multiplexing of multiple functions by controlling the second control signal Sn and the first control signal S'n, such as shielding of chip battery voltage detection, switching of single cell voltage and temperature measurement, control of chip power consumption under normal working state of the chip, and coordinated work between single cell voltage detection and balancing to avoid synchronous acquisition of unstable battery voltage under battery balancing state, etc.

[0041] When the circuit is in the on state, the gate and drain of the second PMOS tube PM2 and the fourth PMOS tube PM4 are connected to each other. Because their VGS=VDS, the MOS tubes always work in the saturation region, forming a special diode connection mode. When the second NMOS tube NM2 is turned on and the first NMOS tube NM1 is turned off, the second PMOS tube PM2 and the fourth PMOS tube PM4 will also be turned on. At the same time, their gates will establish a stable gate voltage so that the first PMOS tube PM1 and the third PMOS tube PM3 will also be turned on synchronously. The second PMOS tube PM2 and the fourth PMOS tube PM4 are turned on synchronously. The advantage of PM4 having the same function and being connected in series is that the voltage division ensures that each MOS tube will not be damaged due to high voltage. At the same time, the gate voltage of the third PMOS tube PM3 will be more stable due to the filtering of the previous stage. When the first PMOS tube PM1 and the third PMOS tube PM3 are turned on, a stable voltage will be established on the first resistor R1, and at the same time, the fifth PMOS tube PM5 is turned on, so that the third NMOS tube NM3 and the fourth NMOS tube NM4 as well as the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are turned on, so that the circuit path of the input voltage VCn and the output voltage Vo is opened.

[0042] When the circuit is in the off state, the second NMOS tube NM2 is turned off, and the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5, and the sixth NMOS tube NM6 will be at a low level because the gate voltage is embedded in the path of the eighth NMOS tube NM8. At the same time, because the first NMOS tube NM1 is turned on, the residual charges of the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5, and the sixth NMOS tube NM6 will be cleared, so that they can be turned off more quickly.

[0043] In this circuit, the second resistor R2 is used to limit the current in the on state, and cooperates with the second capacitor C2 to filter some interference caused by the input voltage VCn. The first capacitor C1 also filters the voltage of the input voltage VCn. The first TVS diode D1 is used to prevent the external abnormal voltage input of the input voltage VCn from damaging the switch circuit. The fifth NMOS tube NM5 and the sixth NMOS tube NM6 are redundant designs of the third NMOS tube NM3 and the fourth NMOS tube NM4, ensuring that the circuit can still work normally when the third NMOS tube NM3 or the fourth NMOS tube NM4 is damaged, thereby providing circuit stability.

[0044] Since this circuit operates in a high-voltage environment, the third PMOS transistor PM3, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6 are all MOS transistors fabricated using a high-voltage BCD process. The switching module is used to conduct or cut off the path between the input voltage VCn and the output voltage Vo, and includes an input module and an output module.

[0045] Referring to Figure 2 , the present invention is applicable to a multiplexing switch module. The battery pack module is composed of multiple single-cell voltages connected in series and supplies power to all circuits. The multiplexing switch module is used to control and isolate the connection between the battery voltage and the subsequent modules, and the level conversion module is used to adjust the level of the battery voltage as a basis for the processing of subsequent battery voltages.

[0046] It should be understood that in the development process of any actual implementation, such as in any engineering or design project, a large number of specific implementation decisions may be made. Such development efforts may be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, without excessive experimentation, the development efforts will be a routine task of design, manufacturing, and production.

[0047] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A multiplexer switch circuit of a battery management chip, characterized in that: include, A current mirror module, used for mirror-copying the current on the second PMOS tube PM2 and the fourth PMOS tube PM4 to the first PMOS tube PM1 and the third PMOS tube PM3; A control module 1 is used to control the second control signal Sn to turn on or off the second NMOS transistor NM2, so as to control whether there is a current path on the second PMOS transistor PM2 and the fourth PMOS transistor PM4; The freewheeling module is used to establish a voltage on the first resistor R1 by receiving the current input on the first PMOS tube PM1 and the third PMOS tube PM3 to control the on and off of the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the sixth NMOS tube NM6; The control module 2 is used to control the first control signal S'n to quickly turn off the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the sixth NMOS tube NM6, and clear the residual charge of the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the sixth NMOS tube NM6; The switch module is used to turn on or off the path between the input voltage VCn and the output voltage Vo, and includes an input module and an output module; The current mirror module and the freewheeling module include a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, and a fourth PMOS tube PM4. The source of the first PMOS tube PM1 and the source of the second PMOS tube PM2 are connected to the total voltage VCP, the gate of the first PMOS tube PM1 is connected to the gate of the second MOS tube, the drain of the first PMOS tube PM1 is connected to the source of the third PMOS tube PM3, the drain of the second PMOS tube PM2 is respectively connected to its own gate and the source of the fourth PMOS tube PM4, the gate of the third PMOS tube PM3 is connected to the gate of the fourth PMOS tube PM4, the drain of the third PMOS tube PM3 is connected to the source of the fifth PMOS tube PM5 through the first resistor R1, and the drain of the fourth PMOS tube PM4 is connected to the drain of the second NMOS tube NM2; The control module 2 includes a first NMOS transistor NM1, a gate of the first NMOS transistor NM1 is connected to the first control signal S'n, a drain of the first NMOS transistor NM1 is connected to the gate of the third NMOS transistor NM3, and a source of the first NMOS transistor NM1 is connected to the source of the third NMOS transistor NM3; The control module 1 includes a second NMOS tube NM2, a ninth NMOS tube NM9 and an eighth NMOS tube NM8, the gate of the second NMOS tube NM2 is connected to the second control signal Sn, the source of the second NMOS tube NM2 is connected to the drain of the ninth NMOS tube NM9; the drain of the eighth NMOS tube NM8 is connected to the drain of the third PMOS tube PM3, the gate of the eighth NMOS tube NM8 is respectively connected to the control single level VCTRL and the gate of the ninth NMOS tube NM9, the source of the eighth NMOS tube NM8 is connected to the ground, the drain of the ninth NMOS tube NM9 is connected to the second NMOS tube NM2, and the source of the ninth NMOS tube NM9 is connected to the ground; The input module includes a third NMOS transistor NM3, a first TVS diode D1, a fifth NMOS transistor NM5, a second capacitor C2, and a first capacitor C1. The drain of the third NMOS transistor NM3 is connected to the input voltage VCn and is connected to the ground through the first TVS diode D1 and the first capacitor C1, respectively. The gate of the third NMOS transistor NM3 is connected to the drain of the third PMOS transistor PM3 and the gate of the fifth NMOS transistor NM5. The source of the third NMOS transistor NM3 is connected to the ground and the source of the fourth NMOS transistor NM4 through the second capacitor C2 and the second resistor R2, respectively. The output module includes a fourth NMOS tube NM4 and a sixth NMOS tube NM6. The gate of the fourth NMOS tube NM4 is respectively connected to the drain of the third PMOS tube PM3 and the gate of the sixth NMOS tube NM6. The drain of the fourth NMOS tube NM4 is connected to the output voltage Vo. The drain of the fifth NMOS tube NM5 is connected to the drain of the third NMOS tube NM3. The source of the fifth NMOS tube NM5 is connected to the source of the third NMOS tube NM3. The source of the sixth NMOS tube NM6 is connected to the source of the fourth NMOS tube NM4. The drain of the sixth NMOS tube NM6 is connected to the drain of the fourth NMOS tube NM4. The gate of the fifth PMOS tube PM5 is connected to the source of the fourth NMOS tube NM4. The drain of the fifth PMOS tube PM5 is connected to the ground.

2. The multiplexer switch circuit of the battery management chip according to claim 1, characterized in that: The input voltage VCn is the input voltage of the circuit, which is the single cell voltage of any string of batteries. The output voltage Vo is the output voltage of the circuit, which is the input of the subsequent level conversion module.

3. The multiplexer switch circuit of the battery management chip according to claim 2, characterized in that: The first control signal S'n and the second control signal Sn are from the same control signal and present opposite levels. When the first control signal S'n is at a high level, the second control signal Sn is at a low level. When the first control signal S'n is at a low level, the second control signal Sn is at a high level, and is used to control the opening and closing of the first NMOS tube NM1 and the second NMOS tube NM2.

4. The multiplexer switch circuit of the battery management chip according to claim 3, characterized in that: The total voltage VCP is a voltage higher than the total voltage of the battery pack that is output by the battery management monitoring chip after processing the total voltage of the battery pack.

5. The multiplexer switch circuit of the battery management chip according to claim 4, characterized in that: Control level Control level V CTRL The control level signal provided for the battery management monitoring chip provides a gate voltage for turning on the eighth NMOS tube NM8 and the ninth NMOS tube NM9.

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