An asynchronous SAR analog-to-digital converter

Abstract

The application discloses an asynchronous SAR analog-to-digital converter, comprising a comparator, an asynchronous clock generation module, a successive approximation module and a perturbation injection module; the comparator is connected with a sampling signal and outputs a differential comparison result; the successive approximation module acquires a quantization result of a current bit according to the differential comparison result; the asynchronous clock generation module outputs an asynchronous clock to the comparator, so that the comparator performs a comparison process of the current bit by an effective pulse of a current bit of the asynchronous clock; a first time delay is provided between adjacent effective pulses of the asynchronous clock; the perturbation injection module generates a perturbation signal according to the asynchronous clock and outputs the perturbation signal to the comparator, so that the comparator outputs the differential comparison result of the current bit after the comparator enters a metastable state; an effective pulse of a current bit of the perturbation signal is generated after a second time delay from a starting time of an effective pulse of a current bit of the asynchronous clock. The technical scheme provided by the application can reduce the metastable state rate of the SAR analog-to-digital converter and avoid conversion data errors.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital converter, and particularly relates to an asynchronous SAR analog-to-digital converter. BACKGROUND

[0002] With the rapid development of process, successive approximation register analog-to-digital converter (SAR ADC) is paid more and more attention. In high-speed applications, asynchronous clock SAR ADC is generally used. Since the digital quantization of SAR ADC is successive, the comparison time left for the comparator is very short, and the comparator is easy to be in a metastable state, thereby causing the conversion data of SAR ADC to be wrong.

[0003] Specifically, the SAR ADC will perform a plurality of comparator comparison processes after each sampling is completed, and each comparison needs to be controlled by a clock. The asynchronous clock does not depend on the system clock, but generates the next comparator clock after a certain delay (such as Tr) after each comparison is completed. The comparator metastable state occurs when the input voltage of the comparator is too small, at which time the output of the comparator cannot obtain a correct output for a long time, and further causes the asynchronous clock to fail to generate the next clock for a long time, resulting in a jam or even termination of the quantization process, and causing the ADC to work abnormally. SUMMARY

[0004] Embodiments of the present application provide an asynchronous SAR analog-to-digital converter to reduce the metastable state rate of the SAR analog-to-digital converter and avoid conversion data error of the SAR analog-to-digital converter.

[0005] Embodiments of the present application provide an asynchronous SAR analog-to-digital converter, which comprises a comparator, an asynchronous clock generation module, a successive approximation module and a perturbation injection module.

[0006] An input end of the comparator is used to access the positive end voltage and the negative end voltage of a sampling signal; an output end of the comparator outputs a differential comparison result; the successive approximation module is connected with the output end of the comparator and is used to acquire and store the quantization result of a current bit according to the differential comparison result;

[0007] The asynchronous clock generation module is connected with the comparator and is used to output an asynchronous clock to the comparator, so as to control the comparator to perform a comparison process of a current bit through the effective pulse of the current bit of the asynchronous clock; the adjacent effective pulses of the asynchronous clock are separated by a first time delay;

[0008] The perturbation injection module is connected with the asynchronous clock generation module and the comparator respectively, and is configured to generate a perturbation signal according to the asynchronous clock and output the perturbation signal to the comparator, so that the effective pulse of the perturbation signal forces the comparator to output a differential comparison result of a current bit after the comparator enters a metastable state; and the effective pulse of the current bit of the perturbation signal is generated after a second time delay from a starting time of the effective pulse of the current bit of the asynchronous clock.

[0009] In the application, the asynchronous SAR analog-to-digital converter converts a sampling signal into a multi-bit differential comparison result through a comparator, and a successive approximation module obtains quantization results of bits in sequence according to the differential comparison result. In the comparison process of the comparator, an asynchronous clock generation module controls the comparator to perform a comparison process of a current bit through an effective pulse of an asynchronous clock, and controls the comparator to perform a comparison process of a next bit after a first time delay from completion of the comparison process of the current bit. An effective pulse of a perturbation signal is formed by the perturbation injection module after a second time delay from a starting time of the comparison of the comparator. If the comparator has completed the comparison process of the current bit, the effective pulse of the perturbation signal will not affect the operation of the comparator. If the comparator is in a metastable state, the effective pulse of the perturbation signal can force the comparator to immediately output a differential comparison result, end the metastable state process, and will not cause interruption of the quantization process or large failure of the conversion data of the asynchronous SAR analog-to-digital converter. Moreover, the quantization process is not interrupted, so it is not necessary to find the digital bit in which the metastable state occurs in time, and therefore, a position interruption judgment circuit is not introduced, and the risk of judgment error is not introduced. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 FIG. 1 is a structural schematic diagram of an asynchronous SAR analog-to-digital converter in the prior art;

[0011] Figure 2 FIG. 2 is a comparator clock timing diagram of the asynchronous SAR analog-to-digital converter in the prior art; Figure 1

[0012] Figure 3 FIG. 3 is a structural schematic diagram of a SAR analog-to-digital converter provided by an embodiment of the application;

[0013] Figure 4 FIG. 4 is a comparator clock timing diagram of the asynchronous SAR analog-to-digital converter in the embodiment of the application; Figure 3

[0014] Figure 5 FIG. 5 is a structural schematic diagram of another SAR analog-to-digital converter provided by an embodiment of the application;

[0015] Figure 6 FIG. 6 is a comparator clock timing diagram of the asynchronous SAR analog-to-digital converter in the embodiment of the application; Figure 5 ​​​

[0016] Figure 7 A schematic diagram of the structure of a comparative asynchronous SAR analog-to-digital converter provided in an embodiment of the present invention;

[0017] Figure 8 for Figure 7 Timing diagram of the comparator clock when metastability occurs in the asynchronous SAR analog-to-digital converter;

[0018] Figure 9 for Figure 7 Timing diagram of the comparator clock for the asynchronous SAR analog-to-digital converter, which experiences metastability due to latch metastability. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0020] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of an asynchronous SAR analog-to-digital converter (ADC) in the prior art. The asynchronous SAR ADC mainly consists of a digital-to-analog converter 11', a comparator 12', a comparison completion detection circuit 13', a successive approximation logic 14', and an asynchronous clock generation circuit 15'. After each sampling, each sampling period T1' requires multiple comparator comparisons, and the result of each comparator is stored in the corresponding location (such as a register) to complete one quantization. For example, the sampled signal is converted into a 4-bit digital signal by the asynchronous SAR ADC. Each comparator comparison requires clock control. Figure 2 As shown, Figure 2 for Figure 1 The timing diagram of the comparator clock during metastability in an asynchronous SAR analog-to-digital converter (ADC) is shown. In a typical synchronous clock system, the comparator clock is generated by the system clock. However, in an asynchronous clock system, the comparator clock clkc' becomes valid (e.g., pulled high) after a fixed delay (e.g., Tr') following each comparator comparison and is reset (e.g., pulled low) after the comparison, thus it is independent of the system clock. Since the comparator comparison speed is negatively correlated with the comparator input voltage, the comparator clock period in a synchronous clock system must satisfy the maximum comparator comparison time, i.e., the comparison time corresponding to the smallest input voltage that needs to be resolved. In contrast, in an asynchronous clock system, the comparison time for each comparison is determined by the magnitude of each input voltage, thus saving additional time overhead and accelerating the operation of the SAR ADC. For example, as shown... Figure 2As shown, in one sampling period T1', the asynchronous clock system completes four comparison processes in sequence: S1', S2', S3', and S4'. The time interval Tr' between two adjacent comparison processes effectively speeds up the operation of the SAR ADC.

[0021] However, due to the operating characteristics of asynchronous clocks, if the comparator input voltage is too small during a comparison (e.g., much smaller than the minimum voltage required to be distinguished), the comparator will require much longer than expected to obtain the comparison result. This situation is called metastability. Figure 2 As shown, in the second sampling period T1', after the asynchronous clock system completes the first comparison process S1', the comparator input voltage is too low in the second comparison process S2', causing the second comparison process S2' to last too long. When metastability occurs, the quantization time of the current sample will be severely prolonged, or even quantization will terminate, resulting in the failure to complete the current quantization before the start of the next sampling, leading to an incorrect quantization result.

[0022] like Figure 2 As shown, taking a 4-bit SAR ADC as an example, it can be seen that in the first sampling period T1', because the input voltage is different each time the comparator operates, the effective time of the comparator clock is different each time (the durations of S2' and S3' are different). Each comparator clock is generated by Tr' after the previous comparison is completed, and finally, four comparisons are completed before the effective pulse T2' of the next sampling clock arrives. Therefore, the first sampling completes normal quantization. In the second sampling period T1', the first comparator comparison S1' is completed within a finite time (sampling period T1'). However, metastability occurs during the second comparator comparison S2', occupying a very long comparison time. This prevents the third and fourth comparisons from being performed before the effective pulse of the next sampling clock arrives, resulting in incorrect quantization results.

[0023] To effectively avoid the impact of metastability on data conversion, embodiments of the present invention provide a SAR analog-to-digital converter, such as... Figure 3 As shown, Figure 3 A schematic diagram of a SAR analog-to-digital converter provided in an embodiment of the present invention includes: a comparator 12, an asynchronous clock generation module 15, a successive approximation module 14, and a perturbation injection module 16;

[0024] The input terminal of comparator 12 is used to receive the positive and negative voltage terminals of the sampled signal; the output terminal of comparator 12 outputs the differential comparison result; the successive approximation module 14 is connected to the output terminal of comparator 12 and is used to obtain and store the quantization result Dout of the current bit based on the differential comparison result.

[0025] The asynchronous clock generation module 15 is connected to the comparator 12 and is used to output an asynchronous clock clkc to the comparator 12 so as to control the comparator 12 to perform the comparison process of the current bit by the valid pulse of the current bit of the asynchronous clock clkc; the interval between adjacent valid pulses of the asynchronous clock clkc is a first time delay Tr.

[0026] The perturbation injection module 16 is connected to the asynchronous clock generation module 15 and the comparator 12 respectively. It is used to generate a perturbation signal preamp_rd according to the asynchronous clock clkc and output it to the comparator 12, so that after the comparator 12 enters the metastable state, the effective pulse of the perturbation signal preamp_rd forces the comparator 12 to output the differential comparison result of the current bit. The effective pulse of the current bit of the perturbation signal preamp_rd is generated after the second time delay Tmeta at the start time of the effective pulse of the current bit of the asynchronous clock clkc.

[0027] Optionally, the asynchronous clock generation module 15 can also be used to control the valid pulse of the current bit of the asynchronous clock clkc to be reset after the comparator 12 completes the comparison process. Then, the end time of the current bit comparison process of the comparator 12 is the end time of the valid pulse of the current bit of the asynchronous clock clkc.

[0028] In this embodiment of the invention, the asynchronous SAR analog-to-digital converter converts the sampled signal into a multi-bit differential comparison result through a comparator. The successive approximation module sequentially obtains the quantization result of each bit based on the differential comparison result. During the comparison process of the comparator, the asynchronous clock generation module controls the comparator to execute the comparison process of the current bit through the effective pulse of the asynchronous clock, and controls the comparator to start the comparison process of the next bit after the first time delay after the completion of the current bit comparison process. The perturbation injection module generates an effective pulse of the perturbation signal after a second time delay at the start of the comparator comparison. If the comparator has completed the comparison process of the current bit, the effective pulse of the perturbation signal will not affect the operation of the comparator. If the comparator is in a metastable state, the effective pulse of the perturbation signal can force the comparator to immediately output the differential comparison result, ending the metastable process, and there will be no interruption of the quantization process, thus avoiding the major error of data conversion interruption of the asynchronous SAR analog-to-digital converter. Furthermore, since there is no interruption of the quantization process, it is not necessary to search for the digital bit where the metastable state occurs in a timely manner, and therefore no interruption position judgment circuit is introduced, eliminating the risk of judgment errors.

[0029] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0030] The comparator 12 has a positive input and an inverting input, which are respectively connected to the positive and negative voltages of the sampled signal. The comparator 12 can output a differential comparison result including the positive and negative signals. The successive approximation module 14 quantizes the differential comparison result to form the quantized result Dout. The SAR analog-to-digital converter is used to sample and quantize the analog signal to form a digital signal including multiple digital bits. During each sampling process (each sampling corresponds to a sampling period T1), comparator 12 needs to perform multiple comparisons to form multiple differential comparison results. Each differential comparison result corresponds to a quantization result, that is, a numerical bit. The asynchronous clock generation module 15 can generate an asynchronous clock clkc. The comparison process of the current bit of comparator 12 is controlled by the valid pulse of the current bit of asynchronous clock clkc. The valid pulse starts from the start time (if high level is valid, it is the rising edge). Comparator 12 starts to execute the comparison process of the current bit. When comparator 12 finishes the comparison process of the current bit, asynchronous clock generation module 15 ends the valid pulse of the current bit (if high level is valid, it is the falling edge). After that, asynchronous clock generation module 15 pauses for a first time delay T. After r, the valid pulse corresponding to the next digital bit is output to control comparator 12 to start the comparison process for the next bit. It should be noted that the first comparison clock (valid pulse) of comparator 12 is determined by the delay of the valid pulse T2 of the sampling clock, and subsequent comparison clocks are generated by the asynchronous clock generation module 15. For example, after the first comparison is completed, comparator 12 outputs a valid result, and then this valid indication signal is input to the asynchronous clock generation module 15. The asynchronous clock generation module 15 generates the second comparison clock. Due to the delay of digital logic and the setup time of the switched capacitor array, the asynchronous clock generation module 15 outputs the comparison clock to comparator 12 after a certain delay Tr after receiving the valid indication signal, and this cycle continues until the last bit of the sampling point is converted.

[0031] The perturbation injection module 16 generates a perturbation signal preamp_rd based on the asynchronous clock clkc generated by the asynchronous clock generation module 15, and outputs the perturbation signal preamp_rd to the comparator 12 after a second time delay Tmeta following the start of the comparison process. Figure 4 As shown, Figure 4 for Figure 3 The clock timing diagram of the comparator when the asynchronous SAR analog-to-digital converter enters a metastable state. Generally, the disturbance signal preamp_rd is small. If comparator 12 has not entered a metastable state at this time, such as... Figure 4 During the comparison processes S1, S3, and S4, the differential comparison result of the comparator will not change due to the disturbance signal preamp_rd. If the comparator enters a metastable state at this time, such as... Figure 4In the comparison process S2, the perturbation signal preamp_rd can force comparator 12 to output a differential comparison result. After obtaining the differential comparison result, the asynchronous clock can still generate the next valid pulse and continue to complete the entire quantization process without interruption of the working state. This effectively eliminates the influence of metastability on the SAR analog-to-digital converter and avoids major errors such as interruption of asynchronous SAR analog-to-digital converter data conversion. In addition, even if the time of injection of the perturbation signal preamp_rd coincides with the time when the comparator completes the comparison process, by controlling the second delay Tmeta, it can be ensured that the input of comparator 12 is much smaller than the minimum voltage that needs to be resolved. Therefore, even if the perturbation signal preamp_rd causes an incorrect flip, the final error will still be within one least significant bit (LSB), which is still acceptable.

[0032] Continue to refer to Figure 3 Optionally, when no metastability occurs, the valid pulse of the current bit of the perturbation signal `preamp_rd` does not cause the comparator to output the differential comparison result of the current bit; when metastability occurs, the valid pulse of the current bit of the perturbation signal `preamp_rd` forces the comparator to output the differential comparison result of the current bit before the valid pulse of the next bit of the asynchronous clock `clkc`. That is, the end time of the valid pulse of the perturbation signal `preamp_rd` is earlier than the start time of the valid pulse of the next bit of the asynchronous clock `clkc`. Therefore, the magnitude of the perturbation signal `preamp_rd` is selected so that it will not cause the comparator to flip when no metastability occurs, and can ensure that the comparator flips quickly when metastability occurs. In this embodiment, the perturbation signal `preamp_rd` can force the comparator to output the differential comparison result quickly after entering a metastable state, eliminating the interference of metastability, and does not affect the comparator's next bit comparison process.

[0033] Continue to refer to Figure 3Optionally, comparator 12 may include: amplifier 121 and latch 122; the input of amplifier 121 is used to connect the positive and negative voltages of the sampled signal; amplifier 121 is used to output the differential comparison result to the input of latch 122 according to the sampled signal; latch 122 is used to hold the differential comparison result for one comparison period and output it to successive approximation module 14; asynchronous clock generation module 15 is used to output asynchronous clock clkc to latch 122; perturbation injection module 16 is used to send perturbation signal preamp_rd to amplifier 121 or latch 122. In a real circuit, comparator 12 can be composed of amplifier 121 and latch 122, where amplifier 121 is responsible for amplifying the comparator input to a size that can trigger latch 122 to latch. When latch 122 completes latching, the comparator completes one comparison process. When the input of latch 122 is extremely small, latch 122 cannot trigger latching, and the comparator enters a metastable state. Latch 122 receives an asynchronous clock clkc. In metastable state, perturbation injection module 16 sends a perturbation signal preamp_rd to amplifier 121 or latch 122, forcing amplifier 121 or latch 122 to output a differential comparison result. This result can be maintained for one comparison period and output to successive approximation module 14. It should be noted that in practical applications, amplifier 121 is not a necessary component of comparator 12. Comparator 12 can also be constructed from other devices. This embodiment is only used as a specific example for explanation and does not constitute a limitation on the specific structure of comparator 12.

[0034] like Figure 3 As shown, optionally, the perturbation injection module 16 may include: a delay circuit 162 and a perturbation generation circuit 161; the delay circuit 162 is used to send the asynchronous clock clkc to the perturbation generation circuit 161 after a second delay Tmeta; the perturbation generation circuit 161 is used to generate a perturbation signal preamp_rd based on the asynchronous clock clkc after the second delay Tmeta. The delay circuit 162 is used to generate the second delay Tmeta, and the perturbation generation circuit 161 is used to inject the perturbation signal preamp_rd after the second delay Tmeta. This embodiment provides perturbations in many ways, including but not limited to using capacitors or switches to provide asymmetrical voltage changes to the differential input of the latch 122.

[0035] Figure 5This is a schematic diagram of another SAR analog-to-digital converter provided in an embodiment of the present invention. Optionally, the perturbation injection module 16 may include: a reset circuit 17; the reset circuit 17 is connected to the asynchronous clock generation module 15 and the comparator 12 respectively; the reset circuit 17 is used to generate a reset signal preamp_rstn for the comparator 12 according to the asynchronous clock clkc; the effective pulse of the reset signal preamp_rstn is generated by delaying the effective pulse of the asynchronous clock clkc by a second time delay Tmeta; the reset signal preamp_rstn is multiplexed into a perturbation signal preamp_rd. It should be noted that the reset circuit 17 is only an optional module provided in this embodiment, and not all embodiments require the setting of the reset circuit 17. This embodiment only extends the structure of the SAR analog-to-digital converter by example, but is not intended to limit the SAR analog-to-digital converter.

[0036] Optionally, the end time of the valid pulse of the current bit of the perturbation signal preamp_rd is before the start time of the valid pulse of the next bit of the asynchronous clock clkc. For example, if the valid level of the asynchronous clock clkc is high and the valid level of the reset signal preamp_rstn is low, then the rising edge of the valid pulse of the current bit of the perturbation signal preamp_rd is before the rising edge of the valid pulse of the next bit of the asynchronous clock clkc. The start time of the valid pulse of the current bit of the reset signal preamp_rstn differs from the start time of the valid pulse of the current bit of the asynchronous clock clkc by a second time delay Tmeta.

[0037] Figure 6 for Figure 5 The comparator clock timing diagram for metastability in the asynchronous SAR analog-to-digital converter is shown. In this embodiment, the perturbation injection module 16 sends a perturbation signal preamp_rd to amplifier 121 as an example. In this embodiment, the perturbation of latch 122 can be achieved by using the reset operation of amplifier (preamp) 121. The specific timing is as follows: Figure 6 As shown, a reset signal (such as preamp_rstn, for example, active low) is generated for amplifier 121. The rising edge of preamp_rstn coincides with the rising edge of clkc (the effective pulse of the next bit), or the rising edge of preamp_rstn precedes the rising edge of clkc (the effective pulse of the next bit). The falling edge of preamp_rstn is generated after a certain delay (such as the second delay Tmeta) of the rising edge of clkc (the effective pulse of the current bit). The length of the second delay Tmeta should ensure that the comparator can compare the minimum voltage value that needs to be distinguished.

[0038] Under normal circumstances, amplifier 121 should be reset after the comparison is completed, such asFigure 6 As shown in the first, third, and fourth comparisons. However, when the comparison time exceeds Tmeta, as... Figure 6 In the second comparison, the preamp will be reset prematurely. Ideally, during the preamp reset process, the preamp's output voltage is pulled to near zero differential voltage. However, due to switching mismatch, preamp mismatch, and latch mismatch, this process will introduce a non-zero voltage change at the latch input. This deviates from the current input voltage that triggers metastability and forces the latch to trigger latching. After a finite comparison time, the comparison is completed. It is worth noting that this finite comparison time will be much shorter than the comparison time required in the metastable state.

[0039] In asynchronous clocks, clkc always generates the start signal for the next comparison after a fixed delay Tr following the completion of the previous comparison. However, this implementation forces the latch to latch after a metastability occurs, pulling clkc low, allowing the asynchronous clock generation circuit to continue operating. Therefore, it does not affect the entire asynchronous timing cycle generation process and has minimal impact on the system structure. The only thing to note is the need to properly arrange the delays to ensure that the preamp is fully reset before the next clkc arrives in all cases.

[0040] Optionally, the asynchronous SAR analog-to-digital converter may further include: a digital-to-analog converter 11; the digital-to-analog converter 11 is connected to the successive approximation module 14 for acquiring a sampling clock signal; the digital-to-analog converter 11 is connected to a comparator 12 for outputting a sampling signal to the comparator 12 in one sampling period; the comparator 12 is used to sequentially complete the comparison process of multiple digital bits in one sampling period.

[0041] Optionally, the asynchronous SAR analog-to-digital converter may further include: a comparison completion detection circuit 13; the comparison completion detection circuit 13 is connected to the output of the comparator 12 and is used to output a valid indication signal comp_ready to the asynchronous clock generation module 15 when the differential comparison result is detected to be valid; the asynchronous clock generation module 15 is used to output a valid pulse to the comparator 12 after a first time delay Tr.

[0042] This embodiment finds an asynchronous SAR analog-to-digital converter that eliminates metastability, which is comparable to the embodiment of this invention, in the prior art. This embodiment can be called a comparative example, specifically as follows: Figure 7 As shown, Figure 7This is a schematic diagram of a comparative asynchronous SAR analog-to-digital converter provided in an embodiment of the present invention. In the prior art, the solution to metastability in asynchronous SAR ADCs can be called a "metastable-then-set" type. This involves monitoring the operating state of the comparator and generating a metastability flag signal (such as MD) when metastability is detected, terminating the comparator's operation, retaining the existing comparator output and storing it in a register, and assigning a specific codeword (such as 100…00 or 011…11) to the register containing the remaining unobtained comparator output through the digital output correction module 16'. At this point, the maximum output error is one least significant bit (LSB), which is within an acceptable error range, thus effectively reducing the metastability rate. Figure 8 for Figure 7 The comparator clock timing diagram for the metastability of the asynchronous SAR analog-to-digital converter. (See diagram below.) Figure 8 As shown, it can be seen that compared to Figure 1 The traditional asynchronous SAR analog-to-digital converter (ADC) in this paper adds a metastability monitoring module 17' and a digital codeword correction module 16'. The metastability monitoring module 17' consists of a comparison time monitoring circuit 171' and a latch 172'. When the comparison time exceeds a preset value (e.g., Tmeta), ... Figure 8 In the second comparison process S2, the comparison time monitoring circuit 171' outputs Tm and is valid. The latch 172' latches the generated MD signal, terminating the further operation of the comparator. The digital output correction module 16' combines the output comparison result with a specific codeword (such as 100…00 or 011…11) to generate an output result Dout with an error range not exceeding 1 LSB, effectively reducing the metastability rate.

[0043] The problem with the existing technology is that it requires an additional metastability monitoring module 17' and digital output correction module 16', increasing circuit overhead. More importantly, since the metastability monitoring module 17' requires a latch structure to generate the MD flag, and the latch structure itself may also encounter metastability, it may cause the flag generation time to be inconsistent with expectations. At the same time, since the "Metastable-then-set" technique will interrupt the normal quantization process of the ADC, if the metastability of latch 172' causes the generation of the MD flag to occur after the current bit codeword is latched, the comparison process of the next bit will be prematurely terminated, and subsequent digital correction will introduce serious output errors.

[0044] Figure 9 for Figure 7 Timing diagram of the comparator clock for the asynchronous SAR analog-to-digital converter, which experiences metastability due to latch metastability. Figure 9The timing diagram for handling erroneous metastability judgments caused by latch metastability involves a second bit comparison duration only slightly longer than Tmeta. Tm is only valid after the comparison time exceeds Tmeta and before the current bit comparison is complete, resulting in an extremely narrow pulse width for the Tm signal. Since latch 172' has a requirement for the effective duration of the input signal Tm, it may cause latch 172' to enter a metastable state. The MD signal output by latch 172' will only be partially established and not fully valid, and the MD signal may be established in the next bit. If the MD signal is established in the next bit, such as during the third bit comparison, it will cause the ADC to experience an erroneous quantization interrupt at the third bit and assign a value to the remaining codeword instead of the second bit. Since the third bit is not metastable, forcibly assigning a value to the remaining codeword will lead to a significant error.

[0045] As can be seen from the comparative example above, the "Metastable-then-set" type asynchronous SAR analog-to-digital converter monitors metastable states to promptly acquire them and halt the quantization process at that moment. This not only prematurely terminates the next bit comparison process but also introduces serious output errors in subsequent digital correction. The comparative example's scheme has a large error, while the scheme in this embodiment does not involve monitoring metastable states; it merely introduces perturbations through a fixed delay. Therefore, it avoids triggering the metastable state of related metastable state monitoring modules, achieving stable metastable state elimination. This embodiment avoids the use of metastable state monitoring modules, thereby fundamentally preventing the occurrence of related decision circuits, such as the metastable state of metastable state monitoring modules, achieving a stable and reliable solution for reducing the metastable rate. Furthermore, compared to the comparative example, this embodiment introduces fewer new modules, resulting in lower manufacturing costs.

[0046] In summary, the core idea of ​​this invention is to inject a perturbation into the comparator after a constant time delay (such as Tmeta) following the start of comparison. If the comparator has completed the comparison, the perturbation will not affect the comparison result; if the comparator is in a metastable state, the perturbation can force the comparator to obtain the comparison result, thereby eliminating the influence of the comparator's metastability on the asynchronous clock SAR ADC, reducing the metastability rate of the SAR analog-to-digital converter, and avoiding data conversion errors by the SAR analog-to-digital converter.

[0047] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An asynchronous SAR analog-to-digital converter, characterized by, The asynchronous SAR ADC comprises a comparator, an asynchronous clock generation module, a successive approximation module and a perturbation injection module. An input end of the comparator is connected to a positive voltage and a negative voltage of a sampling signal; an output end of the comparator outputs a differential comparison result; the successive approximation module is connected to the output end of the comparator and is used to acquire and store a quantization result of a current bit according to the differential comparison result; The asynchronous clock generation module is connected to the comparator and is used to output an asynchronous clock to the comparator, so that the comparator performs a comparison process of the current bit by an effective pulse of a current bit of the asynchronous clock; adjacent effective pulses of the asynchronous clock are separated by a first time delay; The perturbation injection module is connected to the asynchronous clock generation module and the comparator respectively, is used to generate a perturbation signal according to the asynchronous clock and output the perturbation signal to the comparator, so that an effective pulse of the perturbation signal forces the comparator to output the differential comparison result of the current bit after the comparator enters a metastable state; wherein the effective pulse of the current bit of the perturbation signal is generated after a second time delay from a starting time of the effective pulse of the current bit of the asynchronous clock.

2. The asynchronous SAR ADC of claim 1, wherein when the metastable state does not occur, the effective pulse of the current bit of the perturbation signal does not cause the differential comparison result of the current bit output by the comparator to change; when the metastable state occurs, the effective pulse of the current bit of the perturbation signal forces the comparator to output the differential comparison result of the current bit before an effective pulse of a next bit of the asynchronous clock. The comparator comprises an amplifier and a latch; 3. The asynchronous SAR analog-to-digital converter of claim 1, wherein, an input end of the amplifier is connected to a positive voltage and a negative voltage of a sampling signal; the amplifier is used to output a differential comparison result to an input end of the latch according to the sampling signal; the latch is used to maintain the differential comparison result for a comparison period and output the differential comparison result to the successive approximation module; the asynchronous clock generation module is used to output the asynchronous clock to the latch; the perturbation injection module is used to send the perturbation signal to the amplifier or the latch. The perturbation injection module comprises a delay circuit and a perturbation generation circuit; 4. The asynchronous SAR analog-to-digital converter of claim 1, wherein, the delay circuit is used to delay the asynchronous clock by the second time delay and send the delayed asynchronous clock to the perturbation generation circuit; the perturbation generation circuit is used to generate the perturbation signal according to the delayed asynchronous clock. The perturbation injection module comprises a reset circuit; 5. The asynchronous SAR analog-to-digital converter of claim 1, wherein, the reset circuit is connected to the asynchronous clock generation module and the comparator respectively; the reset circuit is used to generate a reset signal of the comparator according to the asynchronous clock; an effective pulse of the reset signal is generated at a starting time of an effective pulse of the asynchronous clock after the second time delay; the reset signal is multiplexed as the perturbation signal.

6. The asynchronous SAR ADC of claim 5, wherein an ending time of the effective pulse of the current bit of the perturbation signal is before a starting time of an effective pulse of a next bit of the asynchronous clock. The asynchronous SAR ADC further comprises a digital-to-analog converter.

7. The asynchronous SAR analog-to-digital converter of claim 1, wherein, ​ ​ The digital-to-analog converter is connected with a successive approximation module, and is configured to obtain a sampling clock signal; the digital-to-analog converter is connected with the comparator, and is configured to output a sampling signal to the comparator in a sampling period; The comparator is configured to sequentially complete comparison processes of multiple digital bits in a sampling period.

8. The asynchronous SAR analog-to-digital converter of claim 2, wherein, Further comprising: a comparison completion detection circuit; the comparison completion detection circuit is connected with an output end of the comparator, and is configured to output a valid indication signal to the asynchronous clock generation module when detecting that the differential comparison result is valid; the asynchronous clock generation module is configured to output a valid pulse to the comparator after the first time delay.

9. The asynchronous SAR analog-to-digital converter of claim 1, wherein, The asynchronous clock generation module is further configured to reset the valid pulse of the current bit of the asynchronous clock after the comparator completes the comparison process.

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