Split gate type MOSFET structure and manufacturing method thereof

Abstract

The invention provides a split gate type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof. The method comprises the following steps of: forming a groove in a substrate; forming a medium filling part in the groove, wherein the top surface of the medium filling part is lower than the top surface of the substrate; forming a groove in the dielectric filling part to obtain a shield gate dielectric layer, wherein the width of a top opening of the groove is greater than that of the bottom of the groove; forming a shield gate electrode layer in the groove; an isolation layer, a control gate dielectric layer and a control gate electrode layer are formed in the groove, the control gate electrode layer is located above the shield gate electrode layer, the isolation layer is located between the shield gate electrode layer and the control gate electrode layer, and the control gate dielectric layer is located between the side wall of the control gate electrode layer and the side wall of the groove. According to the invention, the shield gate dielectric layer which is gradually thickened from top to bottom can be formed, the breakdown voltage of the device can be improved, the thickness of each part of the shield gate dielectric layer is easy to control respectively, and finer voltage-withstanding characteristic regulation and control can be realized.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit design and manufacturing, and relates to a split-gate MOSFET structure and a manufacturing method thereof. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field effect transistor that can be widely used in analog and digital circuits. Among them, the split gate trench MOSFET (SGTMOS) is also a widely used device. It introduces a split gate design based on the traditional trench MOSFET and adopts deep trench isolation technology to achieve excellent performance such as low on-resistance, low gate charge and high breakdown voltage. As an advanced power MOSFET structure, it is widely used in medium and low voltage fields.

[0003] Specifically, SGTMOS buries the gate in a deep trench and adds a polysilicon electrode, i.e., a shielding electrode, under the gate. Through the charge coupling effect, SGTMOS can reduce the critical electric field strength in the drift region, thereby reducing the on-resistance of the device and making the conduction loss of the device lower. In addition, the split-gate design reduces the Miller capacitance and gate charge, speeds up the switching speed of the device, and reduces the switching loss. By optimizing the electric field distribution, SGTMOS can obtain a higher breakdown voltage at the same doping concentration.

[0004] In the high-voltage field, the voltage withstand capability of SGTMOS is a key parameter to characterize device performance and has always been the focus of people's attention. The voltage withstand capability of SGTMOS is greatly affected by the thickness of the oxide layer at the bottom and side walls of the trench. At present, the oxide layer in the trench of SGTMOS is formed by thermal oxidation growth or deposition growth, and the thickness of the oxide layer at the bottom and side walls of the trench is almost the same. In this way, it is impossible to achieve the purpose of increasing the voltage withstand capability by only increasing the oxide layer at the bottom of the trench.

[0005] Therefore, how to provide a split-gate MOSFET structure and a manufacturing method thereof to further improve the voltage withstand capability of the device has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a split-gate MOSFET structure and a manufacturing method thereof, so as to solve the problem that the voltage resistance of the split-gate MOSFET structure in the prior art needs to be further improved.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a split-gate MOSFET structure, comprising the following steps: providing a substrate, and forming a groove in the substrate; forming a dielectric filling portion in the trench, wherein a top surface of the dielectric filling portion is lower than a top surface of the substrate; forming a groove in the dielectric filling portion to obtain a shielding gate dielectric layer, wherein the width of the top opening of the groove is greater than the bottom width of the groove; forming a shielding gate electrode layer in the groove; An isolation layer, a control gate dielectric layer and a control gate electrode layer are formed in the groove, wherein the control gate electrode layer is located above the shielding gate electrode layer, the isolation layer is located between the shielding gate electrode layer and the control gate electrode layer, and the control gate dielectric layer is located between the side wall of the control gate electrode layer and the side wall of the groove.

[0009] Optionally, forming a dielectric filling portion in the trench comprises the following steps: Depositing a first dielectric layer, wherein the first dielectric layer covers the substrate and fills the trench; removing a portion of the first dielectric layer that is higher than the top surface of the substrate; The first dielectric layer is etched back so that the top surface of the first dielectric layer is lower than the top surface of the substrate by a preset distance, thereby obtaining the dielectric filling portion.

[0010] Optionally, forming a groove in the medium-filled portion comprises the following steps: forming a patterned mask layer, wherein the patterned mask layer covers the substrate and the dielectric filling portion and has a mask opening at a position where the groove is to be formed; The dielectric filling portion is etched based on the patterned mask layer to obtain the groove.

[0011] Optionally, the inclination angle of the side wall of the groove ranges from 80° to 89°.

[0012] Optionally, the thickness of the shielding gate dielectric layer at the bottom wall of the trench is D1, the bottom thickness of the shielding gate dielectric layer at the side wall of the trench is D2, and the top thickness of the shielding gate dielectric layer at the side wall of the trench is D3, wherein D1>D2>D3.

[0013] Optionally, the range of D1 / D2 is 1.2~3, and the range of D1 / D3 is 1.5~4.

[0014] Optionally, the method further comprises the following steps: forming a body region on the upper surface layer of the substrate at both sides of the trench; forming a source region on the upper surface of the body region; forming an interlayer dielectric layer above the substrate; forming a contact hole, wherein the contact hole penetrates the interlayer dielectric layer and extends into the source region and the body region; An upper metal layer is formed above the interlayer dielectric layer and in the contact hole.

[0015] The present invention also provides a split-gate MOSFET structure, comprising: substrate; A groove is formed on the top surface of the substrate; A dielectric filling portion, located in the groove, wherein a top surface of the dielectric filling portion is lower than a top surface of the substrate; A groove is formed on the top surface of the dielectric filling portion to form a shielding gate dielectric layer, wherein the width of the top opening of the groove is greater than the bottom width of the groove; A shielding gate electrode layer is located in the groove; a control gate electrode layer, located in the trench and above the shielding gate electrode layer; an isolation layer, located between the shielding gate electrode layer and the control gate electrode layer; The control gate dielectric layer is located between the sidewall of the control gate electrode layer and the sidewall of the trench.

[0016] Optionally, the inclination angle of the side wall of the groove ranges from 80° to 89°.

[0017] Optionally, the thickness of the shielding gate dielectric layer at the bottom wall of the trench is D1, the bottom thickness of the shielding gate dielectric layer at the side wall of the trench is D2, and the top thickness of the shielding gate dielectric layer at the side wall of the trench is D3, wherein D1>D2>D3.

[0018] Optionally, the range of D1 / D2 is 1.2~3, and the range of D1 / D3 is 1.5~4.

[0019] Optionally, it also includes: A body region located on the upper surface layer of the substrate at both sides of the trench; A source region, located on the upper surface of the body region; An interlayer dielectric layer, located above the substrate; A contact hole, penetrating the interlayer dielectric layer and extending into the source region and the body region; The upper metal layer is located above the interlayer dielectric layer and in the contact hole.

[0020] As described above, the manufacturing method of the split-gate MOSFET structure of the present invention includes the following steps: forming a groove in a substrate; forming a dielectric filling portion in the groove, the top surface of the dielectric filling portion being lower than the top surface of the substrate; forming a groove in the dielectric filling portion to obtain a shielding gate dielectric layer, the width of the top opening of the groove being greater than the bottom width of the groove; forming a shielding gate electrode layer in the groove; forming an isolation layer, a control gate dielectric layer and a control gate electrode layer in the groove, the control gate electrode layer being located above the shielding gate electrode layer, the isolation layer being located between the shielding gate electrode layer and the control gate electrode layer, and the control gate dielectric layer being located between the sidewall of the control gate electrode layer and the sidewall of the groove. The manufacturing method of the split-gate MOSFET structure of the present invention can form a shielding gate dielectric layer that gradually becomes thicker from top to bottom, which helps to improve the breakdown voltage of the device, and the thickness of each part of the shielding gate dielectric layer is easy to control separately, which helps to achieve more refined voltage withstand characteristic regulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The process flow chart of the manufacturing method of the split-gate MOSFET structure of the present invention is shown.

[0022] Figure 2 It is a schematic diagram showing the structure obtained after forming a trench in a substrate according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0023] Figure 3 It is a schematic diagram showing the structure obtained after removing the portion of the first dielectric layer that is higher than the top surface of the substrate according to the method for manufacturing the split-gate MOSFET structure of the present invention.

[0024] Figure 4 It is a schematic diagram showing the structure obtained after the first dielectric layer is back-etched to obtain the dielectric filling portion in the manufacturing method of the split-gate MOSFET structure of the present invention.

[0025] Figure 5 It is a schematic diagram showing the structure obtained after forming a groove in the dielectric filling part according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0026] Figure 6 It is a schematic diagram showing the structure obtained after forming a shielding gate electrode layer in the groove according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0027] Figure 7 It is a schematic diagram showing the structure obtained after forming an isolation layer according to the method for manufacturing a split-gate MOSFET structure of the present invention.

[0028] Figure 8 It is a schematic diagram showing the structure obtained after forming the control gate dielectric layer according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0029] Fig. 9 It is a schematic diagram showing the structure obtained after forming the control gate electrode layer according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0030] Fig.10 It is a schematic diagram showing the structure obtained after the body region is formed according to the method for manufacturing the split-gate MOSFET structure of the present invention.

[0031] Fig.11 It is a schematic diagram showing the structure obtained after forming the source region according to the method for manufacturing the split-gate MOSFET structure of the present invention.

[0032] Fig.12 It is a schematic diagram showing the structure obtained after forming the interlayer dielectric layer and the contact holes according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0033] Fig.13 It is a schematic diagram showing the structure obtained after forming the upper metal layer according to the manufacturing method of the split-gate MOSFET structure of the present invention.

[0034] Explanation of the reference numerals: steps S1 to S5, 101 substrate, 102 groove, 103 dielectric filling portion, 103a first dielectric layer, 103b shielding gate dielectric layer, 104 groove, 105 shielding gate electrode layer, 106 isolation layer, 107 control gate dielectric layer, 108 control gate electrode layer, 109 body region, 110 source region, 111 interlayer dielectric layer, 112 contact hole, 113 upper metal layer. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0037] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0038] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0039] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0040] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0041] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] The present invention provides a method for manufacturing a split-gate MOSFET structure. Figure 1 , shown as a process flow chart of the method, comprising the following steps: S1: providing a substrate and forming a groove in the substrate; S2: forming a dielectric filling portion in the trench, wherein a top surface of the dielectric filling portion is lower than a top surface of the substrate; S3: forming a groove in the dielectric filling portion to obtain a shielding gate dielectric layer, wherein a width of a top opening of the groove is greater than a width of a bottom of the groove; S4: forming a shielding gate electrode layer in the groove; S5: forming an isolation layer, a control gate dielectric layer and a control gate electrode layer in the groove, wherein the control gate electrode layer is located above the shielding gate electrode layer, the isolation layer is located between the shielding gate electrode layer and the control gate electrode layer, and the control gate dielectric layer is located between the side wall of the control gate electrode layer and the side wall of the groove.

[0043] The above steps are described in detail below with reference to the structural diagram.

[0044] First see Figure 2 , perform the step S1: provide a substrate 101 and form a groove 102 in the substrate 101 .

[0045] As an example, the substrate 101 may be any suitable substrate known to those skilled in the art, including but not limited to a silicon substrate, a III-V compound substrate, a silicon carbide substrate, a silicon carbonitride substrate, and the like.

[0046] In some embodiments, the substrate 101 includes an epitaxial layer, and the trench 102 is formed in the epitaxial layer.

[0047] As an example, the method for forming the groove 102 includes at least one of dry etching and wet etching. For example, in some embodiments, a groove photomask can be used to perform a photolithography process to define the pattern of the groove, and then a deep groove is etched at the corresponding position by dry etching. The dry etching can be, for example, reactive ion etching RIE, and the etching gas can include a mixed gas such as Cl2, HBr, O2, N2, etc.

[0048] In some embodiments, the depth of the groove 102 is in the range of 2-10 microns, such as 3 microns, 5 microns, etc., and the width is in the range of 0.8-3 microns, such as 1 micron, 2 microns, etc.

[0049] Please see again Figure 3 to Figure 4 , executing the step S2: forming a dielectric filling portion 103 in the trench 102, wherein a top surface of the dielectric filling portion 103 is lower than a top surface of the substrate.

[0050] In some embodiments, forming the dielectric filling portion 103 in the trench 102 includes the following steps: (1) depositing a first dielectric layer 103 a by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable methods, wherein the first dielectric layer 103 a covers the substrate 101 and fills the trench 102 . In the present invention, the first dielectric layer 103 a completely fills the trench 102 ; (2) using chemical mechanical polishing (CMP), etching or other suitable methods to remove the portion of the first dielectric layer 103a that is higher than the top surface of the substrate 101, to obtain Figure 3 The structure shown; (3) The first dielectric layer 103a is back-etched so that the top surface of the first dielectric layer 103a is lower than the top surface of the substrate 101 by a preset distance, and the following is obtained: Figure 4In the structure shown, the remaining first dielectric layer 103 a in the trench 102 serves as the dielectric filling portion 103 .

[0051] Specifically, the first dielectric layer 103a may be made of silicon oxide, silicon nitride, silicon oxynitride or other suitable shielding gate dielectric materials.

[0052] In some embodiments, a portion of the first dielectric layer 103a in the groove 102 can be removed by a selective etching process without a mask to obtain the dielectric filling portion 103. The selective etching process can be dry etching or wet etching. For example, in one embodiment, the substrate is made of single crystal silicon, and the first dielectric layer 103a is made of silicon oxide. When selectively etching a portion of the first dielectric layer 103a in the groove 102, CF4 / CHF3 gas with a ratio of 3:1 can be used as a reaction gas for dry etching, or a diluted hydrofluoric acid (HF) solution can be used for wet etching.

[0053] In some embodiments, the preset distance ranges from 0.6 to 1.8 microns, such as 0.8 microns, 1 micron, 1.2 microns, 1.5 microns, etc.

[0054] Please see again Figure 5 , performing the step S3: forming a groove 104 in the dielectric filling portion 103 to obtain a shielding gate dielectric layer 103 b , wherein a width W1 of a top opening of the groove 104 is greater than a bottom width W2 of the groove 104 .

[0055] In some embodiments, forming the groove 104 in the medium-filled portion 103 includes the following steps: (1) forming a patterned mask layer by using a photolithography process, wherein the patterned mask layer covers the substrate 101 and the dielectric filling portion 103 and has a mask opening at a position where the groove 104 is to be formed; (2) Etching the dielectric filling portion 103 based on the patterned mask layer to obtain the groove 104 .

[0056] Specifically, since the width W1 of the top opening of the groove 104 is greater than the bottom width W2 of the groove 104, the groove 104 has an inclined sidewall, so that the shielding gate dielectric layer 103b has a structure that is narrow at the top and wide at the bottom. In other words, the shielding gate dielectric layer 103b on the sidewall of the trench 102 gradually becomes thicker from top to bottom.

[0057] In some embodiments, the sidewall inclination angle θ of the groove 104 ranges from 80° to 89°.

[0058] Specifically, the groove 104 can be obtained by dry etching, wet etching or a combination of the two. For example, in some embodiments, the groove 104 is formed by ion beam etching, wherein the ion beam is incident on the surface of the medium filling portion 103 at a certain angle, and the material is removed by physical sputtering. The larger the incident angle of the ion beam, the more obvious the inclination angle of the side wall of the groove 104.

[0059] In other embodiments, the groove 104 is formed by reactive ion etching (RIE), wherein RIE combines chemical reaction and physical sputtering, and the etching gas generates active ions in the plasma, and these ions are vertically incident on the surface of the dielectric filling part 103 to achieve anisotropic etching. By adjusting the gas composition (such as increasing the flow rate of the polymer generating gas), a polymer layer can be formed during the etching process to obtain an inclined side wall.

[0060] In some other embodiments, the groove 104 is formed by plasma etching, etc., wherein during the plasma etching process, the etching gas generates active ions and free radicals in the plasma, and these active substances chemically react with the material of the dielectric filling part 103 to achieve etching. By adjusting the flow rate and composition of the etching gas, the anisotropy of the etching can be controlled to achieve an inclined groove sidewall.

[0061] In some other embodiments, the inclined groove sidewall may be achieved by step-etching, that is, by multiple etching steps.

[0062] Specifically, Figure 5 As shown, the thickness of the shielding gate dielectric layer 103b located at the bottom wall of the trench 102 is D1, the bottom end thickness of the shielding gate dielectric layer located at the side wall of the trench 102 is D2, and the top end thickness of the shielding gate dielectric layer located at the side wall of the trench 102 is D3. In some embodiments, D1>D2>D3, that is, the thickness of the shielding gate dielectric layer at the bottom wall of the trench 102 is thicker than the thickness of the shielding gate dielectric layer at the side wall of the trench 102, and the thickness of the shielding gate dielectric layer at the side wall of the trench 102 gradually increases from top to bottom.

[0063] In some embodiments, D1 / D2 may range from 1.2 to 3, for example, 1.3, 1.5, 1.8, 2.0, 2.5, 2.8, etc., and D1 / D3 may range from 1.5 to 4, for example, 1.6, 1.8, 2.0, 2.5, 2.8, 3, 3.2, 3.5, 3.7, 3.9, etc.

[0064] Specifically, the thickness of the shield gate dielectric layer 103b located at the bottom wall of the groove 102 can be controlled by controlling the etching depth of the groove 104, that is, the control of D1 can be achieved; the inclination angle of the side wall of the groove 102 can be controlled by controlling the width of the mask opening and the specific etching process parameters, that is, the control of D2 and D3 can be achieved. In other words, the manufacturing method of the split-gate MOSFET structure of the present invention can control the thickness of each part of the shield gate dielectric layer separately, and achieve more refined voltage resistance characteristic regulation.

[0065] It should be pointed out that the thickness of each part of the shielding gate dielectric layer 103 b can be set according to the withstand voltage requirement of the actual device, and is not particularly limited in the present invention.

[0066] Please see again Figure 6 , executing the step S4: forming a shielding gate electrode layer 105 in the groove 104 .

[0067] As an example, the shielding gate electrode layer 105 may be made of doped polysilicon, metal (such as TiN, TaN), metal silicide (such as WSi 2 ) or other suitable materials.

[0068] In some embodiments, low pressure chemical vapor deposition (LPCVD) can be used to deposit polysilicon or physical vapor deposition (PVD) can be used to deposit metal as a shielding gate electrode material to fill the groove 104, and excess shielding gate electrode material outside the groove 104 can be removed by chemical mechanical polishing (CMP), etching and other processes to obtain the shielding gate electrode layer 105 located in the groove 104.

[0069] Please see again Figures 7 to 9 , perform the step S5: form an isolation layer 106, a control gate dielectric layer 107 and a control gate electrode layer 108 in the groove 102, the control gate electrode layer 108 is located above the shielding gate electrode layer 105, the isolation layer 106 is located between the shielding gate electrode layer 105 and the control gate electrode layer 108, and the control gate dielectric layer 107 is located between the side wall of the control gate electrode layer 108 and the side wall of the groove 102.

[0070] As an example, the isolation layer 106 may be made of silicon oxide, silicon nitride or other suitable insulating materials to achieve electrical isolation between the control gate electrode layer 108 and the shielding gate electrode layer 105 .

[0071] As an example, the control gate dielectric layer 107 may be made of silicon oxide, silicon oxynitride (SiON), a high-k dielectric (such as HfO 2 , Al 2 O 3 , etc.) or other suitable gate dielectric materials.

[0072] As an example, the thickness of the control gate dielectric layer 107 is less than the thickness of any part of the shield gate dielectric layer 103b. For example, the thickness of the control gate dielectric layer 107 ranges from 300 angstroms to 1000 angstroms, and may specifically be 500 angstroms, 600 angstroms, 700 angstroms or 800 angstroms.

[0073] As an example, the control gate electrode layer 108 may be made of doped polysilicon, metal (such as TiN, TaN), metal silicide (such as WSi 2 ) or other suitable gate materials.

[0074] In some embodiments, forming the isolation layer 106, the control gate dielectric layer 107, and the control gate electrode layer 108 in the trench 102 includes the following steps: (1) If Figure 7 As shown, a silicon oxide layer is grown as the isolation layer 106 by high density plasma chemical vapor deposition (HDP CVD) or other suitable methods, and then etched back to make the isolation layer 106 have a set thickness; (2) If Figure 8 As shown, a thermal oxide layer of a certain thickness is grown on the exposed sidewall of the trench 102 by a thermal oxidation method to serve as the control gate dielectric layer 107; (3) If Fig. 9 As shown, a polysilicon layer is deposited as the control gate electrode layer 108 by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or other suitable methods, and excess polysilicon material outside the groove 102 is removed by chemical mechanical polishing (CMP), etching and other processes.

[0075] As an example, the method for manufacturing a split-gate MOSFET structure of the present invention further comprises the following steps: (1) If Fig.10 As shown, ion implantation, annealing and other processes are used to form a body region 109 on the upper surface of the substrate 101 on both sides of the trench 102. The bottom surface of the body region 109 is higher than the top surface of the shielding gate electrode layer 105. The implanted ions may include boron (B), and the implantation dose range is 6e12 cm -2 ~2e13c m -2 (e.g. 1e13 cm -2 , 1.5e13 cm -2 ), the injection energy range is 70 keV~300 keV (for example, 100 keV, 200 keV).

[0076] (2) If Fig.11As shown, the source region 110 is formed on the upper surface layer of the body region 109 by ion implantation, annealing and other processes. The implanted ions may include arsenic (As) and the implantation dose range is 1e15 cm -2 ~2e16 cm -2 (e.g. 5e15 cm -2 , 1e16 cm -2 ), the injection energy range is 60 keV~200 keV (for example 80keV, 150keV).

[0077] (3) If Fig.12 As shown, an interlayer dielectric layer 111 is formed on the substrate 101 by chemical vapor deposition or other suitable processes, and a contact hole 112 is formed by photolithography, etching and other processes. The contact hole 112 penetrates the interlayer dielectric layer 111 and extends into the source region 110 and the body region 109. The interlayer dielectric layer 111 can be a silicon oxide layer or other suitable dielectric layer. The depth of the contact hole 112 can be, for example, 0.3 microns to 0.6 microns.

[0078] (4) If Fig.13 As shown, an upper metal layer 113 is formed on the interlayer dielectric layer 111 and in the contact hole 112 by sputtering, electroplating or other suitable methods to be electrically connected to the source region 110 and the body region 109. The upper metal layer 113 can be made of, for example, Al, Cu, W or other suitable conductive metal materials. The thickness of the upper metal layer 113 can be, for example, 2 microns to 8 microns.

[0079] As an example, the method for manufacturing a split-gate MOSFET structure of the present invention may further form a drain region and a back metal layer electrically connected to the drain region on the back side of the substrate 101 .

[0080] The manufacturing method of the split-gate MOSFET structure of the present invention can not only thicken the shielding gate dielectric layer at the bottom of the trench, but also gradually thicken the shielding gate dielectric layer at the sidewall of the trench from top to bottom, thereby effectively improving the breakdown voltage of the device and enhancing the voltage resistance performance of the device.

[0081] The present invention also provides a split-gate MOSFET structure, see Fig.13, which is a cross-sectional schematic diagram of the split-gate MOSFET structure, includes a substrate 101, a trench 102, a dielectric filling portion 103, a recess 104, a shielding gate electrode layer 105, an isolation layer 106, a control gate electrode layer 108 and a control gate dielectric layer 107, wherein the trench 102 is opened on the top surface of the substrate 101, the dielectric filling portion 103 is located in the trench 102, and the top surface of the dielectric filling portion 103 is lower than the top surface of the substrate 101, and the recess 104 is opened on the top surface of the dielectric filling portion 103. The top surface is used to form a shielding gate dielectric layer 103b, the width of the top opening of the groove 104 is greater than the bottom width of the groove 104, the shielding gate electrode layer 105 is located in the groove 104, the control gate electrode layer 108 is located in the groove 102 and above the shielding gate electrode layer 105, the isolation layer 106 is located between the shielding gate electrode layer 105 and the control gate electrode layer 108, and the control gate dielectric layer 107 is located between the side wall of the control gate electrode layer 108 and the side wall of the groove 102.

[0082] As an example, the sidewall inclination angle of the groove 104 ranges from 80° to 89°.

[0083] As an example, the thickness of the shielding gate dielectric layer 103b located at the bottom wall of the trench 102 is D1, the bottom thickness of the shielding gate dielectric layer 103b located at the side wall of the trench 102 is D2, and the top thickness of the shielding gate dielectric layer 103b located at the side wall of the trench 102 is D3, wherein D1>D2>D3.

[0084] As an example, the range of D1 / D2 is 1.2~3, and the range of D1 / D3 is 1.5~4.

[0085] As an example, the split-gate MOSFET structure also includes a body region 109, a source region 110, an interlayer dielectric layer 111, a contact hole 112 and an upper metal layer 113, wherein the body region 109 is located on the upper surface layer of the substrate 101 on both sides of the groove 102, the source region 110 is located on the upper surface layer of the body region 109, the interlayer dielectric layer 111 is located above the substrate 101, the contact hole 112 penetrates the interlayer dielectric layer 111 and extends into the source region 110 and the body region 109, and the upper metal layer 113 is located above the interlayer dielectric layer 111 and in the contact hole 112.

[0086] In the split-gate MOSFET structure of the present invention, the thickness of the shielding gate dielectric layer on the trench sidewall gradually increases from top to bottom, and the thickness of the shielding gate dielectric layer at the bottom of the trench can be greater than the thickness of the shielding gate dielectric layer on the trench sidewall, thereby having better voltage resistance performance.

[0087] In summary, the manufacturing method of the split-gate MOSFET structure of the present invention includes the following steps: forming a groove in a substrate; forming a dielectric filling portion in the groove, the top surface of the dielectric filling portion is lower than the top surface of the substrate; forming a groove in the dielectric filling portion to obtain a shielding gate dielectric layer, the width of the top opening of the groove is greater than the bottom width of the groove; forming a shielding gate electrode layer in the groove; forming an isolation layer, a control gate dielectric layer and a control gate electrode layer in the groove, the control gate electrode layer is located above the shielding gate electrode layer, the isolation layer is located between the shielding gate electrode layer and the control gate electrode layer, and the control gate dielectric layer is located between the side wall of the control gate electrode layer and the side wall of the groove. The manufacturing method of the split-gate MOSFET structure of the present invention can form a shielding gate dielectric layer that gradually becomes thicker from top to bottom, which helps to improve the breakdown voltage of the device, and the thickness of each part of the shielding gate dielectric layer is easy to control separately, which helps to achieve more refined voltage resistance characteristic regulation. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a split-gate MOSFET structure, characterized in that: The following steps are involved: providing a substrate, and forming a groove in the substrate; forming a dielectric filling portion in the trench, wherein a top surface of the dielectric filling portion is lower than a top surface of the substrate; forming a groove in the dielectric filling portion to obtain a shielding gate dielectric layer, wherein the width of the top opening of the groove is greater than the bottom width of the groove; forming a shielding gate electrode layer in the groove; An isolation layer, a control gate dielectric layer and a control gate electrode layer are formed in the groove, wherein the control gate electrode layer is located above the shielding gate electrode layer, the isolation layer is located between the shielding gate electrode layer and the control gate electrode layer, and the control gate dielectric layer is located between the side wall of the control gate electrode layer and the side wall of the groove.

2. The method for manufacturing a split-gate MOSFET structure according to claim 1, characterized in that: Forming a dielectric filling portion in the trench comprises the following steps: Depositing a first dielectric layer, wherein the first dielectric layer covers the substrate and fills the trench; removing a portion of the first dielectric layer that is higher than the top surface of the substrate; The first dielectric layer is etched back so that the top surface of the first dielectric layer is lower than the top surface of the substrate by a preset distance, thereby obtaining the dielectric filling portion.

3. The method for manufacturing a split-gate MOSFET structure according to claim 1, characterized in that: Forming a groove in the dielectric filling portion includes the following steps: forming a patterned mask layer, wherein the patterned mask layer covers the substrate and the dielectric filling portion and has a mask opening at a position where the groove is to be formed; The dielectric filling portion is etched based on the patterned mask layer to obtain the groove.

4. The method for manufacturing a split-gate MOSFET structure according to claim 1, wherein: The side wall inclination angle of the groove ranges from 80° to 89°.

5. The method for manufacturing a split-gate MOSFET structure according to claim 1, characterized in that: The thickness of the shielding gate dielectric layer at the bottom wall of the trench is D1, the bottom thickness of the shielding gate dielectric layer at the side wall of the trench is D2, and the top thickness of the shielding gate dielectric layer at the side wall of the trench is D3, wherein D1>D2>D3.

6. The method for manufacturing a split-gate MOSFET structure according to claim 5, characterized in that: The range of D1 / D2 is 1.2~3, and the range of D1 / D3 is 1.5~4.

7. The method for manufacturing a split-gate MOSFET structure according to claim 1, characterized in that: The following steps are also included: forming a body region on the upper surface layer of the substrate at both sides of the trench; forming a source region on the upper surface of the body region; forming an interlayer dielectric layer above the substrate; forming a contact hole, wherein the contact hole penetrates the interlayer dielectric layer and extends into the source region and the body region; An upper metal layer is formed above the interlayer dielectric layer and in the contact hole.

8. A split-gate MOSFET structure, characterized in that: include: substrate; A groove is formed on the top surface of the substrate; A dielectric filling portion, located in the groove, wherein a top surface of the dielectric filling portion is lower than a top surface of the substrate; A groove is formed on the top surface of the dielectric filling portion to form a shielding gate dielectric layer, wherein the width of the top opening of the groove is greater than the bottom width of the groove; A shielding gate electrode layer is located in the groove; a control gate electrode layer, located in the trench and above the shield gate electrode layer; an isolation layer, located between the shielding gate electrode layer and the control gate electrode layer; The control gate dielectric layer is located between the sidewall of the control gate electrode layer and the sidewall of the trench.

9. The split-gate MOSFET structure according to claim 8, characterized in that: The side wall inclination angle of the groove ranges from 80° to 89°.

10. The split-gate MOSFET structure according to claim 8, characterized in that: The thickness of the shielding gate dielectric layer at the bottom wall of the trench is D1, the bottom thickness of the shielding gate dielectric layer at the side wall of the trench is D2, and the top thickness of the shielding gate dielectric layer at the side wall of the trench is D3, wherein D1>D2>D3.

11. The split-gate MOSFET structure according to claim 10, characterized in that: The range of D1 / D2 is 1.2~3, and the range of D1 / D3 is 1.5~4.

12. The split-gate MOSFET structure according to claim 8, characterized in that: Also includes: A body region located on the upper surface layer of the substrate at both sides of the trench; A source region, located on the upper surface of the body region; An interlayer dielectric layer, located above the substrate; A contact hole, penetrating the interlayer dielectric layer and extending into the source region and the body region; The upper metal layer is located above the interlayer dielectric layer and in the contact hole.

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