Semiconductor device and forming method thereof

Abstract

The semiconductor device includes: a nanostructure stack; a first layer over the nanostructure stack and offset relative to the nanostructure stack; an internal spacer between the first layer and the nanostructure stack; and a gate structure wrapping the nanostructure stack. The gate structure includes a gate dielectric on the nanostructure and between the internal spacer and the nanostructure of the nanostructure stack; and a gate metal on the gate dielectric. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack comprising alternating first and second semiconductor layers on a substrate; forming a sacrificial gate structure on the stack; forming a gate spacer adjacent to the sacrificial gate structure; releasing the first semiconductor layer by removing the second semiconductor layer; forming a gate dielectric on the side surfaces of the first semiconductor layer and the gate spacer; forming a reduced gate dielectric by removing a portion of the gate dielectric from the side surfaces of the gate spacer, the portion being laterally adjacent to the first semiconductor layer; and forming a gate metal layer on the reduced gate dielectric and the exposed portion of the gate spacer.

[0004] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a dielectric protection layer over a stack of alternating first and second nanostructures; forming a gate spacer adjacent to the first nanostructure; forming an internal spacer between the first nanostructures; releasing the first nanostructure by removing the second nanostructure; forming a gate dielectric on the first nanostructure, the dielectric protection layer and the gate spacer; forming a capping layer on the dielectric protection layer, the capping layer having a width exceeding the width of the dielectric protection layer; forming a reduced gate dielectric by removing a first portion of the gate dielectric from a side surface of the gate spacer, the portion having a width substantially equal to the width of the dielectric protection layer; and forming a gate metal layer on the reduced gate dielectric and the exposed portion of the gate spacer.

[0005] Still other embodiments of the present application provide a semiconductor device comprising: a nanostructure stack; a first layer located above the nanostructure stack and offset relative to the nanostructure stack; an internal spacer located between the first layer and the nanostructure stack; and a gate structure wrapping the nanostructure stack, the gate structure comprising: a gate dielectric located on the nanostructure and between the internal spacer and the nanostructure of the nanostructure stack; and a gate metal located on the gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A and Figure 1B is a schematic cross-sectional side view of a portion of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figures 2A to 18 are views of various embodiments of semiconductor structures at various stages of fabrication according to various aspects of the disclosed embodiments.

[0009] Fig.19 is a flow chart of a method of forming an IC device according to various embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Terms expressing relative degrees, such as "about," "substantially," and the like, should be interpreted as meaning that one of ordinary skill in the art would understand given the current technical specifications.

[0013] The terms "first", "second", "third", etc. may be used herein to describe the order of events or the sequential order of elements, but may be interchanged or varied in some contexts. For example, a second layer may be formed on a first layer (e.g., sequentially after the first layer), but in some contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0014] The term "surrounding" may be used herein to describe a structure that completely or partially surrounds another element or structure, for example in three dimensions. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In another example, a first structure may partially wrap around a second structure, for example, by wrapping around three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0015] A source / drain region may refer to a source region or structure or a drain region or structure, alone or together depending on the context.

[0016] The presently disclosed embodiments relate generally to semiconductor devices, and more particularly to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0017] Embodiments of the present disclosure include a gate protection top (GPT) hard mask or "dielectric protection layer" that can help selectively remove some of the high-k dielectric material from the low-k dielectric spacers. By reducing the amount of high-k dielectric material on the low-k dielectric spacers, embodiments of the present disclosure reduce parasitic capacitance and improve device performance. Reliability is improved by increasing the distance between the source / drain contacts and the gate contact via thicker low-k dielectric spacers that replace the HK material at the sidewalls.

[0018] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, less than the spacing obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0019] Figure 1A and Figure 1B is a schematic cross-sectional side view of a portion of a nanostructured device 10 according to various embodiments. Figure 1A A view in the XZ plane is shown. Figure 1B A view in the YZ plane perpendicular to the XZ plane is shown. Figure 1A , Figure 1B The nanostructured device 10 is provided to provide a method for understanding Figures 2A to 18 The context of the technical features and benefits of various embodiments described in the present invention.

[0020] refer to Figure 1A , nanostructure devices 20A, 20B may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). For example, nanostructure device 20A may be a PFET and nanostructure device 20B may be an NFET. Nanostructure devices 20A, 20B are formed over and / or in substrate 110 and generally include gate structures 200 (see FIG. 1 ) that span and / or wrap semiconductor channels 22A, 22B, 22C (alternately referred to as “nanostructures”) over semiconductor fins 32 that protrude from and are separated by isolation structures 36. Figure 1B ). The semiconductor channels 22A, 22B, 22C may be collectively referred to as channels 22. The gate structure 200 controls the current flowing through the channels 22A, 22B, 22C between the source / drain 82N, 82P on either side thereof.

[0021] Nanostructure devices 20A, 20B are shown to include three channels 22A, 22B, 22C, which are laterally adjacent to source / drain features 82N, 82P and are covered and surrounded by gate structure 200. Typically, the number of channels 22 is two or more, such as three or four or more, but may be one in some embodiments. Based on the voltage applied at gate structure 200 and at source / drain features 82N, 82P, gate structure 200 controls the flow of current through channels 22A, 22B, 22C to and from source / drain features 82N, 82P.

[0022] In some embodiments, the fin structure 32 comprises silicon. In some embodiments, the nanostructure device 20B comprises an NFET and its source / drain features 82N comprise silicon phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, SiGe, combinations thereof, or the like. In some embodiments, the nanostructure device 20A comprises a PFET and its source / drain features 82P comprise undoped or doped silicon germanium (SiGe) to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. In general, the source / drain features 82N, 82P may comprise any combination of suitable semiconductor materials and suitable dopants. As Figure 1B As depicted in FIG. 4 , adjacent fins 32 may be separated by a distance D2 in a range of about 20 nm to about 60 nm.

[0023] Each of the channels 22A, 22B, 22C includes a semiconductor material, for example, silicon or germanium or a semiconductor alloy (such as SiGe, GeSn, SiGeSn, GaAs, InGaAs), one or more two-dimensional materials having semiconductor properties (such as MoS2, WS2), a combination thereof, etc. The channels 22A, 22B, 22C are nanostructures (for example, having at least one dimension in the range of several nanometers), and may also each have an elongated shape and extend in the X direction. In some embodiments, each of the channels 22A, 22B, 22C has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of the channels 22A, 22B, 22C may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination thereof.

[0024] In some embodiments, the lengths of the channels 22A, 22B, 22C (eg, measured in the X direction) may be different from each other, for example, due to tapering during a fin etching process (see Figure 3A , Figure 3B). In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. Each of channels 22A, 22B, and 22C may not have a uniform thickness (e.g., along the X-axis direction), for example, due to a channel trimming process used to expand the spacing between channels 22A, 22B, and 22C (e.g., measured in the Z-axis direction) to increase the gate structure manufacturing process window. For example, the middle portion of each of channels 22A, 22B, and 22C may be thinner than the two ends of each of channels 22A, 22B, and 22C. Such shapes may be collectively referred to as "dog bone" shapes.

[0025] In some embodiments, the spacing between channels 22A, 22B, 22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 5.5 nanometers (nm) and about 15 nm, but ranges above or below the range may also be beneficial. In some embodiments, the thickness of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 1 nm and about 10 nm, but ranges above or below the range may also be beneficial. In some embodiments, the width of each of channels 22A, 22B, 22C (e.g., measured in the Y direction) is in a range between about 10 nm and about 10 nm, but ranges above or below the range may also be beneficial. Figure 3B , orthogonal to the XZ plane) is at least about 8 nm, however in some embodiments the width may be less than 8 nm.

[0026] The gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, respectively. In some embodiments, the gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, and the channels 22A, 22B, and 22C are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interface layer (IL) 210, one or more gate dielectric layers 600 on the interface layer 210, and a metal core layer 290 on the gate dielectric layer 600. For example, one or more work function adjustment layers 900 (see Fig.17 ) may be present on the gate dielectric layer 600 between the gate dielectric layer 600 and the metal core layer 290.

[0027] An interface layer 210 (which may be an oxide of the material of the channels 22A, 22B, 22C) is formed on the exposed areas of the channels 22A, 22B, 22C and the top surface of the fin 32. The interface layer 210 promotes adhesion of the gate dielectric layer 600 to the channels 22A, 22B, 22C. In some embodiments, the interface layer 210 has a thickness of about 5 angstroms (A) to about 50 angstroms (A). In some embodiments, the interface layer 210 has a thickness of about 10 A. An interface layer 210 having a thickness that is too thin may exhibit voids or insufficient adhesion properties. An interface layer 210 that is too thick may consume the gate fill window, which is related to threshold voltage adjustment and resistance. In some embodiments, the interface layer 210 is doped with a dipole such as lanthanum for threshold voltage adjustment.

[0028] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 Å to about 100 Å. The gate dielectric layer 600 may be a single layer or a multilayer.

[0029] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material such as Co, W, Ru, combinations thereof, etc. In some embodiments, the metal core layer 290 is or includes a compound or alloy based on Co, W, or Ru, including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, etc. Between the channels 22A, 22B, 22C, the metal core layer 290 is circumferentially surrounded (in the cross-sectional view) by one or more work function metal layers 900, which in turn are circumferentially surrounded by a gate dielectric layer 600, which is circumferentially surrounded by an interface layer 210.

[0030] like Figure 1A, the nanostructured devices 20A, 20B may also include a source / drain contact 120 formed above the source / drain features 82N, 82P. The source / drain contact 120 may include a core layer that is or includes a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The core layer may be surrounded by one or more liner (or "barrier") layers such as SiN or TiN, which helps prevent or reduce material from diffusing from and into the source / drain contact 120. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 50 nm.

[0031] The silicide layer 118 may be located between the source / drain components 82N, 82P and the source / drain contact 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide layer 118 may have a thickness in the range of about 1nm to about 10nm. A thickness lower than about 1nm may result in insufficient reduction of the contact resistance. A thickness above about 10nm may cause an electrical short circuit of the nanostructure 22. In some embodiments, the silicide layer 118 is present below the etch stop layer 131 and is in contact with the etch stop layer 131 .

[0032] like Figure 1B As depicted in FIG. 1 , the nanostructured devices 20A, 20B may also include an interlayer dielectric (ILD) 130. The ILD 130 provides electrical isolation between the various components of the nanostructured devices 20A, 20B discussed above, such as between adjacent pairs of source / drain contacts 120 and / or source / drain 82P (or source / drain 82N). An etch stop layer 131 may be formed prior to forming the ILD 130 and may be laterally located between the ILD 130 and the gate spacers 41 and vertically located between the ILD 130 and the source / drain features 82N, 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x, Al2O3 or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm. In some embodiments, in the absence of ILD 130 (e.g., completely removed before forming source / drain contacts 120), the etch stop layer 131 may contact the source / drain contacts 120. Before forming the source / drain contacts 120, the etch stop layer 131 may be trimmed, for example, in the X-axis direction to improve the filling quality of the source / drain contacts 120.

[0033] Nanostructured devices 20A, 20B include gate spacers 41 disposed on the sidewalls of metal core layer 290 above channel 22C, and internal spacers 74 disposed on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, 22C. Internal spacers 74 are also disposed between channels 22A, 22B, 22C. Figure 1A In the embodiment depicted in , the gate spacer 41 includes a first spacer layer 41A and a second spacer layer 41B on the first spacer layer 41A. The first spacer layer 41A and the second spacer layer 41B may each include a dielectric material, for example, a low-k material such as SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, the second spacer layer 41B does not exist. The materials of the first spacer layer 41A and the second spacer layer 41B may be the same or different from each other. In some embodiments, the upper portion of the second spacer layer 41B (or the first spacer layer 41A when the second spacer layer 41B does not exist) may be partially or completely removed to increase the aspect ratio of the opening through which the source / drain regions 82N, 82P are formed. Figure 1A An embodiment is depicted in which the upper portion of the second spacer layer 41B is not thinned.

[0034] Fig.19 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of an embodiment of the present disclosure is depicted. The method 1000 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 1000. Additional steps may be provided before, during, and after the method 1000, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2A to 18 The method 1000 is described with reference to partial perspective views and / or cross-sectional views of a workpiece at different stages of manufacture shown in FIG. For the avoidance of doubt, throughout the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that because the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0035] Figures 2A to 18 is a diagram of an intermediate stage in the fabrication of a FET, such as a nanostructure FET, according to some embodiments.

[0036] exist Figure 2A and Figure 2B In the embodiment, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0037] In addition, Figure 2A and Figure 2B In the embodiment of the present invention, a multilayer stack 25 or "lattice" is formed over a substrate 110 of alternating layers of first semiconductor layers 21A, 21B (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layers 21 may be formed of a first semiconductor material such as Si, SiGe, Ge, GaAs, InGaAs, MoS, WS2, etc., and the second semiconductor layers 23 may be formed of a second semiconductor material such as SiGe, Ge, Si, InGaAs, AlGaAs, etc. Each of the layers 21, 23 of the multilayer stack 25 may be formed to have a thickness in a range of about 1 nm to about 10 nm.

[0038] Three layers of the first semiconductor layer 21 and four layers of the second semiconductor layer 23 are shown. In some embodiments, the multilayer stack 25 can include fewer or additional numbers of the first semiconductor layers 21 and the second semiconductor layers 23. Although the multilayer stack 25 is shown as including the second semiconductor layer 23 as the bottom-most layer and the top-most layer, in some embodiments, the bottom-most layer and / or the top-most layer of the multilayer stack 25 can be the first semiconductor layer 21.

[0039] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of a nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of a nanoFET.

[0040] exist Figure 2A and Figure 2B In the embodiment of the present invention, a sacrificial capping structure 26S is formed on the multilayer stack 25. The sacrificial capping structure 26S may include third semiconductor layers 29L', 29U' with a fourth semiconductor layer 28S' therebetween. The third semiconductor layers 29L', 29U' may include the same semiconductor material (e.g., silicon) as the first semiconductor layer 21. The fourth semiconductor layer 28S' may include a third semiconductor material, such as a high germanium concentration semiconductor material. The high germanium concentration semiconductor material may be a SiGe material having a germanium concentration exceeding about 50%, such as about 50% to 100% (i.e., pure Ge). In some embodiments, a lower third semiconductor layer 29L' is formed, and then a fourth semiconductor layer 28S' is formed on the lower third semiconductor layer 29L', and then an upper third semiconductor layer 29U' is formed on the fourth semiconductor layer 28S'. The lower third semiconductor layer 29L' and the upper third semiconductor layer 29U' may still be the same semiconductor material (e.g., silicon) as the first semiconductor layer 21, or may be other semiconductor materials. The formation of the third semiconductor layer 29L′, 29U′ and the fourth semiconductor layer 28S′ may be similar in most respects to the formation of the first semiconductor layer 21 and the second semiconductor layer 23 described previously.

[0041] exist Figure 3A and Figure 3B In the embodiment, the fin 32 is formed in the substrate 110, the nanostructures 22 and 24 are formed in the multilayer stack 25, and the third semiconductor nanostructures 29L, 29U and the fourth semiconductor nanostructure 28S are also formed, corresponding to Fig.19Step 1100. In some embodiments, the nanostructures 22, 24 and the fins 32 may be formed by etching grooves in the multilayer stack 25, the sacrificial capping structure 26S and the substrate 110. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The first nanostructures 22A, 22B, 22C (hereinafter also referred to as "channels 22") are formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The third nanostructures 29L, 29U are formed by the third semiconductor layers 29L', 29U'. The fourth nanostructure 28S is formed by the fourth semiconductor layer 28S'. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18 nm to about 100 nm. To simplify the description, in Figure 3A and Figure 3B A portion of device 10 including two fins 32 is shown in FIG. Fig.19 The process 1000 shown in FIG. 1 can be extended to any number of fins and is not limited to Figures 3A to 18 Two fins 32 are shown in FIG.

[0042] The fin 32 and the nanostructures 22, 24 can be patterned by any suitable method. For example, the fin 32 and the nanostructures 22, 24 can be formed using one or more photolithography processes including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing a spacing smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer can be formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers can be used to pattern the fin 32.

[0043] Figure 3A and Figure 3B The fin 32 is shown with tapered sidewalls, such that the width of the fin 32 and / or each of the nanostructures 22, 24 increases continuously in a direction toward the substrate 110. In such an embodiment, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fin 32 and nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0044] exist Figure 3A and Figure 3BIn the embodiment of the present invention, an isolation region, component or structure 36 is formed adjacent to the fin 32, which may be a shallow trench isolation (STI) region, component or structure. The isolation region 36 may be formed by depositing an insulating material over the substrate 110, the fin 32 and the nanostructures 22, 24 and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fin 32 and the nanostructures 22, 24. Thereafter, a core material, such as those discussed above, may be formed over the liner.

[0045] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material over the nanostructures 22, 24. After the removal process is completed, the top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material.

[0046] The insulating material is then recessed to form isolation regions 36. After recessing, upper portions of nanostructures 22, 24 and fins 32 may protrude from between adjacent isolation regions 36. Isolation regions 36 may have top surfaces that are flat, convex, concave, or a combination thereof as shown. In some embodiments, isolation regions 36 are recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to insulating materials and leaves fins 32 and nanostructures 22, 24 substantially unchanged.

[0047] In some embodiments, the fourth semiconductor nanostructure 28S has the same width in the Y-axis direction as the channel 22, which is formed by an anisotropic etching process that forms a trench through the stack 25 and the sacrificial capping structure 26S. Therefore, in most embodiments, the gate protection top (GPT) hard mask or "dielectric protection layer" 78 (see FIG. 1 ) of the fourth semiconductor nanostructure 28S is replaced in a later operation. Fig. 7A) has the same width as the channel 22 in the Y-axis direction. The GPT hard mask 78 is used to protect the underlying channel 22 during etching of the mask layer 500 used in the selective etching of the gate dielectric layer 600. In some embodiments, the GPT hard mask 78 has a width in the Y-axis direction that is slightly greater than the width of the channel 22. In some embodiments, the GPT hard mask 78 has a width in the Y-axis direction that exceeds the width of the channel 22 in the Y-axis direction. In some embodiments, the protruding portion of the GPT hard mask 78 that exceeds the channel 22 is in the range of about 0 nm to about 4 nm. Various methods can be used to achieve the GPT hard mask 78 having a width in the Y-axis direction that is slightly greater than the width of the channel 22. For example, an etchant that is selective to the material of the channel 22 compared to the material with respect to the GPT hard mask 78 can be used to perform a trimming procedure on the channel 22. For example, the etch selectivity of the etchant between the semiconductor material of the channel 22 and the dielectric material of the GPT hard mask 79 can range between about 10x and about 100x, inclusive. In some embodiments, the GPT hard mask 78 has a width equal to the width of the channel 22 .

[0048] FIG. 2A to FIG. 3B One embodiment of forming the fin 32 and nanostructures 22, 24 is shown (e.g., etched later). In some embodiments, the fin 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., etched first). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0049] exist Figure 3A and Figure 3B In the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24 and / or isolation regions 36. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, but in-situ doping and implantation doping may be used together.

[0050] exist FIG. 4A to FIG. 4C In the embodiment, a dummy or sacrificial gate structure 40 is formed over the fin 32, the nanostructures 22, 24, the third conductor nanostructures 29L, 29U and the fourth semiconductor nanostructure 28S, corresponding to Fig.19Step 1200. A dummy or sacrificial gate layer 45 is formed over the fin 32 and / or nanostructures 22, 24. The sacrificial gate layer 45 may be or include a material having a high etch selectivity relative to the isolation region 36. The sacrificial gate layer 45 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon (poly-silicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, etc., is formed over the sacrificial gate layer 45. In some embodiments, before the sacrificial gate layer 45, a gate dielectric layer 43 is formed between the sacrificial gate layer 45 and the fin 32 and / or nanostructures 22, 24. In some embodiments, mask layer 47 includes a first mask layer 47A in contact with sacrificial gate layer 45, and a second mask layer 47B on and in contact with first mask layer 47A. First mask layer 47A may be or include the same or different material as second mask layer 47B.

[0051] A spacer layer 41 is formed over the sidewalls of the mask layer 47 and the sacrificial gate layer 45. According to some embodiments, the spacer layer 41 is or includes an insulating material such as SiOCN, SiOC, SiCN, etc. (or reference numerals). Figure 1A and Figure 1B The spacer layer 41 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the sacrificial gate layer 45. According to some embodiments, the portion of the spacer material layer located between the sacrificial gate structures 40 is removed using an anisotropic etching process. In some embodiments, as shown in FIG. Figure 4B , Figure 4C As shown in detail in FIG. 1 , the spacer layer 41 includes a first spacer layer 41A separated from the nanostructure 22C by the sacrificial capping structure 26S and in contact with the gate dielectric layer 43, the sacrificial gate layer 45, and the first mask layer 47A and the second mask layer 47B. The second spacer layer 41B of the spacer layer 41 may be in contact with the first spacer layer 41A. The first spacer layer 41A may be or include a material that is the same as or different from that of the second spacer layer 41B.

[0052] exist Figure 5A and Figure 5BIn the embodiment, source / drain openings 59 are formed by performing an etching process to etch the protruding fins 32, the third conductor nanostructures 29L, 29U and the fourth semiconductor nanostructures 28S and / or the portions of the nanostructures 22, 24 that are not covered by the sacrificial gate structure 40. The recess may be anisotropic so that the portions of the fins 32 directly below the sacrificial gate structure 40 and the spacer layer 41 are protected and substantially not etched. According to some embodiments, the top surface of the recessed fins 32 may be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, the top surface of the recessed fins 32 may be lower than the top surface of the isolation region 36, such as Figure 5B For simplicity, Figure 5A Three vertical stacks of nanostructures 22, 24 after the etching process are depicted. In general, the etching process may be used to form fewer or additional vertical stacks of nanostructures 22, 24 over the fins 32. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to removal of upper portions of the spacer layers 41A, 41B during the etching process. Figure 5B Fin spacers 41F are depicted, which are portions of the first spacer layer 41A and / or the second spacer layer 41B that overlie the isolation regions 36 adjacent to respective fins 32 .

[0053] exist Figure 5C and Figure 5D In the embodiment of the present invention, the upper third semiconductor nanostructure 29U and the fourth semiconductor nanostructure 28S are removed, and the groove 64 is formed by removing the end portion of the nanostructure 24. For example, a selective etching process is performed to recess the end portion of the nanostructure 24 exposed by the opening in the spacer layer 41 without substantially attacking the nanostructure 22 or slightly thinning the end portion of the nanostructure 22. In some embodiments, the selective etching process includes a chlorine or fluorine-based wet etching process. After the selective etching process, the groove 64 is formed at the position where the removed end portion of the nanostructure 24 was once located. Because the fourth semiconductor nanostructure 28S includes a high Ge% semiconductor material, and the nanostructure 24 includes a lower Ge% semiconductor material, the etching of the fourth semiconductor nanostructure 28S can be performed faster than the etching of the nanostructure 24, so that the entire fourth semiconductor nanostructure 28S can be removed, and only the end portion of the nanostructure 24 can be removed. The upper third semiconductor nanostructure 29U may have a thickness thinner than that of the lower third semiconductor nanostructure 29L in the Z-axis direction, which may allow the upper third semiconductor nanostructure 29U to be completely removed while only partially removing the lower third semiconductor nanostructure 29L. The removal of the fourth semiconductor nanostructure 28S forms an opening 28H in which the fourth semiconductor nanostructure 28S is located.

[0054] Then, in Fig. 6A and Figure 6B In the embodiment of the present invention, after forming the groove 64 and the opening 28H, an internal spacer layer 74L is formed to fill (partially or entirely) the groove 64 and the opening 28H formed by the previous selective etching process in the nanostructure 24. The internal spacer layer 74L can completely fill the opening 28H remaining after removing the upper third semiconductor nanostructure 29U and the fourth semiconductor nanostructure 28S. In some embodiments, there may be a seam or air gap in the material of the internal spacer layer 74L in the opening 28H. The internal spacer layer 74L can be a suitable dielectric material such as silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), etc. formed by a suitable deposition method such as PVD, CVD, ALD, etc.

[0055] exist Fig. 7A and Figure 7B In the embodiment of the present invention, after forming the inner spacer layer 74L, an etching process, such as an anisotropic etching process, is performed to remove the portion of the inner spacer layer 74L disposed outside the groove 64 and the opening 28H (e.g., on the sidewalls of the nanostructure 22, the gate spacer 41, and the fin 32). The remaining portion of the inner spacer layer 74L (e.g., the portion disposed inside the groove in the nanostructure 24) forms the inner spacer 74 and the gate protection top (GPT) hard mask 78. Because the inner spacer 74 and the GPT hard mask 78 are formed in the same deposition and etching operation, the material of the inner spacer 74 and the GPT hard mask 78 is the same material. Since the GPT hard mask 78 and the channel 22 can have the same width in the X-axis direction due to being formed by the same process of forming the source / drain opening 59. In some embodiments, the thickness of the GPT hard mask 78 in the Z-axis direction is in the range of about 1 nm to about 10 nm.

[0056] exist Fig. 8A In the process, a first semiconductor layer 110A is formed in the source / drain opening 59. In some embodiments, the first semiconductor layer 110A is an undoped silicon layer that can be deposited or epitaxially grown on the exposed surface of the fin 32. The deposition may include one or more operations, such as CVD, which may be ultra-high vacuum chemical vapor deposition (UHV-CVD), which allows improved control of the deposition rate and purity of the first semiconductor layer 110A. In some embodiments, a silicon-containing precursor gas may be introduced into the process chamber, and the reaction therebetween forms a silicon material that is deposited into the source / drain opening 59. In some embodiments, the first semiconductor layer 110A has an upper surface that is located at a level substantially coplanar with the upper surface of the fin 32.

[0057] Fig. 8AThe formation of source / drain regions 82P or "source / drain 82P" according to various embodiments is also depicted. In the illustrated embodiment, the source / drain regions 82P are epitaxially grown from an epitaxial material. In some embodiments, the source / drain regions 82P apply stress in the corresponding channels 22A, 22B, 22C, thereby improving performance. The source / drain regions 82P are formed so that each sacrificial gate structure 40 is disposed between corresponding adjacent pairs of source / drain regions 82P. In some embodiments, the spacer layer 41 separates the source / drain regions 82P from the sacrificial gate layer 45 by an appropriate lateral distance to prevent electrical bridging to a subsequently formed gate of the resulting device. The source / drain regions 82P may be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. The source / drain regions 82P may apply compressive strain in the channel region. The source / drain region 82P may have a surface elevated from a corresponding surface of the first semiconductor layer 110A and may have a small facet. In some embodiments, adjacent source / drain regions 82P may be merged to form a single source / drain region 82P adjacent to two adjacent fins 32. Fig. 8A and Figure 8B The view in FIG. 1 is omitted, but the device 10 may include an N-type source / drain 82N formed before or after the formation of the P-type source / drain 82P (see FIG. 1 ). Figure 1A ). The N-type source / drain 82N may be or include a reference Figure 1A and Figure 1B Source / drain 82N may be formed by an epitaxial growth process similar in most respects to the process used to form source / drain 82P, for example, except for the differences in precursor gas and / or dopant gas ratios.

[0058] exist Figure 8B In the embodiment, after forming the source / drain regions 82N, 82P, the ILD 130 may be formed to cover the source / drain regions 82N, 82P and abut the spacer layer 41. In some embodiments, the ESL 131 is formed before forming the ILD 130. The ESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from the ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x, Al2O3 or one or more of other suitable materials. After depositing ESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process, including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on glass (SOG), or a combination thereof. The ILD 130 may be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or another deposition process.

[0059] exist 9A to 16B , after forming the source / drain 82N, 82P, ESL 131 and ILD 130, an active gate structure 200 may be formed. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD 130 and the ESL 131. In the planarization process, portions of the hard masks 47A, 47B and the gate spacers 41 are also removed. After the planarization process, the sacrificial gate layer 45 is exposed. The top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the sacrificial gate layer 45 and the gate spacers 41.

[0060] Next, if Fig.9A and Fig. 9B As depicted in , the sacrificial gate layer 45 is removed in an etching process, thereby forming an opening or "gate trench" 92. In some embodiments, the sacrificial gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 45 without etching the spacer layer 41. When etching the sacrificial gate layer 45, the sacrificial gate dielectric 43 (when present) can be used as an etch stop layer. Then, the sacrificial gate dielectric 43 can be removed after removing the sacrificial gate layer 45.

[0061] Removing nanostructure 24 to release nanostructure 22 corresponds to Fig.19Step 1300. After removing the nanostructures 24, the nanostructures 22 form a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of the substrate 110). In some embodiments, the nanostructures 24 are removed by a selective etching process using an etchant that is selective to the material of the nanostructures 24, so that the nanostructures 24 are removed without substantially attacking the nanostructures 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, a combination thereof, and the like.

[0062] In some embodiments, nanostructure 24 is removed, and nanostructure 22 is patterned to form channel regions for PFET and NFET. However, in some embodiments, nanostructure 24 may be removed, and nanostructure 22 may be patterned to form channel regions for NFET, and nanostructure 22 may be removed, and nanostructure 24 may be patterned to form channel regions for PFET. In some embodiments, nanostructure 22 may be removed, and nanostructure 24 may be patterned to form channel regions for NFET, and nanostructure 24 may be removed, and nanostructure 22 may be patterned to form channel regions for PFET. In some embodiments, nanostructure 22 may be removed, and nanostructure 24 may be patterned to form channel regions for PFET and NFET.

[0063] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the reshaping, the nanosheet 22 may have a dog-bone shape, wherein the middle portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X direction. Fig.9A In the embodiment depicted in , the middle portion is thicker than the peripheral portions.

[0064] Then, a replacement gate 200 is formed. The replacement gate 200 may be referred to as an active gate 200 or a gate structure 200. The gate structure 200 may be formed by a series of deposition operations, such as ALD cycles, of the various layers of the gate structure 200 in the opening, as described below. Fig.17 Description. Reference Fig.17 The formation of the gate structure 200 is described in detail to provide a reference for understanding FIG. 10A to FIG. 16B Context of the described embodiments.

[0065] Fig.17is a detailed view of a portion of a gate structure 200. The gate structure 200 generally includes an interfacial layer (IL, or "first IL" below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0066] refer to Fig.17 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, for example, silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The first IL 210 has a thickness in a range between about 5 angstroms and about 50 angstroms. The first IL 210 may be formed by thermal oxidation or another suitable process of oxidizing the semiconductor material of the channel 22 and the fin 32.

[0067] Still reference Fig.17 , a gate dielectric layer 600 is formed over the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using about 40 to 80 deposition cycles at a temperature range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as a precursor. Such an ALD process can form the dielectric layer 600 to have a thickness in a range between about 10 angstroms and about 100 angstroms.

[0068] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructured device 20A, 20B.

[0069] In an embodiment of the present disclosure, the gate dielectric layer 600 is reshaped via a selective etching process that removes material of the gate dielectric layer 600 from the side surfaces of the gate spacer 41, which can improve device performance, such as by reducing the capacitance between the gate structure 200 and the source / drain 82P. The presence of the gate dielectric layer 600 on the surface of the channel 22 is beneficial for improving the isolation between the gate structure 200 and the channel 22. The presence of the gate dielectric layer 600 on the surface of the inner spacer 74 is beneficial for increasing the on-current "I ON Therefore, in the embodiment of the present disclosure, the gate dielectric layer 600 remains on the channel 22 and the inner spacer 74 and is removed from the gate spacer 41. FIG. 10A to FIG. 16B A process for selectively removing the gate dielectric layer 600 is described.

[0070] Further references Fig.17 , after forming the gate dielectric layer 600, a metal layer 290 is formed on the gate dielectric layer 600. Before forming the metal layer 290, additional layers such as a second IL 240, a second work function layer 700, and a work function metal layer 900 may be formed. For example, an optional second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 also provides improved thermal stability for the gate structure 200, and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k cap layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO or other suitable materials. In one embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited at a temperature of about 400 degrees Celsius to about 450 degrees Celsius by using about 40 to about 100 cycles of ALD. In some embodiments, a thermal anneal is then performed to form a second IL 240, which can be or include TiSiNO. After the second IL 240 is formed by thermal annealing, an atomic layer etch (ALE) with artificial intelligence (AI) control can be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle can include a first WCl5 pulse, followed by an Ar purge, followed by a second O2 pulse, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage adjustment by metal gate patterning.

[0071] In addition, Fig.17 In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function barrier layer 700 is optionally formed on the gate structure 200. The work function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function barrier layer 700 is TiN. The work function barrier layer 700 may have a thickness ranging from about 5 Å to about 20 Å. Including the work function barrier layer 700 provides additional threshold voltage adjustment flexibility. Generally, the work function barrier layer 700 increases the threshold voltage for NFET transistor devices and reduces the threshold voltage (magnitude) for PFET transistor devices.

[0072] In some embodiments, the work function metal layer 900 is formed on the work function barrier layer 700, and the work function metal layer 900 may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating and / or other suitable methods, and has a thickness between about 10A and 20A. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN or another suitable material, and has a thickness between about 10A and 20A. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which will cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer, and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness between about 10 Å and about 20 Å.

[0073] Fig.17A metal core layer 290 is also shown. In some embodiments, a glue layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can promote and / or enhance the adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride using ALD, such as TiN, TaN, MoN, WN, or another suitable material. In some embodiments, the thickness of the glue layer is between about 10A and about 25A. The metal core layer 290 can be formed on the glue layer and can include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal core layer 290 can be deposited using processes such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510 is formed in the metal core layer 290 vertically located between the channels 22A, 22B, and 22C, and the seam 510 can be an air gap. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. The seam 510 may be formed due to merging of the sidewall deposited films during conformal deposition. In some embodiments, the seam 510 does not exist between adjacent channels 22A, 22B, 22C.

[0074] In some embodiments, one or more of the metal layers including the core layer 290 and the work function layers 700, 900 in the PFET device may include Ti, Al, Zn, W, Nb, Co, etc., and the total thickness of the combination of the metal layers on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm. In some embodiments, one or more of the metal layers including the core layer 290 and the work function layers 700, 900 in the NFET device may include Ti and / or Al, etc., and the total thickness of the combination of the metal layers on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm.

[0075] exist FIG. 10A to FIG. 10D The high-k dielectric layer 600 is as shown above. Fig.17 The formation described corresponds to Fig.19 Step 1400. A high-k dielectric layer 600 may be present on the channel 22, the fin 32, the GPT hard mask 78, the inner spacer 74, and the gate spacer 41. The high-k dielectric layer 600 may be in direct contact with the inner spacer, the GPT hard mask 78, and the gate spacer 41, and may be separated from the channel 22 by the first IL 210.

[0076] Fig. 10A A spacing L1 or gap length L1 between gate spacers 41 on either side of gate opening 92 is depicted. Spacing L1 may also be referred to as a "polysilicon gate length." In some embodiments, spacing L1 is in a range of about 8 nm to about 15 nm. Fig. 10AAlso depicted is a spacing L2 between the internal spacers 74, including the width of the high-k dielectric layer 600 on its side surface. The spacing L2 may also be referred to as an "internal gate length". In some embodiments, the spacing L2 is in a range of about 8 nm to about 15 nm. In some embodiments, the spacings L1 and L2 are equal to or unequal to each other.

[0077] like Fig. 10B As depicted in FIG. 1 , the GPT hard mask 78 may extend beyond the channel 22 by a distance D1. In some embodiments, the distance D1 is in the range of 0 nm (ie, no extending portion) to about 4 nm. FIG. 12A to FIG. 12D In the later process described, the overhanging portion of the GPT hard mask 78 is beneficial for protecting the channel 22 during the etching of the mask layer 500, and the increased overhanging portion can improve the process window of the etching process of the mask layer 500. However, after the selective etching, the overhanging portion also causes additional material of the high-k dielectric layer 600 to remain on the gate spacer 41.

[0078] exist Fig. 10C and Fig. 10D In the embodiment of the present invention, an additional transition metal capping layer 710 (or simply "capping layer 710") is formed on the GPT hard mask 78 with the increased extension, which can advantageously allow a higher etch rate that can produce a non-tapered or vertical profile of the high-k dielectric layer 600 after selective etching. In some embodiments, the transition metal capping layer 710 is or includes TiN that can be formed via a suitable deposition process (such as PVD). Due to the depth of the surface of the isolation region 36, the PVD TiN may not be deposited on the isolation region 36. Because it is protected by the GPT hard mask 78, the PVD TiN is generally not deposited on the underlying nanostructures 22. In some embodiments, including the PVD TiN capping layer 710 can allow the extension to extend to Fig. 10D The difference between the extension distance D1' and the distance D1 (e.g., the additional extension portion obtained due to the capping layer 710) can be in the range of about 0.5 nm to about 4 nm, including 0.5 nm and 4 nm. The capping layer 710 can be additionally formed on the upper surfaces of the gate spacers 41, the ILD 130, and the ESL 131, which can also produce an extension portion at the upper end of the gate trench 92, such as Fig. 10C Described in.

[0079] exist FIG. 11A to FIG. 11DIn the embodiment of the present invention, a mask layer 500 is formed in the gate trench 92, covering the channel 22, the GPT hard mask 78, and the optional cap layer 710. In some embodiments, the mask layer 500 is a bottom anti-reflective coating (BARC) layer and is referred to as a BARC layer 500. The process of forming the BARC layer 500 in the gate trench 92 can begin with one or more cleaning processes, such as RCA cleaning (cleaning involving a mixture of hydrogen peroxide, ammonia, and water), to prepare the exposed surface for BARC adhesion. The BARC material is then applied to the device 10. This can be done using spin coating for liquid BARC or chemical vapor deposition (CVD) for inorganic BARC. During spin coating, the device 10 can be rotated at a high speed to evenly distribute the BARC material across the surface (including the walls and bottom of the gate trench 92). After application, the BARC layer 500 can undergo a baking process to remove the solvent (in the example of liquid BARC) and improve material properties, such as adhesion to the device 10 and its optical properties.

[0080] exist FIG. 12A to FIG. 12DIn the embodiment of the present invention, after forming the BARC layer 500, one or more removal processes may be performed to remove portions of the BARC layer 500 located outside the channel 22 and the internal spacer 74. The removal process may include one or more etching processes. In some embodiments, the etching process may involve wet chemical etching, dry plasma etching, or reactive ion etching (RIE), among other techniques. In some embodiments, the etching process involves material removal by chemical reaction or physical sputtering. For example, plasma etching may use reactive plasma to remove the material of the BARC layer 500. The selection of etching chemicals and process parameters may be beneficial for effectively removing the BARC layer 500 without damaging underlying layers or structures, such as the channel 22 and the isolation structure 36. The etching chemicals may include oxygen (O2) plasma, which may generate reactive oxygen species (ROS), such as atomic oxygen, which reacts with carbon in the organic BARC layer 500, converting it into volatile compounds, such as carbon dioxide (CO2) and water (H2O). In some embodiments, argon is added to the oxygen plasma to enhance the physical sputtering effect, which helps to more effectively remove the organic material. Argon atoms (which are inert) may not react chemically, but contribute to the physical removal of materials by ion bombardment. In some embodiments, hydrogen is added to the plasma to promote the removal of oxygen-containing groups in the BARC material, further promoting its conversion to volatile products. Process parameters may include RF power, which is the power applied to generate plasma. RF power may significantly affect the etching rate and selectivity. Higher power levels increase the density of active species, resulting in faster etching rates. Too high power may also increase damage to the underlying structure. Other process parameters may include chamber pressure, gas flow rate, temperature, and etching time. The chamber pressure during etching may affect the mean free path of active species and ions, thereby affecting etching uniformity and rate. Lower pressures can be used for anisotropic etching, while higher pressures promote chemical reactions by increasing the density of active species. The rate at which the etching gas is introduced into the chamber can be selected to provide sufficient active species supply for the etching reaction while avoiding excess that may cause non-uniform etching or damage. Substrate and chamber temperatures may affect reaction rates and byproduct volatility. In some embodiments, the temperature is kept moderate to provide effective etching without damaging the integrity of the substrate or nearby structures. A post-etch cleaning step may be required to remove any residues or byproducts left on the substrate after plasma etching the BARC layer 500. This step may typically involve a wet chemical clean or additional plasma treatment selected to improve cleaning of the substrate.

[0081] For example, the GPT hard mask 78 may be used as a mask to prevent removal of a portion of the BARC layer 500 located below the GPT hard mask 78. For example, the BARC layer 500 may be patterned using a reactive ion etching (RIE) dry etching process to achieve a BARC layer 500' remaining on the channel layer 22 and the high-k dielectric layer 600. In some embodiments, because the GPT hard mask 78 has a width extending beyond the width of the channel layer 22, the etched BARC layer 500' remains on the sidewalls of the channel layer 22. In some embodiments, the etched BARC layer 500' wraps around the channel layer 22 and the high-k dielectric layer 600.

[0082] like Fig. 12B As depicted in , the etched BARC layer 500' may have a tapered sidewall in the YZ plane. That is, the distance W1 between the top nanostructure 22C and the outer sidewall of the BARC layer 500' and the distance W2 between the bottom nanostructure 22A and the outer sidewall of the BARC layer 500' may be different. For example, the distance W2 may exceed the distance W1, which means that the width of the BARC layer 500' in the Y-axis direction increases as it approaches the fin 32 and decreases as it approaches the GPT hard mask 78. In some embodiments, the distance W1 may be in the range of about 1.5 nm to about 20 nm. The BARC layer 500' may extend from the side surface or corner of the high-k dielectric layer 600 on the GPT hard mask 78 to a position on the isolation region 36. The taper angle θ1 between the plane of the upper surface of the isolation region 36 and the outer sidewall of the BARC layer 500' may be in the range of about 60 degrees to about 85 degrees.

[0083] exist Fig.12D In the embodiment of the present invention, due to the additional overhang provided by the PVD TiN capping layer 710, a higher etch rate can be used, which can produce a smaller taper of the outer sidewall of the BARC layer 500'. The higher etch rate can be achieved by one or a combination of the parameters described above. Due to the higher etch rate, the taper angle θ1 between the plane of the upper surface of the isolation region 36 and the outer sidewall of the BARC layer 500' can be in the range of about 85 degrees to 90 degrees. Fig.12D A distance W3 between the outer sidewalls of the nanostructures 22 and the BARC layer 500' is depicted. Due to increased etch rates, the distance W3 may be substantially uniform with increasing proximity to the fins 32 and / or the GPT hard mask 78 and may be in a range of about 1.5 nm to about 20 nm.

[0084] Fig. 12B and Fig.12DIt is also depicted that the BARC layer 500' may include internal spacer regions 500B that overlap the internal spacers 74 between the channels 22 and between the channels 22A and the fins 32. The BARC layer 500' may also include extended regions 500A that are laterally located outside of or adjacent to the channels 22. The extended regions 500A may have a non-uniform width in the Y-axis direction due to tapering, or may have a substantially uniform width in the Y-axis direction due to a higher etch rate when the capping layer 710 is in place.

[0085] After the etching operation that shapes the BARC layer 500 to form the BARC layer 500′, the BARC layer 500′ covers the high-k dielectric layer 600, the inner spacers 74, and the small portions of the gate spacers 41 associated with the extension regions 500A on the channels 22. The BARC layer 500′ exposes excess material 600X of the high-k dielectric layer 600 that is located on the gate spacers 41. Typically, the excess material 600X extends over the GPT hard mask 78 and also includes portions that are laterally located between the channel stacks 22.

[0086] exist FIG. 13A to FIG. 13D , removing excess material 600X of high-k dielectric layer 600, corresponding to Fig.19 Step 1500. Excess material 600X of the high-k dielectric layer 600 may be removed by one or more etching operations that remove material of the high-k dielectric layer 600 without substantially attacking the BARC layer 500', the gate spacers 41, and the isolation regions 36. The excess material 600X may be removed by a suitable etching operation, such as a wet chemical etch using dilute hydrofluoric acid or a buffered oxide etch, or a dry etch, such as a chlorine-based plasma etch. The etching operation may remove or thin the high-k dielectric layer 600 on the top surface of the GPT hard mask 78, except for the excess material 600X, and may remove the high-k dielectric layer 600 on the upper surface of the isolation regions 36. Fig. 13B In the case where there is no capping layer 710 in place, the etching operation can remove the high-k dielectric layer 600 on the upper surface and side surfaces of the GPT hard mask 78, and can leave a portion of the high-k dielectric layer 600 located on the bottom corner area of ​​the GPT hard mask 78, as shown. Fig.13D In the embodiment of the present invention, the capping layer 710 extends beyond the side surface of the high-k dielectric layer 600 on the GPT hard mask 78 so that the high-k dielectric layer 600 is in place on the side surface of the GPT hard mask 78 after the etching operation. In some embodiments, the portion of the high-k dielectric layer 600 that is laterally adjacent to the GPT hard mask 78 is separated from the GPT hard mask 78 by the high-k dielectric layer 600.

[0087] exist Fig. 13C and Fig.13DIn the embodiment of the present invention, the capping layer 710 is removed after or simultaneously with etching the high-k dielectric layer 600. The capping layer 710 may be removed by a suitable etching operation, such as a wet etch or a dry etch including a chlorine or fluorine based plasma.

[0088] exist FIG. 14A to FIG. 14E In the embodiment, the BARC layer 500' is removed. The BARC layer 500' can be removed by a suitable removal process, such as an ashing process. As the BARC layer 500' is removed, the high-k dielectric layer 600 is exposed in the gate trench 92. Fig. 14B As depicted, the reduced high-k dielectric layer 600S may inherit the reference Fig. 12A and Fig. 12B The profile of the BARC layer 500' is described. Fig.14D As depicted, the reduced high-k dielectric layer 600S may inherit the reference Fig. 12C and Fig.12D 3. The reduced high-k dielectric layer 600S may include a channel region 600C on the channel 22 and an internal spacer region 600B overlapping the internal spacer 74 between the channel 22 and between the channel 22A and the fin 32. The reduced high-k dielectric layer 600S may also include an extended region 600A laterally located outside or adjacent to the channel 22. The extended region 600A may have a non-uniform width in the Y-axis direction due to the tapering ( Fig. 14B ), or may have a substantially uniform width in the Y-axis direction due to a higher etch rate when the capping layer 710 is in place ( Fig.14D ). The cone angle θ1 and the distances W1, W2, and W3 can be compared with the reference Fig. 12B and Fig.12D That is, the taper angle θ1 is Fig. 14B can be in the range of about 60 degrees to about 85 degrees, and Fig.14D The angle W1, W2, W3 may be in the range of about 85 to 90 degrees. The distances W1, W2, W3 may be in the range of about 1.5 nm to about 20 nm. The reduced high-k dielectric layer 600S may expose a portion 41A of the gate spacer 41 located below the GPT hard mask 78 and between the nanostructure stack 22.

[0089] Fig.14E An embodiment in which the extension region 600A is not present is depicted. In some embodiments, the BARC layer 500' does not include the extension region 500A, so that the excess material 600X includes material of the high-k dielectric layer 600 that is immediately adjacent to the channel region 600C on the channel 22. That is, in reference to FIG. 13A to FIG. 13DAfter the depicted etching operation, the reduced high-k dielectric layer 600S includes only the channel region 600C and the inner spacer region 600B overlapping the channel 22 , the GPT hard mask 78 , and the inner spacer 74 between the fins 32 , and does not include the extension region 600A.

[0090] exist FIG. 14A to FIG. 14E In some embodiments, the reduced high-k dielectric layer 600S may cover a portion of the surface area of ​​the side surface of the gate spacer 41. In some embodiments, the portion may be measured as a percentage of the surface area of ​​the gate spacer 41. For example, the portion of the gate spacer 41 covered by the reduced high-k dielectric layer 600S may be 0% ( Fig.14E ) to about 50%. In some embodiments, the portion is in the range of about 5% to about 25%. In some embodiments, the profile of the etched BARC layer 500' can be configured by adjusting one or more of the following parameters: (1) etching bias voltage (e.g., higher bias for sharper profiles and vice versa) or (2) etching gas of N2 and H2 mixed plasma.

[0091] exist FIG. 15A to FIG. 15D In FIG. 1 , the metal layer 290 of the gate structure 200 is formed on the reduced high-k dielectric layer 600S. The formation of the metal layer 290 can be similar in most aspects to the reference Fig.17 Typically, metal layer 290 may fill gate trench 92 and may be located between and on fin 32, channel 22, and GPT hard mask 78. Metal layer 290 may extend to the top of gate trench 92, such as to have an upper surface coplanar with the upper surfaces of gate spacer 41, ILD 130, and ESL 131.

[0092] Fig.15E and Fig.15F is along Fig. 15B and Fig.15D The plane diagram of the section lines EE and FF. Fig.15E , because the reduced high-k dielectric layer 600S is in place, the metal layer 290 can be in direct contact with the exposed portions of the gate spacers 41, such as the portions of the gate spacers 41 that are not covered by the inner spacer regions 600B and the extension regions 600A of the reduced high-k dielectric layer 600S. In some embodiments, as shown in reference Fig.17As described, additional layers may be located between the metal layer 290 and the gate spacer 41. For example, the second IL 240, the second work function layer 700, the work function adjustment layer 900, an optional glue layer, or a combination thereof may be present between the metal layer 290 and the gate spacer 41 without a reduced high-k dielectric layer 600S therebetween. For example, the second IL 240 may be in direct contact with the gate spacer 41. In another example, the second work function layer 700 may be in direct contact with the gate spacer 41. In yet another example, the work function adjustment layer 900 may be in direct contact with the gate spacer 41.

[0093] Fig.16A and Fig. 16B Depicted are views of a device 10 according to various embodiments. In some embodiments, as Fig.16A Described in and previously referenced FIG. 13A to FIG. 13D As described, the lower portion 600L of the reduced high-k dielectric layer 600S may be located on the bottom surface of the GPT hard mask 78 and may extend beyond the corner region of the GPT hard mask 78. For example, the lower portion 600L may extend beyond the corner region of the GPT hard mask 78 by a distance not exceeding the thickness of the reduced hard mask layer 600S. Fig.17 As described, the high-k dielectric layer 600 and the reduced high-k dielectric layer 600S may have a thickness in a range of about 0.5 nm to about 10 nm. Fig.16A In the embodiment depicted in , the upper surface of the GPT hard mask 78 may be free of the reduced high-k dielectric layer 600S.

[0094] exist Fig. 16B , the reduced high-k dielectric layer 600S may have an upper portion 600U and a lower portion 600L on the GPT hard mask 78. The lower portion 600L may be similar to the reference Fig.16A The upper portion 600U may be located on the upper surface and optionally on the side surface of the GPT hard mask 78. In some embodiments, the upper portion 600U may have a thickness different from the thickness of the lower portion 600L. In some embodiments, the lower portion 600L may have a thickness that exceeds the thickness of the upper portion 600U by 0 nm (i.e., the same thickness) to a value in the range of about 2 nm. In some embodiments, the thickness of the upper portion 600U is zero, which is consistent with Fig.16A In some embodiments, the thickness of the upper portion 600U exceeds zero and is less than about 8 nm. Fig. 16B In the embodiment depicted in , the GPT hard mask 78 may be completely surrounded by the upper portion 600U and the lower portion 600L of the reduced high-k dielectric layer 600S.

[0095] exist Fig.18In the embodiment, after forming the gate structure 200, source / drain openings may be formed in the ILD 130, and source / drain contacts 120 may be formed in the source / drain openings. The silicide region 118 and the source / drain contact 120 are formed on the source / drain 82, which may be the source / drain 82P, the source / drain 82N, or a combination thereof.

[0096] In some embodiments, the silicide layer 118 is formed before forming the source / drain contacts 120. For example, an N-type or P-type metal layer can be formed as a conformal thin layer over the exposed portions of the source / drain regions 82. The metal layer can be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, the silicide layer 118 can be formed by annealing the device 10. After annealing, the silicide layer 118 may be or include one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide of the silicide layer 118 may diffuse into the region below the ESL 131. The thickness of the silicide layer 118 may be in the range of about 1 nm to about 10 nm. Below about 1 nm, the contact resistance may be too high. Above about 10 nm, the silicide layer 118 may be short-circuited with the channel 22C.

[0097] After forming the silicide layer 118, the source / drain contacts 120 are formed by filling the openings above the source / drain regions 82 with, for example, a liner layer and a filling layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material that is or includes a conductive material such as Co, W, Ru, combinations thereof, and the like. In some embodiments, the source / drain contacts 120 are or include a compound or alloy based on Co, W, or Ru, including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, and the like. The source / drain contacts 120 are bonded on the silicide layer 118 and contact the ESL 131. The description of the device 10 and its illustration in many of the figures are given with reference to a GAAFET including a vertical stack of nanostructures 22. In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and on the source / drain regions 82 of the FinFET device.

[0098] Additional processing may be performed to complete the fabrication of the nanostructure device 20. For example, a gate contact (or gate via) may be formed to electrically couple to the gate structure 200. An interconnect structure may then be formed over the source / drain contacts 120 and the gate contact. The interconnect structure may include a plurality of dielectric layers (including, for example, a second ILD) surrounding metal features including conductive traces and conductive vias that form electrical connections between devices on the substrate 110 (such as the nanostructure devices 20A, 20B, 20C) and to IC devices external to the IC device 10.

[0099] Embodiments may provide advantages. By selectively removing portions of the gate dielectric 600 from the gate spacers 41 that are outside the channel 22 and the inner spacers 74, parasitic capacitance may be reduced without reducing the beneficial on-current I ON Selective removal can be achieved by using a gate top protection hard mask 78 and an optional transition metal capping layer 710 .

[0100] According to at least one embodiment, a method includes: forming a stack including alternating first and second semiconductor layers on a substrate; forming a sacrificial gate structure on the stack; forming a gate spacer adjacent to the sacrificial gate structure; releasing the first semiconductor layer by removing the second semiconductor layer; forming a gate dielectric on side surfaces of the first semiconductor layer and the gate spacer; forming a reduced gate dielectric by removing portions of the gate dielectric from the side surfaces of the gate spacer, the portions being laterally adjacent to the first semiconductor layer; and forming a gate metal layer on the reduced gate dielectric and exposed portions of the gate spacer.

[0101] According to at least one embodiment, a method includes: forming a dielectric protection layer over a stack of alternating first and second nanostructures; forming a gate spacer adjacent to the first nanostructure; forming an internal spacer between the first nanostructures; releasing the first nanostructure by removing the second nanostructure; forming a gate dielectric on the first nanostructure, the dielectric protection layer, and the gate spacer; forming a capping layer on the dielectric protection layer, the capping layer having a width exceeding the width of the dielectric protection layer; forming a reduced gate dielectric by removing a first portion of the gate dielectric from a side surface of the gate spacer, the portion having a width substantially equal to the width of the dielectric protection layer; and forming a gate metal layer on the reduced gate dielectric and the exposed portion of the gate spacer.

[0102] According to at least one embodiment, a device includes: a nanostructure stack; a first layer located above the nanostructure stack and offset relative to the nanostructure stack; an internal spacer located between the first layer and the nanostructure stack; and a gate structure wrapping the nanostructure stack. The gate structure includes: a gate dielectric located on the nanostructure and between the internal spacer and the nanostructure of the nanostructure stack; and a gate metal located on the gate dielectric.

[0103] Some embodiments of the present application provide a method, comprising: forming a stack comprising alternating first and second semiconductor layers on a substrate; forming a sacrificial gate structure on the stack; forming a gate spacer adjacent to the sacrificial gate structure; releasing the first semiconductor layer by removing the second semiconductor layer; forming a gate dielectric on the side surfaces of the first semiconductor layer and the gate spacer; forming a reduced gate dielectric by removing a portion of the gate dielectric from the side surfaces of the gate spacer, the portion being laterally adjacent to the first semiconductor layer; and forming a gate metal layer on the reduced gate dielectric and the exposed portion of the gate spacer.

[0104] In some embodiments, the method further comprises: forming a dielectric protection layer over the stack before forming the sacrificial gate structure. In some embodiments, forming the dielectric protection layer over the stack comprises forming the dielectric protection layer having a width exceeding those of the first semiconductor layers. In some embodiments, forming the dielectric protection layer over the stack comprises forming the dielectric protection layer having a width substantially the same as a width of at least one of the first semiconductor layers. In some embodiments, forming the gate dielectric comprises forming the gate dielectric on the dielectric protection layer. In some embodiments, forming the reduced gate dielectric comprises: forming a mask layer on the gate dielectric, the mask layer covering the gate spacers; etching the mask layer by removing portions of the mask layer using the dielectric protection layer as a first mask to form a reduced mask layer; and etching the gate dielectric using the reduced mask layer as a second mask. In some embodiments, forming the reduced mask layer comprises forming the reduced mask layer having a tapered profile that increases in width as it approaches the substrate.

[0105] Other embodiments of the present application provide a method, comprising: forming a dielectric protection layer over a stack of alternating first and second nanostructures; forming a gate spacer adjacent to the first nanostructure; forming an internal spacer between the first nanostructures; releasing the first nanostructure by removing the second nanostructure; forming a gate dielectric on the first nanostructure, the dielectric protection layer and the gate spacer; forming a capping layer on the dielectric protection layer, the capping layer having a width exceeding the width of the dielectric protection layer; forming a reduced gate dielectric by removing a first portion of the gate dielectric from a side surface of the gate spacer, the portion having a width substantially equal to the width of the dielectric protection layer; and forming a gate metal layer on the reduced gate dielectric and the exposed portion of the gate spacer.

[0106] In some embodiments, forming the reduced gate dielectric comprises: forming a mask layer on the gate dielectric, the mask layer covering the gate spacer; etching the mask layer by removing portions of the mask layer using the covering layer as a first mask to form a reduced mask layer; and etching the gate dielectric using the reduced mask layer as a second mask. In some embodiments, forming the covering layer comprises forming a transition metal nitride layer on the dielectric protection layer. In some embodiments, forming the dielectric protection layer comprises: forming a stack of first and second semiconductor layers associated with the stack of alternating first and second nanostructures; forming a third semiconductor layer on the stack of first and second semiconductor layers; forming a third nanostructure by forming a source or drain opening extending through the stack of first and second semiconductor layers and the third semiconductor layer; forming an opening by removing the third nanostructure; and forming the dielectric protection layer in the opening. In some embodiments, forming the dielectric protection layer in the opening is performed during forming an internal spacer between the first nanostructures. In some embodiments, forming the third semiconductor layer comprises forming the third semiconductor layer having a germanium concentration exceeding those of the first semiconductor layer and the second semiconductor layer. In some embodiments, forming the reduced gate dielectric comprises removing a second portion of the gate dielectric from an upper surface of the dielectric cap layer.

[0107] Still other embodiments of the present application provide a device comprising: a nanostructure stack; a first layer located above the nanostructure stack and offset relative to the nanostructure stack; an internal spacer located between the first layer and the nanostructure stack; and a gate structure wrapping the nanostructure stack, the gate structure comprising: a gate dielectric located on the nanostructure and between the internal spacer and the nanostructure of the nanostructure stack; and a gate metal located on the gate dielectric.

[0108] In some embodiments, the width of the first layer exceeds the width of the nanostructures of the nanostructure stack. In some embodiments, the gate dielectric on the internal spacer has a tapered profile below the first layer. In some embodiments, the gate dielectric is adjacent to more than one side of the first layer. In some embodiments, a first portion of the gate dielectric on the top surface of the first layer has a thickness that is less than a thickness of a second portion of the gate dielectric on the bottom surface of the first layer. In some embodiments, the portion of the gate dielectric below the first layer has a substantially uniform width between the first layer and the bottom-most nanostructure of the nanostructure stack.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a stack including alternating first and second semiconductor layers on a substrate; forming a sacrificial gate structure on the stack; forming a gate spacer adjacent to the sacrificial gate structure; releasing the first semiconductor layer by removing the second semiconductor layer; forming a gate dielectric on side surfaces of the first semiconductor layer and the gate spacer; forming a reduced gate dielectric by removing a portion of the gate dielectric from the side surfaces of the gate spacers, the portion being laterally adjacent to the first semiconductor layer; as well as A gate metal layer is formed on the reduced gate dielectric and the exposed portions of the gate spacers.

2. The method according to claim 1, further comprising: Before forming the sacrificial gate structure, a dielectric protection layer is formed over the stack.

3. The method according to claim 2, wherein: Forming the dielectric cap layer over the stack includes forming the dielectric cap layer having widths exceeding those of the first semiconductor layer.

4. The method according to claim 2, wherein: Forming the dielectric cap layer over the stack includes forming the dielectric cap layer having a width substantially the same as a width of at least one of the first semiconductor layers.

5. The method according to claim 2, wherein: Forming the gate dielectric includes forming the gate dielectric on the dielectric cap layer.

6. The method according to claim 2, wherein: Forming a reduced gate dielectric includes: forming a mask layer on the gate dielectric, the mask layer covering the gate spacer; forming a reduced mask layer by removing portions of the mask layer by etching the mask layer using the dielectric cap layer as a first mask; and The gate dielectric is etched using the reduced mask layer as a second mask.

7. The method according to claim 1, wherein: Forming the reduced mask layer includes forming the reduced mask layer having a tapered profile that increases in width as it approaches the substrate.

8. A method of forming a semiconductor device, comprising: forming a dielectric cap layer over the stack of alternating first and second nanostructures; forming a gate spacer adjacent to the first nanostructure; forming internal spacers between the first nanostructures; releasing the first nanostructure by removing the second nanostructure; forming a gate dielectric on the first nanostructure, the dielectric protection layer, and the gate spacer; forming a capping layer on the dielectric protection layer, the capping layer having a width exceeding a width of the dielectric protection layer; forming a reduced gate dielectric by removing a first portion of the gate dielectric from side surfaces of the gate spacers, the portion having a width substantially equal to a width of the dielectric cap layer; as well as A gate metal layer is formed on the reduced gate dielectric and the exposed portions of the gate spacers.

9. The method according to claim 8, wherein: Forming the reduced gate dielectric includes: forming a mask layer on the gate dielectric, the mask layer covering the gate spacer; forming a reduced mask layer by removing portions of the mask layer by etching the mask layer using the capping layer as a first mask; and The gate dielectric is etched using the reduced mask layer as a second mask.

10. A semiconductor device comprising: Nanostructured stacks; a first layer located above and offset relative to the nanostructure stack; an internal spacer disposed between the first layer and the nanostructure stack; as well as A gate structure wrapping the nanostructure stack, the gate structure comprising: a gate dielectric on the nanostructures and between the inner spacers and the nanostructures of the nanostructure stack; as well as A gate metal is located on the gate dielectric.

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