Semiconductor device and preparation method

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor device and a preparation method thereof, and the preparation method comprises the steps: providing a substrate, and forming a buried oxide layer at one side of the substrate; performing ion implantation on one side, facing the substrate, of the buried oxide layer; forming an epitaxial layer and a hard mask layer on one side, deviating from the substrate, of the buried oxide layer; performing deep groove isolation etching on the hard mask layer and the epitaxial layer to form a deep groove; etching the deep groove until the deep groove penetrates through the buried oxide layer, and filling polycrystalline silicon in the deep groove; performing chemical mechanical polishing to the hard mask layer, and then removing the hard mask layer; and forming an active layer on one side, deviating from the buried oxide layer, of the epitaxial layer. By adopting the semiconductor device, the ionizing radiation resistance of the semiconductor device can be improved, and the use reliability of the semiconductor device in a severe environment can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] With the advancement of space technology, the demand for the integration of electronic systems is increasing, but at the same time, devices are required to have radiation resistance. In the field of CMOS (Complementary Metal-Oxide-Semiconductor), SOI (Silicon-On-Insulator) devices have been widely studied due to their excellent radiation resistance. SOI BCD devices refer to semiconductor devices based on SOI that integrate Bipolar (Bipolar Transistor), CMOS and DMOS (Diffused Metal-Oxide-Semiconductor), such as Smart Power IC (Smart Power Integrated Circuit). Existing SOI-based Smart Power ICs are still insufficient in TID (Total Ionizing Dose) protection, resulting in insufficient resistance to ionizing radiation of SOI BCD devices, which affects the reliability of chips in harsh environments.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In view of the problems in the prior art, the purpose of the present application is to provide a semiconductor device and a preparation method to improve the semiconductor device's resistance to ionizing radiation and improve the reliability of the semiconductor device when used in harsh environments.

[0005] An embodiment of the present application provides a method for preparing a semiconductor device, wherein the semiconductor device is a SOI BCD device, and the method comprises the following steps: Providing a P-type substrate, wherein a buried oxide layer is provided on one side of the P-type substrate; Performing N-type ion implantation on a side of the buried oxide layer facing the P-type substrate to form a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region; forming an epitaxial layer and a hard mask layer on a side of the buried oxide layer away from the P-type substrate; Performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form deep trenches; Etching the deep trench to penetrate the buried oxide layer, and filling the deep trench with polysilicon, wherein the deep trench is opposite to the heavily doped N-type region; After chemical mechanical polishing to the hard mask layer, removing the hard mask layer; forming an active layer on a side of the epitaxial layer away from the buried oxide layer; forming an interlayer dielectric layer on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; A conductive metal is filled in the contact hole, and the semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

[0006] In some embodiments, after the hard mask layer and the epitaxial layer are subjected to deep trench isolation etching to form deep trenches, the following steps are further included: Angle heavy ion implantation is performed on the sidewalls of the deep trench.

[0007] In some embodiments, after the hard mask layer and the epitaxial layer are subjected to deep trench isolation etching to form deep trenches, the following steps are further included: An isolation layer is formed on the sidewall of the deep trench.

[0008] In some embodiments, forming an isolation layer on the sidewall of the deep trench comprises the following steps: TEOS is grown to form an isolation layer on a side of the hard mask layer away from the epitaxial layer and in the deep trench.

[0009] In some embodiments, etching the deep trench to penetrate the buried oxide layer comprises the following steps: The deep trench is etched by adopting a full etching process to expand the cavity diameter of the deep trench and make the deep trench pass through the buried oxide layer.

[0010] In some embodiments, filling the deep trench with polysilicon includes: filling the deep trench with N-type polysilicon.

[0011] In some embodiments, removing the hard mask layer includes removing the hard mask layer by dry etching or wet etching.

[0012] The embodiment of the present application further provides a semiconductor device, which is obtained by using the method for preparing the semiconductor device, wherein the semiconductor device is a SOI BCD device and includes: P-type substrate; A buried oxide layer is provided on one side of the P-type substrate, wherein a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region are formed on a side of the P-type substrate facing the buried oxide layer; An epitaxial layer is formed on a side of the buried oxide layer away from the P-type substrate, a deep trench is formed in the epitaxial layer and the buried oxide layer, the deep trench is filled with polysilicon, and the deep trench is opposite to the heavily doped N-type region; An active layer formed on a side of the epitaxial layer away from the buried oxide layer; An interlayer dielectric layer, formed on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; A conductive metal is filled in the contact hole, and the semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

[0013] The semiconductor device and preparation method provided in this application have the following advantages: The present application is further expanded based on the deep trench isolation technology to produce a polysilicon-filled deep trench isolation that passes through the buried oxide layer in the SOI substrate. The charges accumulated in the buried oxide layer are guided out of the substrate through the polysilicon portion in the deep trench isolation to avoid charge retention in the buried oxide layer, so that the electric field of the buried oxide layer is restored to balance, and ionizing radiation is prevented from charging the buried oxide layer due to the Bragg effect, resulting in an unexpected inversion layer. This is beneficial to improving the semiconductor device's ability to resist ionizing radiation, improving the reliability of semiconductor devices when used in harsh environments, and improving the comprehensive performance of space technology equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0015] Figure 1 It is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present application.

[0016] Figure 2 It is a schematic diagram of performing ion implantation below a buried oxide layer according to an embodiment of the present application.

[0017] Figure 3 It is a schematic diagram after forming a hard mask layer according to an embodiment of the present application.

[0018] Figure 4It is a schematic diagram of coating photoresist on the hard mask layer according to an embodiment of the present application.

[0019] Figure 5 FIG. 1 is a schematic diagram of an embodiment of the present application after photolithography.

[0020] Figure 6 FIG. 1 is a schematic diagram of forming a linear oxide layer by thermal oxidation according to an embodiment of the present application.

[0021] Figure 7 FIG. 1 is a schematic diagram of an embodiment of the present application after forming a deep groove.

[0022] Figure 8 It is a schematic diagram of an embodiment of the present application after forming an isolation layer.

[0023] Fig. 9 It is a schematic diagram of a deep trench penetrating through the buried oxide layer according to an embodiment of the present application.

[0024] Fig.10 This is a schematic diagram of an embodiment of the present application after filling with polysilicon.

[0025] Fig.11 It is a schematic diagram of chemical mechanical polishing according to an embodiment of the present application.

[0026] Fig.12 It is a schematic diagram after forming an active layer according to an embodiment of the present application.

[0027] Fig.13 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both mean "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.

[0029] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.

[0030] In view of the problem that the SOI BCD device in the prior art has insufficient ionizing radiation protection capability, the present application provides a method for preparing a semiconductor device and a semiconductor device obtained by using the preparation method, aiming to improve the ionizing radiation protection capability of the SOI BCD device and enable the semiconductor device to be used in ionizing radiation scenarios. The present application is applied to the preparation of SOI BCD devices, integrating bipolar transistors (Bipolar), CMOS logic circuits and DMOS power devices on the same chip.

[0031] like Figure 1 As shown, the embodiment of the present application provides a method for preparing a semiconductor device, comprising the following steps: S100: providing a substrate, wherein a buried oxide layer (BOX) is provided on one side of the substrate; In this embodiment, the substrate is a P-type substrate; The buried oxide layer is a silicon dioxide layer, i.e., an insulating layer. When obtaining a substrate, a substrate with a buried oxide layer already provided thereon is obtained. This application does not involve the formation process of the buried oxide layer. Above the buried oxide layer is a P-type single crystal silicon film layer (P-type silicon thin film), i.e., the lower half of the top silicon layer used to make the device. S200: performing N-type ion implantation on a side of the buried oxide layer facing the substrate to form a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region; Ion implantation is an important process for accurately controlling the distribution of impurities in semiconductor manufacturing. The purpose of step S200 is to form a specific type of doped region on the side of the buried oxide layer facing the substrate to improve the electrical performance of the device. In this embodiment, the N-type doped region formed by ion implantation on the side of the single crystal silicon substrate structure close to the buried oxide layer is a local doped region. In this embodiment, step S200 includes: performing N-type doping ion implantation on a side of the buried oxide layer facing the substrate to form an N-type doping region; specifically, performing ion implantation below the buried oxide layer where a P-type active region (AA region) is to be formed; N-type doping is usually performed by implanting pentavalent impurity elements such as phosphorus (P) and arsenic (As), so that a large number of free electrons exist in the doping region as majority carriers; in the subsequent device manufacturing process, the P-type active region and the N-type doping region will form a specific PN junction structure, thereby realizing the electrical function of the device; S300: forming an epitaxial layer and a hard mask layer on a side of the buried oxide layer away from the substrate; The epitaxial layer is a layer of semiconductor material formed by epitaxial growth technology on the side of the buried oxide layer away from the substrate; in this embodiment, the epitaxial layer is a P-type epitaxial layer (P-EPI); the hard mask layer is a thin film with a certain hardness and chemical stability formed on the P-type epitaxial layer, and the main function of the hard mask layer is to protect the epitaxial layer in the subsequent etching process to ensure that the etching process can be accurately performed in the specified area; S400: performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form a deep trench; In this embodiment, a DTI Etch (Deep Trench Isolation Etch) method is used to form a longitudinal deep trench in the hard mask layer and the epitaxial layer; S500: etching the deep trench to penetrate the buried oxide layer, and filling the deep trench with polysilicon; In this embodiment, filling the deep trench with polysilicon includes: filling the deep trench with N-type doped polysilicon (N-Poly); polysilicon is a semiconductor material with good conductivity and thermal stability, and is often used to fill deep trenches to achieve electrical connection and isolation; S600: After chemical mechanical polishing to the hard mask layer, remove the hard mask layer; Chemical Mechanical Polishing (CMP) is a process for flattening the surface of a semiconductor chip. Through chemical mechanical polishing, excess polysilicon on the surface of the chip can be removed to make the surface highly flat. In this embodiment, in step S600, the hard mask layer is removed by dry etching or wet etching. Dry etching uses plasma to chemically react with the hard mask layer material to remove it layer by layer. Wet etching uses chemical solution to chemically react with the hard mask layer material to dissolve and remove it. Dry etching or wet etching is selected according to the material and process requirements of the hard mask layer. S700: forming an active layer on the side of the epitaxial layer away from the buried oxide layer; that is, completing the FEOL (Front End Of Line) manufacturing. The active layer is the key area for realizing electrical functions in semiconductor devices, which includes various active devices such as transistors and diodes. The process of forming the active layer usually includes multiple process steps such as photolithography, ion implantation, and diffusion; S800: forming an interlayer dielectric layer on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; S900: Filling a conductive metal in the contact hole, the semiconductor device being configured to receive an external bias voltage and applying the bias voltage to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

[0032] SOI BCD devices realize BCD integration based on silicon-on-insulator materials. The SOI structure consists of top silicon (Active Layer), buried oxide layer (BOX) and substrate silicon (Substrate). The buried oxide layer plays the role of electrical isolation, which greatly reduces the parasitic capacitance between the device on the top silicon and the substrate silicon. In SOI BCD devices, each structure is made on the top silicon and its epitaxial layer, and the buried oxide layer is used for isolation, which reduces the mutual interference between devices. When high-energy particles penetrate the buried oxide layer, they will deposit charges in the buried oxide layer due to the Bragg effect (Bragg Peak), causing charge accumulation. Charge accumulation may cause the electric field of the buried oxide layer to be distorted, and then form an unintended inversion layer (Unintended Inversion Layer) on the surface of the top silicon (such as the P-type active area), destroying the function of the semiconductor device. The principle of producing an unexpected inversion layer is as follows: ionizing radiation will excite electron-hole pairs at a deeper position in the thick oxide layer. Since the electron mobility is about 2 orders of magnitude higher than the hole mobility in the buried oxide layer of silicon dioxide - about 100 times, the electrons in the oxide layer will gradually be lost, while the holes will not be lost, resulting in the buried oxide layer being positively charged, and ultimately leading to an unexpected inversion layer, i.e. a conductive channel, on the side of the upper surface of the buried oxide layer that contacts the top silicon layer.

[0033] This application is further expanded based on the deep trench isolation technology to produce a polysilicon-filled deep trench isolation that passes through the buried oxide layer in the SOI substrate. The charges accumulated in the buried oxide layer are guided out of the substrate through the polysilicon part in the deep trench isolation to avoid the charge being retained in the buried oxide layer, so that the electric field of the buried oxide layer is restored to balance, and the ionizing radiation is prevented from charging the buried oxide layer due to the Bragg effect, resulting in an unexpected inversion layer, which is beneficial to improving the ionizing radiation resistance of semiconductor devices, improving the reliability of semiconductor devices used in harsh environments, and improving the comprehensive performance of space technology equipment. Specifically, since the heavily doped N-type region under the buried oxide layer forms a conductive connection with the outside through the polysilicon and the conductive metal in the contact hole, a negative bias voltage can be applied to the heavily doped N-type region under the buried oxide layer through the conductive path to offset the built-in electric field caused by the positively charged holes retained in the buried oxide layer, thereby preventing the formation of an unexpected inversion layer between the buried oxide layer and the top silicon, and improving the performance of the semiconductor device. The negative bias voltage can be applied to the semiconductor device through a separate external port.

[0034] In this embodiment, after the step S400: performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form deep trenches, the following steps are also included: The sidewalls of the deep trench are implanted with angled heavy ions. In this embodiment, the angled heavy ion implantation is a P-type implantation.

[0035] In the electron-hole pairs generated by radiation on the sidewalls of the isolated deep trenches, the hole migration speed is slow and they are easily captured by the sidewalls of the deep trenches, thereby accumulating positive charges in these areas. As the total ionization dose increases, the number of accumulated charges will also increase. In order to solve this problem, the present application adopts an angled heavy ion implantation method for the sidewalls of the deep trenches, which increases the difficulty of generating an inversion layer on the semiconductor side of the deep trench sidewalls (the single crystal silicon side close to the device area). It is a key process for the total ionization dose protection of the sidewalls of the isolated deep trenches, and heavy ion doping must be performed. Angled heavy ion implantation uses high-concentration ions on the basis of ordinary ion implantation, allowing the ion beam to be incident at a certain angle to the normal to the wafer surface. This type of implantation method is conducive to improving the controllability of ion implantation, and by precisely controlling the angle and dose of ion implantation, it is beneficial to improve the operating performance of semiconductor devices.

[0036] In this embodiment, after the step S400: performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form deep trenches, the following steps are also included: An isolation layer is formed on the sidewall of the deep trench. In this embodiment, the isolation layer is a silicon dioxide isolation layer, which forms electrical isolation by filling the sidewall of the deep trench to prevent leakage current between adjacent structures.

[0037] In this embodiment, forming an isolation layer on the sidewall of the deep trench includes the following steps: Tetraethyl orthosilicate (TEOS) is grown to form an isolation layer on the side of the hard mask layer away from the epitaxial layer and in the deep trench. The grown TEOS can be used as a silicon source for chemical vapor deposition (CVD). The silicon dioxide isolation layer is formed by chemical vapor deposition process.

[0038] In this embodiment, the step S500: etching the deep trench to penetrate the buried oxide layer includes the following steps: The deep trench is etched by a blank etching process to expand the cavity diameter of the deep trench and make the deep trench penetrate the buried oxide layer. The blank etching process is a maskless etching process that adjusts the trench size by isotropic etching (such as wet etching).

[0039] In this embodiment, after the step S700 of forming an active layer on a side of the epitaxial layer away from the buried oxide layer, the following steps are further included: An interlayer dielectric layer (ILD) is formed on the side of the active layer away from the epitaxial layer; the interlayer dielectric layer mainly plays the role of insulating and protecting the active layer to prevent short circuits between different metal interconnection layers; the interlayer dielectric layer is usually made of insulating materials such as silicon dioxide or silicon nitride and is formed by methods such as chemical vapor deposition; A plurality of contact holes (CT) are formed in the interlayer dielectric layer, and the positions of the contact holes correspond to the positions of the terminals in the active layer; the formation of the contact holes requires photolithography and etching processes to accurately define the positions and sizes of the contact holes in the interlayer dielectric layer; The contact holes are filled with conductive metal, such as metal tungsten, to lead out various terminals of the active layer.

[0040] Combine the following Figure 2~Figure 10 The implementation process of the method for preparing the semiconductor device in a specific example is specifically introduced. It is understandable that the structures shown in the figure and the following description are only examples and are not intended to limit the scope of protection of the present application.

[0041] Figure 2 FIG. 1 is a schematic diagram of performing ion implantation below a buried oxide layer according to an embodiment of the present application. Figure 2As shown, corresponding to steps S100 and S200, a P-type substrate 100 is provided, and a buried oxide layer 200 is provided above the P-type substrate 100. The buried oxide layer 200 is generally formed by processes such as oxygen injection isolation or bonding, and its thickness is determined according to the performance requirements of the device. Ions are implanted into the P-type substrate 100 below the buried oxide layer 200 where the P-type AA region is to be formed, to form an N+ doped region and an N- doped region. By precisely controlling the position and type of ion implantation, precise control of device characteristics can be achieved. A P-silicon film 300 is also provided above the buried oxide layer 200.

[0042] Figure 3 It is a schematic diagram after forming a hard mask layer according to an embodiment of the present application. Figure 4 It is a schematic diagram of coating photoresist on the hard mask layer according to an embodiment of the present application. Figure 5 FIG. 1 is a schematic diagram of an embodiment of the present application after photolithography. Figure 6 It is a schematic diagram of an embodiment of the present application, after deep trench isolation etching is performed using a hard mask layer as a shielding layer, thermal oxidation is performed to form Liner OX to repair the dangling bonds in the exposed area of ​​the sidewall after etching. Figure 7 FIG. 1 is a schematic diagram of an embodiment of the present application after forming a deep groove. Figure 3 As shown, corresponding to step S400, a P-type epitaxial layer (P-EPI, P-Epitaxy) 400 and a hard mask layer 500 are formed on the P-type silicon film 300. In step S400, the hard mask layer 500 and the epitaxial layer 400 are subjected to deep trench isolation etching to form deep trenches through two-step etching. Figure 4 As shown, the first step of etching includes: firstly coating a photoresist 1001 on the top of the hard mask layer, irradiating the photoresist 1001, and then etching the hard mask layer 500 to form a groove in the hard mask layer 500, that is, forming a Figure 5 The structure shown in FIG. 5 is used to transfer the pattern of the mask to the hard mask layer 500. Figure 6 As shown, the second etching step includes: using the hard mask layer 500 with deep trench plane pattern as a shielding layer to perform deep trench isolation etching, which is the main process step. The deep trench formed by two etchings can better realize the electrical function of the deep trench in the semiconductor device. The first etching can focus on controlling the initial shape of the hard mask, and the second etching focuses on expanding the cavity diameter, sidewall angle and subsequent penetration to the buried oxide layer 200. Further, as Figure 6 As shown, Liner OX is formed on the sidewalls of the deep trenches by thermal oxidation to repair dangling bonds in the exposed areas of the sidewalls of the epitaxial layer 400 and the P-type silicon film 300 .

[0043] like Figure 7As shown, after a longitudinal deep trench 600 is formed in the hard mask layer 500, the epitaxial layer 400 and the P-type silicon film 300 by using a deep trench isolation etching method, an angled heavy ion P-type implantation is performed on the sidewall of the deep trench 600. This implantation method can form a specific P-type doping region on the sidewall of the deep trench 600 to adjust the electrical properties of the deep trench 600. Here, the deep trench 600 refers to a trench that vertically penetrates the hard mask layer 500, the epitaxial layer 400 and the P-type silicon film 300.

[0044] Figure 8 FIG. 1 is a schematic diagram of an embodiment of the present application after forming an isolation layer. Figure 8 As shown, tetraethyl orthosilicate is grown to form an isolation layer 700 on the side of the hard mask layer 500 away from the epitaxial layer 400 and in the deep groove 600. Tetraethyl orthosilicate can be used as a silicon source for chemical vapor deposition. The isolation layer 700 of silicon dioxide material is formed by chemical vapor deposition process. Specifically, during the chemical vapor deposition process, tetraethyl orthosilicate will be heated and decomposed or chemically reacted to release silicon atoms and other related groups. These silicon atoms will react with other reactive gases or substances, and finally deposit on a specific surface to form a silicon dioxide film, i.e., the isolation layer 700. The isolation layer 700 covers the sidewalls of the deep groove 600 to form electrical isolation and prevent leakage current between adjacent structures. The chemical vapor deposition process can accurately control the thickness and quality of the isolation layer 700 to ensure that it has good insulation properties.

[0045] Fig. 9 It is a schematic diagram of a deep trench penetrating through the buried oxide layer according to an embodiment of the present application. Fig.10 Schematic diagram of an embodiment of the present application after filling with polysilicon. Fig. 9 As shown, corresponding to step S500, the adjusted Blank Etch process is used to etch the deep trench, expand the cavity diameter of the deep trench and make the deep trench penetrate the buried oxide layer 200, thereby establishing a channel connected to the buried oxide layer 200. Expanding the cavity diameter of the deep trench can provide sufficient space for subsequent filling of polysilicon, and making the deep trench penetrate the buried oxide layer establishes a channel connected to the buried oxide layer, thereby creating conditions for forming a conductive path. Fig.10 As shown, corresponding to step S500 , N-type polysilicon 800 is filled in the deep trench to form a conductive path extending to and passing through the buried oxide layer 200 .

[0046] Fig.11 Schematic diagram of chemical mechanical polishing after one embodiment of the present application. Fig.11As shown, corresponding to step S600, DTI-CMP (deep trench isolation-chemical mechanical polishing) is performed until the hard mask layer 500 stops. DTI-CMP combines the deep trench isolation process with the chemical mechanical polishing process to provide a flat and insulating surface for the subsequent semiconductor device manufacturing process, which helps to improve the performance and reliability of the chip. The hard mask layer 500 serves as an etch stop layer. The hard mask layer 500 can optionally use a silicon nitride (SiN) layer, and the difference in polishing rates between silicon nitride and silicon dioxide / polysilicon is used to achieve an etching stop effect, which is conducive to accurately controlling the polishing end point. When polishing to the hard mask layer 500, since the polishing rate of the hard mask layer 500 is slow, polishing can be stopped in time to avoid excessive polishing and damaging the epitaxial layer 400 below.

[0047] Fig.12 FIG. 1 is a schematic diagram of an embodiment of the present application after forming an active layer. Fig.12 As shown, corresponding to step S600, the hard mask layer is removed by dry etching or wet etching to expose the epitaxial layer 400. Corresponding to step S700, an active layer 900 is formed on the side of the epitaxial layer 400 away from the buried oxide layer 200 (including the use of gate formation, source and drain injection and other processes), completing the FEOL (Front-End-of-Line) manufacturing of the semiconductor device. Fig.12 In the figure, G, D, and source represent the corresponding positions of the gate, drain, and source respectively, NWL (N-Well Layer) represents the N-type well layer, HNN (High-Voltage N-layer) represents the high-voltage N layer, and PBD (P-type Body Diode) represents the P-type body diode.

[0048] Fig.13 Schematic diagram of the structure of a semiconductor device according to an embodiment of the present application. Fig.13 As shown, an interlayer dielectric layer 110 is formed on the side of the active layer away from the epitaxial layer 400. The interlayer dielectric layer 110 is generally made of insulating materials, such as silicon dioxide, etc., and is used to provide electrical isolation to prevent current short circuits between different layers. A plurality of contact holes 120 are formed in the interlayer dielectric layer 110, and the positions of the contact holes 120 correspond to the positions of the terminals in the active layer. Conductive metal, such as metal tungsten, is filled in the contact holes 120 to lead out the terminals of the active layer.

[0049] like Fig.13 As shown, the embodiment of the present application further provides a semiconductor device, which is obtained by using the semiconductor device preparation method, and the semiconductor device includes: P-type substrate 100; The buried oxide layer 200 is provided on one side of the P-type substrate 100. A lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region are formed on the side of the P-type substrate 100 facing the buried oxide layer 200. Therefore, an N+ doped region and an N- doped region are formed below the buried oxide layer 200 corresponding to the active region. The N+ doped region is formed by high-dose N-type impurity ion implantation, has a high impurity concentration and good conductivity, and is mainly used to form an ohmic contact and reduce the contact resistance of the device. The N- doped region is formed by low-dose N-type impurity ion implantation, has a relatively low impurity concentration, and can be used to adjust the electrical properties of the device, such as threshold voltage, etc. An epitaxial layer 400 is formed on a side of the buried oxide layer 200 away from the P-type substrate 100, and deep grooves are formed in the epitaxial layer 400 and the buried oxide layer 200, and the deep grooves are filled with polysilicon; a P-type silicon film 300 may also be provided between the buried oxide layer 200 and the epitaxial layer 400, and the deep grooves are opposite to the heavily doped N-type region; Active layer 900 (indicated at Fig.12 ), formed on the side of the epitaxial layer 400 away from the buried oxide layer 200. The active layer 900 is the core area of ​​the semiconductor device to realize the electrical function, and includes various active devices such as transistors and diodes.

[0050] The semiconductor device is obtained by adopting the above-mentioned method for preparing the semiconductor device, and the technical effect of the above-mentioned method for preparing the semiconductor device can be obtained, which will not be traced here.

[0051] In this embodiment, if Fig.13 As shown, an interlayer dielectric layer 110 is also arranged above the active layer 900, and a plurality of contact holes 120 are formed in the interlayer dielectric layer. The contact holes 120 are filled with a conductive metal (not shown in the figure), such as metal tungsten, and some of the contact holes 120 are opposite to the polysilicon filled in the deep trench. The interlayer dielectric layer 110 mainly plays the role of insulating and protecting the active layer 900 to prevent short circuits between different metal interconnection layers. The function of the contact holes 120 is to achieve electrical connection between the active layer 900 and the upper metal interconnection layer. The semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

[0052] In summary, the semiconductor device and preparation method provided by the present application have the following advantages: The present application is further expanded based on the deep trench isolation technology to produce a polysilicon-filled deep trench isolation that passes through the buried oxide layer in the SOI substrate. The charges accumulated in the buried oxide layer are guided out of the substrate through the polysilicon portion in the deep trench isolation to avoid charge retention in the buried oxide layer, so that the electric field of the buried oxide layer is restored to balance, and ionizing radiation is prevented from charging the buried oxide layer due to the Bragg effect, resulting in an unexpected inversion layer. This is beneficial to improving the semiconductor device's ability to resist ionizing radiation, improving the reliability of semiconductor devices when used in harsh environments, and improving the comprehensive performance of space technology equipment.

[0053] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The semiconductor device is a SOI BCD device, and the method comprises the following steps: Providing a P-type substrate, wherein a buried oxide layer is provided on one side of the P-type substrate; Performing N-type ion implantation on a side of the buried oxide layer facing the P-type substrate to form a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region; forming an epitaxial layer and a hard mask layer on a side of the buried oxide layer away from the P-type substrate; Performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form deep trenches; Etching the deep trench to penetrate the buried oxide layer, and filling the deep trench with polysilicon, wherein the deep trench is opposite to the heavily doped N-type region; After chemical mechanical polishing to the hard mask layer, removing the hard mask layer; forming an active layer on a side of the epitaxial layer away from the buried oxide layer; forming an interlayer dielectric layer on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; A conductive metal is filled in the contact hole, and the semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

2. The method for preparing a semiconductor device according to claim 1, wherein: After the hard mask layer and the epitaxial layer are subjected to deep trench isolation etching to form deep trenches, the following steps are also included: Angle heavy ion implantation is performed on the sidewalls of the deep trench.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: After the hard mask layer and the epitaxial layer are subjected to deep trench isolation etching to form deep trenches, the following steps are also included: An isolation layer is formed on the sidewall of the deep trench.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: Forming an isolation layer on the sidewall of the deep trench comprises the following steps: TEOS is grown to form an isolation layer on a side of the hard mask layer away from the epitaxial layer and in the deep trench.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: Etching the deep trench to penetrate the buried oxide layer comprises the following steps: The deep trench is etched by adopting a full etching process to expand the cavity diameter of the deep trench and make the deep trench pass through the buried oxide layer.

6. The method for preparing a semiconductor device according to claim 1, wherein: Filling polysilicon in the deep trench includes: filling N-type polysilicon in the deep trench.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The removing of the hard mask layer includes removing the hard mask layer by dry etching or wet etching.

8. A semiconductor device, characterized in that: The semiconductor device is obtained by the method for preparing a semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is a SOI BCD device and comprises: P-type substrate; A buried oxide layer is provided on one side of the P-type substrate, wherein a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region are formed on a side of the P-type substrate facing the buried oxide layer; An epitaxial layer is formed on a side of the buried oxide layer away from the P-type substrate, a deep trench is formed in the epitaxial layer and the buried oxide layer, the deep trench is filled with polysilicon, and the deep trench is opposite to the heavily doped N-type region; An active layer formed on a side of the epitaxial layer away from the buried oxide layer; An interlayer dielectric layer, formed on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; A conductive metal is filled in the contact hole, and the semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

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