Integrated circuit and method of manufacturing the same

Abstract

An integrated circuit and a method of manufacturing the same are disclosed. The integrated circuit may include: a plurality of wells extending parallel to each other in a first direction on a substrate having a first conductivity type, the plurality of wells having a second conductivity type; a plurality of first doped regions disposed on the plurality of wells in the first region and the second region, the first region being separated from the second region in the first direction, the plurality of first doped regions having a first conductivity type; a plurality of second doped regions disposed on the substrate between the plurality of wells in the first region and the second region and having a second conductivity type; and a plurality of third doped regions disposed in a third region of the substrate between the first region and the second region and having the first conductivity type.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0153101 filed on November 7, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosure relates to integrated circuits and methods of manufacturing the integrated circuits. Background Art

[0003] An integrated circuit may include not only devices such as transistors but also structures for driving the devices or preventing leakage current from occurring. For example, an integrated circuit may include a structure for biasing a substrate or a well on which the devices are disposed, and the substrate and the well may be biased. Due to the advancement of semiconductor processes, the size of devices included in an integrated circuit may be reduced, and various limitations may occur due to the reduced size of the devices. Summary of the invention

[0004] In view of the above concerns, an effective structure for protecting or driving a device may be desirable.

[0005] An integrated circuit including a bias unit for providing a reduced area and a method of manufacturing the integrated circuit are disclosed.

[0006] According to the disclosed example embodiments, an integrated circuit may include: a plurality of wells extending parallel to each other along a first direction on a substrate having a first conductivity type, the plurality of wells having a second conductivity type; a plurality of first doped regions disposed on the plurality of wells in a first region and a second region, the first region and the second region being separated from each other in the first direction, the plurality of first doped regions having the first conductivity type; a plurality of second doped regions disposed on the substrate between the plurality of wells in the first region and the second region and having the second conductivity type; a plurality of third doped regions disposed in a third region of the substrate between the first region and the second region and having the first conductivity type; and a plurality of fourth doped regions disposed on the plurality of wells in the third region and having the second conductivity type. The third region may extend in a second direction perpendicular to the first direction.

[0007] According to a disclosed example embodiment, an integrated circuit may include: a plurality of functional units arranged in a first region and a second region, the first region and the second region being separated from each other in a first direction; and a series of bias units arranged in a third region of a substrate between the first region and the second region, the third region extending in a second direction perpendicular to the first direction, wherein the series of bias units may include: a plurality of first bias units configured to bias the substrate and having a first conductivity type; and a plurality of second bias units configured to bias a plurality of wells, the plurality of wells extending parallel to each other along the first direction on the substrate and having a second conductivity type, wherein the plurality of first bias units and the plurality of second bias units are alternately arranged in the second direction.

[0008] According to a disclosed example embodiment, a method for manufacturing an integrated circuit may include: laying out a bias unit for biasing a substrate and a plurality of wells, the substrate having a first conductivity type, the plurality of wells extending parallel to each other along a first direction on the substrate and having a second conductivity type; and laying out a functional unit in an area where the bias unit is not laid out based on input data. The step of laying out the bias unit may include: alternately laying out a plurality of first bias units for biasing the substrate and a plurality of second bias units for biasing the plurality of wells in a second direction perpendicular to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of some disclosed embodiments will become more apparent from the following description in conjunction with the accompanying drawings, in which: Figure 1 is a plan view of a layout of an integrated circuit according to one or more embodiments; Figure 2A is a cross-sectional view of an example of a layout of an integrated circuit according to one or more embodiments; Figure 2B is a cross-sectional view of an example of a layout of an integrated circuit according to one or more embodiments; Figure 3A is a diagram of an example of a device according to one or more embodiments; Figure 3B is a diagram of an example of a device according to one or more embodiments; Figure 3C is a diagram of an example of a device according to one or more embodiments; Figure 3D is a diagram of an example of a device according to one or more embodiments; Figure 4 is a view schematically illustrating a process of forming a doped region according to one or more embodiments; Figure 5A is a plan view of a doping region according to one or more embodiments; Figure 5B is a plan view of a layout of an integrated circuit according to one or more embodiments; Fig. 6A is a plan view of a doped region according to one or more embodiments; Figure 6B is a plan view of a layout of an integrated circuit according to one or more embodiments; Figure 7 is a plan view of a doped region according to one or more embodiments; Figure 8 is a plan view of a layout of an integrated circuit according to one or more embodiments; Fig. 9 is a flow chart of a method of manufacturing an integrated circuit according to one or more embodiments; Fig.10 is a flow chart of a method of manufacturing an integrated circuit according to one or more embodiments; Fig.11 is a block diagram of a system on a chip (SoC) according to one or more embodiments; and Fig.12 is a block diagram of a computing system including a memory storing programs according to one or more embodiments. DETAILED DESCRIPTION

[0010] Figure 1 is a layout of an integrated circuit according to one or more embodiments Fig.10 For example, Figure 1 The plan view shows a layout corresponding to a portion of an integrated circuit in a plane defined by an X-axis and a Y-axis. Fig.10 .

[0011] Here, the X-axis direction and the Y-axis direction may be referred to as the first direction and the second direction, respectively, and the Z-axis direction may be referred to as the vertical direction or the third direction. The plane defined by the X-axis and the Y-axis may be referred to as the horizontal plane. An element that is relatively more offset than other elements in the +Z direction may be referred to as being arranged above the other elements, and an element that is relatively more offset than other elements in the -Z direction may be referred to as being arranged below the other elements. In addition, the area of ​​an element may represent the size occupied by the element in a plane parallel to the horizontal plane, and the width of the element may represent the length of the element in a direction intersecting with the direction in which the element extends. The surface exposed in the +Z direction may be referred to as the top surface, the surface exposed in the -Z direction may be referred to as the bottom surface, and the surface exposed in the ±X direction or the ±Y direction may be referred to as the side surface. In the accompanying drawings, for ease of illustration, only some layers may be shown.

[0012] Reference Figure 1 ,cloth Fig.10 The substrate SUB may be included, and a first well W11 and a second well W12 may be included on the substrate SUB and extend parallel to each other in the X-axis direction. Devices (eg, transistors) may be provided on the substrate SUB, the first well W11, and the second well W12, and patterns for connecting the transistors to each other may be provided above the transistors. FIG. 3A to FIG. 3D An example of a transistor is described. According to some embodiments, the integrated circuit may include a backside pattern arranged below a substrate SUB, and may include a via (e.g., a through silicon via (or through silicon via, TSV)) connecting the backside pattern to a device and / or to a pattern arranged above the device. Here, it is assumed that the substrate SUB may be doped with a P-type material, and the well may be doped with an N-type material. However, the embodiment is not limited thereto.

[0013] An integrated circuit may include a plurality of units. Figure 1 As shown in Fig.10 The first cell C1 arranged in the first row ROW1, the second cell C2 arranged in the second row ROW2, the third cell C3 arranged in the third row ROW3 and the fourth row ROW4 continuously, and the fourth cell C4 arranged in the fourth row ROW4 may be included. The first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4 may extend in the X-axis direction and may have a height H. According to some embodiments, the rows may have different heights from each other. The cell may be a unit of a layout included in an integrated circuit and may be referred to as a standard cell. The cell may include a transistor and may be designed to perform a predefined function. The cells arranged in one row (such as the first cell C1, the second cell C2, and the fourth cell C4) may be referred to as a single-height cell and may have a height H. The cells arranged in two or more rows continuously (such as the third cell C3) may be referred to as a multi-height cell.

[0014] N-channel field effect transistors (NFETs) may be arranged on the substrate SUB, and P-channel field effect transistors (PFETs) may be arranged on the first well W11 and the second well W12. Figure 1 As shown in , the cell may be stacked with a substrate SUB and a well, and therefore, the cell may include an NFET arranged on the substrate SUB and a PFET arranged on the well. In order to drive the NFET, the substrate SUB may be biased to a negative power supply voltage (which may be referred to herein as a first power supply voltage), and in order to drive the PFET included in the cell, the first well W11 and the second well W12 may be biased to a positive power supply voltage (which may be referred to herein as a second power supply voltage).

[0015] The integrated circuit may include a unit for biasing the substrate SUB, the first well W11, and the second well W12, and the unit may be regularly arranged in the layout. Fig.10 For example, Figure 1 As shown in Fig.10 A series of units arranged in the first column COL1, the second column COL2, and the third column COL3 and biasing the substrate SUB, the first well W11, and / or the second well W12 may be included. Here, the unit biasing the substrate SUB and / or the well may be referred to as a bias unit, and the units other than the bias unit (e.g., the first unit C1 to the fourth unit C4) may be referred to as functional units. The bias unit may provide a power supply voltage for driving the transistor, and may prevent latch-up to prevent leakage current from occurring.

[0016] As described above with reference to the drawings, the bias unit may have a reduced width (ie, a length in the X-axis direction). Therefore, the width (ie, the length in the X-axis direction) of each of the first column COL1, the second column COL2, and the third column COL3 may be reduced. Fig.10 The area of ​​the integrated circuit can be reduced, and the efficiency of the integrated circuit can be improved. In addition, the bias unit can have a simple structure, and therefore, the cost of the integrated circuit can be reduced, and the yield of the integrated circuit can be improved.

[0017] Figure 2A and Figure 2B is a cross-sectional view of an example of a layout of an integrated circuit according to an embodiment. For example, Figure 2A The cross-sectional view shows Figure 1 Cloth Fig.10 An example of a cross-sectional view taken along line Y1-Y1', and Figure 2B The cross-sectional view shows Figure 1 Cloth Fig.10 An example of a cross-sectional view taken along line Y2-Y2'. Figure 1 To describe Figure 2A and Figure 2B , and in regard to Figure 2A and Figure 2B In the description of the present invention, the same aspects will not be described repeatedly.

[0018] Reference Figure 2A , the layout 21 may include a substrate SUB, and may include a first well W11 and a second well W12 extending parallel to each other along the X-axis direction on the substrate SUB. Figure 1As described above, the NFET may be arranged on the substrate SUB, and the PFET may be arranged on the first well W11 and the second well W12. Therefore, the N+ region corresponding to the source / drain of the NFET may be arranged on the substrate SUB, and the P+ region corresponding to the source / drain of the PFET may be arranged on the first well W11 and the second well W12. For example, Figure 2A As shown in , the first N+ region N11, the second N+ region N12, the third N+ region N13, and the fourth N+ region N14 may be disposed on the substrate SUB, and the first P+ region P11, the second P+ region P12, the third P+ region P13, and the fourth P+ region P14 may be disposed on the first well W11 and the second well W12. According to some embodiments, the P+ region may have a higher doping concentration than that of the substrate SUB, and the N+ region may have a higher doping concentration than that of the first well W11 and the second well W12. Here, the N+ region may be referred to as an N-type doped region, the P+ region may be referred to as a P-type doped region, and the N+ region and the P+ region may be collectively referred to as a doped region.

[0019] Reference Figure 2B , the layout 22 may include a substrate SUB, and may include a first well W11 and a second well W12 extending parallel to each other along the X-axis direction on the substrate SUB. Figure 1 As described above, the bias unit may be arranged in the second column COL2, and the bias unit may bias the substrate SUB, the first well W11, or the second well W12. The conductivity type of the substrate SUB may be P type, and a P+ region may be provided on the substrate SUB to bias the substrate SUB. For example, Figure 2B As shown in , the second P+ region P22 and the fourth P+ region P24 may be disposed on the substrate SUB, and a negative power supply voltage may be applied to the second P+ region P22 and the fourth P+ region P24. In addition, the conductivity type of the first well W11 and the second well W12 may be N-type, and an N+ region may be disposed on the first well W11 and the second well W12 to bias the first well W11 and the second well W12. For example, Figure 2B As shown in FIG. 1 , the second N+ region N22 and the fourth N+ region N24 may be disposed on the first well W11 and the second well W12 , and a positive power supply voltage may be applied to the second N+ region N22 and the fourth N+ region N24 .

[0020] According to some embodiments, contacts and / or vias may be arranged in the second P+ region P22 and the fourth P+ region P24, and the contacts and / or vias may be connected to the pattern of the wiring layer providing the negative power supply voltage. According to some embodiments, TSVs passing through the substrate may be arranged in the second P+ region P22 and the fourth P+ region P24, and the TSVs may be connected to the pattern of the backside wiring layer providing the negative power supply voltage. According to some embodiments, contacts may be arranged in the second N+ region N22 and the fourth N+ region N24, and vias may be arranged on the contacts, wherein the vias may be connected to the pattern of the wiring layer providing the positive power supply voltage. According to some embodiments, TSVs passing through the substrate may be arranged in the second N+ region N22 and the fourth N+ region N24, and the TSVs may be connected to the pattern of the backside wiring layer providing the positive power supply voltage.

[0021] According to some embodiments, the bias unit may include not only a doped region for biasing the substrate SUB and the well, but also an additional doped region. Figure 2B As shown in , the first N+ region N21 and the third N+ region N23 disposed on the substrate SUB may be disposed in the second column COL2, and the first P+ region P21 disposed on the first well W11 and the third P+ region P23 disposed on the second well W12 may be disposed in the second column COL2. According to some embodiments, the additional doping region may be removed from the bias unit. For example, Figure 2B The first N+ region N21, the first P+ region P21, the third N+ region N23, and the third P+ region P23 may be removed after being formed through a semiconductor process.

[0022] FIG. 3A to FIG. 3D is a diagram of an example of a device according to an embodiment. For example, Figure 3A A fin field effect transistor (FinFET) 30 a is shown, Figure 3B A gate all around field effect transistor (GAAFET) 30b is shown, Figure 3C A multi-bridge channel field effect transistor (MBCFET) 30c is shown, and Figure 3D A vertical field effect transistor (VFET) 30d is shown. For ease of illustration, FIG. 3A to FIG. 3C shows the shape with one of the source / drain regions removed, and Figure 3D A cross-sectional view of the VFET 30 d is shown, taken along a plane passing through the channel CH of the VFET 30 d and parallel to a plane defined by the Y-axis and the Z-axis.

[0023] Reference Figure 3A, the FinFET 30a may be formed by an active pattern having a fin shape extending in the X-axis direction between shallow trench isolations (STIs) and a gate electrode G extending in the Y-axis direction. Source / drain regions SD may be formed on both sides of the gate electrode G, and thus, the source and the drain may be spaced apart from each other in the X-axis direction. An insulating layer may be formed between the channel CH and the gate electrode G. According to some embodiments, the FinFET 30a may be formed by the gate electrode G and a plurality of active patterns spaced apart from each other in the Y-axis direction, and may have an extended channel.

[0024] Reference Figure 3B , the GAAFET 30b may be formed by active patterns (i.e., nanowires) spaced apart from each other in the Z-axis direction and extending in the X-axis direction, and a gate electrode G extending in the Y-axis direction. The source / drain regions SD may be formed on both sides of the gate electrode G, and thus, the source and the drain may be spaced apart from each other in the X-axis direction. An insulating layer may be formed between the channel CH and the gate electrode G. It may be noted that the number of nanowires included in the GAAFET 30b is not limited to Figure 3B The quantity shown in .

[0025] Reference Figure 3C , the MBCFET 30c may be formed by active patterns (i.e., nanosheets) spaced apart from each other in the Z-axis direction and extending in the X-axis direction, and a gate electrode G extending in the Y-axis direction. The source / drain regions SD may be formed on both sides of the gate electrode G, and thus, the source and the drain may be spaced apart from each other in the X-axis direction. An insulating layer may be formed between the channel CH and the gate electrode G. It may be noted that the number of nanosheets included in the MBCFET 30c is not limited to Figure 3C The quantity shown in .

[0026] Reference Figure 3D , the VFET 30d may include a top source / drain region T_SD and a bottom source / drain region B_SD, the top source / drain region T_SD and the bottom source / drain region B_SD are spaced apart from each other in the Z-axis direction, and a channel CH is between the top source / drain region T_SD and the bottom source / drain region B_SD. The VFET 30d may include a gate electrode G surrounding the periphery of the channel CH between the top source / drain region T_SD and the bottom source / drain region B_SD. An insulating layer may be formed between the channel CH and the gate electrode G.

[0027] Hereinafter, an integrated circuit including the FinFET 30A or the MBCFET 30C will be mainly described. However, it may be noted that the devices included in the integrated circuit are not limited to FIG. 3A to FIG. 3DFor example, the integrated circuit may include a fork field effect transistor (ForkFET), in which a nanosheet for a P-type transistor and a nanosheet for an N-type transistor are separated from each other by a dielectric wall, so that the N-type transistor and the P-type transistor may have a structure with increased proximity. In addition, the integrated circuit may include not only FETs (such as complementary field effect transistors (CFETs), negative capacitance field effect transistors (NCFETs), carbon nanotube (CNT) FETs, etc.), but also bipolar junction transistors.

[0028] Figure 4 Schematically illustrates a process of forming a doped region according to one or more embodiments. Figure 4 The process of forming a doped region in a layout 40 in which a functional unit is arranged is shown. As described above with reference to the drawings, an N+ region corresponding to the source / drain of an NFET may be arranged on a substrate SUB, and a P+ region corresponding to the source / drain of a PFET may be arranged on a well.

[0029] Reference Figure 4 , the layout 40 may include a substrate SUB and a first well W41 and a second well W24 extending parallel to each other along the X-axis direction on the substrate SUB. A first sub-process 41 for forming an N+ region on the substrate SUB may be performed on the layout 40. For example, Figure 4 As shown in , the first sub-process 41 may form N+ regions in the first N-doped region ND1, the second N-doped region ND2, and the third N-doped region ND3 corresponding to the upper surface of the substrate SUB exposed in the +Z-axis direction, for example, by implantation. In addition, a second sub-process 42 for forming a P+ region on the well may be performed on the layout 40. For example, as Figure 4 As shown in , the second sub-process 42 may form a P+ region in the first P-doped region PD1 and the second P-doped region PD2 corresponding to the first well W41 and the second well W42, for example, by implantation. Each of the doped regions formed by the first sub-process 41 and the second sub-process 42 may be divided into a plurality of doped regions, or may be partially removed by a subsequent process. Here, a region doped with impurities by a sub-process to form a doped region in a layout may be referred to as a doped region.

[0030] like Figure 4 As shown in , the doped region may have a width (i.e., a length in the Y-axis direction) corresponding to the height H of the row (or single-height cell). As the size of the transistors included in the integrated circuit decreases, the size of the cell may decrease, and the height H of the row may decrease. Due to semiconductor processes, it is difficult and / or expensive to manufacture a doped region having a width smaller than its height H. Therefore, as described below with reference to Figure 5A , Fig. 6A and Figure 7 As described above, a doping region for forming a P+ region disposed on the substrate SUB and an N+ region disposed on the well (ie, a doped region included in the bias unit) may be useful.

[0031] Figure 5A is a plan view of a doped region according to one or more embodiments, and Figure 5B is a plan view of a layout 50 of an integrated circuit according to one or more embodiments. For example, Figure 5A The plan view shows doped regions used to form doped regions in a layout 50 of an integrated circuit, and Figure 5B Shown including through Figure 5A For ease of explanation, although Figure 5B The doped regions extending in the X-axis direction are shown, but each of the doped regions may be divided into a plurality of doped regions, or may be partially removed by subsequent processes. Figure 8 As described above, each of the doped regions may be separated by a diffusion break and / or a gate electrode extending in the Y-axis direction. Figure 5A and Figure 5B In the description, the same aspects will not be described repeatedly.

[0032] Reference Figure 5A , the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4 may extend in the X-axis direction. The functional unit may be disposed in the first region R1 and the second region R2, and the bias unit may be disposed in the third region R3 between the first region R1 and the second region R2. The first region R1 and the second region R2 are separated from each other in the X-axis direction. For example, the first bias unit C51, the second bias unit C52, the third bias unit C53, and the fourth bias unit C54 may be arranged in the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4, respectively. As described above with reference to Figure 4 As mentioned above, when the doped region has a width smaller than its height H, fabrication may be difficult. Figure 5A As shown in , each of the N-doped region and the P-doped region may have a shape having a length in the X-axis direction and in the Y-axis direction that is greater than or equal to the height H. The length of the third region R3 in the X-axis direction (i.e., the widths of the first bias unit C51, the second bias unit C52, the third bias unit C53, and the fourth bias unit C54) may correspond to the first length L1.

[0033] Reference Figure 5B, the layout 50 may include a substrate SUB and a first well W51 and a second well W52 extending parallel to each other along the X-axis direction on the substrate SUB. In addition, the layout 50 may include Figure 5A For example, Figure 5B As shown in , the layout 50 may include a first N+ region N11, a second N+ region N12, a third N+ region N13, a fourth N+ region N14, a first P+ region P11, a second P+ region P12, a third P+ region P13, and a fourth P+ region P14 disposed in the first region R1. In addition, the layout 50 may include a first N+ region N21, a second N+ region N22, a third N+ region N23, a fourth N+ region N24, a first P+ region P21, a second P+ region P22, a third P+ region P23, and a fourth P+ region P24 disposed in the second region R2. In addition, the layout 50 may include a first N+ region N31, a second N+ region N32, a third N+ region N33, a fourth N+ region N34, a first P+ region P31, a second P+ region P32, a third P+ region P33, and a fourth P+ region P34 disposed in the third region R3.

[0034] According to some embodiments, the first N+ region N31, the second N+ region N32, the third N+ region N33 and the fourth N+ region N34 disposed in the third region R3 may be aligned (or overlapped) with the first P+ region P11, the second P+ region P12, the third P+ region P13 and the fourth P+ region P14 disposed in the first region R1 in the X-axis direction, and may be aligned (or overlapped) with the first P+ region P21, the second P+ region P22, the third P+ region P23 and the fourth P+ region P24 disposed in the second region R2 in the X-axis direction. According to some embodiments, the first P+ region P31, the second P+ region P32, the third P+ region P33 and the fourth P+ region P34 disposed in the third region R3 may be aligned (or overlapped) with the first N+ region N11, the second N+ region N12, the third N+ region N13 and the fourth N+ region N14 disposed in the first region R1 in the X-axis direction, and may be aligned (or overlapped) with the first N+ region N21, the second N+ region N22, the third N+ region N23 and the fourth N+ region N24 disposed in the second region R2 in the X-axis direction.

[0035] When the N+ region and the P+ region provided in the first region R1 and the second region R2 may correspond to the source / drain region of the transistor, the N+ region and the P+ region provided in the third region R3 may correspond to the N+ region and the P+ region for biasing the substrate SUB and the well. For example, the first bias unit C51 may include a first P+ region P31 for biasing the substrate SUB and a first N+ region N31 for biasing the first well W51. The second bias unit C52 may include a second N+ region N32 for biasing the first well W51 and a second P+ region P32 for biasing the substrate SUB. The third bias unit C53 may include a third P+ region P33 for biasing the substrate SUB and a third N+ region N33 for biasing the second well W52. The fourth bias unit C54 may include a fourth N+ region N34 for biasing the second well W52 and a fourth P+ region P34 for biasing the substrate SUB. When a positive power supply voltage may be applied to the first N+ region N31, the second N+ region N32, the third N+ region N33, and the fourth N+ region N34 disposed in the third region R3, a negative power supply voltage may be applied to the first P+ region P31, the second P+ region P32, the third P+ region P33, and the fourth P+ region P34 disposed in the third region R3. Figure 5A and Figure 5B In an example of , one bias unit may include both a P+ region for biasing the substrate SUB and an N+ region for biasing the well.

[0036] According to some embodiments, the N+ region and / or P+ region of the first region R1 and / or the second region R2 may extend to the third region R3. For example, at least one of the first N+ region N11 to the fourth N+ region N14 of the first region R1 and the first N+ region N21 to the fourth N+ region N24 of the second region R2 may extend in the X-axis direction to be close to at least one of the first P+ region P31 to the fourth P+ region P34 of the third region R3. In addition, at least one of the first P+ region P11 to the fourth P+ region P14 of the first region R1 and the first P+ region P21 to the fourth P+ region P24 of the second region R2 may extend in the X-axis direction to be close to at least one of the first N+ region N31 to the fourth N+ region N34 of the third region R3. As described above, the extended N+ region and P+ region may be separated by diffusion interruptions and / or gate electrodes extending in the Y-axis direction.

[0037] Fig. 6A is a plan view of a doped region according to one or more embodiments, and Figure 6B is a plan view of a layout 60 of an integrated circuit according to one or more embodiments. For example, Fig. 6AThe plan view shows doped regions used to form doped regions in a layout 60 of an integrated circuit, and Figure 6B Shown including through Fig. 6A For ease of explanation, although Figure 6B The doped regions extending in the X-axis direction are shown, but each of the doped regions may be divided into a plurality of doped regions or partially removed by subsequent processes. Figure 8 As described above, each of the doped regions may be separated by diffusion interrupts and / or gate electrodes extending in the Y-axis direction. Fig. 6A and Figure 6B In the description, the same aspects will not be described repeatedly.

[0038] Reference Fig. 6A , the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4 may extend in the X-axis direction. The functional unit may be disposed in the first region R1 and the second region R2, and the bias unit may be disposed in the third region R3 between the first region R1 and the second region R2. For example, the first bias unit C61, the second bias unit C62, the third bias unit C63, and the fourth bias unit C64 may be disposed in the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4, respectively. As described above with reference to Figure 4 As mentioned above, it may not be easy when the doped region has a width less than the height H. Therefore, as Fig. 6A As shown in , each of the N-doped region and the P-doped region may have a shape having a length in the X-axis direction and the Y-axis direction that is greater than or equal to the height H. The length of the third region R3 in the X-axis direction (i.e., the width of the first bias unit C61, the second bias unit C62, the third bias unit C63, and the fourth bias unit C64) may correspond to the second length L2, and the second length L2 may be less than Figure 5A and Figure 5B The first length L1.

[0039] Reference Figure 6B , the layout 60 may include a substrate SUB and a first well W61 and a second well W62 extending parallel to each other along the X-axis direction on the substrate SUB. In addition, the layout 60 may include Fig. 6A For example, Figure 6BAs shown in , the layout 60 may include a first N+ region N11, a second N+ region N12, a third N+ region N13, a fourth N+ region N14, a first P+ region P11, a second P+ region P12, a third P+ region P13, and a fourth P+ region P14 disposed in the first region R1. In addition, the layout 60 may include a first N+ region N21, a second N+ region N22, a third N+ region N23, a fourth N+ region N24, a first P+ region P21, a second P+ region P22, a third P+ region P23, and a fourth P+ region P24 disposed in the second region R2. In addition, the layout 60 may include a first N+ region N31, a second N+ region N32, a first P+ region P31, and a second P+ region P32 disposed in the third region R3. As shown in Figure 6B As shown in FIG, the first N+ region N31, the second N+ region N32, the first P+ region P31, and the second P+ region P32 may be aligned (or overlapped) in the Y-axis direction in the third region R3. The third region may extend in the Y-axis direction.

[0040] According to some embodiments, the first N+ region N31 and the second N+ region N32 disposed in the third region R3 may be aligned (or overlapped) with the first P+ region P11 and the third P+ region P13 disposed in the first region R1 in the X-axis direction, respectively, and may be aligned (or overlapped) with the first P+ region P21 and the third P+ region P23 disposed in the second region R2 in the X-axis direction. According to some embodiments, the first P+ region P31 and the second P+ region P32 disposed in the third region R3 may be aligned (or overlapped) with the second N+ region N12 and the fourth N+ region N14 disposed in the first region R1 in the X-axis direction, respectively, and may be aligned (or overlapped) with the second N+ region N22 and the fourth N+ region N24 disposed in the second region R2 in the X-axis direction.

[0041] When the N+ region and the P+ region provided in the first region R1 and the second region R2 may correspond to the source / drain region of the transistor, the N+ region and the P+ region provided in the third region R3 may correspond to the N+ region and the P+ region for biasing the substrate SUB and the well. For example, the first bias unit C61 may include a first N+ region N31 for biasing the first well W61. The second bias unit C62 may include a first P+ region P31 for biasing the substrate SUB. The third bias unit C63 may include a second N+ region N32 for biasing the second well W62. The fourth bias unit C64 may include a second P+ region P32 for biasing the substrate SUB. When a positive power supply voltage may be applied to the first N+ region N31 and the second N+ region N32 provided in the third region R3, a negative power supply voltage may be applied to the first P+ region P31 and the second P+ region P32 provided in the third region R3.

[0042] exist Fig. 6A and Figure 6B In the example of , one bias unit may include a P+ region for biasing the substrate SUB or an N+ region for biasing the well. Therefore, the bias unit for biasing the substrate SUB and the bias unit for biasing the well may be alternately arranged in the Y-axis direction in the third region. For example, when the first bias unit C61 and the third bias unit C63 respectively arranged in the first row ROW1 and the third row ROW3 may bias the first well W61 and the second well W62 respectively, the second bias unit C62 and the fourth bias unit C64 respectively arranged in the second row ROW2 and the fourth row ROW4 may bias the substrate SUB. Since the second length L2 is less than Figure 5A and 5B The first length L1, therefore Figure 5B Layout 60 may have a reduced area compared to layout 50 .

[0043] According to some embodiments, the N+ region and / or P+ region of the first region R1 and / or the second region R2 may extend to the third region R3. For example, the first N+ region N11 and the third N+ region N13 of the first region R1 may extend in the X-axis direction, the first N+ region N21 and the third N+ region N23 of the second region R2 may extend in the X-axis direction, and the first N+ region N11 and the third N+ region N13 of the first region R1 may be connected to the first N+ region N21 and the third N+ region N23 of the second region R2, respectively, in the third region R3. In addition, at least one of the second N+ region N12 and the fourth N+ region N14 of the first region R1 and the second N+ region N22 and the fourth N+ region N24 of the second region R2 may extend in the X-axis direction to approach at least one of the first P+ region P31 and the second P+ region P32 of the third region R3. For example, the second P+ region P12 and the fourth P+ region P14 of the first region R1 may extend in the X-axis direction, and the second P+ region P22 and the fourth P+ region P24 of the second region R2 may extend in the X-axis direction, and the second P+ region P12 and the fourth P+ region P14 of the first region R1 may be connected to the second P+ region P22 and the fourth P+ region P24 of the second region R2, respectively, in the third region R3. In addition, at least one of the first P+ region P11 and the third P+ region P13 of the first region R1 and the first P+ region P21 and the third P+ region P23 of the second region R2 may extend in the X-axis direction to approach at least one of the first N+ region N31 and the second N+ region N32 of the third region R3. As described above, the extended N+ region and the P+ region may be separated by diffusion interruptions and / or gate electrodes extending in the Y-axis direction.

[0044] Figure 7 is a plan view of a doped region according to one or more embodiments. For example, Figure 7 The plan view shows the Figure 6B The doping region of the doped region of the layout 60. Fig. 6A and Figure 6B describe Figure 7 .

[0045] Reference Figure 7 , the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4 may extend in the X-axis direction. The functional unit may be disposed in the first region R1 and the second region R2, and the bias unit may be disposed in the third region R3 between the first region R1 and the second region R2. For example, the first bias unit C71, the second bias unit C72, the third bias unit C73, and the fourth bias unit C74 may be disposed in the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4, respectively. As described above with reference to Figure 4As mentioned above, it may not be easy when the doped region has a width less than the height H. Therefore, as Fig. 6A As shown in , each of the N-doped region and the P-doped region may have a shape in which the N-doped region or the P-doped region may have a length greater than or equal to the height H in the X-axis direction and the Y-axis direction. The length of the third region R3 in the X-axis direction (i.e., the widths of the first bias unit C71, the second bias unit C72, the third bias unit C73, and the fourth bias unit C74) may correspond to the third length L3, and the third length L3 may be equal to Fig. 6A and Figure 6B The second length L2 is less than Figure 5A and Figure 5B The first length L1.

[0046] and Fig. 6A Compared to the example, Figure 7 The doped regions of the third region R3 may not be aligned (or overlapped) in a row. Fig. 6A The N-doped region in the third region R3 may include a portion offset from the N-doped regions of the first region R1 and the second region R2 in the -Y axis direction, and the offset portion may be aligned (or overlapped) in each of the boundaries of the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4. In addition, Fig. 6A The P-doped region in the third region R3 may include portions offset from the P-doped regions of the first region R1 and the second region R2 in the -Y axis direction, and the offset portions may be aligned (or overlapped) in each of the boundaries of the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4. Figure 7 The N-doped regions in the third region R3 may include portions offset from the N-doped regions of the first region R1 and the second region R2 in the -Y axis direction, and the offset portions may not be aligned (or overlapped) in each of the boundaries of the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4. Figure 7 The P-doped region in the third region R3 may include portions offset from the P-doped regions of the first region R1 and the second region R2 in the -Y axis direction, and the offset portions may not be aligned (or overlapped) in each of the boundaries of the first row ROW1, the second row ROW2, the third row ROW3, ​​and the fourth row ROW4.

[0047] Figure 8 is a plan view of a layout 80 of an integrated circuit according to one or more embodiments. For example, Figure 8 The plan view of FIG. 8 shows a layout 80 including a bias cell including a diffusion interrupt. Figure 8 In the description of the present invention, the same aspects as those described above with reference to the accompanying drawings will not be repeatedly described.

[0048] Reference Figure 8 , the first row ROW1, the second row ROW2, the third row ROW3 and the fourth row ROW4 may extend in the X-axis direction. The functional unit may be arranged in the first region R1 and the second region R2, and the bias unit may be arranged in the third region R3 between the first region R1 and the second region R2. For example, four bias units may be arranged in the first row ROW1, the second row ROW2, the third row ROW3 and the fourth row ROW4, respectively. The layout 80 may include a substrate SUB and a first well W81 and a second well W82 extending parallel to each other in the X-axis direction on the substrate SUB. In addition, as described above with reference to the accompanying drawings, the layout 80 may include a doped region. The layout 80 may include a gate electrode extending in the Y-axis direction. As Figure 8 As shown in , the gate electrodes may be arranged in the X-axis direction according to a contacted poly pitch (CPP).

[0049] According to some embodiments, the layout 80 may include one or more diffusion interruptions in the third region R3 that are adjacent to (e.g., abutting) the first region R1 and extending in the Y-axis direction, and one or more diffusion interruptions that are adjacent to (e.g., abutting) the second region R2 and extending in the Y-axis direction. Figure 8 As shown in , the first diffusion interruption FC1, the second diffusion interruption FC2, and the third diffusion interruption FC3 adjacent to the first region R1 may extend in the Y-axis direction in the third region R3. In addition, the fourth diffusion interruption FC4, the fifth diffusion interruption FC5, and the sixth diffusion interruption FC6 adjacent to the second region R2 may extend in the Y-axis direction in the third region R3. Therefore, the four bias units may respectively include portions of one or more diffusion interruptions (i.e., the first diffusion interruption FC1, the second diffusion interruption FC2, or the third diffusion interruption FC3) adjacent to the first region R1 and extending in the Y-axis direction. In addition, the four bias units may respectively include portions of one or more diffusion interruptions (i.e., the fourth diffusion interruption FC4, the fifth diffusion interruption FC5, or the sixth diffusion interruption FC6) adjacent to the second region R2 and extending in the Y-axis direction.

[0050] According to some embodiments, each of the first diffusion interrupt FC1, the second diffusion interrupt FC2, the third diffusion interrupt FC3, the fourth diffusion interrupt FC4, the fifth diffusion interrupt FC5 and the sixth diffusion interrupt FC6 may be a double diffusion interrupt (DDB). Figure 8As shown in , each of the first diffusion interrupt FC1, the second diffusion interrupt FC2, the third diffusion interrupt FC3, the fourth diffusion interrupt FC4, the fifth diffusion interrupt FC5, and the sixth diffusion interrupt FC6 may correspond to a region between adjacent gate electrodes. According to some embodiments, the gate electrodes adjacent to the first diffusion interrupt FC1, the second diffusion interrupt FC2, the third diffusion interrupt FC3, the fourth diffusion interrupt FC4, the fifth diffusion interrupt FC5, and the sixth diffusion interrupt FC6 may be filled with an insulator and may be referred to as a dummy gate electrode. According to some embodiments, functional units adjacent to each other in the X-axis direction in the first region R1 and the second region R2 may be separated from each other by a single diffusion interrupt (SDB), and the SDB may have a width corresponding to the width of one gate electrode (i.e., a length in the X-axis direction) and may extend in the Y-axis direction.

[0051] Fig. 9 is a flow chart of a method of manufacturing an integrated circuit (IC) according to one or more embodiments. In detail, Fig. 9 The flowchart of FIG. 1 shows an example of a method of manufacturing an IC including a standard cell. Fig. 9 As shown in , the method of manufacturing an IC may include a plurality of operations S10 , S30 , S50 , S70 , and S90 .

[0052] The cell library (or standard cell library) D12 may include information about the standard cell (e.g., information about functions, characteristics, layout, etc.). According to some embodiments, the cell library D12 may define not only a functional unit that generates an output signal from an input signal, but also a bias unit. For example, the cell library D12 may include a bias unit including a P+ region for biasing a substrate, a bias unit including an N+ region for biasing a well, and a bias unit including a P+ region and an N+ region for biasing both a substrate and a well. As described above with reference to the accompanying drawings, the bias unit may have a structure corresponding to a doping region that is easy to implement. In addition, the bias unit may have a reduced width, and therefore, the area of ​​the IC may be reduced.

[0053] The design rule D14 may include requirements to be followed by the layout of the integrated circuit IC. For example, the design rule D14 may include requirements regarding the spacing between patterns in the same layer, the minimum width of the pattern, the routing direction of the line layer, etc. According to some embodiments, the design rule D14 may define the minimum width of the active pattern, the minimum distance between the active patterns, etc.

[0054] In operation S10, a logic synthesis operation for generating netlist data D13 from RTL data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis based on RTL data D11 written in a hardware description language (HDL) (such as VHSIC hardware description language (VHDL) and Verilog) by referring to a cell library D12, and thus may generate netlist data D13 including a bitstream or a netlist. Netlist data D13 may correspond to an input of placement and routing described below. Here, netlist data D13 may be referred to as input data.

[0055] In operation S30, cells may be laid out. For example, a semiconductor design tool (e.g., a P&R tool) may lay out cells used in the netlist data D13 with reference to the cell library D12 and the design rule D14. In addition, with reference to the cell library D12 and the design rule D14, the semiconductor design tool may lay out not only cells used in the netlist data D13 but also bias cells. Fig.10 An example of operation S30 is described.

[0056] In operation S50, the pins of the unit may be wired. For example, the semiconductor design tool may generate an interconnection that electrically connects the output pin of the functional unit of the layout to the input pin. In addition, the semiconductor design tool may generate an interconnection that connects the pin (i.e., doped region) of the bias unit to a power node (e.g., a node to which a positive power supply voltage is applied or a node to which a negative power supply voltage is applied). The interconnection may include a via of a via layer and / or a pattern of a line layer. The semiconductor design tool may generate layout data D15 that defines the unit of the layout and the generated interconnection. The layout data D15 may have a format such as GDSII, for example, and may include geometric information of the unit and the interconnection. The semiconductor design tool may refer to the design rule D14 when wiring the pins of the unit. The layout data D15 may correspond to the output of the layout and wiring. Operation S50 may be individually referred to as a method for designing or manufacturing an integrated circuit, or operation S30 and operation S50 may be collectively referred to as a method for manufacturing an integrated circuit.

[0057] In operation S70, an operation of manufacturing a mask may be performed. For example, optical proximity correction (OPC) for correcting distortion (such as refraction) caused by characteristics of light in photolithography may be applied to the layout data D15. In order to form patterns laid out on a plurality of layers based on the data to which the OPC is applied, the patterns on the mask may be defined, and at least one mask (or photomask) for forming the pattern of each of the plurality of layers may be manufactured. According to some embodiments, the layout of the IC may be changed in a limited manner in operation S70, and changing the IC in a limited manner in operation S70 may indicate a post-process for optimizing the structure of the IC, and may be referred to as design polishing.

[0058] In operation S90, an operation of manufacturing an IC may be performed. For example, a plurality of layers may be patterned to manufacture the IC by using at least one mask manufactured in operation S70. The front-end process (FEOL) may include, for example, planarization and cleaning of a wafer, formation of a trench, formation of a well, formation of a gate electrode, and formation of a source and a drain, and through the FEOL, an independent device (e.g., a transistor, a capacitor, a resistor, etc.) may be formed on a substrate. In addition, the back-end process (BEOL) may include, for example, silicide of a gate and source and drain regions, addition of a dielectric, planarization, formation of a hole, addition of a metal layer, formation of a via, formation of a passivation layer, etc., and through the BEOL, independent devices (e.g., a transistor, a capacitor, a resistor, etc.) may be connected to each other. According to some embodiments, an intermediate process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed in independent devices. Thereafter, the IC may be packaged in a semiconductor package and used as a component for various applications.

[0059] Fig.10 is a flow chart of a method for manufacturing an IC according to one or more embodiments. In detail, Fig.10 The flow chart shows Fig. 9 As shown above with reference to the example of operation S30 in Fig. 9 As stated in Fig.10 In operation S30', the cells may be laid out. Fig.10 As shown in FIG. 1 , operation S30′ may include operation S31 and operation S32. Fig. 9 describe Fig.10 .

[0060] Reference Fig.10 In operation S31, a bias unit may be arranged. As described above with reference to the accompanying drawings, the bias unit may bias the substrate and / or the well, and for this purpose, the bias unit may include a doped region. The bias unit may be regularly arranged in the layout of the integrated circuit so that the potentials of the substrate and the well may be uniformly formed. For example, as described above with reference to the accompanying drawings, Figure 1 The above-mentioned, each comprises a series of columns of bias units (for example, Figure 1 A first column COL1 , a second column COL2 , and a third column COL3 of the IC may be laid out in a layout of the IC, and according to some embodiments, the distance between the columns may be constant.

[0061] According to some embodiments, the cell library D12 may define a first bias unit for biasing a substrate and a second bias unit for biasing a well. The first bias unit may include a P+ region disposed on the substrate, and the second bias unit may include an N+ region disposed on the well. The semiconductor design tool may identify an area (e.g., a column) where the bias unit is to be laid out, and may alternately lay out a plurality of first bias units and a plurality of second bias units in the identified column with reference to the design rule D14. Therefore, due to the reduced width of the first bias unit and the second bias unit, the area of ​​the area where the bias unit is laid out may be reduced, and therefore, the area of ​​the IC may be reduced. According to some embodiments, each of the first bias unit and the second bias unit may include one or more diffusion interrupts.

[0062] In operation S32, the functional unit may be laid out. For example, the semiconductor design tool may identify the functional unit with reference to the netlist data D13, and in operation S32, the functional unit may be laid out in an area other than an area in which the bias unit is laid out. The functional unit may include a transistor, and the source / drain area of ​​the transistor may correspond to the doped area. For example, an N+ area disposed on a substrate may correspond to a source / drain of an NFET, and a P+ area disposed on a well may correspond to a source / drain of a PFET.

[0063] Fig.11 1 is a block diagram of a system on chip (SoC) 110 according to one or more embodiments. The SoC 110 may be a semiconductor device, and the SoC 110 may include an integrated circuit according to one or more embodiments. The SoC 110 may be a single chip in which complex blocks such as intellectual property (IP) blocks configured to perform various functions are implemented. The SoC 110 may be designed by a method of manufacturing an integrated circuit according to an embodiment, and therefore, the SoC 110 may have a reduced area. Fig.11 , SoC 110 may include a modem 112, a display controller 113, a memory 114, an external memory controller 115, a central processing unit (CPU) 116, a transaction unit 117, a power management integrated circuit (PMIC) 118, and a graphics processing unit (GPU) 119, and each of the functional blocks of SoC 110 may communicate with each other through a system bus 111.

[0064] The CPU 116 configured to control the operation of the SoC 110 at the uppermost layer may control the operations of other functional blocks 112 to 119. The modem 112 may demodulate a signal received from the outside of the SoC 110, or may modulate a signal generated in the SoC 110 and transmit the modulated signal to the outside. The external memory controller 115 may control the operation of transmitting and receiving data to and from an external memory device connected to the SoC 110. For example, a program and / or data stored in the external memory device may be provided to the CPU 116 or the GPU 119 under the control of the external memory controller 115. The GPU 119 may execute program instructions related to graphics processing. The GPU 119 may receive graphics data through the external memory controller 115, or may transmit graphics data processed by the GPU 119 to the outside of the SoC 110 through the external memory controller 115. The transaction unit 117 may monitor the data transaction of each functional block, and the PMIC 118 may control the power supplied to each functional block according to the control of the transaction unit 117. The display controller 113 may control a display (or display device) outside the SoC 110 to transmit data generated in the SoC 110 to the display. The memory 114 may include a nonvolatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, etc., and may include a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.

[0065] Fig.12 1 is a block diagram of a computing system 120 including a memory storing a program according to one or more embodiments. At least a portion of the method of manufacturing an integrated circuit according to an embodiment (for example, at least one of the operations of the flowchart described above) may be performed in the computing system (or computer) 120.

[0066] The computing system 120 may be a fixed computing system (such as a desktop computer, a workstation, a server, etc.), or may be a portable computing system (such as a laptop computer, etc.). Fig.12 As shown in , the computing system 120 may include a processor 121, an input and output (I / O) device 122, a network interface 123, a random access memory (RAM) 124, a read-only memory (ROM) 125, and a storage device 126. The processor 121, the input and output device 122, the network interface 123, the RAM 124, the ROM 125, and the storage device 126 may be connected to a bus 127 and may communicate with each other through the bus 127.

[0067] The processor 121 may be referred to as a processing unit and may include at least one core (such as a microprocessor, an application processor (AP), a digital signal processor (DSP), a GPU, etc.) configured to execute any instruction set (e.g., Intel Architecture (IA)-32, 64-bit extended IA-32, x86-64, PowerPC, Scalable Processor Architecture (Sparc), Million Instructions Per Second (MIPS), Advanced Reduced Instruction Set Machine (ARM), IA-64, etc.). For example, the processor 121 may access a memory (i.e., RAM 124 or ROM 125) through a bus 127 and may execute instructions stored in the RAM 124 or ROM 125.

[0068] The RAM 124 may store a program PGM or at least a portion of the program PGM for the method of manufacturing an integrated circuit according to one or more embodiments, and through the program PGM, the processor 121 may execute the method of manufacturing an integrated circuit (for example, Fig. 9 That is, the program PGM may include a plurality of instructions executable by the processor 121, and the plurality of instructions included in the program PGM may allow the processor 121 to perform at least one of the operations included in the above-described flowcharts.

[0069] Even when the power supply to the computing system 120 is blocked, the storage device 126 may not lose the stored data. For example, the storage device 126 may include a non-volatile memory device, and may include a storage medium (such as a tape, an optical disk, or a magnetic disk). In addition, the storage device 126 may be detachable from the computing system 120. The storage device 126 may store a program PGM according to one or more embodiments, and before the program PGM is executed by the processor 121, the program PGM or at least a portion of the program PGM may be loaded from the storage device 126 to the RAM 124. Alternatively, the storage device 126 may store a file written in a program language, and the program PGM or at least a portion of the program PGM generated by a compiler or the like may be loaded from the file to the RAM 124. In addition, as Fig.12 As shown in FIG. 1 , the storage device 126 may store a database DB, and the database DB may include information required for designing an integrated circuit (eg, information about a designed block) and Fig. 9 cell library D12 and / or design rules D14).

[0070] The storage device 126 may store data to be processed by the processor 121 or data processed by the processor 121. That is, according to the program PGM, the processor 121 may generate data by processing the data stored in the storage device 126, or may store the generated data in the storage device 126. For example, the storage device 126 may store Fig. 9RTL data D11, netlist data D13 and / or layout data D15.

[0071] The input and output device 122 may include an input device (such as a keyboard, a pointing device, etc.), and may include an output device (such as a display device, a printer, etc.). For example, a user may trigger the processor 121 to execute the program PGM through the input and output device 122. Fig. 9 The RTL data D11 and / or netlist data D13 can be identified Fig. 9 Layout data D15.

[0072] The network interface 123 may provide access to a network external to the computing system 120. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other form of links.

[0073] While certain embodiments of the disclosure have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: a plurality of wells extending parallel to each other along a first direction on a substrate having a first conductivity type, the plurality of wells having a second conductivity type; A plurality of first doped regions are disposed on the plurality of wells in the first region and the second region of the substrate, the first region is separated from the second region in a first direction, and the plurality of first doped regions have a first conductivity type; A plurality of second doped regions are disposed on the substrate between the plurality of wells in the first region and the second region, the plurality of second doped regions having a second conductivity type; A plurality of third doped regions disposed in a third region of the substrate between the first region and the second region and having a first conductivity type; as well as a plurality of fourth doped regions disposed on the plurality of wells in the third region and having a second conductivity type, The third region extends in a second direction perpendicular to the first direction.

2. The integrated circuit according to claim 1, wherein: The plurality of third doped regions include at least one third doped region at least partially overlapping at least one second doped region among the plurality of second doped regions in the first direction.

3. The integrated circuit according to claim 2, wherein: The at least one third doped region overlaps the at least one second doped region in the first direction.

4. The integrated circuit according to claim 1, wherein: The plurality of fourth doped regions include at least one fourth doped region at least partially overlapping at least one first doped region among the plurality of first doped regions in the first direction.

5. The integrated circuit according to claim 4, wherein: The at least one fourth doped region overlaps the at least one first doped region in the first direction.

6. The integrated circuit according to any one of claims 1 to 5, further comprising: at least one first double diffused interruption, in the third region, the at least one first double diffused interruption adjoining the first region and extending in the second direction; as well as At least one second double diffused interruption, in the third region, the at least one second double diffused interruption adjoins the second region and extends in the second direction.

7. An integrated circuit according to any one of claims 1 to 5, in, The plurality of first doped regions and the plurality of third doped regions each have a doping concentration of the first conductivity type greater than a doping concentration of the substrate, and The plurality of second doped regions and the plurality of fourth doped regions each have a doping concentration of the second conductivity type greater than a doping concentration of the plurality of wells.

8. An integrated circuit according to any one of claims 1 to 5, in, The substrate is configured to be biased to a first power supply voltage through the plurality of third doped regions, and The plurality of wells are configured to be biased to a second power supply voltage through the plurality of fourth doped regions.

9. An integrated circuit comprising: A plurality of functional units are arranged in a first area and a second area of ​​the substrate, wherein the first area is separated from the second area in a first direction; as well as A series of biasing units are arranged in a third region of the substrate between the first region and the second region, the third region extending in a second direction perpendicular to the first direction, wherein the series of biasing units include: a plurality of first bias units configured to bias a substrate having a first conductivity type; and A plurality of second bias units are configured to bias a plurality of wells extending parallel to each other along a first direction on a substrate and having a second conductivity type, wherein the plurality of first bias units and the plurality of second bias units are alternately arranged in a second direction.

10. The integrated circuit of claim 9, wherein: Each of the plurality of functional units comprises: at least one first doped region disposed on one of the plurality of wells and having a first conductivity type; and At least one second doped region is disposed on the substrate between the plurality of wells and has a second conductivity type.

11. The integrated circuit of claim 10, wherein: Each of the plurality of first bias units includes a third doped region disposed on the substrate between the plurality of wells and having a first conductivity type.

12. The integrated circuit of claim 11, wherein: The third doped region overlaps the at least one second doped region in the first direction.

13. The integrated circuit of claim 11, wherein: The at least one first doped region and the third doped region have a doping concentration of the first conductivity type that is greater than a doping concentration of the substrate.

14. The integrated circuit of claim 11, wherein: The substrate is configured to be biased to a first power supply voltage through the third doped region.

15. The integrated circuit of claim 10, wherein: Each of the plurality of second bias units includes a fourth doped region disposed on the plurality of wells and having a second conductivity type.

16. The integrated circuit of claim 15, wherein: The fourth doped region overlaps the at least one first doped region in the first direction.

17. The integrated circuit of claim 15, wherein: The at least one second doped region and the fourth doped region have a doping concentration of the second conductivity type greater than a doping concentration of the plurality of wells.

18. The integrated circuit of claim 15, wherein: The plurality of wells are configured to be biased to a second power supply voltage through a fourth doped region.

19. An integrated circuit according to any one of claims 9 to 18, wherein: Each bias unit in the series of bias units comprises: at least one first double diffusion interruption adjacent to the first region and extending in the second direction; and At least one second double diffusion interruption adjoins the second region and extends in the second direction.

20. A method of manufacturing an integrated circuit, the method comprising: Arrange a bias unit for biasing a substrate and a plurality of wells, the substrate having a first conductivity type, the plurality of wells extending parallel to each other along a first direction on the substrate and having a second conductivity type; as well as placing the functional unit in an area of ​​the substrate where no bias unit is placed based on the input data, The step of arranging the biasing units includes: alternately arranging a plurality of first biasing units for biasing the substrate and a plurality of second biasing units for biasing the plurality of wells in a second direction perpendicular to the first direction.

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