Article and method of making same
By adjusting the dimensional relationship between the substrate and the bonding layer and setting gaps in the edge area of the bonding layer, the problem of uneven bonding layer thickness in the light emitting diode is solved, and the laser peeling efficiency is improved.
Patent Information
- Application Number
- CN202411948475.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-05-09
AI Technical Summary
During the production process of the light emitting diode, the bonding layer between the epitaxial layer and the substrate is uneven, resulting in low laser peeling efficiency.
By adjusting the dimensional relationship between the substrate and the bonding layer, the size of the substrate is smaller than that of the bonding layer, and a notch is provided in the edge area of the bonding layer so that the glue material overflows to the side wall of the substrate, avoiding the formation of a bonding layer with an excessively thick thickness.
The uniformity of the bonding layer thickness between the substrate and the epitaxial layer is achieved, the efficiency of laser peeling is improved, and the problem of the bonding layer being too thick at the edge area of the substrate is avoided.
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Figure CN119967976A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a product and a preparation method thereof. Background Art
[0002] Light Emitting Diode (LED) is a new product with great influence in the optoelectronics industry. Light Emitting Diode usually includes substrate, bonding layer and epitaxial layer. When the light emitting diode is manufactured, the epitaxial layer needs to be separated from the substrate by laser stripping, and then the light emitting diode is bonded to the circuit board to form a display panel.
[0003] In the related art, when bonding an epitaxial layer to a substrate, a glue layer is usually formed on the surfaces of the substrate and the epitaxial layer, and then the two surfaces of the epitaxial layer and the substrate with the glue layer are pressed together to form a bonding layer between the epitaxial layer and the substrate.
[0004] However, when the epitaxial layer and the substrate are pressed together, the adhesive material will be squeezed to the edge area of the epitaxial layer and the substrate, so that the thickness of the bonding layer formed in the edge area of the epitaxial layer and the substrate is relatively large. Therefore, when performing the laser lift-off process, the epitaxial layer in the edge area of the substrate is difficult to be peeled off from the substrate due to the relatively thick bonding layer of the epitaxial layer in the edge area of the substrate, which affects the laser lift-off efficiency. Summary of the invention
[0005] The embodiments of the present disclosure provide a product and a method for preparing the same, which can improve the thickness uniformity of the bonding layer between the substrate and the epitaxial layer and enhance the efficiency of laser lift-off. The technical solution is as follows:
[0006] On the one hand, an embodiment of the present disclosure provides a product, which includes: a substrate, a bonding layer and an epitaxial layer, wherein the bonding layer and the epitaxial layer are sequentially stacked on the surface of the substrate; the orthographic projection of the substrate on the surface of the epitaxial layer close to the substrate is a first projection, and the orthographic projection of the bonding layer on the surface of the epitaxial layer close to the substrate is a second projection, and the first projection is located within the second projection.
[0007] In one implementation of the present disclosure, the outer contour of the first projection is a first contour line, the outer contour of the second projection is a second contour line, and the minimum spacing D between the first contour line and the second contour line is N×T×R; wherein N is a correction coefficient, N is a constant, T is the thickness of the bonding layer, and R is the radius of the substrate.
[0008] In another implementation of the present disclosure, the correction coefficient has a value range of 0.2 to 0.4.
[0009] In another implementation of the present disclosure, a portion of the bonding layer located outside the first projection is attached to a side wall of the substrate.
[0010] In another implementation of the present disclosure, the thickness of the bonding layer within the first projection is the same.
[0011] In a second aspect, an embodiment of the present disclosure also provides a method for preparing a product, the method comprising: forming an epitaxial layer on a temporary substrate; forming a bonding layer between the epitaxial layer and a substrate, bonding the epitaxial layer to the surface of the substrate, and removing the temporary substrate, the orthographic projection of the substrate on the surface of the epitaxial layer close to the substrate is a first projection, the orthographic projection of the bonding layer on the surface of the epitaxial layer close to the substrate is a second projection, and the first projection is located within the second projection.
[0012] Optionally, bonding the epitaxial layer to the surface of the substrate includes: forming a first glue layer on the surface of the epitaxial layer away from the temporary substrate; forming a second glue layer on the surface of the substrate, wherein the peripheral edge of the second glue layer has a plurality of spaced-apart notches; and pressing the first glue layer of the epitaxial layer and the second glue layer of the substrate together to form the bonding layer.
[0013] Optionally, the orthographic projection of the notch on the surface of the substrate is a third projection, and a width of the third projection on a side close to the center of the second adhesive layer is smaller than a width of the third projection on a side away from the center of the second adhesive layer.
[0014] Optionally, the shape of the third projection includes a triangle and a trapezoid.
[0015] Optionally, the outer contour of the first projection is a first contour line, the outer contour of the second projection is a second contour line, and the minimum spacing D between the first contour line and the second contour line is D=N×T×R; wherein N is a correction coefficient, N is a constant, T is the thickness of the bonding layer, and R is the radius of the substrate.
[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0017] The product provided by the embodiment of the present disclosure includes a substrate and a bonding layer and an epitaxial layer stacked on the substrate in sequence. Among them, the first projection of the substrate on the surface of the epitaxial layer is located within the second projection of the bonding layer on the surface of the epitaxial layer, that is, the size of the substrate is smaller than the size of the bonding layer. When such a product is bonded, due to the small size of the substrate, during the process of pressing the epitaxial layer and the substrate together, even if the glue layer is squeezed to the edge area of the substrate, the glue is more likely to overflow to the side wall of the substrate, and will not be too concentrated in the edge area of the epitaxial layer and the substrate, so that the thickness of the glue layer in the edge area of the substrate and the epitaxial layer is too large. This avoids the problem of the bonding layer formed between the substrate and the epitaxial layer being too thick in the edge area of the substrate, so that when the substrate is subsequently laser-stripped, the thickness of the bonding layer between the edge area of the substrate and the epitaxial layer will not be too large to be difficult to strip, thereby effectively improving the efficiency of laser stripping. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 is a bottom view of a product provided by an embodiment of the present disclosure;
[0020] Figure 2 is a partial schematic diagram of a product provided by an embodiment of the present disclosure;
[0021] Figure 3 is a structural schematic diagram of a product provided by an embodiment of the present disclosure;
[0022] Figure 4 is a flow chart of a method for preparing a product provided by an embodiment of the present disclosure;
[0023] Figure 5 It is a schematic diagram of a second adhesive layer in an edge area of a substrate provided by an embodiment of the present disclosure.
[0024] The descriptions of the marks in the figure are as follows:
[0025] 10. substrate; 11. first contour line;
[0026] 20, bonding layer; 21, second contour line; 22, second adhesive layer; 220, notch;
[0027] 30. epitaxial layer; 31. first semiconductor layer; 32. active layer; 33. second semiconductor layer;
[0028] 41. electrode; 42. welding point block;
[0029] 50. Passivation layer. DETAILED DESCRIPTION
[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0031] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0032] Figure 1 It is a bottom view of a product provided by an embodiment of the present disclosure. Figure 2 It is a partial schematic diagram of a product provided by an embodiment of the present disclosure. Figure 2 It indicates Figure 1 The local hierarchical structure diagram at point A in the middle.
[0033] like Figure 2 As shown, the product includes: a substrate 10, a bonding layer 20 and an epitaxial layer 30, and the bonding layer 20 and the epitaxial layer 30 are sequentially stacked on the surface of the substrate 10.
[0034] The orthographic projection of the substrate 10 on the surface of the epitaxial layer 30 close to the substrate 10 is the first projection, and the orthographic projection of the bonding layer 20 on the surface of the epitaxial layer 30 close to the substrate 10 is the second projection.
[0035] like Figure 1 As shown, the first projection is located within the second projection.
[0036] The product provided by the embodiment of the present disclosure includes a substrate and a bonding layer 20 and an epitaxial layer 30 sequentially stacked on the substrate. Among them, the first projection of the substrate on the surface of the epitaxial layer 30 is located within the second projection of the bonding layer 20 on the surface of the epitaxial layer 30, that is, the size of the substrate is smaller than the size of the bonding layer 20. When bonding such a product, due to the small size of the substrate, during the process of pressing the epitaxial layer 30 and the substrate together, even if the glue layer is squeezed to the edge area of the substrate, the glue is more likely to overflow to the side wall of the substrate, and will not be too concentrated in the edge area of the epitaxial layer 30 and the substrate, so that the thickness of the glue layer in the edge area of the substrate and the epitaxial layer 30 is too large. This avoids the problem of the bonding layer 20 formed between the substrate and the epitaxial layer 30 being too thick in the edge area of the substrate, so that when the substrate is subsequently laser-stripped, the thickness of the bonding layer 20 between the edge area of the substrate and the epitaxial layer 30 will not be too large to be difficult to strip, thereby effectively improving the efficiency of laser stripping.
[0037] Alternatively, if Figure 1 As shown, the outer contour of the first projection is the first contour line 11 , and the outer contour of the second projection is the second contour line 21 .
[0038] Exemplarily, the minimum distance D between the first contour line 11 and the second contour line 21 is N×T×R.
[0039] Wherein, N is a correction coefficient, N is a constant, T is the thickness of the bonding layer 20, and R is the radius of the substrate.
[0040] Exemplarily, the correction coefficient N ranges from 0.2 to 0.4.
[0041] As an example, in the embodiment of the present disclosure, the correction coefficient is 0.3.
[0042] In the above implementation, the thickness of the bonding layer 20, the correction coefficient and the size of the substrate can be used to determine a minimum spacing D of reasonable size, ensuring that the spacing between the first contour line 11 and the second contour line 21 is at an appropriate distance. This can avoid the situation where the size of the substrate is too large, resulting in too small a space for overflow of the bonding layer 20, and the thickness of the bonding layer 20 in the edge area of the substrate is still too large; it can also avoid the situation where the size of the substrate is too small, resulting in a small contact area between the bonding layer 20 and the substrate, thereby reducing the connection reliability between the bonding layer 20 and the substrate.
[0043] Alternatively, if Figure 2 As shown, a portion of the bonding layer 20 located outside the first projection is attached to the side wall of the substrate.
[0044] In the disclosed embodiment, when the substrate and the epitaxial layer 30 are bonded, the adhesive layer on the surface of the substrate will be squeezed to the peripheral edge of the substrate. Since the size of the substrate is smaller than the size of the epitaxial layer 30, the adhesive layer will overflow from between the epitaxial layer 30 and the substrate and adhere to the side wall of the substrate, thereby avoiding the adhesive layer squeezed to the peripheral edge being concentrated in the edge area of the substrate and the epitaxial layer 30, which will cause the adhesive layer thickness in the edge area of the substrate and the epitaxial layer 30 to be too large, affecting the subsequent laser lift-off efficiency.
[0045] Alternatively, if Figure 2 As shown, the thickness of the bonding layer 20 located within the first projection is the same. In the disclosed embodiment, the thickness of the bonding layer 20 located between the substrate and the epitaxial layer 30 is the same, that is, the thickness uniformity of the bonding layer 20 is good, and the thickness of the bonding layer 20 in the edge area of the substrate and the epitaxial layer 30 is not large, so that the edge area of the substrate and the epitaxial layer 30 is also easier to laser lift off.
[0046] Optionally, the bonding layer 20 may be a silicon oxide layer having a thickness of 1000 angstroms to 20000 angstroms, for example, a thickness of 8000 angstroms.
[0047] Figure 3 Schematic diagram of a product provided by an embodiment of the present disclosure. Figure 3 As shown, the epitaxial layer 30 includes a first semiconductor layer 31, an active layer 32 and a second semiconductor layer 33 which are stacked on a substrate.
[0048] In the embodiment of the present disclosure, one of the first semiconductor layer 31 and the second semiconductor layer 33 is a p-type layer, and the other of the first semiconductor layer 31 and the second semiconductor layer 33 is an n-type layer.
[0049] As an example, the first semiconductor layer 31 is a p-type layer, and the second semiconductor layer 33 is an n-type layer.
[0050] Optionally, the first semiconductor layer 31 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
[0051] Optionally, the active layer 32 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The active layer 32 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.
[0052] As an example, in the embodiment of the present disclosure, the active layer 32 includes five periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
[0053] Optionally, the thickness of the active layer 32 may be 150 nm to 200 nm.
[0054] Optionally, the second semiconductor layer 33 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
[0055] Alternatively, if Figure 3 As shown, the light emitting diode includes two electrodes 41. The surface of the second semiconductor layer 33 has a groove exposing the first semiconductor layer 31, one of the two electrodes 41 is located in the groove, and the other of the two electrodes 41 is located on the surface of the second semiconductor layer 33 away from the substrate.
[0056] Alternatively, the electrode 41 includes an Au layer, an AuGe layer, and a Pt layer sequentially stacked on the surface of the epitaxial layer 30 .
[0057] The last metal layer of the electrode 41 is set as a Pt layer, and the Pt layer covers the AuGe layer. In this way, the Pt layer can effectively prevent the Ge element from diffusing upward during annealing, thereby ensuring the total amount of elements diffused into the semiconductor, so that the electrode 41 can achieve a better ohmic contact effect.
[0058] Optionally, the thickness of the Au layer is 80 angstroms to 150 angstroms. The Au layer has good electrical conductivity and can improve the ohmic contact effect between the electrode 41 and the epitaxial layer 30 .
[0059] Illustratively, the Au layer has a thickness of 100 angstroms.
[0060] Optionally, the thickness of the AuGe layer is 800 angstroms to 1500 angstroms. The AuGe layer also has good electrical conductivity, and can reduce the amount of Au metal used, thereby reducing the preparation cost of the electrode 41.
[0061] Illustratively, the AuGe layer has a thickness of 1000 angstroms.
[0062] Optionally, the thickness of the Pt layer is 450 angstroms to 600 angstroms. The last metal layer of the electrode 41 is set as a Pt layer, and the Pt layer covers the AuGe layer, so that the AuGe layer can be guaranteed.
[0063] Illustratively, the thickness of the Pt layer is 500 angstroms.
[0064] Alternatively, if Figure 3 As shown, the light emitting diode further includes a passivation layer 50 , which is located at least on the surface of the second semiconductor layer 33 , the bottom surface of the groove and the surfaces of the two electrodes 41 .
[0065] Exemplarily, the passivation layer 50 has via holes respectively exposing the two electrodes 41 .
[0066] Alternatively, the passivation layer 50 may include a DBR layer or a silicon oxide layer.
[0067] The electrode 41 located in the groove is an n-electrode 41 , and the electrode 41 located on the second semiconductor layer 33 is a p-electrode 41 .
[0068] Alternatively, if Figure 3 As shown, the light emitting diode further includes: two soldering blocks 42, the two soldering blocks 42 are located on the passivation layer 50, and the two soldering blocks 42 are connected to the two electrodes 41 through two via holes respectively.
[0069] Optionally, a protective layer is further provided on the surface of the passivation layer 50 and the improvement layer, and the protective layer extends from the surface of the passivation layer 50 and the surface of the improvement layer to the substrate, and the protective layer has through holes exposing the solder joint blocks 42 for electrical connection.
[0070] Illustratively, in the embodiment of the present disclosure, the protective layer may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.
[0071] Figure 4 is a flow chart of a method for preparing a product provided by an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:
[0072] Step 101: forming an epitaxial layer 30 on a temporary substrate.
[0073] Step 102: forming a bonding layer 20 between the epitaxial layer 30 and the substrate, bonding the epitaxial layer 30 to the surface of the substrate, and removing the temporary substrate.
[0074] The orthographic projection of the substrate on the surface of the epitaxial layer 30 close to the substrate is the first projection, the orthographic projection of the bonding layer 20 on the surface of the epitaxial layer 30 close to the substrate is the second projection, and the first projection is located within the second projection.
[0075] The product prepared by the preparation method provided by the embodiment of the present disclosure includes a substrate and a bonding layer 20 and an epitaxial layer 30 stacked on the substrate in sequence. Among them, the first projection of the substrate on the surface of the epitaxial layer 30 is located within the second projection of the bonding layer 20 on the surface of the epitaxial layer 30, that is, the size of the substrate is smaller than the size of the bonding layer 20. When such a product is bonded, due to the small size of the substrate, during the process of pressing the epitaxial layer 30 and the substrate together, even if the glue layer is squeezed to the edge area of the substrate, the glue is more likely to overflow to the side wall of the substrate, and will not be too concentrated in the edge area of the epitaxial layer 30 and the substrate, so that the thickness of the glue layer in the edge area of the substrate and the epitaxial layer 30 is too large. This avoids the problem that the thickness of the bonding layer 20 formed between the substrate and the epitaxial layer 30 is too thick in the edge area of the substrate, so that when the substrate is subsequently laser-stripped, the thickness of the bonding layer 20 between the edge area of the substrate and the epitaxial layer 30 will not be too large to be difficult to strip, thereby effectively improving the efficiency of laser stripping.
[0076] Alternatively, if Figure 1 As shown, the outer contour of the first projection is the first contour line 11 , and the outer contour of the second projection is the second contour line 21 .
[0077] Exemplarily, the minimum distance D between the first contour line 11 and the second contour line 21 is N×T×R.
[0078] Wherein, N is a correction coefficient, N is a constant, T is the thickness of the bonding layer 20, and R is the radius of the substrate.
[0079] Exemplarily, the correction coefficient N ranges from 0.2 to 0.4.
[0080] As an example, in the embodiment of the present disclosure, the correction coefficient is 0.3.
[0081] In the above implementation, the thickness of the bonding layer 20, the correction coefficient and the size of the substrate can be used to determine a minimum spacing D of reasonable size, ensuring that the spacing between the first contour line 11 and the second contour line 21 is at an appropriate distance. This can avoid the situation where the size of the substrate is too large, resulting in too small a space for overflow of the bonding layer 20, and the thickness of the bonding layer 20 in the edge area of the substrate is still too large; it can also avoid the situation where the size of the substrate is too small, resulting in a small contact area between the bonding layer 20 and the substrate, thereby reducing the connection reliability between the bonding layer 20 and the substrate.
[0082] Step 101 may include the following steps:
[0083] The first step is to provide a temporary substrate.
[0084] Illustratively, the temporary substrate may be a GaAs wafer.
[0085] In the second step, an epitaxial layer 30 is formed on the temporary substrate.
[0086] The preparation of the epitaxial layer 30 may include: growing a second semiconductor layer 33 , an active layer 32 , and a first semiconductor layer 31 which are sequentially stacked on a GaAs wafer.
[0087] For example, the second semiconductor layer 33 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
[0088] Exemplarily, the first semiconductor layer 31 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
[0089] Optionally, the active layer 32 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different. The active layer 32 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked.
[0090] As an example, in the embodiment of the present disclosure, the active layer 32 includes five periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
[0091] Optionally, the thickness of the active layer 32 may be 150 nm to 200 nm.
[0092] In the second step, an etching stop layer may be grown before growing the second semiconductor layer 33 , and an AlInP carrier confinement layer may be grown before growing the active layer 32 .
[0093] A GaP window layer may be further grown after the first semiconductor layer 31 is grown, wherein the thickness of the GaP window layer is 10000 angstroms to 50000 angstroms.
[0094] Exemplarily, the GaP window layer has a thickness of 40,000 angstroms.
[0095] Step 102 may include the following steps:
[0096] In the first step, a first glue layer is formed on the surface of the epitaxial layer 30 away from the temporary substrate.
[0097] Specifically, the method may include coating 12000 angstroms of bonding material on the epitaxial layer 30, baking it at 100° C. for 5 minutes using a hot plate, and then baking it at 150° C. for 3 minutes using a hot plate to form a first adhesive layer.
[0098] Wherein, the first adhesive layer is a silicon oxide layer.
[0099] In the second step, a second adhesive layer 22 is formed on the surface of the substrate.
[0100] Exemplarily, the substrate is a sapphire substrate. Since the sapphire substrate has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of a sapphire substrate can enable the light-emitting diode to have good light-emitting effect and stability.
[0101] Figure 5 FIG. 2 is a schematic diagram of a second adhesive layer 22 in an edge region of a substrate provided by an embodiment of the present disclosure. Figure 5 As shown, the peripheral edge of the second adhesive layer 22 has a plurality of gaps 220 arranged at intervals.
[0102] Exemplarily, the peripheral edge of the second glue layer 22 does not exceed the peripheral edge of the substrate.
[0103] In the above implementation, a notch 220 is set at the peripheral edge of the second glue layer 22, so that when the epitaxial layer 30 and the substrate are bonded, the glue squeezed to the edge area of the substrate during the pressing process of the first glue layer and the second glue layer 22 can fill the notch 220, which can effectively avoid the problem of excessive thickness of the glue layer in the edge area of the substrate and the epitaxial layer 30.
[0104] Alternatively, if Figure 5 As shown, the orthographic projection of the notch 220 on the surface of the substrate is a third projection, and the width of the third projection close to the center of the second adhesive layer 22 is smaller than the width of the third projection away from the center of the second adhesive layer 22 .
[0105] Exemplarily, the shape of the third projection includes a triangle and a trapezoid. As an example, Figure 5 As shown, the shape of the third projection is a triangle.
[0106] Since the glue layer is easily squeezed to the edge area when the substrate and the epitaxial layer 30 are bonded, making the width of the edgemost part of the third projection larger is beneficial for the gap 220 to accommodate more overflowed glue layer and avoid the thickness of the bonding layer 20 in the edge area of the substrate and the epitaxial layer 30 being too large.
[0107] In the third step, the first glue layer of the epitaxial layer 30 and the second glue layer 22 of the substrate are pressed together to form a bonding layer 20 .
[0108] After the first adhesive layer and the second adhesive layer 22 are pressed together, they can be baked on a hot plate at 100° C. for 5 to 20 minutes, and then baked on a hot plate at 150° C. for 2 to 20 minutes to solidify the adhesive layer to obtain the bonding layer 20.
[0109] After step 102, the following steps may also be included:
[0110] First, the surface of the second semiconductor layer 33 is etched to form a groove exposing the first semiconductor layer 31. The epitaxial layer 30 is etched to expose the substrate.
[0111] Then, the electrode 41 is deposited on the surface of the second semiconductor layer 33 and in the groove.
[0112] The electrode 41 in the groove may have the same conductivity type as the first semiconductor layer 31. For example, if the first semiconductor layer 31 is an n-type layer, the electrode 41 in the groove may be an n-electrode 41.
[0113] The electrode 41 located on the surface of the second semiconductor layer 33 has the same conductivity type as the second semiconductor layer 33. For example, if the second semiconductor layer 33 is a p-type layer, the electrode 41 located on the second semiconductor layer 33 may be a p-electrode 41.
[0114] Illustratively, the evaporated electrode 41 may include an Au layer, an AuGe layer, and a Pt layer stacked in sequence.
[0115] Optionally, the thickness of the Au layer is 80 angstroms to 150 angstroms. The Au layer has good electrical conductivity, and setting the metal layer in contact between the electrode 41 and the epitaxial layer 30 as the Au layer can improve the ohmic contact effect between the electrode 41 and the epitaxial layer 30 .
[0116] Illustratively, the Au layer has a thickness of 100 angstroms.
[0117] Optionally, the thickness of the AuGe layer is 800 angstroms to 1500 angstroms. The AuGe layer also has good conductivity, and due to the addition of Ge metal, the ohmic contact can be improved, and the amount of Au metal used can also be reduced, thereby reducing the preparation cost of the electrode 41.
[0118] Illustratively, the AuGe layer has a thickness of 1000 angstroms.
[0119] Optionally, the Pt layer has a thickness of 450 angstroms to 600 angstroms.
[0120] The last metal layer of the electrode 41 is set as a Pt layer, and the Pt layer covers the AuGe layer. In this way, the Pt layer can effectively prevent the Ge element from diffusing upward during annealing, thereby ensuring the total amount of elements diffused into the semiconductor, so that the electrode 41 can achieve a better ohmic contact effect.
[0121] Illustratively, the thickness of the Pt layer is 500 angstroms.
[0122] Next, a passivation layer 50 is formed on the surface of the epitaxial layer 30 and the surface of the electrode 41 .
[0123] The manufactured passivation layer 50 is at least located in the second semiconductor layer 33 , the electrode 41 and the groove.
[0124] Optionally, the passivation layer 50 includes a silicon oxide layer.
[0125] When preparing the passivation layer 50, the deposition temperature of the passivation layer 50 is controlled to be 150°C to 250°C, and the deposition rate of the passivation layer 50 is controlled to be 15 angstroms / second to 25 angstroms / second. The passivation layer 50 prepared according to this process can release stress and improve the preparation quality of the light-emitting diode.
[0126] Exemplarily, the deposition temperature of the passivation layer 50 is 200° C., and the deposition rate of the passivation layer 50 is 20 angstroms / second.
[0127] Then, two via holes are made on the passivation layer 50 to expose the two electrodes 41 respectively.
[0128] Specifically, the method may include: forming a photoresist layer on the surface of the passivation layer 50 , opening a hole in the photoresist layer in a region corresponding to the via hole, and then etching the passivation layer 50 with a buffered oxide etching solution to form the via hole on the passivation layer 50 .
[0129] The buffered oxide etching solution is a mixture of hydrofluoric acid and water, or a mixture of ammonium fluoride and water.
[0130] Next, solder joints 42 are formed on the surface of the passivation layer 50 away from the product to be evaporated.
[0131] The soldering point block 42 is connected to the electrode 41 through a via hole.
[0132] Specifically, it may include: sequentially evaporating a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au alloy layer on the surface of the passivation layer 50 to form the solder joint block 42 on the surface of the passivation layer 50 .
[0133] The soldering point block 42 is connected to the electrode 41 through a via hole.
[0134] Exemplarily, the thickness of the Cr layer is 50 angstroms to 150 angstroms. For example, the thickness of the Cr layer is 100 angstroms.
[0135] Exemplarily, the thickness of the Al layer is 2500 angstroms to 3500 angstroms. For example, the thickness of the Al layer is 3000 angstroms.
[0136] Exemplarily, the thickness of the Ti layer is 400 angstroms to 600 angstroms. For example, the thickness of the Ti layer is 500 angstroms.
[0137] Exemplarily, the thickness of the Ni layer is 1000 angstroms to 3000 angstroms. For example, the thickness of the Ni layer is 2000 angstroms.
[0138] Exemplarily, the thickness of the Au alloy layer is 15000 angstroms to 25000 angstroms. For example, the thickness of the Au layer is 20000 angstroms.
[0139] Then, a protection layer is formed on the surface of the passivation layer 50 , and the protection layer extends from the surface of the passivation layer 50 to the substrate.
[0140] Illustratively, in the embodiment of the present disclosure, the protective layer may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.
[0141] It should be noted that after the protective layer is grown on the surface of the passivation layer 50 , a through hole exposing the solder joint block 42 can be etched on the surface of the protective layer using photolithography technology to facilitate electrical connection.
[0142] The product prepared in the embodiment of the present disclosure can be divided into a plurality of light-emitting diodes by invisible cutting and splitting of the substrate. Then, the substrate is peeled off from the epitaxial layer 30 by a laser lift-off process, and each light-emitting diode is transferred to a circuit board to obtain a display panel.
[0143] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. The data therein only represent illustrative examples. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A product, characterized in that: The product comprises: a substrate (10), a bonding layer (20) and an epitaxial layer (30), wherein the bonding layer (20) and the epitaxial layer (30) are sequentially stacked on the surface of the substrate (10); The orthographic projection of the substrate (10) on the surface of the epitaxial layer (30) close to the substrate (10) is a first projection, the orthographic projection of the bonding layer (20) on the surface of the epitaxial layer (30) close to the substrate (10) is a second projection, and the first projection is located within the second projection.
2. The product according to claim 1, characterized in that The outer contour of the first projection is a first contour line (11), the outer contour of the second projection is a second contour line (21), and the minimum distance D between the first contour line (11) and the second contour line (21) is N×T×R; Wherein, N is a correction coefficient, N is a fixed value, T is the thickness of the bonding layer (20), and R is the radius of the substrate (10).
3. The product according to claim 2, characterized in that The correction coefficient has a value range of 0.2 to 0.
4.
4. The product according to any one of claims 1 to 3, characterized in that The portion of the bonding layer (20) located outside the first projection is attached to the side wall of the substrate (10).
5. The product according to any one of claims 1 to 3, characterized in that The thickness of the bonding layer (20) located within the first projection is the same.
6. A method for preparing a product, characterized in that: The preparation method comprises: forming an epitaxial layer (30) on a temporary substrate; A bonding layer (20) is formed between the epitaxial layer (30) and the substrate (10), the epitaxial layer (30) is bonded to the surface of the substrate (10), and the temporary substrate is removed, the orthographic projection of the substrate (10) on the surface of the epitaxial layer (30) close to the substrate is a first projection, the orthographic projection of the bonding layer (20) on the surface of the epitaxial layer (30) close to the substrate (10) is a second projection, and the first projection is located within the second projection.
7. The preparation method according to claim 6, characterized in that: Bonding the epitaxial layer (30) to the surface of the substrate comprises: forming a first glue layer on a surface of the epitaxial layer (30) away from the temporary substrate; A second adhesive layer (22) is formed on the surface of the substrate, wherein the peripheral edge of the second adhesive layer (22) has a plurality of gaps (220) arranged at intervals; The first glue layer of the epitaxial layer (30) and the second glue layer (22) of the substrate are pressed together to form the bonding layer (20).
8. The preparation method according to claim 7, characterized in that: The orthographic projection of the notch (220) on the surface of the substrate is a third projection, and the width of the third projection on a side close to the center of the second adhesive layer (22) is smaller than the width of the third projection on a side away from the center of the second adhesive layer (22).
9. The preparation method according to claim 8, characterized in that: The shape of the third projection includes a triangle and a trapezoid.
10. The preparation method according to any one of claims 6 to 9, characterized in that: The outer contour of the first projection is a first contour line (11), the outer contour of the second projection is a second contour line (21), and the minimum distance D between the first contour line (11) and the second contour line (21) is N×T×R; Wherein, N is a correction coefficient, N is a fixed value, T is the thickness of the bonding layer (20), and R is the radius of the substrate.