A gate-controlled Hall element based on a silicon-germanium quantum well and a method for realizing the same

Abstract

The present invention discloses a gate-controlled Hall element based on a silicon-germanium quantum well and a method for realizing the same. The present invention adopts a silicon-germanium quantum well structure, which is compatible with the traditional silicon MOS process, avoids the high cost of developing a new material substrate, and can conveniently match the existing silicon-based integrated circuits; by regulating the carrier concentration through the gate voltage, the present invention can respectively adapt to the constant voltage and constant current working modes; and can be regulated to a high mobility, effectively reducing the heat dissipation and power consumption of the device; in addition, the gate voltage can flexibly adjust the sensitivity of the Hall element, match the magnetic field range under different loads, and adapt to different application requirements; the solution of the present invention significantly improves the performance and working flexibility of the device, enables a single device to have a high-sensitivity measurement ability and adapt to multiple working modes, helps to reduce the number of components, optimize the circuit design, and improve the convenience of large-scale integration and development; the present invention is applied to magnetic field measurement, and is particularly suitable for detecting weak magnetic fields in a low-temperature environment.

Description

Technical Field

[0001] The present invention relates to semiconductor magnetic sensor technology, and particularly to a gate-controlled Hall element based on a silicon-germanium quantum well and a method for realizing the same. Background Art

[0002] A Hall sensor is an electronic device that uses the Hall effect to measure a magnetic field and has been widely used in fields such as industrial control systems, intelligent meters, and consumer electronic products. A Hall element refers to the part in the sensor where the Hall effect occurs. The Hall effect means that when an electric current passes through a conductor or semiconductor placed in a magnetic field, charge carriers are deflected under the influence of the Lorentz force, and an electric potential difference is generated in the direction perpendicular to the current and the magnetic field. Based on the change in the transverse Hall voltage, the change in the magnetic field can be detected. Through microscopic derivation, the Hall sensitivities of the element can be obtained: S_I = 1 / (ned), S_V = µW / L, where S_I and S_V represent the Hall sensitivities under unit current and unit voltage, corresponding to the constant-current and constant-voltage modes respectively, n is the carrier concentration, e is the elementary charge, d is the thickness of the working substance of the Hall element, µ is the carrier mobility, and W and L are the width and length of the conductive channel respectively. It can be seen that high carrier mobility and low carrier concentration will make the Hall element have high sensitivity. Commercial Hall element materials commonly use elemental semiconductor materials such as Si and Ge, but the carrier mobilities of such materials are generally not high, and the corresponding Hall element sensitivities are relatively low. Hall elements based on group III-V compound semiconductors such as GaAs and InSb have higher carrier mobilities and higher Hall sensitivities. However, the processes of such Hall elements have poor compatibility with the gate-controlled structure and often use modulation doping technology, resulting in relatively fixed carrier concentration and mobility in the channel, and the functions of the elements are relatively single. Multiple devices with different functions need to be integrated in different scenarios to meet the actual usage requirements, thus increasing the complexity of the manufacturing process.

[0003] With the development of materials science and nanotechnology, Hall elements based on two-dimensional materials and semiconductor quantum wells have shown great potential in terms of sensitivity and may gradually replace traditional elements in some high-precision applications. However, currently widely studied two-dimensional materials, such as graphene and transition metal dichalcogenides, as well as group III-V compound quantum wells such as GaAs / AlGaAs and AlGaN / GaN, still face problems such as complex manufacturing processes and incompatibility with traditional silicon MOS processes, which seriously restrict the large-scale integration and practical application of Hall elements. Summary of the Invention

[0004] To solve the problems existing in the above prior art, the present invention proposes a gate-controlled Hall element based on a silicon-germanium quantum well and its implementation method. By using a silicon-germanium quantum well, it has a very high mobility and can sensitively respond to weak magnetic fields, solving the problem of low sensitivity of existing Hall elements. The gate voltage regulates the carrier concentration and mobility of the Hall element, enabling multiple working modes and solving problems such as the single function and power consumption waste of existing devices.

[0005] An object of the present invention is to propose a gate-controlled Hall element based on a silicon-germanium quantum well.

[0006] The gate-controlled Hall element based on a silicon-germanium quantum well of the present invention includes: a substrate, a buffer layer, a silicon-germanium quantum well structure, a source electrode, a drain electrode, a measurement electrode, an oxide insulating layer, and a gate; wherein, a buffer layer is formed on the substrate; a silicon-germanium quantum well structure is formed on the buffer layer;

[0007] The silicon-germanium quantum well structure sequentially includes a first barrier layer, a well layer, a second barrier layer, and a capping layer from bottom to top; the materials of the first barrier layer and the second barrier layer are silicon-germanium compounds, the material of the well layer is germanium, the mobility of germanium is higher than that of silicon, the valence band of the barrier layer is lower than the valence band of the well layer, forming a potential well for holes, and the holes serve as carriers, thus confining the holes at the well layer, away from ionized impurities, forming a two-dimensional hole gas with high mobility, and the lattice constants of the barrier layer and the well layer are similar, with small lattice defects; a conductive channel is defined in the well layer, and a source electrode, a drain electrode, and two pairs of measurement electrodes are arranged around the conductive channel, the source electrode and the drain electrode are respectively located at both longitudinal ends of the conductive channel, the two pairs of measurement electrodes are respectively located on both lateral sides of the conductive channel, and the source electrode, the drain electrode, and the two pairs of measurement electrodes are respectively electrically connected to the conductive channel to form a bridge-shaped Hall bar structure;

[0008] An oxide insulating layer is formed on the silicon-germanium quantum well structure; a gate is formed on the oxide insulating layer, and the gate is located directly above the conductive channel;

[0009] The source electrode and the drain electrode are connected to a constant voltage source for the constant voltage mode, or the source electrode and the drain electrode are connected to a constant current source for the constant current mode; the two pairs of measurement electrodes are connected to an external measurement circuit; the gate is connected to a regulation voltage source;

[0010] A constant voltage or a constant current is input from the source electrode and the drain electrode through the constant voltage source or the constant current source, generating a longitudinal current between the source electrode and the drain electrode; a magnetic field perpendicular to the plane of the element is applied, and under the influence of the external magnetic field, holes accumulate on both sides of the conductive channel controlled by the gate voltage applied by the gate, the holes deflect, generating a transverse Hall voltage; the transverse Hall voltage is measured through the measurement electrodes located on both sides of the conductive channel, thereby obtaining magnetic field information through the transverse Hall voltage;

[0011] A gate voltage is applied to the gate by regulating a voltage source to adjust the Fermi level and carrier concentration of the potential well layer, thereby regulating the carrier mobility and achieving the purpose of regulating the Hall sensitivity; increasing the carrier concentration of the potential well layer and reducing the scattering of holes by impurities and defects at the distant interface, thereby enhancing the carrier mobility;

[0012] In the constant current mode, by regulating the voltage source to reduce the gate voltage applied to the gate, the carrier concentration is lowered; or in the constant voltage mode, by regulating the voltage source to increase the gate voltage applied to the gate, the carrier mobility is increased, and the Hall sensitivity can be improved in the constant current mode or the constant voltage mode respectively.

[0013] The substrate is made of n-type Si.

[0014] The materials of the first barrier layer and the second barrier layer are silicon germanium compound Si x Ge 1-x , where x is the silicon component in the first barrier layer and the second barrier layer. The silicon component x in the first barrier layer and the second barrier layer is 0.1 - 0.3.

[0015] The buffer layer includes a composition-unstrained buffer layer and a composition-graded buffer layer. For the barrier layer Si with a high Ge content x Ge 1-x , the material of the composition-unstrained buffer layer is germanium, and the material of the composition-graded buffer layer is silicon germanium compound Si z Ge 1-z , where z is the silicon component in the composition-graded buffer layer, 0 ≤ z ≤ x; the silicon component in the composition-graded buffer layer gradually changes from 0 to x from bottom to top, and the lattice constant gradually transitions from the composition-unstrained buffer layer to the first barrier layer Si x Ge 1-x ; the setting of the buffer layer achieves the effect of reducing crystal defects and gradually releasing stress.

[0016] The capping layer is made of silicon; it protects the underlying SiGe surface from natural oxidation and damage.

[0017] The shape of the conductive channel is rectangular, with a length of 100 - 300 μm and a width of 20 - 80 μm; appropriately increasing the width W and / or reducing the length L of the conductive channel, thereby providing high voltage sensitivity. The source electrode and the drain electrode are located at both ends of the short side of the Hall bar, and the measurement electrodes for measuring the transverse Hall voltage are located on both sides of the long side of the Hall bar, with two electrodes parallel to each other on the same side; the two electrodes on the opposite side are aligned with each other. Multiple electrodes parallel to each other on the long side are provided for measuring the longitudinal resistance by the four-terminal method, as well as increasing the fault tolerance rate for the situation where some electrodes are not conducting during fabrication and can be used for the constant current and constant voltage working modes respectively. The thicknesses of the source electrode, the drain electrode, and the measurement electrode are 50 - 100 nm; the thickness of the oxide insulating layer is 20 - 80 nm; the thickness of the gate is 150 - 300 nm.

[0018] The Hall sensitivity reflects the response ability of the Hall element to the magnetic field. \(S_A\) is the absolute Hall sensitivity, representing the change in the transverse Hall voltage \(V\) caused by a unit change in the magnetic field, which reflects the sensitivity of the Hall signal of the element to the magnetic field change. \(S_I\) and \(S_V\) represent the Hall sensitivities under a unit current and a unit voltage respectively. The larger the Hall sensitivity \(S_I\) under a unit current or the Hall sensitivity \(S_V\) under a unit voltage, the larger the Hall sensitivity can be obtained with a unit external bias current or voltage. The Hall sensitivity \(S_I\) under a unit current is inversely proportional to the carrier concentration, while the Hall sensitivity \(S_V\) under a unit voltage is proportional to the carrier mobility. Therefore, by regulating the voltage source to reduce the gate voltage applied to the gate, the carrier concentration can be lowered in the constant current mode, and by regulating the voltage source to increase the gate voltage applied to the gate, the carrier mobility can be increased in the constant voltage mode, so as to achieve high Hall sensitivity in the constant current mode and the constant voltage mode respectively. xy The change amount reflects the sensitivity of the Hall signal of the element to the magnetic field change. \(S_I\) and \(S_V\) represent the Hall sensitivities under a unit current and a unit voltage respectively. The larger the Hall sensitivity \(S_I\) under a unit current or the Hall sensitivity \(S_V\) under a unit voltage, the larger the Hall sensitivity can be obtained with a unit external bias current or voltage. The Hall sensitivity \(S_I\) under a unit current is inversely proportional to the carrier concentration, while the Hall sensitivity \(S_V\) under a unit voltage is proportional to the carrier mobility. Therefore, by regulating the voltage source to reduce the gate voltage applied to the gate, the carrier concentration can be lowered in the constant current mode, and by regulating the voltage source to increase the gate voltage applied to the gate, the carrier mobility can be increased in the constant voltage mode, so as to achieve high Hall sensitivity in the constant current mode and the constant voltage mode respectively.

[0019] The voltage range of the constant voltage source is 0.1 - 1 mV, the current range of the constant current source is 0.1 - 1 μA, and the voltage range of the regulating voltage source is -2.5 - -2.2 V.

[0020] Another object of the present invention is to propose a method for realizing a gate - controlled Hall element based on a silicon - germanium quantum well.

[0021] The method for realizing a gate - controlled Hall element based on a silicon - germanium quantum well of the present invention includes the following steps:

[0022] 1) Connection of the gate - controlled Hall element:

[0023] The source electrode and the drain electrode are connected to a constant voltage source for the constant current mode, or the source electrode and the drain electrode are connected to a constant current source for the constant voltage mode; two pairs of measurement electrodes are connected to an external measurement circuit; the gate is connected to a regulating voltage source;

[0024] 2) Magnetic field measurement:

[0025] a) Input a constant voltage or a constant current from the source electrode and the drain electrode through the constant voltage source or the constant current source to generate a longitudinal current between the source electrode and the drain electrode;

[0026] b) Apply a magnetic field perpendicular to the plane of the element. Affected by the external magnetic field, the holes deflect, and the holes accumulate on both sides of the conductive channel controlled by the gate voltage applied to the gate, generating a transverse Hall voltage;

[0027] c) Measure the transverse Hall voltage through two pairs of measurement electrodes located on both sides of the conductive channel, and thus obtain the magnetic field from the transverse Hall voltage;

[0028] 3) Gate voltage regulation:

[0029] a) By controlling the voltage source to apply a gate voltage to the gate, the carrier concentration in the potential well layer is changed, thereby adjusting the carrier mobility, so as to achieve the purpose of regulating the Hall sensitivity; increasing the carrier concentration in the potential well layer reduces the scattering of holes by impurities and defects at the distant interface, thereby enhancing the carrier mobility;

[0030] b) In the constant current mode, by controlling the voltage source to reduce the gate voltage applied to the gate, the carrier concentration is lowered; or in the constant voltage mode, by controlling the voltage source to increase the gate voltage applied to the gate, the carrier mobility is increased, and the Hall sensitivity can be increased respectively in the constant current mode or the constant voltage mode.

[0031] The implementation method of the gate-controlled Hall element based on silicon-germanium quantum well of the present invention further includes a preparation method of the gate-controlled Hall element, which includes the following steps:

[0032] a) Form a buffer layer on the substrate;

[0033] b) Form a silicon-germanium quantum well structure on the buffer layer: sequentially form a first barrier layer, a potential well layer, a second barrier layer, and a capping layer from bottom to top on the buffer layer; the materials of the first barrier layer and the second barrier layer are silicon-germanium compounds, the material of the potential well layer is germanium, holes are confined at the potential well layer, and holes are used as carriers to form a two-dimensional hole gas with high mobility;

[0034] c) Define a conductive channel in the potential well layer, and set a source electrode, a drain electrode, and two pairs of measurement electrodes around the conductive channel. The source electrode and the drain electrode are respectively located at both longitudinal ends of the conductive channel, and the two pairs of measurement electrodes are respectively located on both lateral sides of the conductive channel. The source electrode, the drain electrode, and the two pairs of measurement electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure;

[0035] d) Form an oxide insulating layer on the silicon-germanium quantum well structure;

[0036] e) Form a gate on the oxide insulating layer, and the gate is located directly above the conductive channel.

[0037] Advantages of the present invention:

[0038] The present invention adopts a silicon-germanium quantum well structure, which is compatible with the traditional silicon MOS process, avoiding the high cost of developing new material substrates and enabling convenient matching with existing silicon-based integrated circuits. The gate-controlled Hall element proposed by the present invention, on the one hand, can regulate the carrier concentration through the gate voltage and can be adapted to constant voltage and constant current working modes respectively; on the other hand, it can be regulated to a high mobility, effectively reducing the heat dissipation and power consumption of the device. In addition, the gate voltage can flexibly adjust the sensitivity of the Hall element in the same mode, match the magnetic field range under different loads, and adapt to different application requirements. For example, it provides high sensitivity in weak magnetic field detection, while reducing the sensitivity in a strong magnetic field environment to ensure stability. Compared with the traditional Hall element using channel materials with fixed carrier concentration and mobility, the present invention significantly improves the performance and working flexibility of the device, enabling a single device to have both high-sensitivity measurement capabilities and adapt to multiple working modes, which helps to reduce the number of components, optimize the circuit design, and enhance the convenience of large-scale integration and development. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a top view of an embodiment of the gate-controlled Hall element based on silicon-germanium quantum well of the present invention;

[0040] Figure 2 is a cross-sectional view of an embodiment of the gate-controlled Hall element based on silicon-germanium quantum well of the present invention;

[0041] Figure 3 is a curve graph of the gate voltage regulating the carrier concentration and mobility obtained according to an embodiment of the gate-controlled Hall element based on silicon-germanium quantum well of the present invention;

[0042] Figure 4 is a curve graph of the Hall sensitivity under unit current and unit voltage under the gate voltage regulation within a suitable range according to an embodiment of the gate-controlled Hall element based on silicon-germanium quantum well of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0044] As Figure 1 and 2 shown, the gate-controlled Hall element based on silicon-germanium quantum well of this embodiment includes: a substrate, a buffer layer, a silicon-germanium quantum well structure, a source electrode 201, a drain electrode 202, a measurement electrode 203, an oxide insulating layer 300, and a gate 400; wherein, a buffer layer is formed on the substrate; a silicon-germanium quantum well structure is formed on the buffer layer;

[0045] The silicon-germanium quantum well structure sequentially includes a first barrier layer 100, a quantum well layer 101, a second barrier layer 102, and a capping layer 103 from bottom to top; the materials of the first barrier layer 100 and the second barrier layer 102 are Si xGe 1-x where \(x\) and \(1 - x\) are the compositions of silicon and germanium respectively. The material of the potential well layer 101 is germanium, and holes are confined in the potential well layer. As carriers, the holes are far from ionized impurities, forming a two-dimensional hole gas 400 with high mobility. A conductive channel 104 is defined in the potential well layer, and a source electrode, a drain electrode, and two pairs of measurement electrodes are arranged around the conductive channel. The source electrode and the drain electrode are located at the two longitudinal ends of the conductive channel respectively, and the two pairs of measurement electrodes are located on the two lateral sides of the conductive channel respectively. The rectangular area surrounded by the source electrode, the drain electrode, and the two pairs of measurement electrodes forms the conductive channel. The source electrode, the drain electrode, and the two pairs of measurement electrodes are electrically connected to the conductive channel respectively to form a bridge-type Hall bar structure;

[0046] An oxide insulating layer 300 is formed on the silicon-germanium quantum well structure; a gate 400 is formed on the oxide insulating layer, and the gate is located directly above the conductive channel;

[0047] The source electrode is connected to a constant voltage source or a constant current source, and the drain electrode is grounded; the two pairs of measurement electrodes are connected to an external measurement circuit; the gate is connected to a control voltage source through a pad.

[0048] The implementation method of the gate-controlled Hall element based on the silicon-germanium quantum well in this embodiment includes the following steps:

[0049] 1) Preparation of the gate-controlled Hall element:

[0050] a) Using an n-type Si(001) as the substrate, a buffer layer is formed on the substrate; the buffer layer includes a 600-nm-thick strain-free Ge buffer layer and a 2-μm-thick compositionally graded Si z Ge 1-z buffer layer, where \(z\) gradually changes from 0 to 0.2 from bottom to top; the setting of the buffer layer achieves the effect of reducing crystal defects and gradually releasing stress;

[0051] b) Forming a silicon-germanium quantum well structure on the buffer layer:

[0052] The silicon-germanium quantum well structure successively forms a first barrier layer, a potential well layer, a second barrier layer, and a capping layer from bottom to top; the first barrier layer is a 500-nm-thick Si 0.2 Ge 0.8 , the potential well layer is an 18-nm-thick Ge, the second barrier layer is a 38-nm-thick Si 0.2 Ge 0.8 , the capping layer is a 2-nm-thick Si, forming a silicon-germanium quantum well structure; a relatively high potential barrier is formed in the energy band structure to confine carriers in the potential well layer; the capping layer uses Si to protect the underlying structure from oxidation;

[0053] The above growth method uses ultra-high vacuum chemical vapor deposition to ensure the interface quality between layers;

[0054] Hall bar platform etching: Take a substrate with a silicon-germanium quantum well structure, clean the sample and dry it with high-purity nitrogen after cleaning; spin-coat the photoresist, perform electron beam lithography, and develop and fix the image to determine the shape of the etching area; use the method of reactive ion etching (RIE) to etch a Hall bar platform on the silicon-germanium quantum well structure, and set a rectangular conductive channel in the potential well layer through the above method, with a length of 195 μm and a width of 35 μm;

[0055] c) Preparation of metal Al electrodes:

[0056] Expose the electrode area that needs to contact the conductive channel on the Hall bar platform, wash away the natural oxide layer on the surface with hydrofluoric acid HF, and deposit a film by electron beam evaporation; note that the vacuum degree of the electron beam chamber is preferably lower than 5×10 -8 Torr, the thickness of Al is 80 nm as the measurement electrode, source electrode, and drain electrode. After film deposition, perform in-situ annealing for 2 h to recover the defects caused during the etching, exposure, and film deposition processes. During the annealing process, Al diffuses into Ge to achieve ohmic contact between the electrode and the conductive channel, forming a bridge-type Hall bar structure; finally, perform the lift-off process. Put the film-deposited substrate into acetone to wash away the photoresist. After the excess photoresist and metal are peeled off, the source electrode, drain electrode, and measurement electrode with the required shape can be obtained. Finally, dry the sample with high-purity nitrogen;

[0057] d) Preparation of the oxide insulating layer: Deposit Al2O3 as the oxide insulating layer on the silicon-germanium quantum well structure using atomic layer deposition (ALD); turn on high-purity nitrogen (carrier gas, trimethylaluminum TMA reacts with water to form Al2O3), the temperature is 100~300 °C, preferably 150 °C, the thickness is about 60 nm, and the deposition process is completed in about ten minutes;

[0058] e) Preparation of the gate: Spin-coat the photoresist, perform electron beam lithography, deposit a film, develop and fix the image, and perform lift-off to obtain the gate; confirm the gate pattern through exposure, and then deposit a metal film Au using electron beam evaporation to obtain the gate; ensure that the gate covers the conductive channel to ensure that the gate voltage of the two-dimensional hole gas is adjustable;

[0059] 2) Connection of the gate-controlled Hall element:

[0060] Connect the source electrode and the drain electrode to a constant voltage source for the constant voltage mode, or connect the source electrode and the drain electrode to a constant current source for the constant current mode; connect the two pairs of measurement electrodes to an external measurement circuit; connect the gate to a control voltage source;

[0061] 3) Magnetic field measurement:

[0062] a) Input a constant voltage or constant current from the source electrode and the drain electrode through a constant voltage source or a constant current source to generate a longitudinal current between the source electrode and the drain electrode; apply a gate voltage to the gate through a control voltage source;

[0063] b) Apply a magnetic field perpendicular to the plane of the element. Affected by the external magnetic field, the holes are deflected and accumulate on both sides of the range of the conductive channel controlled by the gate voltage applied to the gate, generating a transverse Hall voltage V xy ;

[0064] c) Measure the transverse Hall voltage through two pairs of measurement electrodes located on both sides of the conductive channel, and thus obtain the magnetic field from the transverse Hall voltage;

[0065] 4) Gate voltage regulation:

[0066] a) Apply a gate voltage to the gate through a regulated voltage source to change the carrier concentration in the potential well layer, and then adjust the carrier mobility to achieve the purpose of regulating the Hall sensitivity; increasing the carrier concentration in the potential well layer is beneficial to reducing the scattering of holes by impurities and defects at the distant interface, thereby enhancing the carrier mobility;

[0067] b) In the constant current mode, reduce the gate voltage applied to the gate through a regulated voltage source to lower the carrier concentration; or in the constant voltage mode, increase the gate voltage applied to the gate through a regulated voltage source to increase the carrier mobility, which can respectively achieve an increase in Hall sensitivity in the constant current mode or the constant voltage mode.

[0068] In subsequent applications, multiple Hall elements perpendicular to the xyz axes are placed three-dimensionally, and each of the multiple Hall elements is sensitive to the magnetic field component corresponding to the respective axis. Dynamically adjust the sensitivity of each Hall element through the gate voltage, and then combine circuit design and direction correction to obtain the magnitude and direction of the magnetic field in the actual three-dimensional space.

[0069] Perform basic characterization on a silicon-germanium quantum well hole-type Hall bar. The drain electrode is grounded, and a constant-amplitude alternating current is input to the source electrode. Conduct electrical transport measurements by changing conditions such as the gate voltage V g and the magnetic field B. Using holes as carriers, obtain the basic carrier transport properties of the silicon-germanium quantum well structure, such as n / μ-V g . Obtain the curve of the transverse Hall voltage V xy changing with the magnetic field B, calculate the Hall sensitivity of the element. As can be seen from Figure 2 , the slope of the curve is very large and the sensitivity is high, so it can be used to detect weak magnetic fields. The adjustable gate voltage allows different working modes or parameter settings to be achieved on the same Hall element. Lowering the carrier concentration in the constant current mode and increasing the carrier mobility in the constant voltage mode can respectively achieve an increase in Hall sensitivity in the constant current mode and the constant voltage mode.

[0070] Principle of gate voltage regulation and realization of high sensitivity of a gate-controlled Hall element:

[0071] A gate voltage is applied to the gate by regulating a voltage source to adjust the Fermi level and carrier concentration of the potential well layer, thereby regulating the carrier mobility to achieve the purpose of regulating the Hall sensitivity; the ability of the gate voltage to adjust the carrier concentration in the potential well layer depends on the capacitance of its equivalent parallel-plate capacitor; for the same oxide insulating layer material of the parallel-plate capacitor, the thinner its thickness, the larger the capacitance of the parallel-plate capacitor, and the stronger the ability of the gate voltage to adjust the carrier concentration and mobility; the ability of the gate voltage to adjust the hole concentration in the potential well layer depends on the capacitance of its equivalent parallel-plate capacitor; the parallel-plate capacitance formula is C = εS / 4πkt, where C is the capacitance of the parallel-plate capacitor, ε is the dielectric constant of the oxide insulating layer, S is the facing area of the electrode plates, k is the electrostatic constant, and t is the thickness of the oxide insulating layer.

[0072] The physical quantities represented by letters in the following derivation: B is the magnetic field strength perpendicular to the plane of the Hall bar. μ is the carrier mobility, n is the carrier concentration, e is the elementary charge; V xy is the transverse Hall voltage, V xx is the longitudinal voltage, I is the longitudinal current. W is the width (transverse) of the conductive channel, and L is the length (longitudinal) of the conductive channel. The carrier concentration n = B / eR xy , and the thickness of the two-dimensional conductive channel is not considered.

[0073] The carrier mobility μ = σ / ne = 1 / (neρ) = (V xy / V xx )*(L / BW).

[0074] Among them, σ is the conductivity and ρ is the resistivity. The Hall sensitivity reflects the response ability of the Hall element to the magnetic field. S_A is the absolute Hall sensitivity, which represents the change in the transverse Hall voltage caused by a unit change in the magnetic field, that is, the slope of the V xy -B linear relationship.

[0075] Absolute Hall sensitivity: ;

[0076] Hall sensitivity under unit current: ; Hall sensitivity under unit voltage: ;

[0077] In the constant current mode, from V xy / I = B / ne; we get S_I = V xy / BI = 1 / ne, with the dimension of V / (AT);

[0078] In the constant voltage mode, from μ = σ / ne = 1 / (neρ) = (V xy / V xx )*(L / BW); we get S_V = V xy / (BVxx ) = μW / L, with the dimension of V / (VT).

[0079] Gate control function: Gate voltage V g The absolute value is positively correlated with the carrier concentration n and the carrier mobility μ. By changing the gate voltage V g or conditions such as magnetic field B for electrical transport measurement, the Hall sensitivity changes with the gate voltage V according to the above formula g to obtain the n / μ-V g relationship, as Figure 3 shown. By simply electrically controlling the carriers, the sensitivity can be switched under different working conditions, as Figure 4 shown. Under the geometric conditions of the conductive channel in this embodiment, the length of the conductive channel is 195 μm and the width is 35 μm. Within the appropriate gate voltage range for the Hall element to work, the Hall sensitivity SI per unit current can reach 3000 - 10000 V / (AT), and the Hall sensitivity SV per unit voltage can reach 1 - 6 V / (VT), indicating that the Hall element can be highly sensitive in both the constant current mode and the constant voltage mode, and the sensitivity change range in a single mode is large, which can meet different application requirements.

[0080] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention. However, those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the present invention shall be defined by the scope defined in the claims.

Claims

1. A gate-controlled Hall element based on a silicon-germanium quantum well, characterized in that, The gated Hall element includes: a substrate, a buffer layer, a silicon-germanium quantum well structure, a source electrode, a drain electrode, a measurement electrode, an oxide insulating layer, and a gate; wherein, a buffer layer is formed on the substrate; a silicon-germanium quantum well structure is formed on the buffer layer; The silicon-germanium quantum well structure sequentially includes a first barrier layer, a quantum well layer, a second barrier layer, and a cap layer from bottom to top; the materials of the first barrier layer and the second barrier layer are silicon-germanium compounds, the material of the quantum well layer is germanium, and through the confinement of the quantum well layer and the material characteristics of germanium, holes with high mobility are formed in the quantum well layer as carriers; a conductive channel is defined in the quantum well layer, and a source electrode, a drain electrode, and two pairs of measurement electrodes are arranged around the conductive channel. The source electrode and the drain electrode are respectively located at both longitudinal ends of the conductive channel, and the two pairs of measurement electrodes are respectively located on both lateral sides of the conductive channel. The source electrode, the drain electrode, and the two pairs of measurement electrodes are respectively electrically connected to the conductive channel to form a bridge-shaped Hall bar structure; An oxide insulating layer is formed on the silicon-germanium quantum well structure; a gate is formed on the oxide insulating layer, and the gate is located directly above the conductive channel; The source electrode and the drain electrode are connected to a constant voltage source for the constant voltage mode, or the source electrode and the drain electrode are connected to a constant current source for the constant current mode; the two pairs of measurement electrodes are connected to an external measurement circuit; the gate is connected to a regulation voltage source; The measurement circuit measures the transverse Hall voltage to obtain external magnetic field information; the regulation voltage source changes the gate voltage to respectively achieve an increase in Hall sensitivity in different modes.

2. The gated Hall element according to claim 1, wherein The materials of the first barrier layer and the second barrier layer are silicon germanium compound Si x Ge 1-x , where x is the silicon component in the first barrier layer and the second barrier layer; the silicon component x in the first barrier layer and the second barrier layer is 0.1 to 0.

3.

3. The gated Hall element according to claim 2, wherein The buffer layer includes a compositionally strain-free buffer layer and a compositionally graded buffer layer. The material of the strain-free buffer layer is germanium, and the material of the compositionally graded buffer layer is silicon germanium compound Si z Ge 1-z , where z is the silicon composition in the compositionally graded buffer layer, 0 ≤ z ≤ x; the silicon composition in the compositionally graded buffer layer gradually changes from 0 to x from bottom to top, and the lattice constant gradually transitions from the strain-free buffer layer to the first barrier layer.

4. The gated Hall element according to claim 1, wherein The thickness of the source electrode, the drain electrode, and the measurement electrode is 50 - 100 nm.

5. The gated Hall element according to claim 1, wherein The thickness of the oxide insulating layer is 20 - 80 nm.

6. The gated Hall element according to claim 1, characterized in that, The thickness of the gate is 150 - 300 nm.

7. A method for implementing a gate-controlled Hall element based on a silicon-germanium quantum well as described in claim 1, characterized in that, The implementation method includes the following steps: 1) Connection of the gated Hall element: The source electrode and the drain electrode are connected to a constant voltage source for the constant current mode, or the source electrode and the drain electrode are connected to a constant current source for the constant voltage mode; the two pairs of measurement electrodes are connected to an external measurement circuit; the gate is connected to a regulation voltage source; 2) Magnetic field measurement: a) Input a constant voltage or a constant current from the source electrode and the drain electrode through the constant voltage source or the constant current source to generate a longitudinal current between the source electrode and the drain electrode; b) Apply a magnetic field perpendicular to the plane of the element. Affected by the external magnetic field, the holes deflect, and the holes accumulate on both sides of the conductive channel controlled by the gate voltage applied by the gate, generating a transverse Hall voltage; c) Measure the transverse Hall voltage through the two pairs of measurement electrodes located on both sides of the conductive channel, so as to obtain the magnetic field information through the transverse Hall voltage; 3) Gate voltage regulation: Achieve high Hall sensitivity in different modes by changing the gate voltage applied to the gate by the regulation voltage source.

8. The implementation method according to claim 7, wherein, It also includes a preparation method of the gated Hall element, including the following steps: a) Form a buffer layer on the substrate; b) Form a silicon-germanium quantum well structure on the buffer layer: sequentially form a first barrier layer, a quantum well layer, a second barrier layer, and a cap layer from bottom to top on the buffer layer; the materials of the first barrier layer and the second barrier layer are silicon-germanium compounds, the material of the quantum well layer is germanium, the holes are confined at the quantum well layer, and the holes are used as carriers to form a two-dimensional hole gas; c) Define a conductive channel in the potential well layer, and set a source electrode, a drain electrode, and two pairs of measurement electrodes around the conductive channel. The source electrode and the drain electrode are respectively located at both longitudinal ends of the conductive channel, and the two pairs of measurement electrodes are respectively located on both transverse sides of the conductive channel. The source electrode, the drain electrode, and the two pairs of measurement electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure; d) Form an oxide insulating layer on the silicon-germanium quantum well structure; e) Form a gate on the oxide insulating layer, and the gate is located directly above the conductive channel.

9. The implementation method according to claim 7, wherein, In step 1), by increasing the width W and decreasing the length L of the conductive channel, a high voltage sensitivity is provided.

10. The implementation method according to claim 7, wherein In step 3), the gate voltage regulation includes: in the constant current mode, by regulating the voltage source to reduce the gate voltage applied to the gate and lower the carrier concentration; or in the constant voltage mode, by regulating the voltage source to increase the gate voltage applied to the gate and increase the carrier mobility, the Hall sensitivity can be improved respectively in the constant current mode or the constant voltage mode.

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