Capacitor device, forming method thereof and electronic equipment

Abstract

The invention relates to the technical field of semiconductors, in particular to a capacitor device, a forming method thereof and electronic equipment, and the capacitor device comprises a bottom conductor layer which is located on a substrate; the multiple conductor layers are located on the substrate and comprise a bottom conductor layer, at least one middle conductor layer and a top conductor layer which are sequentially stacked from the substrate; the dielectric layers are located between the adjacent bottom conductor layer and the middle conductor layer, between the two adjacent middle conductor layers and between the adjacent middle conductor layer and the top conductor layer; at least one of the middle conductor layers is provided with a step part, and the step side wall of at least one of the step parts is a transition surface which extends towards the substrate and is inclined relative to the plane of the substrate. The performance and reliability of the capacitor device can be optimized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a capacitor device, a method for forming the capacitor device, and an electronic device. Background Art

[0002] A capacitor is a device that stores energy in an electric field and plays an important role in circuits such as tuning, bypassing, coupling, and filtering. MIM capacitors (Metal-Insulator-Metal) are equivalent to parallel plate capacitors and have advantages such as higher Q value, lower loss, higher withstand voltage, and lower ESR (Equivalent Series Resistance). They can improve system efficiency and have more accurate capacitance values ​​that do not change with bias voltage. They are commonly used capacitors in integrated circuits (ICs).

[0003] The traditional MIM capacitor structure has only a single dielectric layer, and its equivalent capacitance density is limited by the thickness and dielectric constant value of the Hk (high dielectric constant) dielectric layer. Therefore, multi-layer plates are used in advanced processes to obtain higher equivalent capacitance density. However, due to the stacking and covering of multi-layer plates and dielectric layers, there are uneven structures such as sharp corners of layered edges, which cause problems such as uneven local deposition of conductor materials and dielectric materials of the MIM capacitor and large local electric fields. Summary of the invention

[0004] In view of the above problems in the prior art, the present application provides a capacitor device, a method for forming the capacitor device, and an electronic device. The specific technical solutions are as follows:

[0005] In one aspect, the present application provides a capacitive device, the capacitive device comprising:

[0006] substrate;

[0007] A multi-layer conductor layer located on the substrate, the multi-layer conductor layer comprising a bottom conductor layer, at least one intermediate conductor layer and a top conductor layer stacked in sequence from the substrate;

[0008] The dielectric layer is located between the adjacent bottom conductor layer and the intermediate conductor layer, between two adjacent intermediate conductor layers, and between the adjacent intermediate conductor layer and the top conductor layer; at least one of the intermediate conductor layers has a step portion, and the step side wall of at least one of the step portions is a transition surface extending toward the substrate and inclined relative to the substrate plane.

[0009] In a possible implementation manner, the edge sidewall of at least one of the intermediate conductor layers and the bottom conductor layer and the surface adjacent to the edge sidewall are in a corner structure;

[0010] A conductor filling body capable of at least partially filling the corner structure is provided on the dielectric layer covering the corner structure, wherein the surface of the conductor filling body facing away from the dielectric layer where the conductor filling body is located is a transition surface extending toward the substrate and inclined relative to the substrate plane;

[0011] The intermediate conductor layer and / or the dielectric layer located above the conductor filling body has the step portion, and the side wall of the step conforms to the surface of the conductor filling body.

[0012] In a possible implementation manner, the conductor filling body satisfies at least one of the following characteristics:

[0013] The cross section of the conductor filling body is a triangle or an arc-shaped triangle;

[0014] The material of the intermediate conductor layer adjacent to the conductor filling body is the same as that of the conductor filling body.

[0015] In a possible implementation manner, an edge of at least one of the intermediate conductor layers and the bottom conductor layer is a transition structure, and a surface of the transition structure is a transition surface extending toward the substrate and inclined relative to the substrate plane;

[0016] The dielectric layer and / or the intermediate conductor layer located above the transition structure has the step portion, and the side wall of the step conforms to the surface of the transition structure.

[0017] In a possible implementation manner, an angle between the transition surface and the base plane is 50°-80°.

[0018] In a possible implementation manner, the capacitive device satisfies at least one of the following characteristics:

[0019] The thickness of the bottom conductor layer is 300A-800A;

[0020] The thickness of the intermediate conductor layer is 300A-800A;

[0021] The thickness of the top conductor layer is 300A-800A.

[0022] In a possible implementation manner, the capacitive device satisfies at least one of the following characteristics:

[0023] The material of the bottom conductor layer includes one or a combination of titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum, copper, tungsten, tungsten alloy, aluminum, platinum, nickel, aluminum alloy, copper-aluminum alloy;

[0024] The material of the intermediate conductor layer includes one or a combination of titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum, copper, tungsten, tungsten alloy, aluminum, platinum, nickel, aluminum alloy, copper-aluminum alloy;

[0025] The material of the top conductor layer includes one or a combination of titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum, copper, tungsten, tungsten alloy, aluminum, platinum, nickel, aluminum alloy, copper-aluminum alloy;

[0026] The material of the dielectric layer includes one or a combination of hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxynitride, ethyl silicate, glass material, and halogenated silicon oxide.

[0027] In a possible implementation, the capacitive device further includes a first interconnection structure and a second interconnection structure;

[0028] Some of the top conductor layer, each of the intermediate conductor layers and the bottom conductor layer are odd-numbered conductor layers in sequence, and the other parts are even-numbered conductor layers in sequence;

[0029] One of the first interconnect structure and the second interconnect structure is electrically connected to odd-numbered conductor layers among the multi-layer conductor layers, and the other is electrically connected to even-numbered conductor layers among the multi-layer conductor layers.

[0030] In a possible implementation manner, the capacitor device further includes a dummy structure, and the dummy structure is provided on the side of at least one of the top conductor layer, each of the intermediate conductor layers and the bottom conductor layer and is laterally separated from the dummy structure;

[0031] The dummy structure is connected to at least one of the first interconnect structure and the second interconnect structure.

[0032] In a possible implementation manner, the capacitive device further includes:

[0033] an upper metal layer, located on a side of the top conductor layer away from the substrate and spaced apart from the top conductor layer, the upper metal layer being electrically connected to the first interconnect structure and the second interconnect structure respectively;

[0034] A lower metal layer is located in the substrate, and the lower metal layer is electrically connected to the first interconnect structure and the second interconnect structure respectively.

[0035] On the other hand, the present application provides a method for forming a capacitive device, the method comprising:

[0036] Providing a substrate,

[0037] forming a plurality of conductor layers on the substrate, the plurality of conductor layers comprising a bottom conductor layer, at least one intermediate conductor layer and a top conductor layer stacked in sequence, and forming a dielectric layer between adjacent bottom conductor layers and intermediate conductor layers, between two adjacent intermediate conductor layers, and between adjacent intermediate conductor layers and the top conductor layer;

[0038] At least one of the intermediate conductor layers has a step portion, and a step sidewall of at least one of the step portions is a transition surface extending toward the substrate and inclined relative to a substrate plane.

[0039] In a possible implementation manner, the edge sidewall of at least one of the intermediate conductor layers and the bottom conductor layer and the surface adjacent to the edge sidewall present a corner structure; and the process of forming the bottom conductor layer, the intermediate conductor layer and the dielectric layer comprises:

[0040] After forming a dielectric layer covering the corner structure on the bottom conductor layer and / or the middle conductor layer having the corner structure, forming a conductor sacrificial layer covering the corner structure on the dielectric layer;

[0041] Etching the conductor sacrificial layer to form a conductor filling body on the dielectric layer that at least partially fills the corner structure, wherein a surface of the conductor filling body that is away from the dielectric layer where the conductor filling body is located is a transition surface that extends toward the substrate and is inclined relative to the substrate plane;

[0042] The intermediate conductor layer and the dielectric layer are formed on the dielectric layer having the conductor filling body, and the step portion is formed in the region of the intermediate conductor layer and the dielectric layer covering the conductor filling body, and the step sidewall conforms to the surface of the conductor filling body.

[0043] In a possible implementation manner, the conductor filling body is formed by isotropic back etching.

[0044] In a possible implementation manner, the process of forming the bottom conductor layer, the middle conductor layer and the dielectric layer includes:

[0045] The edge of at least one of the intermediate conductor layers and the bottom conductor layer formed on the substrate is a transition structure, and the surface of the transition structure is a transition surface extending toward the substrate and inclined relative to the substrate plane;

[0046] The dielectric layer and / or the intermediate conductor layer are formed on the bottom conductor layer and / or the intermediate conductor layer having the transition structure, and the step portion is formed in the area of ​​the dielectric layer and / or the intermediate conductor layer covering the transition structure, and the step sidewall is contoured to the surface of the transition structure.

[0047] In a possible implementation manner, the forming method further comprises:

[0048] forming longitudinally extending first and second interconnect structures;

[0049] Part of the top conductor layer, each of the intermediate conductor layers and the bottom conductor layer are odd-numbered conductor layers in order, and the other part are even-numbered conductor layers in order, one of the first interconnect structure and the second interconnect structure is electrically connected to the odd-numbered conductor layers in the multi-layer conductor layers, and the other is electrically connected to the even-numbered conductor layers in the multi-layer conductor layers.

[0050] In a possible implementation manner, a lower metal layer is buried in the substrate, and the first interconnect structure and the second interconnect structure respectively extend longitudinally to the lower metal layer and are electrically connected to the lower metal layer;

[0051] The forming method further includes: forming an upper metal layer spaced apart from the top conductor layer on a side of the top conductor layer away from the substrate, wherein the upper metal layer is electrically connected to the first interconnect structure and the second interconnect structure respectively.

[0052] On the other hand, the present application provides an integrated circuit, which includes the above-mentioned capacitor device.

[0053] On the other hand, the present application provides an electronic device, which includes the above-mentioned capacitive device.

[0054] Based on the above technical solution, this application has the following beneficial effects:

[0055] The technical solution of the present application provides a multilayer plate capacitor structure having a stacked bottom conductor layer, at least one intermediate conductor layer and a top conductor layer, and the step side wall of the step portion of at least one intermediate conductor layer is a transition surface extending toward the substrate and inclined relative to the substrate plane, thereby avoiding the formation of a sharp-angle structure there, which causes a large electric field and is not conducive to the deposition of a dielectric layer and a conductor layer, and the step portion and the layers of structure above it form a gentle slope with uniform thickness, effectively reducing the local electric field there, improving the uniformity of the layer thickness and the electric field uniformity of the capacitor device, and improving the performance of the capacitor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 : A schematic diagram of the structure of a capacitor device in the prior art;

[0058] Figure 2 : TEM image of a four-layer TiN MiM capacitor structure in the prior art;

[0059] Figure 3 : A cross-sectional view of a capacitor device provided in an embodiment of the present application;

[0060] Figure 4 : A cross-sectional view of another capacitor device provided in an embodiment of the present application;

[0061] Figure 5 : A cross-sectional view of another capacitor device provided in an embodiment of the present application;

[0062] Figure 6 : A cross-sectional view of a capacitor device during a formation process provided by an embodiment of the present application;

[0063] Figure 7 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0064] Figure 8 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0065] Fig. 9 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0066] Fig.10 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0067] Fig.11 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0068] Fig.12 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0069] Fig.13 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0070] Fig.14 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0071] Fig.15 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0072] Fig.16 : A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0073] Fig.17: A cross-sectional view of a capacitor device during another formation process provided by an embodiment of the present application;

[0074] Figure numerals: 100 - substrate 100, 101 - base 101, 102 - etch stop layer 102, 103 - substrate dielectric layer 103, 201 - bottom conductor layer 201, 202 - top conductor layer 202, 203 - intermediate conductor layer 203, 204 - dielectric layer 204, 205 - step portion 205, 205a - step sidewall 205a, 206 - corner structure 206, 207 - conductor filling body 207, 208 - transition structure 208, 209 - first interconnect structure 209, 210 - second interconnect structure 210, 211 - dummy structure 211, 212 - upper metal layer 212, 213 - lower metal layer 213, 214 - top packaging layer 214, 301 - conductor sacrificial layer 301. DETAILED DESCRIPTION

[0075] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0076] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given in the claims or elsewhere in this specification, these definitions should be applied. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider to be equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a low value and a high value is defined to include all numerical values ​​included in the numerical range and all subranges included in the numerical range.

[0077] It should be noted that, in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0078] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used in the present application can be interpreted accordingly.

[0079] The term "layer" as used in this application refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized area of ​​the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, a metal layer may include one or more metal sublayers, and may have the same or different materials.

[0080] It should be understood that the “surface” used in this application, such as “substrate plane”, “second surface”, etc., refers to the XY plane of the chip or substrate 100, etc., corresponding to the XY plane of the capacitor device, and the “thickness direction” of the device refers to the Z direction relative to the XY plane. The “thickness” or “height” mentioned in this application all refer to the Z-direction thickness or Z-direction height.

[0081] The following combination Figure 3-17 Introduce the capacitor device of the present application. It can be understood that the capacitor device in the drawings is only a technical solution of a specific embodiment of the present application, and the capacitor device of the present application may include fewer or more structural features, and is not limited to the device structure described in the drawings. Figure 3-5The capacitor device includes a substrate 100, a plurality of conductor layers and a dielectric layer 204, wherein the dielectric layer 204 is arranged between adjacent conductor layers in the plurality of conductor layers, and the plurality of conductor layers includes a bottom conductor layer 201 (CBM), at least one intermediate conductor layer 203 and a top conductor layer 202 (CTM) which are stacked in sequence from the substrate, wherein the bottom conductor layer 201 is located on the substrate 100, and the top conductor layer 202 is located on a side of the bottom conductor layer 201 away from the substrate 100 and is longitudinally separated from the bottom conductor layer 201; at least one intermediate conductor layer 203 is located between the top conductor layer 202 and the bottom conductor layer 201; and the dielectric layer 204 is located between adjacent bottom conductor layers 201 and intermediate conductor layers 203, between two adjacent intermediate conductor layers 203, and between adjacent intermediate conductor layers 203 and top conductor layers 202, so as to form a MIM capacitor structure on the substrate 100.

[0082] Specifically, the substrate 100 may be made of one or more of silicon, germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other semiconductor materials. In some embodiments, the substrate 100 may include a substrate 101, an etch stop layer 102 located on the substrate 101, and a substrate dielectric layer 103 (ILD layer) located on the etch stop layer 102; the material of the substrate 101 may be selected from one or more of silicon, germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other semiconductor materials; the etch stop layer 102 is formed of a material with good etching resistance and low residual rate, and may be specifically made of but not limited to silicon nitride (SiN x ), silicon oxide (SiO2), silicon oxynitride (SiON) and other materials; a lower metal layer 213 is also buried in the ILD layer to connect to the conductor layer formed on the substrate 100 as a source region and / or a drain region.

[0083] Specifically, the conductor layer forms the plate of the MIM capacitor structure, including the plates formed by the bottom conductor layer 201, the middle conductor layer 203 and the top conductor layer 202, respectively, which can be made of conductive metal materials, such as titanium (Ti), titanium nitride (TiN), titanium oxide (TiO), tantalum nitride (TaN), tantalum (Ta), copper (Cu), tungsten (W), tungsten alloy, aluminum (Al), platinum (Pt), nickel (Ni), aluminum alloy, copper-aluminum alloy, one or a combination of several, or other conductive metal materials. It can be understood that the materials of the bottom conductor layer 201, the middle conductor layer 203 and the top conductor layer 202 in the same capacitor device can be the same or different.

[0084] In some embodiments, the conductor layer may include a main metal layer and barrier layers (not shown) formed on both surfaces of the main metal layer, the barrier layer is used to block element diffusion and penetration, an anti-oxidation layer to protect the main metal layer, and an interlayer adhesion layer, etc.; it may be formed of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). The conductor layer may be formed by at least deposition, photolithography and etching processes, and the deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and other methods; the photolithography process may include but is not limited to photoresist coating, baking, masking, exposure, development, rinsing and drying, etc.; the etching process may include but is not limited to dry etching, wet etching and other etching methods.

[0085] Specifically, the material of the dielectric layer 204 is a high-k dielectric as an insulating layer between conductor layers, including one or a combination of hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxide nitride, ethyl silicate, glass material, halogenated silicon oxide; such as HfO, HfO2, AlO, Al2O3, ZrO, ZrO2, LaO, La2O3, SiO2, SiC, SiN, Si3N4, TaO2, Ta2O5, TaON, tetraethyl orthosilicate (TEOS), spin-on glass (SOG), halogenated silicon oxide, fluorinated silicate glass (FSG), etc., or other high-k dielectric materials. The dielectric layer 204 can be formed by at least a deposition process and other techniques. By using the above materials as the dielectric layer 204 between the plates, the capacitance density of the capacitor device can be effectively improved.

[0086] In some embodiments, the thickness of the bottom conductor layer 201 is 300A-800A, preferably 400A-600A; in some embodiments, the thickness of the intermediate conductor layer 203 is 300A-800A, preferably 400A-600A; in some embodiments, the thickness of the top conductor layer 202 is 300A-800A, preferably 400A-600A. It can be understood that in the same capacitor device, the thickness of the bottom conductor layer 201, the top conductor layer 202 and the intermediate conductor layer 203 can be the same or different. By setting the thickness of each conductor layer to the above range, the capacitance size and device volume requirements of the capacitor device can be compatible, optimizing device performance while avoiding material waste and excessive device volume.

[0087] Specifically, refer to Figure 3-5At least one of the intermediate conductor layers 203 has a step portion 205, and the step sidewall 205a of at least one of the step portions 205 is a transition surface extending toward the substrate 100 and inclined relative to the substrate plane. After the upper conductor layer covers the edge of the lower conductor layer, the step portion 205 is formed at the position of the upper conductor layer located at the edge, and a height difference is formed on both sides of the step portion 205 in the conductor layer having the step portion 205. By making the step sidewall 205a of the step portion 205 a transition surface extending in a gentle slope, the problem of forming a sharp angle structure at this place, which causes a large electric field and is not conducive to the deposition of the dielectric layer 204 and the conductor layer, is avoided, and the step portion 205 and the layers above the step portion 205 form a gentle slope with uniform thickness, which effectively reduces the local electric field at this place, improves the uniformity of the layer thickness and the uniformity of the electric field of the capacitor device, and improves the performance of the capacitor device. Preferably, the step sidewalls 205 a of the step portion 205 on each intermediate conductor layer 203 are transition surfaces extending toward the substrate 100 and inclined relative to the substrate plane, so as to further improve the performance of the capacitor device.

[0088] Preferably, the step sidewalls 205 a of the step portion 205 of each intermediate conductor layer 203 are transition surfaces extending toward the substrate 100 and inclined relative to the substrate plane, so as to maximize the performance of the capacitor device.

[0089] In the related art, reference Figure 1 and Figure 2 , Figure 1 A capacitor device provided by the prior art is shown in the figure, in which the second metal layer 1 on the substrate covers the edge of the first metal layer 3, and the second metal layer 1 forms a step portion with a sharp corner at the edge. The side wall of the step is almost perpendicular to the substrate plane and forms a corner structure that is almost a right angle. The electric field at the sharp corner of the edge of the first metal layer and the corner structure is higher than that at other positions of the metal layer, which has poor reliability and is not conducive to the deposition and etching of the upper dielectric layer 3 and the metal conductor layer, resulting in uneven electric field and material layer thickness. Reference Figure 2 In the MiM capacitor structure of four TiN layers shown in FIG, the edge of the TiN layer (square dotted frame) is almost vertical, and the other three TiN layers covering the bottom TiN layer all form a step portion (circular dotted frame) with a corner close to 90° at the corresponding position of the edge. By using the above technical solution of the present application, the local electric field is reduced through a simple transition surface design, and the deposition and etching difficulty of the conductor layer and the dielectric layer at the corner is reduced, and the problems of excessive local electric field and uneven layered materials caused by the right-angle step are avoided, thereby effectively improving the performance of the capacitor device.

[0090] As described above, the step portion 205 is formed at a position on the current conductor layer corresponding to the edge of the other conductor layer below. In some embodiments, the edge sidewall of at least one of the intermediate conductor layers 203 and the bottom conductor layer 201 and the surface adjacent to the edge sidewall are corner structures 206, and the surface adjacent to the edge sidewall refers to the surface of the conductor layer below or the substrate 100 adjacent to the edge; Figure 3 Taking the bottom conductor layer 201 as an example, the edge sidewall of the bottom conductor layer 201 forms a corner structure 206 with the surface of the substrate 100, and the corner structure 206 is similar to 90 degrees. Correspondingly, the dielectric layer 204 covering the corner structure 206 has a conductor filling body 207 that can at least partially fill the corner structure 206, and the surface of the conductor filling body 207 that is away from the dielectric layer 204 where it is located is a transition surface extending toward the substrate 100 and inclined relative to the substrate plane; the intermediate conductor layer 203 and / or the dielectric layer 204 located above the conductor filling body 207 has the above-mentioned step portion 205, and the step sidewall 205a is contoured with the surface of the conductor filling body 207.

[0091] Preferably, reference Figure 4 The conductor filling structure is formed at the corner structures 206 on both sides of the same conductor layer to optimize the overall structure of the conductor layer and the dielectric layer 204 .

[0092] Preferably, reference Figure 3-5 The dielectric layer 204 covering the corner structure 206 of the bottom conductor layer 201 has a conductor filling body 207 that can at least partially fill the corner structure 206, so as to form a step portion 205 with a transition gentle slope from the first intermediate conductor layer 203 above the bottom conductor layer 201, thereby improving the overall performance of the capacitor device.

[0093] It can be understood that a dielectric layer 204 is formed on the bottom conductor layer 201 or the intermediate conductor layer 203 having a corner structure 206 to serve as an insulating layer between adjacent conductor layers to form a plate capacitor structure. The dielectric layer 204 formed by deposition and other processes has a cross-sectional structure that is contoured to the conductor layer in which it is located, that is, a contoured corner is formed at the position of the corner structure 206 of the conductor layer, and a conductor filling body 207 is formed and filled at the corner position, preferably covering the side wall and part of the bottom wall at the corner position, and the surface used to contact the next conductor layer is a transition surface. By forming the conductor filling structure, the corner structure 206 that was originally close to a right angle is filled into a gentle slope structure, which is used as a deposition template for subsequent conductor layers and dielectric layers, so that the subsequently formed conductor layer and dielectric layer 204 form a step sidewall 205a and a step portion 205 that imitates the conductor filling body 207 at the position corresponding to the conductor filling body 207, and the surface away from the conductor filling body 207 is also a transition surface, so that the corner shape of subsequent layers can be changed through a single-layer simple corner filling setting, thereby improving the electric field uniformity and layer thickness uniformity of the capacitor device. In some embodiments, the conductor filling body 207 is formed by etching back the deposited conductor sacrificial layer 301.

[0094] In some embodiments, the cross-sectional shape of the conductor filling structure is a triangle or an arc-shaped triangle, and one corner of the triangle or the arc-shaped triangle matches the corner of the corner structure 206. Specifically, the arc-shaped side of the arc-shaped triangle can be an arc-shaped concave toward the triangle vertex or an arc-shaped convex away from the triangle vertex, and the corresponding transition surface is a curved surface. In this way, the conductor layer is shaped by the conductor filling structure of the above shape, which is easy to form and has excellent shaping effect.

[0095] Specifically, the arc-shaped side of the arc-shaped triangle is preferably an arc-shaped arc that is concave toward the apex of the triangle, so that the contact positions of the conductor filling body 207 and its two adjacent planes form a good transition.

[0096] In some embodiments, the material of the intermediate conductor layer 203 adjacent to the conductor filling body 207 is the same as that of the conductor filling body 207; after the conductor filling body 207 is formed, the intermediate conductor layer 203 is formed thereon, and the conductor materials used in the two are the same to ensure the performance uniformity of the single-layer capacitor plate.

[0097] In some other embodiments, reference Figure 5, the edge of at least one of each intermediate conductor layer 203 and the bottom conductor layer 201 is a transition structure 208, the surface of the transition structure 208 is a transition surface extending toward the substrate 100 and inclined relative to the substrate plane; the dielectric layer 204 and / or the intermediate conductor layer 203 located above the transition structure 208 has a step portion 205, and the step sidewall 205a is contoured with the surface of the transition structure 208. Specifically, the conductor layer with the edge of the transition structure 208 is directly formed to serve as a template for forming the subsequent dielectric layer 204 and the conductor layer, so that the edge and each step portion 205 formed thereon are all gentle slope structures with a transition surface, which is conducive to the uniform formation of each dielectric layer 204 and the conductor layer and avoids excessive local electric field.

[0098] Preferably, reference Figure 5 The edge of the bottom conductor layer 201 is a transition structure 208, so that a step portion 205 with a transition gentle slope is formed from the first dielectric layer 204 and the first intermediate conductor layer 203 above the bottom conductor layer 201, thereby improving the overall performance of the capacitor device.

[0099] In some embodiments, the angle between the above-mentioned transition surface and the substrate plane is 50°-80°. It can be understood that the lower limit of the angle can be 50°, 51°, 53°, 55°, 57°, etc., and the upper limit of the angle can be 80°, 78°, 75°, 73°, 70°, etc. The angle value can also be any value within the above range, which is not enumerated here. Preferably, the angle between the transition surface and the substrate plane is 50°-70°. By setting the angle value between the transition surface and the substrate plane in the above range, the electric field uniformity optimization effect of the capacitor device is further ensured and it is helpful to reduce the difficulty of its formation.

[0100] Based on some or all of the above implementations, in the embodiments of this application, reference Figure 3-5 The capacitor device further includes a first interconnect structure 209 and a second interconnect structure 210; a portion of the top conductor layer 202, each intermediate conductor layer 203 and the bottom conductor layer 201 are odd-numbered conductor layers in sequence, and another portion are even-numbered conductor layers in sequence; one of the first interconnect structure 209 and the second interconnect structure 210 is electrically connected to the odd-numbered conductor layers in the multi-layer conductor layers, and the other is electrically connected to the even-numbered conductor layers in the multi-layer conductor layers, so as to be used for connecting the two-pole power supply of the capacitor device.

[0101] Specifically, the conductor layers are arranged from top to bottom or from bottom to top on the substrate 100, and the odd-numbered layers are odd-numbered conductor layers, and the even-numbered layers are even-numbered conductor layers. It can be understood that Figure 3-5The first interconnect structure 209 and the second interconnect structure 210 are only schematic structures. In actual applications, the first interconnect structure 209 and the second interconnect structure 210 can be structures that penetrate all odd-numbered conductor layers or even-numbered conductor layers, or the first interconnect structure 209 and the second interconnect structure 210 can respectively include a plurality of interconnect substructures formed between adjacent odd-numbered conductor layers or a plurality of interconnect substructures formed between adjacent even-numbered conductor layers for electrical connection between layers. It can be understood that the first interconnect structure 209 and the second interconnect structure 210 penetrate the dielectric layer 204.

[0102] The first interconnect structure 209 and the second interconnect structure 210 are made of conductive materials, such as, but not limited to, copper, titanium, tungsten, aluminum, gold, nickel, tantalum, titanium nitride, tantalum nitride, etc., or other alternative conductive materials. Specifically, through holes arranged at intervals can be formed in the dielectric layer 204, and the first interconnect structure 209 or the second interconnect structure 210 is formed in the through holes by metal filling.

[0103] Based on some or all of the above implementations, in the embodiments of this application, reference Figure 3-5 The capacitor device also includes an upper metal layer 212 and a lower metal layer 213. The upper metal layer 212 is located on the side of the top conductor layer 202 away from the substrate 100 and is spaced apart from the top conductor layer 202. The upper metal layer 212 is electrically connected to the first interconnect structure 209 and the second interconnect structure 210 respectively; the lower metal layer 213 is located in the substrate 100, and the lower metal layer 213 is electrically connected to the first interconnect structure 209 and the second interconnect structure 210 respectively, thereby realizing the external connection of the capacitor device.

[0104] Specifically, the upper metal layer 212 is formed above the top conductor layer 202 and is electrically connected to the first interconnect structure 209 and the second interconnect structure 210. The material of the upper metal layer 212 may be, but not limited to, a combination of one or more of copper, titanium, tungsten, aluminum, gold, nickel, tantalum, titanium nitride, and tantalum nitride. The lower metal layer 213 is buried in the base 101 of the substrate 100. The material of the lower metal layer 213 may be, but not limited to, a combination of one or more of copper, titanium, tungsten, aluminum, gold, nickel, tantalum, titanium nitride, and tantalum nitride.

[0105] In some embodiments, reference Figure 3-5The capacitor device further includes a dummy structure 211, and the dummy structure 211 is disposed on the side of at least one of the top conductor layer 202, each intermediate conductor layer 203, and the bottom conductor layer 201 and is laterally separated from the dummy structure 211; the dummy structure 211 is connected to at least one of the first interconnection structure 209 and the second interconnection structure 210. In this way, the preparation of the conductor layer and the filling of the vacant area are balanced by the dummy structure 211, and it is beneficial to the formation, electrical connection, and structural stability of the first interconnection structure 209 and the second interconnection structure 210.

[0106] Specifically, the dummy structure 211 is a semiconductor element or structure without function in the capacitor device, including the same conductor material as the conductor layer of the same layer, and may include but is not limited to a combination of one or more of copper, titanium, tungsten, aluminum, gold, nickel, tantalum, titanium nitride and tantalum nitride. The conductive layer and the dummy structure 211 of the same layer may be formed by the same deposition process, and patterned etching is performed after deposition to obtain the conductive layer and the dummy structure 211. It should be noted that the same layer here refers to the material body formed in the same step of the preparation process.

[0107] Specifically, refer to Figure 3-5 The capacitor device also includes a top packaging layer 214 formed above the top conductor layer 202 for packaging the capacitor device. The upper metal layer 212 is formed on a side of the top packaging layer 214 away from the top conductor layer 202. The first interconnect structure 209 and the second interconnect structure 210 extend from the upper metal layer 212 and penetrate the top packaging layer 214, and are connected to the top conductor layer 202.

[0108] The following combination Figure 5-17 The method for forming a capacitor device provided in an embodiment of the present application is introduced. This specification provides method operation steps such as an embodiment or a flow chart, but more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiment is only one way of executing the order of many steps and does not represent the only execution order. When the preparation method is actually executed, it can be executed in the order of the method shown in the embodiment or the accompanying drawings or in parallel. The method for forming a capacitor device may include S1-S2:

[0109] S1, providing a substrate 100;

[0110] S2, forming a plurality of conductor layers on the substrate 100, the plurality of conductor layers comprising a bottom conductor layer 201, at least one intermediate conductor layer 203 and a top conductor layer 201 which are stacked in sequence, and forming a dielectric layer 204 between adjacent bottom conductor layers 201 and intermediate conductor layers 203, between two adjacent intermediate conductor layers 203, and between adjacent intermediate conductor layers 203 and top conductor layers 202; at least one of each intermediate conductor layer 203 has a step portion 205, and a step side wall 205a of at least one of each step portion 205 is a transition surface extending toward the substrate 100 and inclined relative to the substrate plane.

[0111] Specifically, the conductor layer can be formed at least by deposition, photolithography and etching processes, and the deposition process can include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and other methods; the photolithography process can include but is not limited to photoresist coating, baking, masking, exposure, development, rinsing and drying methods; the etching process can include but is not limited to dry etching, wet etching and other etching methods. The conductor layer can include a main metal layer and a barrier layer formed on both surfaces of the main metal layer, the barrier layer is used to block element diffusion and penetration, an anti-oxidation layer to protect the main metal layer, and an interlayer adhesion layer; the barrier layer can be formed of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). The dielectric layer 204 can be formed at least by deposition processes and other technologies.

[0112] In some embodiments, reference Figure 7 and Fig.11 The edge sidewall of at least one of the intermediate conductor layers 203 and the bottom conductor layer 201 and the surface adjacent to the edge sidewall form a corner structure 206; a dielectric layer is formed on the bottom conductor layer 201 or the intermediate conductor layer 203 having the corner structure 206, and accordingly, the bottom conductor layer 201 and the reference conductor layer 201 are formed. Figure 7-10 , the process of the intermediate conductor layer 203 and the dielectric layer 204 may include S21a-S23a:

[0113] S21a , after forming a dielectric layer 204 covering the corner structure 206 on the bottom conductive layer 201 and / or the middle conductive layer 203 having the corner structure 206 , a conductor sacrificial layer 301 covering the corner structure 206 is formed on the dielectric layer 204 .

[0114] Specifically, the conductor sacrificial layer 301 can be formed by a process including deposition, and its formation method can be the same as that of the conductor layer. The material of the conductor sacrificial layer 301 can be titanium (Ti), titanium nitride (TiN), titanium oxide (TiO), tantalum nitride (TaN), tantalum (Ta), copper (Cu), tungsten (W), tungsten alloy, aluminum (Al), platinum (Pt), nickel (Ni), aluminum alloy, copper-aluminum alloy, one or a combination of several, or other alternative conductive materials. Preferably, the thickness of the formed conductor layer can be greater than or equal to the intermediate conductor layer 203 or the bottom conductor layer 201 it covers, so as to fill the corner structure 206 well.

[0115] S22a, etching the conductor sacrificial layer 301 to form a conductor filling body 207 on the dielectric layer 204 that at least partially fills the corner structure 206, wherein the surface of the conductor filling body 207 that faces away from the dielectric layer 204 is a transition surface that extends toward the substrate 100 and is inclined relative to the substrate plane.

[0116] Specifically, the conductor sacrificial layer 301 is etched to remove the sacrificial layer area on the flat surface, and due to the obstruction of the edge sidewall of the conductor layer, the sacrificial layer area at the corner structure 206 is not easily etched and the etching speed is slow. During the back-etching process, a surface structure with a gently sloped transition surface is naturally formed, which is retained and forms a conductor filling body 207. The etching method here can adopt a process such as dry etching or wet etching. Preferably, the conductor filling body 207 is formed by isotropic back etching to form a conductor filling body 207 with an arc surface, thereby removing the sharp corner structure to form a continuous and smooth layered interface, further optimizing the thickness uniformity and surface smoothness of the subsequently formed conductor layer and dielectric layer 204, and significantly improving the performance of the capacitor device.

[0117] S23a, an intermediate conductor layer 203 and a dielectric layer 204 are formed on the dielectric layer 204 having the conductor filling body 207, and a step portion 205 is formed in the area covering the conductor filling body 207 on the intermediate conductor layer 203 and the dielectric layer 204, and the step side wall 205a is contoured to the surface of the conductor filling body 207.

[0118] Specifically, after forming the conductor filling body 207, an intermediate conductor layer 203 and a dielectric layer 204 covering the conductor filling body 207 and at least a portion of the conductor layer region are sequentially formed thereon. It can be understood that the intermediate conductor layer 203 and the dielectric layer 204 formed by the deposition process form a contoured step portion 205 above the smoothly transitioned conductor filling body 207, so that its step sidewall 205a is a transition surface contoured with the surface of the conductor filling body 207. In this way, the sacrificial layer is etched by the etching process to naturally form the conductor filling body 207, the process is simple and the formation difficulty is low, which is conducive to batch device preparation and application.

[0119] In some other embodiments, the process of forming the bottom conductor layer 201, the middle conductor layer 203 and the dielectric layer 204 includes S21b-S22b:

[0120] S21b, at least one edge of each intermediate conductor layer 203 and the bottom conductor layer 201 formed on the substrate 100 is a transition structure 208, and the surface of the transition structure 208 is a transition surface extending toward the substrate 100 and inclined relative to the substrate plane;

[0121] S22b, a dielectric layer 204 and / or an intermediate conductor layer 203 is formed on the bottom conductor layer 201 and / or the intermediate conductor layer 203 having the transition structure 208, and a step portion 205 is formed in the area of ​​the dielectric layer 204 and / or the intermediate conductor layer 203 covering the transition structure 208, and the step side wall 205a is contoured with the surface of the transition structure 208.

[0122] Specifically, the edge of the conductor layer can be directly formed into a transition structure 208 with a transition surface. Preferably, the transition structure 208 is formed at the edge of the bottom conductor layer 201 so that each dielectric layer 204 and conductor layer has a smooth and continuous surface to improve the reliability of each layer of capacitance.

[0123] Based on some or all of the above embodiments, in some embodiments, the sides of the bottom conductor layer 201, the middle conductor layer 203 or the top conductor layer 202 may have dummy structures 211 separated laterally, as shown in FIG. Fig.14 The dummy structure 211 is formed by dividing the conductor material layer into the dummy structure 211 and the conductor layer through graphic etching after the conductor material layer is deposited.

[0124] After forming the top conductor layer 202, refer to Fig.15 The forming method further includes S3: forming a top packaging layer 214 on the top conductor layer 202 to cover the capacitor structure.

[0125] Based on some or all of the above embodiments, in some embodiments, reference Fig.16 The formation method further includes S4: forming a first interconnect structure 209 and a second interconnect structure 210 extending longitudinally; part of the top conductor layer 202, each intermediate conductor layer 203 and the bottom conductor layer 201 are odd-numbered conductor layers in the order, and the other part is an even-numbered conductor layer in the order, one of the first interconnect structure 209 and the second interconnect structure 210 is electrically connected to the odd-numbered conductor layers in the multi-layer conductor layers, and the other is electrically connected to the even-numbered conductor layers in the multi-layer conductor layers.

[0126] Specifically, a first through hole extending downward through each odd-numbered conductor layer is formed from the top packaging layer 214, and a second through hole extending downward through each even-numbered conductor layer is formed from the top packaging layer 214; conductive material is filled in the first through hole and the second through hole to form a first interconnect structure 209 and a second interconnect structure 210.

[0127] In some embodiments, reference Fig.17 , a lower metal layer 213 is buried in the substrate 100, the first interconnection structure 209 and the second interconnection structure 210 respectively extend longitudinally to the lower metal layer 213 and are electrically connected to the lower metal layer 213; the formation method also includes: forming an upper metal layer 212 spaced from the top conductor layer 202 on a side of the top conductor layer 202 away from the substrate 100, and the upper metal layer 212 is respectively electrically connected to the first interconnection structure 209 and the second interconnection structure 210. Specifically, the formation process of the upper metal layer 212 may at least include processes such as deposition and patterned etching.

[0128] Preferably, the conductor filling structure is formed on the dielectric layer 204 on the bottom conductor layer 201. For example, referring to Figure 6-17 The process of forming the bottom conductor layer 201, the middle conductor layer 203 and the dielectric layer 204 may include: 1) forming the bottom conductor layer 201 on the substrate 100 (refer to Figure 6 ), the edge of the bottom conductor layer 201 and the substrate surface form a corner structure 206, and a lower metal layer 213 is buried in the substrate 100; 2) forming a first dielectric layer 204 on the bottom conductor layer 201 (reference Figure 7 ); 3) forming a conductor sacrificial layer 301 on the first dielectric layer 204 (reference Figure 8 ); 4) forming a conductor filling body 207 by isotropic back etching, the conductor filling body 207 fills the corner structure 206 of the first dielectric layer 204 (reference Fig. 9 5) forming an intermediate conductor layer 203 on the first dielectric layer 204 and the conductor filling layer, and forming a step portion 205 with a step sidewall 205a as a transition surface at a position corresponding to the corner structure 206 on the intermediate conductor layer 203 (reference Fig.10 ); 6) patterning and etching the intermediate conductor layer 203 to remove a portion of the area to expose a portion of the bottom conductor layer 201 and the first dielectric layer 204 (reference Fig.11 ), the edge of the intermediate dielectric layer 204 and the surface of the first intermediate layer form another corner structure 206; 7) forming a second dielectric layer 204 on the intermediate dielectric layer, the second dielectric layer 204 covering the intermediate conductor layer 203 and the exposed portion of the first dielectric layer 204 (refer to Fig.12); 8) forming a conductor filling body 207 filling the corner structure 206 at the edge of the second dielectric layer 204 located at the intermediate dielectric layer 204, the formation method is consistent with the aforementioned steps 3) and 4) (reference Fig.13 ); 9) forming a top conductor layer 202 and a dummy structure 211 on the second dielectric layer 204 by metal deposition and patterning etching, the top conductor layer 202 covers the step portion 205 of the intermediate conductor layer 203 and the conductor filling body 207 thereon, and forming a step portion 205 at a position on the top metal layer corresponding to the step portion 205 and the conductor filling body 207, and the side walls of the two step portions 205 are transition surfaces (reference Fig.14 ); 10) forming a top encapsulation layer 214 on the top conductor layer 202 (reference Fig.15 ) 11) forming a first interconnect structure 209 extending downward from the top packaging layer 214 to penetrate and connect the dummy structure 211, the intermediate conductor layer 203 and the lower metal layer 213, and forming a second interconnect structure 210 extending downward from the top packaging layer 214 to penetrate and connect the top conductor layer 202, the bottom conductor layer 201 and the lower metal layer 213 (reference Fig.16 ) 12) forming an upper metal layer 212 electrically connected to the first interconnect structure 209 and the second interconnect structure 210 above the top packaging layer 214 (reference Fig.17 ), and obtain a capacitor device.

[0129] It can be understood that the above-mentioned capacitor device embodiment and the capacitor device forming method embodiment are based on the same application concept, and the capacitor device can be manufactured by using the above-mentioned capacitor device forming method.

[0130] On the other hand, the present application provides a capacitor, which includes the above-mentioned capacitor device.

[0131] On the other hand, the present application provides an integrated circuit, which includes the above-mentioned capacitor device.

[0132] On the other hand, the present application provides an electronic device, which includes the above-mentioned capacitor device. The electronic device may include any electronic components such as an integrated circuit, an electronic device, etc. Since the working performance of the capacitor device is better, the performance of the electronic device is correspondingly improved.

[0133] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product of an electronic device made of the above-mentioned capacitor device.

[0134] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0135] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A capacitor device, characterized in that: The capacitor device comprises: substrate; A multi-layer conductor layer located on the substrate, the multi-layer conductor layer comprising a bottom conductor layer, at least one intermediate conductor layer and a top conductor layer stacked in sequence from the substrate; A dielectric layer, located between the adjacent bottom conductor layer and the intermediate conductor layer, between two adjacent intermediate conductor layers, and between the adjacent intermediate conductor layer and the top conductor layer; At least one of the intermediate conductor layers has a step portion, and a step sidewall of at least one of the step portions is a transition surface extending toward the substrate and inclined relative to a substrate plane.

2. The capacitive device according to claim 1, characterized in that: The edge sidewall of at least one of the intermediate conductor layers and the bottom conductor layer and the surface adjacent to the edge sidewall are in a corner structure; A conductor filling body capable of at least partially filling the corner structure is provided on the dielectric layer covering the corner structure, wherein the surface of the conductor filling body facing away from the dielectric layer where the conductor filling body is located is a transition surface extending toward the substrate and inclined relative to the substrate plane; The intermediate conductor layer and / or the dielectric layer located above the conductor filling body has the step portion, and the side wall of the step conforms to the surface of the conductor filling body.

3. The capacitive device according to claim 2, characterized in that: The conductor filling body satisfies at least one of the following characteristics: The cross section of the conductor filling body is a triangle or an arc-shaped triangle; The material of the intermediate conductor layer adjacent to the conductor filling body is the same as that of the conductor filling body.

4. The capacitive device according to claim 1, characterized in that: The edge of at least one of the intermediate conductor layers and the bottom conductor layer is a transition structure, and the surface of the transition structure is a transition surface extending toward the substrate and inclined relative to the substrate plane; The dielectric layer and / or the intermediate conductor layer located above the transition structure has the step portion, and the side wall of the step conforms to the surface of the transition structure.

5. The capacitive device according to any one of claims 1 to 4, characterized in that: The angle between the transition surface and the base plane is 50°-80°.

6. The capacitive device according to any one of claims 1 to 4, characterized in that: The capacitor device satisfies at least one of the following characteristics: The thickness of the bottom conductor layer is 300A-800A; The thickness of the intermediate conductor layer is 300A-800A; The thickness of the top conductor layer is 300A-800A.

7. The capacitive device according to any one of claims 1 to 4, characterized in that: The capacitor device satisfies at least one of the following characteristics: The material of the bottom conductor layer includes one or a combination of titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum, copper, tungsten, tungsten alloy, aluminum, platinum, nickel, aluminum alloy, copper-aluminum alloy; The material of the intermediate conductor layer includes one or a combination of titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum, copper, tungsten, tungsten alloy, aluminum, platinum, nickel, aluminum alloy, copper-aluminum alloy; The material of the top conductor layer includes one or a combination of titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum, copper, tungsten, tungsten alloy, aluminum, platinum, nickel, aluminum alloy, copper-aluminum alloy; The material of the dielectric layer includes one or a combination of hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, silicon oxide, silicon nitride, tantalum oxide, tantalum oxynitride, ethyl silicate, glass material, and halogenated silicon oxide.

8. The capacitive device according to any one of claims 1 to 4, characterized in that: The capacitive device further includes a first interconnect structure and a second interconnect structure; One of the first interconnect structure and the second interconnect structure is electrically connected to odd-numbered conductor layers among the multi-layer conductor layers, and the other is electrically connected to even-numbered conductor layers among the multi-layer conductor layers.

9. The capacitive device according to claim 8, characterized in that: The capacitor device further comprises a dummy structure, the dummy structure being disposed on the side of at least one of the top conductor layer, each of the intermediate conductor layers and the bottom conductor layer and being laterally spaced from the dummy structure; The dummy structure is connected to at least one of the first interconnect structure and the second interconnect structure.

10. The capacitive device according to claim 8, characterized in that: The capacitor device further comprises: an upper metal layer, located on a side of the top conductor layer away from the substrate and spaced apart from the top conductor layer, the upper metal layer being electrically connected to the first interconnect structure and the second interconnect structure respectively; A lower metal layer is located in the substrate, and the lower metal layer is electrically connected to the first interconnect structure and the second interconnect structure respectively.

11. A method for forming a capacitor device, characterized in that: The forming method comprises: Providing a substrate, forming a plurality of conductor layers on the substrate, the plurality of conductor layers comprising a bottom conductor layer, at least one intermediate conductor layer and a top conductor layer stacked in sequence, and forming a dielectric layer between adjacent bottom conductor layers and intermediate conductor layers, between two adjacent intermediate conductor layers, and between adjacent intermediate conductor layers and the top conductor layer; At least one of the intermediate conductor layers has a step portion, and a step sidewall of at least one of the step portions is a transition surface extending toward the substrate and inclined relative to a substrate plane.

12. The forming method according to claim 11, characterized in that: The edge sidewall of at least one of the intermediate conductor layer and the bottom conductor layer and the surface adjacent to the edge sidewall are in a corner structure; the process of forming the bottom conductor layer, the intermediate conductor layer and the dielectric layer includes: After forming a dielectric layer covering the corner structure on the bottom conductor layer and / or the middle conductor layer having the corner structure, forming a conductor sacrificial layer covering the corner structure on the dielectric layer; Etching the conductor sacrificial layer to form a conductor filling body on the dielectric layer that at least partially fills the corner structure, wherein a surface of the conductor filling body that is away from the dielectric layer where the conductor filling body is located is a transition surface that extends toward the substrate and is inclined relative to the substrate plane; The intermediate conductor layer and the dielectric layer are formed on the dielectric layer having the conductor filling body, and the step portion is formed in the region of the intermediate conductor layer and the dielectric layer covering the conductor filling body, and the step sidewall conforms to the surface of the conductor filling body.

13. The forming method according to claim 12, characterized in that: The conductor filling body is formed by isotropic back etching.

14. The forming method according to claim 11, characterized in that: The process of forming the bottom conductor layer, the middle conductor layer and the dielectric layer includes: The edge of at least one of the intermediate conductor layers and the bottom conductor layer formed on the substrate is a transition structure, and the surface of the transition structure is a transition surface extending toward the substrate and inclined relative to the substrate plane; The dielectric layer and / or the intermediate conductor layer are formed on the bottom conductor layer and / or the intermediate conductor layer having the transition structure, and the step portion is formed in the area of ​​the dielectric layer and / or the intermediate conductor layer covering the transition structure, and the step sidewall is contoured to the surface of the transition structure.

15. The forming method according to any one of claims 11 to 14, characterized in that: The forming method further comprises: forming longitudinally extending first and second interconnect structures; One of the first interconnect structure and the second interconnect structure is electrically connected to odd-numbered conductor layers among the multi-layer conductor layers, and the other is electrically connected to even-numbered conductor layers among the multi-layer conductor layers.

16. The forming method according to claim 15, characterized in that: A lower metal layer is embedded in the substrate, and the first interconnect structure and the second interconnect structure respectively extend longitudinally to the lower metal layer and are electrically connected to the lower metal layer; The forming method further includes: forming an upper metal layer spaced apart from the top conductor layer on a side of the top conductor layer away from the substrate, wherein the upper metal layer is electrically connected to the first interconnect structure and the second interconnect structure respectively.

17. An electronic device, characterized in that: The electronic device comprises the capacitive device according to any one of claims 1 to 10.

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