In situ carbon liners for high aspect ratio features

Abstract

An exemplary method of semiconductor processing may include etching a first portion of a feature in a substrate disposed within a processing region of a semiconductor processing chamber. The first portion of the feature may extend at least partially through one or more layers of material formed on the substrate. The method may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. The method may include generating a plasma effluent comprising a carbon precursor. The method may include contacting a substrate with a plasma effluent of a carbon-containing precursor. The method may include forming a carbon-containing material on a substrate. The carbonaceous material may be lined with a first portion of a feature extending at least partially through one or more layers of material formed on the substrate. The carbonaceous material may be formed in the same chamber of the etched features.

Description

Technical Field

[0001] This application claims the benefit of and priority to U.S. Patent Application No. 17 / 949,083, filed on September 20, 2022, entitled “IN-SITU CARBON LINER FOR HIGHASPECT RATIO FEATURES,” the entire contents of which are incorporated herein by reference.

[0002] The present technology relates to semiconductor processes and materials. More particularly, the present technology relates to forming a protective layer during processing to etch through a stack of material layers. Background Art

[0003] Integrated circuits are made possible by processes that produce complex patterned material layers on a substrate surface. Producing patterned materials on a substrate requires controlled methods of forming and removing exposed materials. Stacked memories (such as vertical or 3D NAND) may include forming a series of alternating dielectric material layers through which multiple memory holes or pores may be etched. The material properties of the material layers, as well as the process conditions and materials used for etching, may affect the uniformity of the formed structure. Resistance to etchants may result in inconsistent patterning, which may further affect the uniformity of the formed structure.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality components and structures. The present technology addresses these and other needs. Summary of the invention

[0005] Exemplary methods of semiconductor processing may include etching a first portion of a feature in a substrate disposed within a processing region of a semiconductor processing chamber. The first portion of the feature may extend at least partially through one or more material layers formed on the substrate. The methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma effluent of the carbon-containing precursor. The methods may include contacting the substrate with the plasma effluent of the carbon-containing precursor. The methods may include forming a carbon-containing material on the substrate. The carbon-containing material may line the first portion of the feature that extends at least partially through one or more material layers formed on the substrate. The carbon-containing material may be formed in the same chamber in which the feature is etched.

[0006] In some embodiments, the feature is characterized by an aspect ratio greater than or about 10:1. Forming one or more material layers on the substrate may include alternating layers of oxide material and nitride material. The methods may include, after etching a first portion of the feature in the substrate, providing an oxygen-containing precursor. The methods may include contacting the substrate with the oxygen-containing precursor. The contacting may remove etchant byproducts in or above the feature. The methods may include generating a plasma effluent of the oxygen-containing precursor. The carbon-containing precursor may be or include a fluorocarbon. The plasma effluent of the carbon-containing precursor may be generated at a plasma power of less than or about 2,000W. The methods may include applying a bias power while forming the carbon-containing material on the substrate. The bias power may direct the carbon-containing material to the etching front of the feature. The methods may include providing an oxygen-containing precursor and a carbon-containing precursor. The oxygen-containing precursor may be molecular oxygen. During the semiconductor processing method, the temperature in the processing region may be maintained at less than or about 150°C. During the semiconductor processing method, the pressure in the processing region may be maintained at less than or about 500mTorr.

[0007] Some embodiments of the present technology include semiconductor processing methods. The methods may include i) providing one or more etchant precursors to a processing region of a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The methods may include ii) generating plasma effluents of the one or more etchant precursors. The methods may include iii) etching a first portion of a feature in a substrate disposed within the processing region. The first portion of the feature may extend at least partially through one or more material layers formed on the substrate. The methods may include iv) providing a flash precursor to a processing region of a semiconductor processing chamber. The methods may include v) removing etchant byproducts from the substrate. The methods may include vi) providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. The methods may include vii) generating plasma effluents of the carbon-containing precursor. The methods may include viii) forming a carbon-containing material on the substrate. The carbon-containing material may be lined with a first portion of a feature that extends at least partially through one or more material layers formed on the substrate. The methods may include ix) repeating operations i) to viii) for at least five cycles.

[0008] In some embodiments, the one or more etchant precursors may include an oxygen-containing precursor and a fluorine-containing precursor. The carbon-containing precursor may include a precursor containing carbon, hydrogen, and fluorine. The methods may include providing argon to the processing area while providing the flash precursor or providing the carbon-containing precursor. The critical dimension of the feature may be less than or about 550 nm. The methods may include pulsing plasma power during any of operations i) to viii), wherein the frequency of the plasma power is less than or about 500 Hz.

[0009] Some embodiments of the present technology encompass semiconductor processing methods. The methods may include etching a feature in a substrate disposed within a processing region of a semiconductor processing chamber. The feature may extend at least partially through one or more alternating material layers formed on the substrate. The methods may include providing a fluorocarbon precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma effluent of the fluorocarbon precursor. The plasma effluent of the fluorocarbon precursor may be generated at a plasma power of less than or about 1,500 W. The methods may include contacting the substrate with the plasma effluent of the fluorocarbon precursor. The methods may include forming a polymeric carbon-containing material on the substrate. The polymeric carbon-containing material may be lined with a feature that extends at least partially through one or more alternating material layers formed on the substrate.

[0010] In some embodiments, the substrate includes a mask material overlying one or more alternating material layers. The polymeric carbon-containing material may have a thickness of less than or about 30 nm. The feature may be characterized by an aspect ratio of greater than or about 40:1.

[0011] Such techniques may provide many benefits over conventional systems and techniques. For example, such processes and structures may protect against defect formation during etching operations. Additionally, operation of embodiments of the present technology may improve memory hole formation through the stack, thereby allowing more layer pairs to be etched during processing. These and other embodiments and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the accompanying drawings.

[0013] Figure 1 A schematic top view of an exemplary processing system according to some embodiments of the present technology is shown.

[0014] Figure 2 A schematic cross-sectional view of an exemplary processing system according to some embodiments of the present technology is shown.

[0015] Figure 3 Selected operations in a method of forming according to some embodiments of the present technology are shown.

[0016] Figures 4A to 4E Schematic cross-sectional views of substrate materials are shown upon which selected operations are performed in accordance with some embodiments of the present technology.

[0017] Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and are not to be considered to scale unless specifically stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include superfluous or exaggerated material for illustrative purposes.

[0018] In the drawings, similar components and / or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a letter that distinguishes between similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the letter. DETAILED DESCRIPTION

[0019] As the number of cells formed in 3D NAND structures increases, the aspect ratio of memory holes and other structures increases, sometimes dramatically. During 3D NAND processing, a stack of placeholder layers and dielectric materials can be formed first, and memory cells can be formed in these stacks. The placeholder layers can have a variety of operations performed to place the structure before the material is completely removed and replaced with metal. These layers are often formed to overlie a conductor layer, such as, for example, polysilicon. When memory holes are formed, the pores can extend through all alternating material layers before accessing the polysilicon or other material substrate. Subsequent processing can form a stepped structure for contacts, and the placeholder material can also be excavated laterally.

[0020] A reactive-ion etching ("RIE") operation may be performed to create the high aspect ratio memory holes. The RIE process often involves a combination of chemical and physical removal of the alternating layers. As a non-limiting example, where the alternating layers may include silicon oxide and silicon nitride, the silicon oxide may be removed to a greater extent by physically bombarding the layers during the RIE, and the silicon nitride may be removed to a greater extent by chemically reacting the RIE precursor with the nitride material.

[0021] Due to the material differences between the two layer types and the RIE process and materials, conventional techniques may have difficulty achieving uniformity and control during the formation of memory holes. In addition, the memory holes may extend outward during etching, resulting in a widening of the critical dimensions within the stacked layer structure through which RIE can be performed to produce memory holes. Bowing can occur anywhere throughout the structure and may be caused by many problems. For example, bowing may be caused by limited passivation on the sidewalls, which may allow a certain amount of lateral etching to occur. Bowing may also occur due to changes in hard mask materials or other structural features. For example, if the edge of the hard mask may become eroded during the RIE process, ions may be projected into the feature or memory hole at a direction or angle different from the normal to the substrate, which may produce additional lateral etching in some areas of the structure until the hard mask taper is removed or etched away.

[0022] To compensate for these problems, conventional techniques are limited in the number of layer-to-layer stacks that can be etched at any time. As the number of layers increases, many conventional techniques will produce the structure in two discrete cycles. For example, conventional techniques can produce a first set of layers and etch through the layers. The memory holes can be plugged and a second set of layers can be formed overlying the first set of layers. The second set of layers and the plugs in the first set can then be etched to completely form the structure. However, the hole alignment between the groups is rarely perfect and can result in offsets that can affect production and cell formation. In addition, by stopping formation between groups, material differences may develop due to different exposure and processing levels.

[0023] The present technology overcomes these problems by forming a liner layer of a carbonaceous material, which may be a polymeric material. Unlike conventional techniques, the present technology can allow for the formation of a complete set of layer pairs, which may include more than one hundred layers or more. The process can then split the etching operation into two parts, where a liner can be deposited on the initially etched material to limit over-etching when a second etching operation is performed to fully penetrate the stack of layers. This can inhibit lateral etching on the sidewalls and minimize any widening of the critical dimensions of the feature. Additionally, this can ensure that the etching operation is fully aligned through the stack of layers, while allowing for further scaling of the number of layer pairs that can be processed.

[0024] Although the remaining disclosure will routinely identify specific materials and semiconductor structures that utilize the disclosed techniques, it will be readily appreciated that such systems, methods, and materials are equally applicable to many other structures that can benefit from aspects of the present techniques. Therefore, the techniques should not be considered limited to use with only 3D NAND processes or materials. Furthermore, although an exemplary chamber is described to provide a basis for the present techniques, it should be appreciated that the present techniques can be applied to virtually any semiconductor processing chamber that can allow for the described operations.

[0025] Figure 1 1 illustrates a top view of one embodiment of a processing system 10 having deposition, etching, baking and / or curing chambers according to an embodiment. Figure 1 The tool or processing system 10 depicted in the drawings may house a plurality of processing chambers 24a to 24d, a transfer chamber 20, a maintenance chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a to 16b. The processing chamber may include any number of structures or components, and any number of processing chambers or combinations of processing chambers.

[0026] To transfer substrates between chambers, the transfer chamber 20 may house a robotic transfer mechanism 22. The transfer mechanism 22 may have a pair of remote substrate transfer blades 22a, each attached to an extendable arm 22b. The blades 22a may be used to transport individual substrates to and from a processing chamber. In operation, one of the substrate transfer blades of the transfer mechanism 22 (such as blade 22a) may take a substrate W from one of the load lock chambers (such as chambers 16a to 16b) and transport the substrate W to a first processing stage, for example, a processing process as described below in chambers 24a to 24d. Such chambers may be included to perform individual or combined operations of the described technology. For example, while one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform the described pre-processing operations and / or one or more post-processing operations. The present technology encompasses any number of configurations, which may also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0027] If the chamber is occupied, the robot may wait until processing is complete, then remove the processed substrate from the chamber with one blade 22a and insert a new substrate with a second blade. Once the substrate is processed, it may be moved to a second processing stage. For each move, the transport mechanism 22 may typically have one blade to carry the substrate and one empty blade to perform the substrate exchange. The transport mechanism 22 may wait at each chamber until the exchange can be completed.

[0028] Once the processing in the processing chamber is completed, the transfer mechanism 22 can remove the substrate W from the last processing chamber and transfer the substrate W to the box in the load lock chamber 16a to 16b. The substrate can be moved from the load lock chamber 16a to 16b to the factory interface 12. The factory interface 12 is generally operable to transfer substrates between the pod loader 14a to 14d and the load lock chamber 16a to 16b in an atmospheric pressure clean environment. The clean environment in the factory interface 12 can generally be provided by an air filtration process (such as HEPA filtration). The factory interface 12 may also include a substrate orientator / aligner, which can be used to properly align the substrate before processing. At least one substrate robot, such as robots 18a to 18b, can be positioned in the factory interface 12 to transfer substrates between different positions / positions in the factory interface 12, and to transfer substrates to other positions connected thereto. Robots 18a to 18b can be configured to travel from a first end of the factory interface 12 to a second end along a track system in the factory interface 12.

[0029] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals that may provide adaptive control of any of the processes performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology equipment to measure various film properties such as thickness, roughness, composition, and the metrology equipment may further be capable of characterizing grating parameters such as critical dimension, sidewall angle, and feature height under vacuum in an automated manner.

[0030] Each of the processing chambers 24a to 24d can be configured to perform one or more process steps in the manufacture of semiconductor structures, and any number of processing chambers and combinations of processing chambers can be used on the multi-chamber processing system 10. For example, any of the processing chambers can be configured to perform a plurality of substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition; and other operations, including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that can be performed in any chamber or any combination of chambers can be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. As will be readily appreciated by those skilled in the art, any other process can be similarly performed in a specific chamber incorporated into the multi-chamber processing system 10, including any of the processes described below.

[0031] Figure 2A schematic cross-sectional view of an exemplary processing chamber 200 suitable for patterning a material layer disposed on a substrate 202 in the processing chamber 200 is shown. The exemplary processing chamber 200 is suitable for performing a patterning process, but it should be understood that aspects of the present technology can be performed in any number of chambers, and substrate supports according to the present technology can be included in an etching chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 200 may include a chamber body 205 that defines a chamber volume 201 in which a substrate can be processed. The chamber body 205 may have a sidewall 212 and a bottom 218 coupled to a ground 226. The sidewall 212 may have a liner 215 to protect the sidewall 212 and extend the time between maintenance cycles of the plasma processing chamber 200. The size of the chamber body 205 and related components of the plasma processing chamber 200 is not limited and can generally be proportionally larger than the size of the substrate 202 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, 450 mm diameter, etc., such as display or solar cell substrates.

[0032] The chamber body 205 may support a chamber lid assembly 210 to enclose the chamber volume 201. The chamber body 205 may be made of aluminum or other suitable materials. A substrate access port 213 may be formed through a sidewall 212 of the chamber body 205 to facilitate transfer of the substrate 202 into and out of the plasma processing chamber 200. As previously described, the access port 213 may be coupled to a transfer chamber and / or other chambers of a substrate processing system. A pumping port 245 may be formed through the sidewall 212 of the chamber body 205 and connected to the chamber volume 201. A pumping device may be coupled to the chamber volume 201 through the pumping port 245 to evacuate and control the pressure within the processing volume. The pumping device may include one or more pumps and a throttle valve.

[0033] The gas panel 260 may be coupled to the chamber body 205 via a gas line 267 to supply process gases into the chamber volume 201. The gas panel 260 may include one or more process gas sources 261, 262, 263, 264, and may additionally include inert gases, non-reactive gases, and reactive gases, such as may be used for any number of processes. Examples of process gases that may be provided by the gas panel 260 include, but are not limited to, hydrocarbon-containing gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon, chlorine, nitrogen, helium, or oxygen, as well as any number of additional materials. Additionally, the process gases may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as BCl 3 , C 2 F 4 , C 4 F 8 , C 4 F 6 , CHF3 , CH 2 F 2 , CH 3 F. NF 3 NH 3 , CO 2 、SO 2 ,CO,N 2 、NO 2 、N 2 O and H 2 , and any number of additional precursors.

[0034] The valve 266 can control the flow of the process gas from the sources 261, 262, 263, 264 of the gas panel 260 and can be managed by the controller 265. The gas flow supplied from the gas panel 260 to the chamber body 205 can include a combination of gases from one or more sources. The lid assembly 210 can include a nozzle 214. The nozzle 214 can be one or more ports for introducing the process gas from the sources 261, 262, 264, 263 of the gas panel 260 into the chamber volume 201. After the process gas is introduced into the plasma processing chamber 200, the gas can be excited to form a plasma. An antenna 248 (such as one or more inductive coils) can be disposed adjacent to the plasma processing chamber 200. The antenna power supply 242 can power the antenna 248 through the matching circuit 241 to inductively couple energy (such as RF energy) to the process gas to maintain a plasma formed by the process gas in the chamber volume 201 of the plasma processing chamber 200. As an alternative or in addition to the antenna power supply 242, processing electrodes below the substrate 202 and / or above the substrate 202 may be used to capacitively couple RF power to the process gas to maintain the plasma within the chamber volume 201. The operation of the power supply 242 may be controlled by a controller, such as the controller 265, which also controls the operation of other components in the plasma processing chamber 200.

[0035] A substrate support pedestal 235 may be disposed in the chamber volume 201 to support a substrate 202 during processing. The substrate support pedestal 235 may include an electrostatic chuck 222 for holding the substrate 202 during processing. The electrostatic chuck ("ESC") 222 may hold the substrate 202 to the substrate support pedestal 235 using an electrostatic attraction force. The ESC 222 may be powered by an RF power supply 225 integrated with a matching circuit 224. The ESC 222 may include an electrode 221 embedded within a dielectric body. The electrode 221 may be coupled to the RF power supply 225 and may provide a bias that attracts plasma ions formed from a process gas in the chamber volume 201 to the ESC 222 and the substrate 202 on the pedestal. The RF power supply 225 may be cycled on and off or pulsed during processing of the substrate 202. The ESC 222 may have an isolator 228 for making the sidewalls of the ESC 222 less attractive to the plasma to extend the maintenance life cycle of the ESC 222. In addition, the substrate support pedestal 235 may have a cathode liner 236 to protect the sidewalls of the substrate support pedestal 235 from the plasma gas and extend the time between maintenance of the plasma processing chamber 200.

[0036] The electrode 221 may be coupled to a power source 250. The power source 250 may provide a clamping voltage of about 200 volts to about 2000 volts to the electrode 221. The power source 250 may also include a system controller for controlling the operation of the electrode 221 by directing a DC current to the electrode 221 to clamp and unclamp the substrate 202. The ESC 222 may include a heater disposed within a pedestal and connected to a power source for heating the substrate, and a cooling base 229 supporting the ESC 222 may include a conduit for circulating a heat transfer fluid to maintain the temperature of the ESC 222 and the substrate 202 disposed thereon. The ESC 222 may be configured to perform within a temperature range required by a thermal budget of a component fabricated on the substrate 202. For example, the ESC 222 may be configured to maintain the substrate 202 at a temperature of about -150°C or less to about 500°C or more depending on the process being performed.

[0037] A cooling base 229 may be provided to help control the temperature of the substrate 202. To reduce process drift and time, the cooling base 229 may maintain the temperature of the substrate 202 substantially constant throughout the time that the substrate 202 is in the chamber. In some embodiments, the temperature of the substrate 202 may be maintained at a temperature between about -150°C and about 500°C throughout the subsequent process, but any temperature may be utilized. A cover ring 230 may be disposed on the ESC 222 and along the perimeter of the substrate support pedestal 235. The cover ring 230 may be configured to confine the etching gas to a desired portion of the exposed top surface of the substrate 202 while shielding the top surface of the substrate support pedestal 235 from the plasma environment inside the plasma processing chamber 200. Lift pins may selectively translate through the substrate support pedestal 235 to lift the substrate 202 above the substrate support pedestal 235 to facilitate access to the substrate 202 by a transfer robot or other suitable transfer mechanism, as previously described.

[0038] The controller 265 may be used to control the process sequence, regulate the gas flow from the gas panel 260 into the plasma processing chamber 200, and other process parameters. When executed by the CPU, the software routine converts the CPU into a special purpose computer, such as a controller, which can control the plasma processing chamber 200 so that processes are performed according to the present disclosure. The software routine may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 200.

[0039] As described above, the present technique can form a liner along the stack of layer pairs that can protect the overlying layers while etching proceeds through the lower layers to the substrate level. Figure 3 , which illustrates exemplary operations in a method 300 for forming a semiconductor structure according to an embodiment of the present technology. The method 300 may include one or more operations before the method begins, including front-end processing, deposition, etching, polishing, cleaning, or any other operation that may be performed before the operation. For example, the method may begin after multiple layer pairs have been deposited for the production of 3D NAND memory. However, as described above, it should be understood that the accompanying drawings illustrate only an exemplary process in which molecular layer deposition according to an embodiment of the present technology may be employed, and the description is not intended to limit the present technology to only this process. Some or all of the operations may be performed in a chamber or system tool as described above, or may be performed in different chambers on the same system tool, which may include a chamber in which the operations of method 300 may be performed.

[0040] Method 300 may include a number of optional operations as shown, which may or may not be particularly relevant to some embodiments of methods according to the present technology. For example, many of the operations are described to provide a broader range of structure formation, but are not critical to the technology or can be performed by alternative methods, as will be discussed further below. Method 300 describes Figures 4A to 4E The operations schematically shown in FIG. 300 will be described in conjunction with the operations of method 300. It should be understood that Figures 4A to 4E Only partial schematics are shown, and the substrate may include any number of structural sections having aspects as shown, as well as alternative structural aspects that may still benefit from operation of the present technology.

[0041] The method 300 may or may not involve optional operations to develop the semiconductor structure into a specific manufacturing operation. It should be understood that the method 300 can be performed on any number of semiconductor structures or substrates 405, such as Figure 4A As shown, the semiconductor structures or substrates include exemplary structures on which selectively deposited materials may be formed. Figure 4A As shown, substrate 405 may have multiple material layers deposited overlying the substrate. Substrate 405 may be any number of materials, such as a base wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed overlying the substrate during semiconductor processing.

[0042] Structure 400 may show a partial view of a stack of alternating material layers that may be used in 3D NAND memory formation in some embodiments. The alternating material layers may be produced by a variety of methods, including plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal enhanced chemical vapor deposition, or any other formation technique. In some embodiments, plasma enhanced chemical vapor deposition may be performed in a processing chamber, such as the previously described processing chamber 200. Although the remainder of the disclosure will discuss a stack of alternating layers of silicon oxide and silicon nitride, embodiments of the present technology may use different combinations of materials, such as silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials. Although method 300 will discuss forming silicon oxide followed by forming silicon nitride, the order of formation may be reversed in embodiments similarly encompassed by the present technology. Additionally, any number of material layers may be produced in any portion of a stack or any stack, and different portions of a stack may include more, less, or a similar number of layers to any other portion of the stack, according to embodiments of the present technology.

[0043] like Figure 4AAs shown, structure 400 includes a substrate 405 having a stack 410 of alternating layers of silicon oxide and silicon nitride. The stack 410 shown may include a plurality of portions 415, each of which may include at least one silicon oxide material layer 417 and at least one silicon nitride material layer 419. Each portion may also include a plurality of layer pairs, including more than or about 2 layer pairs, more than or about 10 layer pairs, more than or about 50 layer pairs, more than or about 100 layer pairs, or more layer pairs. Any specific number of pairs covered by any of the specified ranges is understood to be as if specifically provided herein. Although three portions 415a, 415b, and 415c are shown, some embodiments according to the present technology may include more or fewer portions.

[0044] In some embodiments, multiple portions, including all portions, may be formed during a single deposition sequence. As discussed above, this may avoid blocking and attempting to align memory holes between groups. Additionally, in some embodiments, the portions may be produced in multiple operations. Mask material 420 may be formed over any portion of the stack before forming a portion of a memory hole or other feature (such as a recess or slit) through the structure. A structure according to the present technology may be characterized by any aspect ratio or height ratio of the structure, but in some embodiments, the material may be characterized by a larger aspect ratio that may increase the impact on various aspects of the structure produced as previously described. For example, in some embodiments, the aspect ratio of an exemplary structure, such as the depth of a pore or memory hole relative to a cross-sectional diameter, may be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater. Such high aspect ratios may hinder many conventional etching operations, or create or exacerbate any of the problems previously described.

[0045] Once the layers have been formed and mask material 420 deposited on the structure, memory holes can be etched through the structure. Method 300 can include partially etching through the stack of layers formed on the substrate at operation 305. The etching process can include providing one or more etchant precursors to a processing region of a semiconductor processing chamber, and in some embodiments, generating a plasma effluent of the one or more etchant precursors. The etching process can be any type of etching, and in some embodiments can be or include a reactive ion etching process as discussed above. In embodiments, the etchant precursor can include a carbon-containing precursor, such as a fluorocarbon, or an oxygen-containing precursor, such as molecular oxygen. The etchant precursor can also include a sulfur-containing precursor, such as carbonyl sulfide (COS), or a fluorine-containing precursor, such as nitrogen trifluoride (NF 3 ).

[0046] like Figure 4B As shown, the initial etching operation can extend through the third portion 415c of the stack, and in an embodiment, can extend at least partially through the second portion 415b. As shown, at a certain depth through the stack, the etching process can be stopped at optional operation 310, and this can occur before the layer stack is completely penetrated. As shown, the first portion 415a may not be etched during the initial etching process. The depth of the initial etching process may depend on the number of layer pairs, the characteristics of the material being etched, or any other aspect that may affect whether the critical dimension can be maintained by etching. Before the critical dimension loss through the structure, the etching can be stopped, and the stop can occur at less than or about 75%, less than or about 50%, less than or about 25%, or less depth through the structure. In an embodiment, the substrate can then be moved to a different chamber within a cluster tool, for example, which can allow the vacuum to be maintained, but in some embodiments, the substrate can be transferred between tools before the liner layer is formed. However, in some embodiments, the substrate may not necessarily be moved and can be processed in the same chamber during each operation of the method 300.

[0047] In an embodiment, an optional flash operation may be performed after etching the first portion of the feature in the substrate. The flash operation may remove material buildup in the opening in the mask material 420. The buildup may be caused by redeposition of etched material when the stack 410 of alternating layers of silicon oxide and silicon nitride is removed, or by one or more etchant precursors deposited on the mask material 420. In order to maintain the critical dimensions of the feature being etched into the substrate, the flash operation may remove any material that changes the dimensions of the feature being etched. At optional operation 315, the method 300 may include providing one or more flash precursors, such as an oxygen-containing precursor, which may be molecular oxygen (O 2 ). A plasma effluent of an oxygen-containing precursor may be generated at optional operation 320. At optional operation 325, a substrate may be contacted with an oxygen-containing precursor or its effluent to remove etchant byproducts in or over the feature being etched. Flashing a precursor, such as an oxygen-containing precursor, may or may not include the delivery of an additional precursor, such as a carrier gas. An inert precursor may include any inert material, such as helium, argon, xenon, or diatomic nitrogen (N 2 ).

[0048] Method 300 may include forming a carbon-containing material along a stack of layers on a substrate. In some embodiments, the formation may be substantially conformal along the etched portions of the layers and on a mask. The deposition may be a plasma enhanced deposition, which, unlike plasma-free deposition, may provide a liner coverage of a few nanometers or more, which may facilitate increased protection and resistance to plasma exposure during subsequent etching. Figure 4C As shown, a liner layer 425 of a carbon-containing material may be conformally formed within the etched features and along the various material layers.

[0049] Forming the liner layer 425 may include providing a carbon-containing precursor at operation 330. The carbon-containing precursor that may be used in operation 330 may be or include any number of carbon-containing precursors. For example, any carbon-containing precursor used to deposit a carbon-containing material (such as a polymeric carbon-containing material) may be used. As a non-limiting example, in embodiments of the present technology, the carbon-containing precursor may also include fluorine and / or hydrogen. For example, the carbon-containing precursor may be a fluorocarbon. In embodiments, the carbon-containing precursor may be or include hexafluoropropylene (C 3 F 6 ), octafluoropropane (C 3 F 8 ), pentafluorocyclobutene (C 4 F 5 ), hexafluorocyclobutene (C 4 F 6 ), difluoromethane (CH 2 F 2 ), acetylene (C 2 H 2 )、1,3,3,3-tetrafluoropropylene (C 3 H 2 F 4 ), or any other carbon-containing precursor.

[0050] The carbon-containing precursor may or may not include the delivery of additional precursors for depositing the carbon- and oxygen-containing material, such as a carrier gas or one or more oxygen-containing precursors, such as molecular oxygen. Although a carrier gas, such as an inert precursor, may be delivered with the deposition precursor, additional precursors intended to react with the deposition precursor and produce a deposition product may not be used. The inert precursor may be any inert material, such as helium, argon, xenon, or diatomic nitrogen (N 2 ).

[0051] Once the one or more carbon-containing precursors are provided to the processing region, method 300 may include forming a plasma of the carbon-containing precursor within the processing region at operation 335. The plasma of the carbon-containing precursor may be generated at a plasma power of greater than or about 200 W, and may be generated at a plasma power of greater than or about 300 W, greater than or about 400 W, greater than or about 500 W, greater than or about 600 W, greater than or about 700 W, greater than or about 800 W, greater than or about 900 W, greater than or about 1,000 W, greater than or about 1,100 W, greater than or about 1,200 W, greater than or about 1,300 W, greater than or about 1,400 W, greater than or about 1,500 W, or more. In embodiments, the plasma of the carbon-containing precursor may be generated at a plasma power of greater than or about 2,000 W, and may be generated at a plasma power of less than or about 1,900 W, less than or about 1,800 W, less than or about 1,700 W, less than or about 1,600 W, less than or about 1,500 W, or less. In embodiments, a bias power may be provided while generating the plasma of the carbon-containing precursor. The bias power may be greater than or about 2,000 W, and may be greater than or about 3,000 W, greater than or about 4,000 W, greater than or about 5,000 W, greater than or about 6,000 W, greater than or about 7,000 W, or more. The bias power may direct the carbon-containing material to the etch front of the feature.

[0052] Plasma power (including both source power and bias power) greater than the amounts previously discussed can increase the directionality of the delivery of the carbon-containing precursor. This directionality can increase the vertical travel of the carbon-containing precursor, thereby performing a more conformal formation or deposition of the liner layer 425 across the etched features at operation 340, as will be described below.

[0053] In an embodiment, the plasma may be formed by pulsed RF power rather than using continuous RF power. The RF power may be repeatedly cycled between "on" and "off" periods. During the "on" period, the RF operating power may be greater than or about 200W or less than or about 2,000W. The pulse frequency may be less than about 10,000Hz, and may be less than about 7,500Hz, less than about 5,000Hz, less than about 2,500Hz, less than about 2,000Hz, less than about 1,500Hz, less than about 1,000Hz, less than about 750Hz, less than about 500Hz, less than about 250Hz, or less. The duty cycle may be between about 5% and 95%, and may be between about 20% and about 80%, between about 30% and about 70%, between about 40% and about 70%, or between about 50% and about 70%. Compared to continuous RF power, pulsed RF power may increase ion density while maintaining average ion energy. The increased ion density can increase the density of the membrane while maintaining the amount of carbonaceous material deposited in the membrane.

[0054] When the carbon-containing precursor or plasma effluent thereof contacts the structure 400, the method 300 may include forming a liner layer 425 of a carbon-containing material at operation 340. The liner layer 425 may line the first portion of the previously etched feature. The liner layer 425 of a carbon-containing material of some embodiments of the present technology may be formed to a thickness greater than or about 1 nm, and may be formed to a thickness greater than or about 5 nm, greater than or about 10 nm, greater than or about 15 nm, greater than or about 20 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, or greater. However, the liner layer 425 may also be effective at reduced thicknesses, such as less than or about 50 nm, less than or about 45 nm, less than or about 40 nm, less than or about 35 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, or less.

[0055] Once a layer of carbon-containing material has been formed overlying the previously etched material, method 300 may include a subsequent etching process. For example, if the substrate was moved in a previous operation, the substrate may be transferred back to the etching chamber and the etching process may be resumed at operation 305 to etch the remaining portion of the stack, which may completely etch through the stack of layers on the substrate. FIG. 4D to FIG. 4EAs shown, the etching process can continue and eventually extend completely through the remaining portion of the stack of layers, and can at least partially etch through the resulting liner layer. Producing a liner layer 425 of a carbon-containing material that can fully protect the previously etched material may be challenged by the material's ability to withstand plasma etching during subsequent etching operations. In some embodiments, etching can completely remove the liner layer 425, but some or all of the liner layer 425 can remain along portions of the layers. Depending on the number of layers etched, in some embodiments, the liner can be re-formed after the second etch and a third etch can be performed. Any number of etching and liner formation sequences can be performed before exposing the substrate. For example, the etching and liner formation sequence can be repeated for two cycles, three cycles, four cycles, five cycles, six cycles, seven cycles, or more. The repeated formation of the liner layer 425 can also line and protect the mask material 420, which can allow the mask material 420 to remain for complete etching of the feature.

[0056] The formation of liner layer 425 can be capable of maintaining a reduced critical dimension of a feature being etched in the semiconductor structure. For example, the critical dimension of the feature can be maintained at less than or about 550 nm, and can be maintained at less than or about 500 nm, less than or about 450 nm, less than or about 400 nm, less than or about 350 nm, less than or about 300 nm, less than or about 250 nm, less than or about 200 nm, less than or about 150 nm, or less.

[0057] If the carbon-containing material does remain after the etching process is completed, the remaining material can be removed at optional operation 345. By utilizing the characteristics of the molecular layer material that can contact the stacked layers, removal or stripping can be performed with limited damage to the stacked layers. For example, an oxidant can be delivered to the processing area to react with the carbon-containing material and etch away an amount sufficient to remove the carbon-containing material. The oxidation can be plasma-enhanced, such as by providing an oxygen-containing precursor and forming a plasma to produce oxygen free radical species that can etch the carbon-containing material. In addition, ozone or some other reactive material can be used to remove the carbon-containing material, and the removal can be non-plasma-enhanced to limit additional damage to the structure. The removal process can also occur as stripping the carbon-containing material with annealing. Although the carbon-containing material can be stable during the etching operation, such materials can still decompose at sufficient temperatures. Thus, in some embodiments, the material can be exposed to an anneal at greater than or about 200°C, and can be exposed to an anneal at greater than or about 250°C, greater than or about 300°C, greater than or about 350°C, greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about 550°C, greater than or about 600°C, or more. Figure 4EAs shown, once the carbon-containing material has been removed, the structure can have fully patterned layers that were all deposited prior to any memory hole formation.

[0058] The deposition temperature of the material may affect the deposition on the exposed material and the degree of conformal coverage. For example, a lower temperature can extend the residence time of the deposited material, which can increase the formation. In addition, some materials may flow more easily during deposition, thereby reducing the conformality of the covering. Therefore, in some embodiments, forming a carbonaceous material may include a specific material delivered at a substrate temperature of less than or about 200°C, and the process can be performed at a temperature of less than or about 190°C, less than or about 180°C, less than or about 170°C, less than or about 160°C, less than or about 150°C, less than or about 140°C, less than or about 130°C, less than or about 120°C, less than or about 110°C, less than or about 100°C, less than or about 90°C, less than or about 80°C, less than or about 70°C, less than or about 60°C, less than or about 50°C, less than or about 40°C, less than or about 30°C, less than or about 20°C, less than or about 10°C, less than or about 0°C, less than or about -10°C or less.

[0059] Deposition pressure may also affect deposition on the exposed material, as well as the degree of conformal coverage. For example, higher pressures may increase the directionality of the carbon-containing precursor, which may increase the conformality of the deposited material. Thus, in some embodiments, forming a carbon-containing material may include a particular material delivered at a substrate temperature of less than or about 1 Torr, less than or about 900 mTorr, less than or about 800 mTorr, less than or about 700 mTorr, less than or about 600 mTorr, less than or about 500 mTorr, less than or about 400 mTorr, less than or about 300 mTorr, less than or about 200 mTorr, less than or about 150 mTorr, less than or about 100 mTorr, or less.

[0060] In an embodiment, the formation of the liner layer 425 of carbon-containing material can be performed at a higher pressure than the etching process and the flash evaporation process, such as the pressure previously discussed. The etching process and the flash evaporation process can be performed at a lower pressure, such as less than or about 100 mTorr, less than or about 90 mTorr, less than or about 80 mTorr, less than or about 70 mTorr, less than or about 60 mTorr, less than or about 50 mTorr, less than or about 40 mTorr, less than or about 30 mTorr, less than or about 20 mTorr, less than or about 10 mTorr, or less.

[0061] In the foregoing description, for the purpose of explanation, many details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0062] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessarily obscuring the present technology, many well-known processes and elements are not described. Therefore, the above description should not be considered to limit the scope of the technology. In addition, the method or process may be described as sequential or step-by-step, but it should be understood that the operations may be performed simultaneously or in an order different from that listed.

[0063] Where a range of values ​​is provided, it is understood that, unless the context clearly indicates otherwise, the smallest fraction of each intervening value between the upper and lower limits of the range to the lower limit unit is also specifically disclosed. Any narrower range between any specified value or unspecified intervening value in the specified range and any other specified value or intervening value in the specified range is included. The upper and lower limits of those smaller ranges may be independently included in or excluded from the range, and the technology also encompasses each range in which any limit is included in the smaller range, none of the limit is included in the smaller range, or both limit values ​​are included in the smaller range, subject to any specifically excluded limit values ​​in the specified range. When a specified range includes one or both of the limit values, a range excluding one or both of the included limit values ​​is also included.

[0064] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0065] Furthermore, when used in this specification and the following claims, the words “comprise(s) / comprising,” “contain(s) / containing,” and “include(s) / including” are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. A semiconductor processing method, comprising: etching a first portion of a feature in a substrate disposed within a processing region of a semiconductor processing chamber, wherein the first portion of the feature extends at least partially through one or more material layers formed on the substrate; providing a carbon-containing precursor to the processing region of the semiconductor processing chamber; generating a plasma effluent of the carbon-containing precursor; contacting the substrate with the plasma effluent of the carbon-containing precursor; as well as A carbon-containing material is formed on the substrate, wherein the carbon-containing material lines the first portion of the feature, the first portion extends at least partially through the one or more material layers formed on the substrate, and wherein the carbon-containing material is formed in the same chamber in which the feature is etched.

2. The semiconductor processing method of claim 1, wherein the feature is characterized by an aspect ratio of greater than or about 10:

1. 3 . The semiconductor processing method of claim 1 , wherein the one or more material layers formed on the substrate include alternating layers of oxide material and nitride material.

4. The semiconductor processing method of claim 1, further comprising: providing an oxygen-containing precursor after etching the first portion of the feature in the substrate; as well as The substrate is contacted with the oxygen-containing precursor, wherein the contacting removes etchant byproducts in or over the feature.

5. The semiconductor processing method of claim 4, further comprising: A plasma effluent of the oxygen-containing precursor is generated.

6. The semiconductor processing method of claim 1 wherein the carbon-containing precursor comprises a fluorocarbon.

7. The semiconductor processing method of claim 1 wherein said plasma effluents of said carbon-containing precursor are generated at a plasma power of less than or about 2,000 W.

8. The semiconductor processing method of claim 1, further comprising: A bias power is applied while forming the carbon-containing material on the substrate, wherein the bias power directs the carbon-containing material to an etch front of the feature.

9. The semiconductor processing method of claim 1, further comprising: An oxygen-containing precursor and the carbon-containing precursor are provided, wherein the oxygen-containing precursor comprises molecular oxygen.

10. The semiconductor processing method according to claim 1, wherein: During the semiconductor processing method, the temperature within the processing region is maintained at less than or about 150° C.; as well as During the semiconductor processing method, the pressure within the processing region is maintained at less than or about 500 mTorr.

11. A semiconductor processing method comprising: i) providing one or more etchant precursors to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber; ii) generating a plasma effluent of said one or more etchant precursors; iii) etching a first portion of a feature in the substrate disposed within the processing region, wherein the first portion of the feature extends at least partially through one or more material layers formed on the substrate, iv) providing a flash vaporized precursor to the processing region of the semiconductor processing chamber; v) removing etchant byproducts from the substrate; vi) providing a carbon-containing precursor to the processing region of the semiconductor processing chamber; vii) generating a plasma effluent of said carbon-containing precursor; viii) forming a carbon-containing material on the substrate, wherein the carbon-containing material lines the first portion of the feature, the first portion extending at least partially through the one or more material layers formed on the substrate; as well as ix) Repeat operations i) to viii) for at least five cycles.

12. The semiconductor processing method of claim 11, wherein the one or more etchant precursors include an oxygen-containing precursor and a fluorine-containing precursor.

13. The semiconductor processing method of claim 11, wherein the carbon-containing precursor comprises a precursor containing carbon, hydrogen, and fluorine.

14. The semiconductor processing method of claim 11, further comprising: Argon gas is provided to the processing region simultaneously with providing the flash precursor or providing the carbon-containing precursor.

15. The semiconductor processing method of claim 11, wherein the critical dimension of the feature is less than or about 550 nm.

16. The semiconductor processing method of claim 11, further comprising: The plasma power is pulsed during any of operations i) to viii), wherein the frequency of the plasma power is less than or about 500 Hz.

17. A semiconductor processing method comprising: etching a feature in a substrate disposed within a processing region of a semiconductor processing chamber, wherein the feature extends at least partially through one or more alternating layers of material formed on the substrate; providing a fluorocarbon precursor to the processing region of the semiconductor processing chamber; generating a plasma effluent of said fluorocarbon precursor, wherein said plasma effluent of said fluorocarbon precursor is generated at a plasma power of less than or about 1,500 W; contacting the substrate with the plasma effluent of the fluorocarbon precursor; as well as A polymeric carbon-containing material is formed on the substrate, wherein the polymeric carbon-containing material lines the features that extend at least partially through the one or more alternating material layers formed on the substrate.

18. The semiconductor processing method of claim 17, wherein the substrate comprises a mask material overlying the one or more alternating material layers.

19. The semiconductor processing method of claim 17, wherein the polymeric carbon-containing material has a thickness of less than or about 30 nm.

20. The semiconductor processing method of claim 17 wherein the feature is characterized by an aspect ratio of greater than or about 40:1.

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