CMOS compatible resistive random access memory device with via device structure

Abstract

The present disclosure provides a crossbar circuit including a crossbar array and a peripheral circuit. A resistive random access memory (RRAM) device in the crossover array includes a bottom electrode fabricated on a first interconnect layer, a top electrode, and a filament forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament forming layer and a portion of the top electrode are fabricated in a via of a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode may be connected to a first metal via and a dielectric layer fabricated in a second interconnect layer fabricated in the second etch stop layer. The peripheral circuit includes a metal via of the second interconnect layer fabricated in the dielectric layer and the first etch stop layer.

Description

Cross-references

[0001] This application claims priority to U.S. patent application No. 17 / 936,830, filed on September 29, 2022, entitled “CMOS-compatible random access memory device with through-hole device structure,” which is incorporated in its entirety into this application. Technical Field

[0002] The present disclosure relates to a random access memory (RRAM) device, and more particularly, to a CMOS (complementary metal oxide semiconductor) compatible RRAM device having a through-hole device structure and a method for manufacturing the same. Background Art

[0003] A resistive random access memory (RRAM) device is a two-terminal passive device with adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying a suitable programming signal to the RRAM device. RRAM devices can be used to form a crossbar array, which can be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, and other applications. Summary of the invention

[0004] The following is a brief summary of the present disclosure, which is used to provide a basic understanding of some aspects of the present disclosure. The summary is not an extensive overview of the present disclosure. The summary is not intended to identify the key or important elements of the present disclosure, nor is it intended to illustrate any scope of a particular implementation of the present disclosure or any scope of the claims. The sole purpose of the summary is to present some concepts of the present disclosure as a language simplification of a more detailed description presented subsequently.

[0005] According to one or more aspects of the present disclosure, a device is provided. The device may be a crossover circuit or include a crossover circuit. The device may include a first resistive random access memory (RRAM) device, including: a first etch stop layer and a second etch stop layer. The first RRAM device includes a first bottom electrode fabricated on a first interconnect layer; a first top electrode; and a first filament forming layer fabricated between the first bottom electrode and the first top electrode. The first filament forming layer includes at least one switching metal oxide. In some embodiments, the first filament forming region in the first filament forming layer and at least a portion of the first top electrode are fabricated in a first through hole in the first etch stop layer. In some embodiments, the second etch stop layer is fabricated on the first top electrode. The device may further include a dielectric layer fabricated on the second etch stop layer; and a first metal through hole of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. In some embodiments, the first top electrode is connected to a bit line via a first metal through hole in the second interconnect layer.

[0006] In some embodiments, the first bottom electrode is fabricated on a first metal pad in the first interconnect layer. In some embodiments, the first metal pad in the first interconnect layer is connected to a first transistor.

[0007] In some embodiments, the switching oxide comprises HfO x 、TaO x 、TiO x 、NbO x 、ZrO x At least one of .

[0008] In some embodiments, the first RRAM device further includes an interface layer formed between the first top electrode and the first filament-forming layer, wherein the interface layer includes Al 2 O 3 ,MgO,Y 2 O 3 ,La 2 O 3 At least one of .

[0009] In some embodiments, the first RRAM device further includes an interface layer formed between the first bottom electrode and the first filament-forming layer, wherein the interface layer includes Al 2 O 3 ,MgO,Y 2 O 3 ,La 2 O 3 At least one of .

[0010] In some embodiments, the interface layer comprises SiO 2 .

[0011] In some embodiments, the first etch stop layer includes at least one of silicon nitride or silicon oxynitride.

[0012] In some embodiments, the second etch stop layer includes at least one of silicon nitride or silicon oxynitride.

[0013] In some embodiments, the apparatus further includes a second RRAM device, the second RRAM device including: a second bottom electrode fabricated on the first interconnect layer; a second top electrode; and a second filament-forming layer fabricated between the second bottom electrode and the second top electrode. In some embodiments, a second filament-forming region of the second filament-forming layer and at least a portion of the second top electrode are fabricated in a second through hole of the first etch stop layer.

[0014] In some embodiments, the second bottom electrode is fabricated on a second metal pad in the first interconnect layer. In some embodiments, the second metal pad in the first interconnect layer may be connected to a second transistor.

[0015] In some embodiments, the second metal via in the second interconnect layer is fabricated on the dielectric layer and the second etch stop layer. The second top electrode may be connected to a bit line through the second metal via of the second interconnect layer.

[0016] In some embodiments, the device further comprises: peripheral circuitry. The peripheral circuitry comprises: a third metal pad in the first interconnect layer; and a third metal via in the second interconnect layer. In some embodiments, a portion of the first etch stop layer is fabricated on the third metal pad in the first interconnect layer. The third metal via is fabricated in a third via trench between a dielectric layer and a portion of the first etch stop layer. In some embodiments, the peripheral circuitry does not include the second etch stop layer.

[0017] In some embodiments, the third metal via in the second interconnect layer connects the third metal pad in the first interconnect layer to the metal pad in the third interconnect layer.

[0018] In some embodiments, a method for manufacturing the device is provided. The method includes: manufacturing one or more bottom electrodes on a substrate including a first interconnect layer; manufacturing a first etch stop layer on the substrate and the one or more bottom electrodes; manufacturing one or more through holes in the first etch stop layer to expose a portion of each bottom electrode; manufacturing a switching oxide layer on the first etch stop layer, wherein at least a portion of the switching oxide layer is manufactured on the exposed portion of the bottom electrode; manufacturing a top electrode layer on the switching oxide layer; manufacturing a second etch stop layer on the switching oxide layer; and manufacturing one or more top electrodes by selectively removing one or more portions of the second etch stop layer and the second etch stop layer.

[0019] In some embodiments, fabricating the one or more bottom electrodes on the first interconnect layer includes fabricating a first bottom electrode on a first metal pad in the first interconnect layer. In some embodiments, fabricating the one or more vias on the first etch stop layer includes fabricating a first via in the first etch stop layer to expose a portion of the first bottom electrode.

[0020] In some embodiments, fabricating one or more top electrodes includes: patterning the second etch stop layer; and etching the second etch stop layer and the top electrode layer.

[0021] In some embodiments, fabricating the one or more bottom electrodes on the first interconnect layer includes fabricating a second bottom electrode on a second metal pad in the first interconnect layer. In some embodiments, fabricating the one or more vias in the first etch stop layer includes fabricating a second via in the first etch stop layer to expose a portion of the second bottom electrode.

[0022] In some embodiments, the method further includes: manufacturing a dielectric layer on the second etch stop layer; and manufacturing a second interconnect layer connecting the first interconnect layer to a third interconnect layer, wherein a first metal via in the second interconnect layer is manufactured in the dielectric layer and the second etch stop layer, and a first metal pad in the first interconnect layer is connected to a first metal pad in the third interconnect layer through the first metal pad in the second interconnect layer.

[0023] In some embodiments, manufacturing the second interconnect layer includes: patterning and etching the dielectric layer to manufacture a first portion of a first through-hole groove; patterning and etching the second etch stop layer to manufacture a second portion of the first through-hole groove; and depositing metal material in the first through-hole groove to manufacture a first metal through-hole of the second interconnect layer.

[0024] In some embodiments, the etching of the dielectric layer stops on the second etch stop layer. The etching of the second etch stop layer stops on the top electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be used to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0026] Figure 1 is a schematic diagram showing an example of a crossover circuit according to some embodiments of the present disclosure.

[0027] Figure 2 is a schematic diagram showing an example of a cross-point device according to some embodiments of the present disclosure.

[0028] Figure 3A and 3B is a schematic diagram showing a cross-sectional view of an example semiconductor device including a CMOS-compatible RRAM according to some embodiments of the present disclosure.

[0029] Figures 4A-4M is a schematic diagram showing a cross-sectional view of a structural strength for manufacturing a semiconductor device including a CMOS-compatible RRAM device according to some embodiments of the present disclosure.

[0030] Figure 5A is a schematic diagram showing an example of a crossover circuit according to some embodiments of the present disclosure.

[0031] Figure 5B-5M The invention is a diagram showing a method for manufacturing a Figure 5A Schematic diagram of a cross-sectional view of the structure of a crossbar circuit.

[0032] Fig. 6A , 6B , 6C, 6D and 6E are schematic diagrams showing cross-sectional views of examples of RRAM devices according to some embodiments of the present disclosure.

[0033] Figure 7 is a flow chart showing an example of a process for manufacturing a crossover circuit according to some embodiments of the present disclosure.

[0034] Figure 8 is a flow chart illustrating an example of a process for fabricating one or more interconnect layers according to some embodiments of the present disclosure.

[0035] Fig. 9A is a flow chart showing an example of a process for fabricating an interconnect structure including metal vias and metal pads in one process.

[0036] Figure 9B-9GIt shows that according to some embodiments of the present disclosure, Fig. 9A Schematic cross-sectional view of the process for fabricating the interconnect structure. DETAILED DESCRIPTION

[0037] Various aspects of the present disclosure provide a resistive random access memory (RRAM) device and a method for manufacturing the RRAM device. A RRAM device is a two-terminal passive device with adjustable resistance. The RRAM device may include a bottom electrode, a top electrode, and a switching oxide layer manufactured between the bottom electrode and the top electrode. The bottom electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc. The top electrode may include a reactive metal, such as tantalum (Ta), etc. The electrode containing the non-reactive metal is also referred to as a "non-reactive electrode" in the present disclosure. The switching oxide layer may include a transition metal oxide, such as hafnium oxide (HfO x ) or tantalum oxide (TaO x ). The RRAM device may be in an initial state or original state and have an initial high resistance before being subjected to an appropriate electrical stimulus (e.g., a voltage or current signal applied to the RRAM device). The RRAM device may be switched from the original state to a low resistance state through a formation process, or may be switched from a high resistance state (HRS) to a low resistance state (LRS) through a setting process. The formation process refers to programming the device from the original state. The setting process refers to programming the device from a high resistance state (HRS). After the reactive metal electrode is deposited on the switching oxide, the reactive metal may absorb oxygen from the switching oxide layer and generate oxygen vacancies in the switching oxide layer, and oxygen ions may migrate in the switching oxide through a vacancy mechanism. During the formation process, a suitable programming signal (e.g., a voltage or current signal) may be applied to the RRAM device, which may cause oxygen ions to switch from the switching oxide to the reactive electrode. Thus, a conductive channel or filament may be formed through the switching oxide layer (e.g., from a reactive electrode to a non-reactive electrode). The RRAM device may then be reset to a high resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Application of a reset signal applied to the RRAM device can cause the oxygen ions to migrate back to the switching oxide layer and thus interrupt the conductive filament. By applying a suitable programming signal (e.g., a voltage signal, a current signal lamp) to the RRAM device, the RRAM device can be electrically switched between a high resistance state and a low resistance state. In a crossbar array circuit, the programming signal can be provided to a specified RRAM device through a selector (e.g., a transistor).

[0038] One of the existing methods for manufacturing a crossbar array of RRAM devices involves manufacturing a bottom electrode wiring, a switching oxide layer located on the bottom electrode wiring, and a top electrode wiring located on the switching oxide layer. The RRAM device can be formed at each intersection of the bottom electrode wiring and the top electrode wiring. Therefore, the size of the RRAM device manufactured using the existing method is limited by the size (e.g., width) of the bottom electrode wiring and the top electrode wiring. Therefore, shrinking such an RRAM device may require a reduction in the size of the bottom electrode wiring and / or the top electrode wiring, and thus may increase the resistance of the bottom electrode wiring and the top electrode wiring. The high wire resistance can act as a voltage divider and can reduce the available voltage of the RRAM device during operation.

[0039] In order to address the above and other defects of conventional RRAM devices, the present disclosure provides a mechanism for manufacturing a RRAM device with a through-hole structure, which can enhance the performance of the RRAM device and can be used for low-power IMC applications. According to some embodiments of the present disclosure, manufacturing a RRAM device may involve providing a substrate including a first interconnect layer including a plurality of metal pads and / or metal through holes. The substrate may further include one or more transistors. The metal pads and / or metal through holes in the first interconnect layer may be connected to the transistor.

[0040] A bottom electrode layer may be fabricated on the substrate and the interconnect layer. The bottom electrode layer may be patterned and etched to fabricate a bottom electrode of the RRAM device. In some embodiments, a first bottom electrode and a second bottom electrode may be fabricated on a first metal pad and a second metal pad in the first interconnect layer, respectively. The first metal pad and the second metal pad may be connected to a first transistor and a second transistor, respectively.

[0041] The first etch stop layer can be fabricated on the bottom electrode and the upper surface of the substrate. Due to the high etch selectivity or high ratio between the etch rate of the dielectric material and the etch rate of the etch stop material, the first etch stop layer may include any suitable material that is resistant to etching of the dielectric layer fabricated on the first etch stop layer. In some embodiments, the first etch stop layer includes silicon nitride and / or silicon oxynitride. One or more through holes can be fabricated by patterning and etching the first etch stop layer, and exposing a portion of each bottom electrode.

[0042] A switching oxide layer can be fabricated on the upper surface of the first etch stop layer after etching, along the sidewalls of the through hole and on the exposed portion of the bottom electrode. The switching oxide layer can be an ultra-thin layer (e.g., a layer of about or thinner than 2 nm) of a switching metal oxide. Due to the ultra-thin thickness of the switching oxide layer, the fabricated portion of the switching oxide layer fills the through hole. One or more portions of the switching oxide layer can be fabricated on the exposed portion of the bottom electrode. The remaining portion of the switching oxide layer can be fabricated on the sidewalls of the first through hole and the upper surface of the first etch stop layer, and does not contact the exposed portion of the bottom electrode. Because this portion of the switching oxide layer has no electric field, the switching metal oxide in the remaining portion of the filament formation layer does not participate in the formation process and switching process of the RRAM device. Therefore, the portion of the switching oxide layer deposited on the exposed portion of the bottom electrode can be used as a filament formation region, in which the filament can be formed during the formation process, the setting process, or the reset process. Therefore, the key device size of each RRAM device is defined by the size of the filament formation region and the opening size of the first through hole (also regarded as a through-hole device structure), rather than by the size of the top electrode wiring and the bottom electrode wiring.

[0043] A top electrode layer may then be fabricated on the switching oxide layer, for example, by depositing one or more reactive metal materials on the switching oxide layer, along the second via sidewalls and across the entire upper surface of the first etch stop layer.

[0044] A second etch stop layer may be fabricated on the top electrode layer. The fabrication of the second etch stop layer may fill the through hole. One or more portions of the second etch stop layer may extend along the sidewalls of the through hole and cover the upper surface of the top electrode.

[0045] The second etch stop layer and the top electrode layer may be selectively etched to manufacture the top electrode of the RRAM device. The etching of the second etch stop layer and the top electrode layer may stop on the switching oxide layer. In some embodiments, the switching oxide layer may be patterned and etched. The etching of the switching oxide layer may stop at the first etch stop layer after etching and expose one or more portions of the first etch stop layer. Therefore, the first etch stop layer may protect the through-hole device structure during the etching process of the top electrode layer and the switching oxide layer.

[0046] In some embodiments, a dielectric layer (e.g., a silicon oxide layer) can be fabricated on the second etch stop layer after etching and the exposed first etch stop layer. A second interconnect layer including one or more metal pads and / or metal vias can be fabricated on the dielectric layer. For example, the dielectric layer can be patterned and etched to fabricate one or more via slots on the dielectric layer. The etching of the dielectric layer can be stopped on the second etch stop layer. Then, the via slot on the dielectric layer can be enlarged by patterning and etching the second etch stop layer after etching. The etching of the second etch stop layer can be stopped on the top electrode.

[0047] In some embodiments, the crossover circuit may also include a peripheral circuit that does not include an RRAM device. The peripheral circuit may include one or more transistors for implementing a logic circuit. The peripheral circuit may include a portion of the first interconnect layer, for example, a third metal pad of the first interconnect layer. The third metal via of the second interconnect layer may be fabricated on the dielectric layer and on the first etch stop layer after etching. The third metal via may contact the third metal pad in the first interconnect layer.

[0048] The third metal via can be manufactured together with the first metal via, the second metal via, etc. in the second interconnect layer. For example, the dielectric layer can be patterned and etched to manufacture the top of the first via slot, the top of the second via slot, and the top of the third via slot in the peripheral circuit. Since the peripheral circuit does not include a second etch stop layer, the etching of the dielectric layer in the peripheral circuit can stop on a portion of the first etch stop layer manufactured in the peripheral circuit. Then, the portion in the first etch stop layer can be etched to expand the third via slot so that it contacts the third metal pad of the first interconnect layer. Therefore, the dielectric layer in the peripheral circuit can be etched to establish a metal contact with the bottom via.

[0049] The etch stop layer described in the present disclosure can protect the through-hole device structure during the etching of the dielectric layer to manufacture the peripheral circuit, and can achieve high etching selectivity during the etching of the dielectric layer. The etch stop layer can be used for etching masks in the etching process described in the present disclosure, thereby reducing manufacturing costs. The etch stop layer (e.g., SiN layer) can also be used as a barrier to isolate oxygen diffusion from the dielectric material into the RRAM device to achieve better device balance and device operation control. The mechanism for manufacturing crossover circuits described in the present disclosure can enable the manufacture of RRAM devices without the use of spacers during the etching process, and can achieve the integration of RRAM devices with lower metal CMOS manufacturing processes.

[0050] Figure 11 is a schematic diagram showing an example of a crossover circuit 100 according to some embodiments of the present disclosure. As shown in the figure, the crossover circuit 100 may include a plurality of interconnected conductive lines, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n and column lines 113a, 113b, ..., 113j, ..., 113m in a crossover array for n rows by m columns. The crossover circuit 100 may further include crossover devices 120a, 120b, ..., 120z, etc. Each crossover device may connect a row line and a column line. For example, the crossover device 110ij may connect the row line 111i and the column line 113j. In some embodiments, the crossover circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC) not shown, a switch (not shown) and / or any other suitable circuit components for implementing a crossover switch device. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

[0051] The row lines 111a-n may include a first row line 111a, a second row line 111b, ..., 111i, ..., and an nth row line 111n. Each of the row lines 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

[0052] The column lines 113a-m may include a first column line 113a, a second column line 113b, ... and an mth column line 111m. Each of the column lines 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

[0053] Each cross-point device 120a-z may be and / or include any suitable device having an adjustable resistance, such as a memristor, a phase change memory (PCM) device, a floating gate, a spintronic device, an RRAM, a static random access memory (SRAM), etc. In some embodiments, one or more cross-point devices 120a-z may include a combination of Figure 3A-6E Each cross-point device 120a-z may be and / or include a combination of the following: Figure 2 The cross-point device.

[0054] The crossbar circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar switch circuit 100. The input signal can flow through the crosspoint devices of the rows of the crossbar switch circuit 100. The conductance of the crosspoint device can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the crosspoint conductance and generates a current flowing through the crosspoint device. Through Kirchhoff's law, the sum of the currents through the devices on each column generates a current as an output signal, which can be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductance matrix of the crosspoint device. Therefore, according to Ohm's law, the input signal is weighted by its conductance at each crosspoint device. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing parallel multiplication and summation in the crossbar array to achieve in-memory computing (IMC).

[0055] Figure 2 2 is a schematic diagram showing an example of a cross-point device 200 according to some embodiments of the present disclosure. As shown in the figure, the cross-point device 200 can connect a bit line (BL) 211, a select line (SEL) 213, and a word line (WL) 215. The bit line 211 and the word line 215 can be respectively combined Figure 1 The column lines and row lines.

[0056] The cross-point device 200 may include a RRAM device 201 and a transistor 203. A transistor is a three-terminal device. The terminals of the transistor may be labeled as a gate (G), a source (S), and a drain (D). The transistor 203 may be connected in series to the RRAM device 201. Figure 2 As shown, the first electrode of the RRAM device 201 may be connected to the drain of the transistor 203. The second electrode of the RRAM device 201 may be connected to the bit line 211. The source of the transistor 203 may be connected to the word line 215. The gate of the transistor 203 may be connected to the select line 213. The RRAM device 201 may include and / or include the following in combination: Figure 3A-6EOne or more RRAM devices 340, 440a, 440b and / or 600a-e are described. The cross-point device 200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. The transistor 203 may be used as a selector as well as a current controller, which may set the current compliance of the RRAM device 201 during programming. The gate voltage of the transistor 203 may set the current compliance of the cross-point device 200 during programming, and thus control the conductance and analog behavior of the cross-point device 200. For example, when the cross-point device 200 is set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) may be provided via a bit line (BL) 211. Another voltage, also referred to as a select voltage or gate voltage, may be applied to the transistor gate via a select line (SEL) 213 to turn on the gate and set the current compliance, while a word line (WL) 215 may be set to ground. When the cross-point device 200 is reset from a low-resistance state to a high-resistance state, a gate voltage may be applied to the gate of the transistor 203 through the select line 213 to turn on the transistor gate. At the same time, a reset signal may be sent to the RRAM device 201 through the word line 215, and the bit line 211 may be set to ground. In some embodiments, the width of the bit line 211 and / or the word line 215 may be about or greater than 1 μm.

[0057] Figure 3A and 3B is a schematic diagram showing cross-sectional views of examples of semiconductor devices 300 a and 300 b including CMOS-compatible RRAM in accordance with some embodiments of the present disclosure.

[0058] As shown in the figure, transistor 303 is fabricated on substrate 301. The transistor 303 may include a source region 303a, a gate 303b and a drain region 303c. Figure 3A One transistor is shown in FIG. 301 , but this is illustrative only. In some embodiments, multiple transistors (not shown) may be fabricated on substrate 301 . The transistors may be isolated by suitable insulators and / or dielectric materials.

[0059] The semiconductor device 300a may include interconnect layers 310 fabricated on the transistor 303 and the substrate 301. Each interconnect layer 310 may provide electrical connections between the transistor 303 and / or one or more other devices (e.g., one or more other transistors, one or more other RRAM devices, etc.). The interconnect layer 310 may include, for example, through-hole layers (or via layers) 311, 312, 313, 314, ... and 315 and metal layers (or pad layers) 321, 322, 323, 324, ... and 325. Although Figure 3A-3BUp to 315 via layers and up to 325 metal layers are shown for brief description, but more via layers and pad layers can be manufactured for integration and / or interconnection requirements. Each via layer may include one or more metal vias. Each metal via may include a suitable metal material, such as Al, Cu, W, etc. Each metal layer may include one or more metal pads. Each metal pad may include a suitable metal material, such as Al, Cu, W, etc. For example, via layer 311 may include metal vias 311a, 311b, and 311c connected to source region 303a, gate 303b, and drain region 303c of transistor 303, respectively. In some embodiments, via layer 311 may include tungsten (W) vias and doped polysilicon (poly-Si) terminals, wherein the poly-Si terminals may directly contact the gate 303b, source region 303a, and drain region 303c of transistor 303. The tungsten vias may directly contact the poly-Si terminals. Other via layers and metal layers on the via layer 311 may be made of Cu, W, Al, etc. The metal layer 321 may include metal pads 321a, 321b, and 321c. The metal pads 321a, 321b, and 321c may be connected to the metal vias 311a, 311b, and 311c, respectively.

[0060] Each interconnect layer can be manufactured by manufacturing a dielectric layer, patterning the dielectric layer, and depositing a suitable metal on the patterned dielectric layer. The dielectric layer may include any suitable dielectric material, such as silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ) etc. For example, to fabricate the first via layer 311, a dielectric layer 351 may be fabricated on the substrate 301 and the transistor 303. The dielectric layer 351 may be processed using any suitable deposition technique. For example, the dielectric layer 351 may be filled by patterning and metal deposition to fabricate metal vias 311a, 311b, and 311c in the dielectric layer 351. In some embodiments, one or more interconnect layers 310 may be fabricated using a dual metal damascene process (e.g., Fig. 9A 900 in the process for manufacturing.

[0061] As shown, a pair of adjacent metal layers can be connected by a via layer made between the adjacent metal layers. For example, the first metal layer 321 can be connected to the second metal layer 322 through the via layer 312. In particular, the metal pad 322a of the metal layer 322 can be connected to the metal pad 321a of the metal layer 321 through the metal via 312a. The metal pad of the metal layer 322 can be connected to the metal pad 321b of the metal layer 321 through the metal via 312b. The metal pad 322c of the metal layer 322 can be connected to the metal pad 321c of the metal layer 321 through the metal via 312c.

[0062] Interconnect layer 310 may have different sizes. The sizes of metal pads of metal layers 321, 322, 323, 324, ..., and 325 may increase in sequence. Similarly, the sizes of metal vias in via layers 311, 312, 313, 314, ..., and 315 may also increase in sequence. For example, semiconductor device 300a may be part of a 65nm technology process. The width and spacing of metal pads in metal layer 321 may be about 90nm. The width and spacing of metal pads in metal layers 322 and 323 may be about 100nm. The width and spacing of metal pads in metal layer 325 may be about 400nm.

[0063] The RRAM device 340 can be manufactured during the manufacturing process of the interconnect layer 310. Therefore, the RRAM device 340 can be referred to as a CMOS compatible RRAM device. For example, one or more first interconnect layers 310a can be manufactured on the transistor 303 and / or the substrate 301. The RRAM device 340 can be manufactured on a metal pad or a metal via in the top interconnect layer of the first interconnect layer 310a. Then, one or more second interconnect layers 310b can be manufactured on the RRAM device 340 and the first interconnect layer 310a. More specifically, for example, a metal pad or a metal via in the bottom interconnect layer of the second interconnect layer 310b can be manufactured on the RRAM device 340 and can directly contact the RRAM device 340. In some embodiments, as Figure 3A As shown, the first interconnect layer 310a may include a via layer 311 and a metal layer 321. The metal layer 321 may be considered as a top interconnect layer of the first interconnect layer 310a. The RRAM device 340 may be fabricated on a metal pad 321c in the metal layer 321. The RRAM device 340 may be connected to the drain region 303c of the transistor 303 through the metal pad 321c in the metal layer 321 and the metal via 311c in the via layer 311. The metal via 312c in the via layer 312 may be fabricated on the RRAM device 340 and may be connected to a bit line (e.g., Figure 2The metal vias 312a and 312b in the via layer 312 may be fabricated on metal pads 321a and 321b, respectively. The metal layer 321 may be considered as a bottom interconnect layer of the second interconnect layer 310b. The second interconnect layer 310b may include one or more metal layers and / or via layers (e.g., metal layers 322, 323, 324, and 325 and via layers 313, 314, and 315) fabricated on the metal layer 321. The RRAM device 340 may include a combination of the following Figures 4A-6E The one or more RRAM devices described.

[0064] In some embodiments, Figure 3B As shown, the RRAM device 340 can be fabricated on a metal pad 322c in a metal layer 322. A via layer 313 can be fabricated on the RRAM device 340. In particular, a metal via 313c in the via layer 313 can be fabricated on the RRAM device 340 and directly contact the RRAM device 340. In this embodiment, the first interconnect layer 310a may include a via layer 311, a metal layer 321, a via layer 312, and a metal layer 322. The metal layer 322 may be considered as the top interconnect layer of the first interconnect layer 310a. The second interconnect layer 310b may include via layers 313, 314, and 315 and metal layers 323, 324, and 325. The via layer 313 may be considered as the bottom interconnect layer of the second interconnect layer 310b.

[0065] although Figure 3A and 3B The overall processing steps for manufacturing the interconnect layer 310 may be the same. Figure 3B The first interconnect layer 310a can be manufactured in Figure 3A There are more steps in manufacturing the first interconnection layer 310a, and Figure 3B The second interconnect layer 310b is fabricated by Figure 3A The RRAM device 340 can be connected to the drain region 303c of the transistor through the metal pad 322c of the metal layer 322, the metal via 312c of the via layer 312, the metal pad 321c of the metal layer 321, and the metal via 311c of the via layer 311. The metal via 313c of the via layer 313 can be fabricated on the RRAM device 340 and connected to the bit line of the circuit (e.g., Figure 2 The metal vias 313a and 313b in the via layer 313 may be fabricated on the metal pads 322a and 322b, respectively.

[0066] Although Figure 3A-3BSpecific interconnect layers (e.g., metal layers and via layers) are shown in FIG. 3 , but this is illustrative only. The semiconductor device 300a may include any suitable number of interconnect layers for implementing various integrated circuits. The first interconnect layer 310a and the second interconnect layer 310b may include any suitable number of interconnect layers. For example, in some embodiments, the RRAM device 340 may be fabricated on the metal layer 323.

[0067] Figures 4A-4M Schematic diagrams showing cross-sectional views of example structures 400a, 400b, 400c, 400d, 400e, 400f, 400g, 400h, 400i, 400j, 400k, 400l of an example semiconductor device example 400 fabricated including a CMOS compatible RRAM device in some embodiments of the present disclosure.

[0068] like Figure 4A As shown, a substrate 410 is provided. The substrate 410 may include one or more layers of any suitable material that can be used as a substrate for manufacturing an RRAM device, for example, silicon (Si), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), etc. In some embodiments, substrate 410 may include diodes, transistors, interconnects, integrated circuits, etc. Substrate 410 may include a driver circuit including one or more circuits (e.g., a circuit array) that can be individually controlled. In some embodiments, the driver circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers. In some embodiments, substrate 410 may include a combination of Figure 3A-3B The one or more dielectric layers and interconnect layers. For example, substrate 410 may include substrate 301, transistor 303, metal vias 311a-311c, etc.

[0069] like Figure 4A As shown, substrate 410 may include a first interconnect layer 411 including one or more metal pads and / or metal vias. For example, first metal layer 411 may include metal pads 411a and 411b. Metal pads 411a and 411b may include any suitable metal, such as tungsten (W). Each metal pad 411a and 411b may be connected to a transistor. For example, each metal pad 411a and 411b may be connected to drain region 303c of transistor 303. Figure 3A The metal pad 321c or Figure 3B As another example, each of metal pads 411a and 411b may be Figure 3A The metal through hole 311c in the.

[0070] like Figure 4B As shown, the first bottom electrode 421a and the second bottom electrode 421b can be fabricated on the metal pad 411a and the metal pad 411b, respectively. As shown, the lateral dimensions of the bottom electrodes 421a-b can be greater than the lateral dimensions of the metal pads 411a-b. The first bottom electrode 421a can directly contact the metal pad 411a to form an ohmic contact. The second bottom electrode 421b can directly contact the second metal pad 411b to form an ohmic contact. The first bottom electrode 421a and the second bottom electrode 421b can further contact one or more portions of the substrate 410, such as one or more portions of the surface 401 of the substrate 410. The first bottom electrode 421a and / or the second bottom electrode 421b may include any suitable material that is conductive and non-reactive to the switching oxide in the RRAM device fabricated on the substrate 410. Examples of non-reactive materials may include platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), etc. In some embodiments, the first bottom electrode 421a and / or the second bottom electrode 421b may include one or more metals that can enhance the adhesion between the first bottom electrode 421a and the metal pad 411a, the adhesion between the second bottom electrode 421b and the second metal pad 411b, and / or the adhesion between the first bottom electrode 421a and the second bottom electrode 421b and the substrate 410, such as tantalum (Ta), titanium (Ti), etc.

[0071] like Figure 4C As shown, the first etch stop layer 430 can be fabricated on the substrate 410, the first bottom electrode 421a and the second bottom electrode 421b. In some embodiments, the first etch stop layer 430 can directly contact the upper surface 401 of the substrate 410, the first bottom electrode 421a and the second bottom electrode 421b. The first etch stop layer 430 may include any suitable material that may be resistant to the etching process implemented on the dielectric layer (e.g., silicon dioxide layer) described in the present disclosure. For example, the first etch stop layer 430 may include one or more layers of silicon nitride (SiNx), silicon oxynitride (SiOxNy), etc.

[0072] like Figure 4DAs shown, one or more portions of the first etch stop layer 430 may be selectively removed to expose a portion of each bottom electrode fabricated on the substrate 410 (e.g., using a suitable photolithography technique). For example, the first etch stop layer 430 may be patterned and etched. The etching of the first etch stop layer 430 may stop on the first bottom electrode 421a and the second bottom electrode 421b. Selectively removing portions of the first etch stop layer 430 may expose one or more portions of the first bottom electrode 421a and the second bottom electrode 421b, and may form through holes 431 and 433 on the etched first etch stop layer (also referred to as the etch stop layer 430a). As shown, the through hole bottom of the through hole 431 may directly contact the exposed portion of the first bottom electrode 421a. Similarly, the through hole bottom of the through hole 433 may directly contact the exposed portion of the second bottom electrode 421b. In some embodiments, the size (e.g., diameter) of the through holes 431 and / or 433 may be about or less than 1 μm. The lateral dimensions of the bottom electrodes 421 a - b and the lateral dimensions of the metal pads 411 a - b may be larger than the dimensions of the vias 431 and / or 433 .

[0073] refer to Figure 4E The switching oxide layer 423 may be fabricated on the etch stop layer 430a and in the through holes 431 and 433. The switching oxide layer 423 may include one or more switching metal oxides of binary oxides, ternary oxides, and high-order oxides, such as TaO x , HfO x 、TiO x 、NbO x 、ZrO x etc., where x can be used to indicate the degree of oxygen deficiency of the oxide compared to its complete (or terminal) oxide, and the value of x can be the ratio of oxygen to metal atoms in the stoichiometric ratio of its complete oxide, such as HfO x Medium x≤2.0(HfO 2 is a complete oxide, and TaO x x≤2.5(Ta 2 O 5is a complete oxide). The switching oxide layer 423 can be conformally fabricated on the etch stop layer 430a and the exposed portions of the first bottom electrode 421a and the second bottom electrode 421b, and along the sidewalls of the through holes 431 and 433. In some embodiments, the switching oxide layer 423 can be fabricated on the entire surface 403 of the etch stop layer 430a. As shown, portions 423a and 423b of the switching oxide layer 423 can be fabricated on the exposed portion of the first bottom electrode 421a in the through hole 431 and the exposed portion of the second bottom electrode 421b in the through hole 433, respectively. The fabrication of the switching oxide layer 423 can form through holes 431a and 433a, which correspond to the portions of the through holes 431 and 433, respectively, that are not filled with the switching oxide layer 423.

[0074] refer to Figure 4F The top electrode layer 425 may be fabricated on the switching oxide layer 423. The top electrode layer 425 may include any suitable material that is conductive and reactive to the transition metal oxide in the switching oxide layer. For example, the top electrode layer 425 may include one or more of Ta, Hf, Ti, TiN, TaN, etc. Figure 4F As shown, the top electrode layer 425 may include a portion 425a fabricated on the portion 423a of the switching oxide layer 423 and a portion 425b fabricated on the portion 423b in the switching oxide layer 423. The formation of the portions 425a and 425b of the top electrode layer 425 may produce vias 431b and 433b, which correspond to the unfilled portions of the vias 431a and 433a, respectively. The portion 425c of the top electrode layer 425 may be formed on the upper surface of the portion 423c in the switching oxide layer 423. Therefore, the top electrode layer 425 may be conformally fabricated on the upper surface of the switching oxide layer 423 and along the sidewalls of the vias 431a and 431b.

[0075] refer to Figure 4G , a second etch stop layer 450 may be fabricated on the top electrode layer 425. The second etch stop layer 450 may include any suitable material that is resistant to the etching process performed on the dielectric layer described herein. For example, the etch stop layer 450 may include one or more layers of SiN x 、SiO x N y Etc. Figure 4G As shown, the second etch stop layer 450 may be fabricated on the upper surface of the top electrode layer 425 and in the through holes 431a and 431b. The second etch stop layer 450 may fill the through holes 431b and 433b and may extend outside the through holes 431b and 433b.

[0076] refer to Figure 4H, the second etch stop layer 450 and the top electrode layer 425 can be selectively etched to manufacture the RRAM devices 440a and 440b (for example, using suitable photolithography techniques). Specifically, the second etch stop layer 450 is patterned. The second etch stop layer 450 and the top electrode layer 425 can be etched to form etch stop layers 450a-450b, a top electrode 445a of the first RRAM device 440a, and a top electrode 445b of the second RRAM device 440b. The second etch stop layer 450 can be used as an etching mask during the etching process of the top electrode layer 425. The etching of the second etch stop layer 450 and the top electrode layer 425 can stop at the switching oxide layer 423 because the second etch stop layer 450 can have high selectivity for etching the metal in the silicon nitride and the switching metal oxide.

[0077] In one embodiment, the switching oxide layer 423 may also be selectively etched to produce the filament-forming layer 443a of the RRAM device 440a and the filament-forming layer 443b of the RRAM device 440b. In other embodiments, the switching oxide layer 423 is not etched during the fabrication of the RRAM devices 440a and 440b and may serve as the filament-forming layers 443a and 443b. The fabrication of the filament-forming layers 443a and 443b may expose one or more portions of the etch stop layer 430a.

[0078] Specifically, portion 425c in the top electrode layer 425 can be selectively etched to produce a first top electrode 445a and a second top electrode 445b. Portion 423c in the switching oxide layer 423 can be selectively etched to produce a first filament-forming layer 443a and a second filament-forming layer 443b. During the etching process of the top electrode layer 425 and / or the switching oxide layer 423, portions 423a and 423b in the switching oxide layer 423 are not etched or are otherwise modified. As discussed in more detail below, each of portions 423a and 423b in the switching oxide layer 423 can be used as a filament-forming region in which a filament can be formed in response to a suitable voltage applied to the RRAM device. The manufacture of filament-forming layers 443a and 443b without etching portions 423a and 423b in the switching oxide layer 423 can avoid device degradation due to the etching process. For example, etching the top electrode layer 425 during the RRAM device manufacturing process may induce the re-deposition of the etched top electrode material on the portion 423c in the switching oxide layer 423. However, this does not lead to deterioration of the performance of the RRAM device to be manufactured, because the portion 423c in the switching oxide layer 423 is not a filament formation region of the RRAM device and the filament formation regions 423a-b are not exposed and affected by the etching process.

[0079] refer to Fig. 4I , a dielectric layer 460 may be fabricated on the exposed portions of the etch stop layers 450a-b and the etch stop layer 430a. The dielectric layer 460 may include any suitable dielectric material, such as silicon dioxide (SiO 2 ) etc. In some embodiments where the switching oxide layer 423 is not etched to produce the filament-forming layers 443 a and 443 b , the dielectric layer 460 may be produced on the etch stop layers 450 a - b and the switching oxide layer 423 .

[0080] refer to Figure 4J , the dielectric layer 460 can be selectively removed to produce the through-hole grooves 461 and 463. For example, the dielectric layer 460 can be patterned and etched to form the through-hole grooves 461 and 463. Since the etch stop layers 450a-b and 430a can resist the etching of the dielectric layer 460, the etching of the dielectric layer 460 can be stopped on the etch stop layers 450a-b. Therefore, the etch stop layers 450a-b can perform high-selectivity etching on the dielectric layer 460 and can protect the first top electrode 445a and the second top electrode 445b during the etching process of the dielectric layer 460. When the entire etch stop layer or a substantial portion of the etch stop layer is not etched during the etching process of the dielectric layer 460, the etching of the dielectric layer 460 can be considered to be stopped at the etch stop layer.

[0081] refer to Figure 4K , one or more portions of the etch stop layers 450a-b may be selectively removed to enlarge the via grooves 461 and 463 and generate via grooves 471 and 473. The via bottoms of the via layers 471 and 473 may contact the first top electrode 445a (e.g., portion 425a of the first top electrode 445a) and the second top electrode 445b (e.g., portion 425b of the second top electrode 445b), respectively. More specifically, for example, the etch stop layer 450a may be patterned and etched to produce the bottom (second portion) of the via groove 471. The etch stop layer 450b may be patterned and etched to produce the bottom (second portion) of the via groove 473. Due to the high selectivity between the etch stop layer and the metal, the etching of the etch stop layers 450a-b may stop on the top electrodes 445a-b, respectively.

[0082] like Figure 4L As shown, the metal vias 413a and 413b of the second interconnect layer 413 can be manufactured by depositing appropriate metal on the via layers 471 and 473. In some embodiments, as shown in FIG. Figure 4MAs shown, the third interconnect layer 415 can be fabricated on the second interconnect layer 413. The third interconnect layer can include metal pads 415a and 415b fabricated on metal vias 413a and 413b, respectively. In some embodiments, metal vias 413a-b and metal pads 415a-b can be fabricated using a dual metal damascene process (e.g., Fig. 9A The process 900 in FIG. 1 is used to manufacture the metal via and the metal pad, wherein the metal via and the metal pad can be manufactured in the same metal deposition and patterning process.

[0083] like Figure 4M As shown, the semiconductor device 400 may include a first RRAM device 440a and a second RRAM device 440b fabricated on metal pads 411a and 411b in a first interconnect layer 411, respectively. The first RRAM device 440a may include a first bottom electrode 421a, a first top electrode 445a, and a first filament formation layer 443a fabricated between the first bottom electrode 421a and the first top electrode 445a. The second RRAM device 440b may include a second bottom electrode 421b, a second top electrode 445b, and a second filament formation layer 443b fabricated between the second bottom electrode 421b and the second top electrode 445b. The first filament formation region 423a and at least a portion 425a of the first top electrode 445a are fabricated on the through hole 431 (also regarded as a "first through hole"). The second filament formation region 423b and at least a portion 425b of the second top electrode 445b are fabricated on the through hole 433 (also regarded as a "second through hole"). In some embodiments, the RRAM device 440a and / or 440b may include a combination of Figures 6A-6E The one or more interface layers, diffusion barrier layers and adhesion layers.

[0084] The metal via 413a of the second interconnect layer 413 may be fabricated in a via trench 471 located on the dielectric layer 460a and the etch stop layer 450a. The metal via 413b of the second interconnect layer 413 may be fabricated in a via trench 473 located on the dielectric layer 460a and the etch stop layer 450b. The metal vias 413a and 413b may directly contact the first top electrode 445a and the second top electrode 445b, respectively.

[0085] When a suitable programming signal (e.g., a set voltage, a reset voltage, etc.) is applied to the first top electrode 445a and the first bottom electrode 421a, a conductive filament may be formed in a portion 423a (also referred to as a “first filament formation region 423a”) in the switching oxide layer 423. Similarly, when a suitable programming signal is applied to the second top electrode 445b and the second bottom electrode 421b, a conductive filament may be formed in a portion 423b (also referred to as a “filament formation region 423b”) of the switching oxide layer 423. For example, each RRAM device 440a-b may have an initial resistance after its manufacture. The initial resistance of the RRAM devices 440a-b may be changed, and the RRAM devices 440a-b may be switched to a lower resistance state through a formation process. During the formation process, a suitable voltage or current signal may be applied to the RRAM devices 440a-b. The application of a voltage or current signal applied to the RRAM device 400a-b can induce the metal material in the top electrode 445a-b to absorb oxygen from the filament formation region 423a-b and generate oxygen vacancies in the filament formation region 423a-b. Therefore, a conductive channel (e.g., a filament) rich in oxygen vacancies can be formed in the filament formation region 423a-b. The portion of the filament formation layer 445a-b that does not contact the bottom electrode 421a-b is not affected by the electric field during the formation process. Only the filament formation region 423a-b in the filament formation layer 423 that contacts the bottom electrode is located between the top electrode and the bottom electrode and is affected by the electric field during the operation of the RRAM device 440a-b. The RRAM device 440a-b can be reset to a high-resistance state by applying a reset signal (e.g., a voltage signal or a current signal) to the RRAM device 440a-b. The application of the reset signal can trigger oxygen to migrate back to the filament forming region 423a-b in the filament forming layer 443a-b and recombine with one or more oxygen vacancies. For example, an interrupted conductive path (not shown) can be formed in the filament forming region 423a-b in the filament forming layer 443a-b during the reset process. The presence of an oxide gap with insufficient oxygen vacancies between the interrupted conductive path and the bottom electrode 421a-b can cause the conductive path to be interrupted. The portion of the filament forming layer 445a-b that does not contact the bottom electrode 421a-b is not affected by the electric field between the top electrode 445a-b and the bottom electrode 421a-b during the reset process. The RRAM device 440a-b can be electrically switched between a high resistance state and a low resistance state by applying a suitable programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device 440a-b.

[0086] The etch stop layer 430 can protect the through-hole device structure of the RRAM device during the process of etching the layer deposited on the RRAM device. The etch stop layer 450 can protect the top electrode in the RRAM device 440a-b during the process of etching the layer deposited on the RRAM device. The etch stop layers 430 and 450 can achieve high etching selectivity during the manufacturing process of the RRAM device 440a-b. The etch stop layer can be used as an etching mask in some etching processes described in the present disclosure, thereby reducing manufacturing costs. The etch stop layers 430 and 450 can also be used as a barrier layer or isolation layer to isolate oxygen diffusion from the dielectric material to the RRAM device to achieve better device uniformity and device operation control. The mechanism for manufacturing crossover circuits described in the present disclosure can enable the manufacture of RRAM devices without the use of isolation layers during the etching process.

[0087] Figure 5A is a schematic diagram showing an example of a crossbar circuit 500 according to some embodiments of the present disclosure. The crossbar circuit 500 may include a crossbar array 501 and a peripheral circuit 505. The crossbar array 501 may include one or more crosspoint device arrays as described in the present disclosure. The crossbar array 501 may include a semiconductor device 400. The peripheral circuit 505 does not include a crosspoint device and / or an RRAM device as described in the present disclosure. The peripheral circuit 505 may include one or more transistors (not shown) for implementing a logic circuit. The peripheral circuit 505 and the crossbar array 501 may be manufactured in combination. Figure 4A The crossbar array 501 is fabricated on the same substrate 410 as described above. The portion of the crossbar array 501 fabricated on the substrate 410 is referred to as substrate 410a in the present disclosure. The portion of the peripheral circuit 505 fabricated on the substrate 410 is referred to as substrate 410b.

[0088] like Figure 5A As shown, a portion of the first etch stop layer 430 (also referred to as "etch stop layer 430b") can be fabricated on the substrate 410b and a portion of the first interconnect layer 411 (e.g., metal pads 411c-d, etc.) fabricated on the substrate 410b. A portion of the dielectric layer 460 is fabricated on the etch stop layer 430b. The peripheral circuit 505 does not include a second etch stop layer fabricated between the etch stop layer 430b and the dielectric layer 460.

[0089] Peripheral circuit 505 may include metal pads 411c and 411d in first interconnect layer 411 and metal vias 413c and 413d in second interconnect layer 413. In some embodiments, peripheral circuit 505 may further include metal pads 415c and 415d in third interconnect layer 415. Metal via 413c may connect metal pads 415c and 411c. Metal via 413d may connect metal pads 415d and 411d. In some embodiments, metal vias 413c and 413d may directly contact metal pads 411c and 411d, respectively. As shown, metal vias 413c and 413d may be fabricated in a via groove located between dielectric layer 460 and first etch stop layer 430b.

[0090] Figure 5B-5L is a schematic diagram showing cross-sectional views of structures 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, 500k, 5001, and 500m for fabricating a crossover circuit 500 according to some embodiments of the present disclosure.

[0091] like Figure 5B As shown, the bottom electrode layer 421 can be deposited on the first interconnect layer 411 and the substrate 410a-b. The bottom electrode layer 421 can be patterned and etched to produce a first bottom electrode 421a and a second bottom electrode 421b. For example, as shown in FIG. Figure 5C As shown, portions of bottom electrode layer 421 deposited on substrate 410b may be removed during etching of bottom electrode layer 421. Thus, etching of bottom electrode layer 421 does not create bottom electrodes on metal pads 411c-d in substrate 410b.

[0092] refer to Figure 5D , a first etch stop layer 430 may be fabricated on the first bottom electrode 421a, the second bottom electrode 421b, the metal pads 411c and 411d, and the upper surface of the substrate 410. The first etch stop layer 430 may be fabricated on the entire surface of the substrates 410a-b. Figure 5E , one or more portions of the first etch stop layer 430 may be selectively removed to expose a portion of the first bottom electrode 421a and a portion of the second bottom electrode 421b. For example, the first etch stop layer 430 may be patterned and etched to produce through holes 431 and 433. The portion of the first etch stop layer deposited on the substrate 410b is not patterned. Figure 5E As shown, no through hole is formed on the etch stop layer 430b.

[0093] refer to Fig. 5F , the switching oxide layer 423 can be fabricated on the etch stop layers 430a-b and in the vias 431 and 433. Figure 5G As shown, the top electrode layer 425 can be fabricated on the switching oxide layer 423. Then, as shown in FIG. Figure 5H As shown, a second etch stop layer 450 may be fabricated on the top electrode layer 425 .

[0094] refer to Fig.5I The second etch stop layer 450 and the top electrode layer 425 can be selectively etched to produce a bonded Figure 4M The RRAM devices 440a and 440b. The etching process may involve patterning and etching the second etch stop layer 450. The etching of the second etch stop layer 450 may stop on the top electrode layer 425. Then, the top electrode layer 425 and the switching oxide layer 423 may be patterned and etched. The etching of the top electrode layer 425 and the switching oxide layer 423 may stop on the etch stop layer 430. More specifically, for example, the etching of the top electrode layer 425 may remove a portion of the top electrode layer 425 deposited on the etch stop layer 430b. The etching of the switching oxide layer 423 may manufacture filament-forming layers 443a and 443b. The etching of the switching oxide layer 423 may remove a portion of the switching oxide layer 423 deposited on the etch stop layer 430b. Therefore, the second etch stop layer 450, the top electrode layer 425, and the portion of the switching oxide layer 423 deposited on the etch stop layer 430b may be removed in the manufacturing of the RRAM devices 440a and 440b.

[0095] like Figure 5J As shown, dielectric layer 460 may be fabricated on etch stop layers 450a, 450b, 430a, and 430b. Figure 5K As shown, via grooves 461, 463, 465, and 467 may be fabricated on dielectric layer 460 by patterning and etching dielectric layer 460. Etching of dielectric layer 460 may stop on etch stop layers 450a, 450b, and / or 430b, and dielectric layers 460a and 460b may be formed. For example, the fabrication process of via grooves 461 and 463 may expose a portion of etch stop layer 450a and a portion of etch stop layer 450b, respectively. The fabrication process of via grooves 465 and 467 may include one or more portions of etch stop layer 430b. Figure 5LAs shown, etch stop layers 450a, 450b, and 430b may be patterned and etched to expand through-hole grooves 461, 463, 465, and 467, and to manufacture through-hole grooves 471, 473, 475, and 477. Through-hole grooves 461, 463, 465, and 467 may be considered as first portions of through-hole grooves 471, 473, 475, and 477, respectively. The etching of etch stop layers 450a and 450b may be stopped on top electrodes 445a and 445b, respectively. The patterning and etching of etch stop layer 450a may expand through-hole groove 461, and may generate the bottom (second portion) of through-hole groove 471. The etching of etch stop layer 430b may be stopped on interconnect layer 411. More specifically, patterning and etching of etch stop layer 430b may expand via trenches 465 and 467 and respectively generate bottoms (second portions) of via trenches 475 and 477. The fabrication of via trenches 475 and 477 may respectively expose a portion of metal pad 411c and a portion of metal pad 411d.

[0096] The etch stop layer disclosed in the present disclosure can protect the via device structure during the etching process of the dielectric layer and the manufacturing process of the peripheral circuit, and can achieve high etching selectivity during the etching process of the dielectric layer. The mechanism for manufacturing the crossover circuit disclosed in the present disclosure can realize the manufacturing of RRAM devices without using spacers during the etching process, and can help promote the integration of RRAM manufacturing into the lower metal interconnection in the CMOS process.

[0097] refer to Figure 5M , suitable metal materials (e.g., Cu, W, etc.) may be deposited on via grooves 471, 473, 475, and 477, respectively, to fabricate metal vias 413a, 413b, 413c, and 413d. Metal vias 413c and 413d may contact metal pads 411c and 411d, respectively. Figure 5A , the metal pads 415a, 415b, 415c, and 415d of the third interconnect layer 415 can be fabricated on the metal vias 413a, 413b, 413c, and 413d, respectively. In some embodiments, the metal vias 413a-b and the metal pads 415a-b can be fabricated using a dual metal damascene process (e.g., Fig. 9A The process is performed by manufacturing the metal vias and metal pads in the same metal deposition and patterning process.

[0098] Fig. 6A , 6B , 6C, 6D, and 6E are schematic diagrams of cross-sectional views of RRAM device examples 600a, 600b, 600c, 600d, and 600e according to some embodiments of the present disclosure.

[0099] like Fig. 6AAs shown, the RRAM device 600a may include a bottom electrode 641, a switching oxide layer 643, an interface layer 645a, and a top electrode 647. The interface layer 645a (also referred to as "interface layer A" or "first interface layer") is fabricated between the top electrode 647 and the switching oxide layer 643.

[0100] The switching oxide layer 643 may include one or more transition metal oxides among binary oxides, ternary oxides, and higher-order oxides, such as TaO x , HfO x 、TiO x 、NbO x 、ZrO x etc., where x can be used to represent an oxide that is oxygen deficient compared to a complete (or terminal) oxide, and the value of x can vary depending on the ratio of oxygen to metal ions in the stoichiometry of the complete oxide, e.g., for HfO x , x≤2.0 (where HfO 2 is a complete oxide), for TaO x , x≤2.5 (where Ta 2 O 5 is a complete oxide). For example, the switching oxide layer 643 may include Ta 2 O 5 For another example, the switching oxide layer 643 may include HfO 2 .

[0101] The interface layer 645a may be and / or include a thin film composed of a first material, and the first material is more chemically stable than the transition metal oxide in the switching oxide layer 643. Therefore, the first material does not react with the transition metal oxide in the switching oxide layer 643. For example, the transition metal oxide in the switching oxide layer may be and / or include one or more transition metal oxides, such as HfO x or TaO y At least one of, wherein x≤2.0 and y≤2.5, the first material may include Al 2 O 3 ,MgO,Y 2 O 3 ,La 2 O 3 wait.

[0102] The interface layer 645a may prevent excessive reaction between the RRAM switching oxide and the electrode due to additional heat exposure of the RRAM device during subsequent fabrication of interconnect layers on the RRAM device.

[0103] The interface layer 645a may have a suitable thickness to achieve a desired forming gas annealing (FGA) resistance. For example, a relatively thick interface layer may have a greater FGA resistance than a relatively thin interface layer. In one embodiment, the interface layer 645a may include Al 2 O 3 、SiO 2 , Y 2 O 3 In some other embodiments, the interface layer 645a may include Al 2 O 3 、SiO 2 , Y 2 O 3 ,La 2 O 3 Continuous film of equal composition.

[0104] In some embodiments, Figure 6B As shown, the RRAM device 600b may include multiple interface layers. For example, the interface layer 645b (also referred to as "interface layer B" or "second interface layer") can be fabricated between the bottom electrode 641 and the switching oxide layer 643. The interface layer 645b can be and / or include a film composed of a second material, and the second material is more chemically stable than the transition metal oxide in the switching oxide layer 643. Therefore, the second material may not react with the transition metal oxide in the switching oxide layer 643. For example, the transition metal oxide in the switching oxide layer can be and / or include one or more transition metal oxides, such as HfO x or TaO y At least one of, wherein x≤2.0 and y≤2.5, the second material may include Al 2 O 3 ,MgO,Y 2 O 3 ,La 2 O 3 The first material in the interface layer 645a and the second material in the interface layer 645b may be the same or different. The interface layer 645b may also be used in the case where a metal nitride is used for one of the bottom electrode or the top electrode.

[0105] The interface layer 645b may have a desired thickness to achieve a desired FGA resistance. For example, a relatively thick interface layer may have a greater FGA resistance than a relatively thin interface layer. In one embodiment, the interface layer 645b may include Al 2 O 3 、SiO 2 , Y 2 O 3In some other embodiments, the interface layer 645b may include Al 2 O 3 、SiO 2 , Y 2 O 3 Continuous film of equal composition.

[0106] like Figure 6C As shown, the RRAM device 600c may include a first diffusion barrier layer 691, a bottom electrode 641, an interface layer 645b, a switching oxide layer 643, an interface layer 645a, a top electrode 647, and a second diffusion barrier layer 693. The bottom electrode 641, the interface layer 645b, the switching oxide layer 643, the interface layer 645a, and the top electrode 647 may be combined with Figure 6A-6B The first diffusion barrier layer 691 can be manufactured in Figures 4A-5M ( Figure 6C The second diffusion barrier layer 693 may be formed between the top electrode 647 and the first interconnect layer 411 (not shown). Figures 4A-5M ( Figure 6C Between the second interconnect layer 413 in (not shown).

[0107] The first diffusion barrier layer 691 and the second diffusion barrier layer 693 may include any suitable material that can prevent the metal in the interconnect layer from diffusing into the RRAM device at the annealing temperature and can exhibit suitable thermal and chemical stability, conductivity, and adhesion. In some embodiments, the first diffusion barrier layer 691 and / or the second diffusion barrier layer 693 may include one or more layers of TaN, TiN, etc.

[0108] The first diffusion barrier layer 691 and / or the second diffusion barrier layer 693 may further improve the annealing resistance of the RRAM device and prevent metal (eg, Cu, Al, W) in the interconnect layer from diffusing into the RRAM device.

[0109] In some embodiments, one or more adhesion layers may be fabricated between the RRAM device 600c and the interconnect layer. Fig.6D As shown, the RRAM device 600c can be manufactured on the first adhesion layer 695. The first adhesion layer 695 can be manufactured on Figure 3A-3B ( Fig.6D On the top interconnect layer in the first interconnect layer 310a in (not shown).

[0110] The second adhesion layer 697 may be fabricated on the RRAM device 600 c and / or the second diffusion barrier layer 693 . Figures 3A-4F ( Fig.6DOne or more interconnect layers 310b (not shown) may be fabricated on the second adhesion layer 697. Each of the first adhesion layer 695 and the second adhesion layer 697 may include a layer or multiple layers of Ti, Ta or a conductive oxide, such as Ti 4 O 7 wait.

[0111] In some embodiments, the first diffusion barrier layer 691 and / or the second diffusion barrier layer 693 may be omitted in the RRAM 600d. Fig. 6E As shown, the RRAM device 600e may include the RRAM device 600b fabricated on the first adhesion layer 695. A second adhesion layer 697 may be fabricated on the top electrode 647.

[0112] Figure 7 is a flow chart illustrating an example process 700 including fabricating a crossbar circuit for CMOS-compatible RRAM according to some embodiments of the present disclosure.

[0113] As shown, process 700 may begin at 705, where a substrate including a first interconnect layer is provided. The first interconnect layer may include one or more metal pads and / or metal vias for connecting a bottom electrode to one or more other components of a semiconductor device. The substrate may be Figure 4A The substrate 410 in FIG.

[0114] In 710, one or more bottom electrodes may be fabricated on the first interconnect layer. For example, a first bottom electrode of a first RRAM device may be fabricated on a first metal pad or metal via in the first interconnect layer. The first metal pad or metal via may be connected to a first transistor. As another example, a second bottom electrode of a second RRAM device may be fabricated on a second metal pad or metal via in the first interconnect layer. The second metal pad or metal via may be connected to a second transistor. The bottom electrodes may include bottom electrodes 421a and 421b, and may be combined as shown in FIG. Figure 4B , 5B and 5C for manufacture.

[0115] The manufacture of one or more bottom electrodes may involve depositing a bottom electrode layer of one or more non-reactive metals (e.g., Pt, Pd, Ir, etc.) on the first interconnect layer and the substrate using physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD) techniques, sputtering deposition techniques, atomic layer deposition (ALD) techniques, and / or any other suitable deposition techniques. In some embodiments, the manufacture of the bottom electrode layer may involve depositing one or more layers of Pt. The bottom electrode layer may then be patterned and etched to manufacture the bottom electrode. In some embodiments, the manufacture of the bottom electrode layer may include depositing a metal nitride on a metal pad or metal via in the first interconnect layer. The metal nitride may include, for example, tantalum nitride, titanium nitride, etc.

[0116] In 715, a first etch stop layer may be fabricated on the substrate and the one or more bottom electrodes. Fabricating the first etch stop layer may involve depositing one or more materials that are resistant to etching of a dielectric layer (e.g., a SiO2 layer) fabricated on the first etch stop layer. For example, fabricating the first etch stop layer may involve depositing one or more layers of SiN using a CVD technique, an ALD technique, a magnetron sputtering technique, etc. x 、SiO x The first etch stop layer may be deposited on the bottom electrode and the portion of the substrate not covered by the bottom electrode. The first etch stop layer may be a combination of Figure 4C and 5D The etching stop layer 430 .

[0117] In 720, one or more through holes may be fabricated on the first etch stop layer to expose at least a portion of each bottom electrode. For example, the first etch stop layer may be patterned and etched to generate a first through hole in the first etch stop layer to expose a portion of the first bottom electrode and / or to generate a second through hole in the first etch stop layer to expose a portion of the second bottom electrode. A through hole bottom of the first through hole and a through hole bottom of the second through hole may directly contact the first bottom electrode and the second bottom electrode, respectively. The through hole may include a bonding Figure 4D and 5E Through holes 431 and 433 are described in .

[0118] In 725, a switching oxide layer may be fabricated on the first etch stop layer and in the via. For example, fabricating the switching oxide layer may involve depositing one or more switching metal oxides, such as TaO x , HfO x 、TiO x 、NbO x 、ZrO x Etc. The switching oxide layer can be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD) and / or any other suitable deposition technique. In some embodiments, the switching oxide layer can be manufactured using bottom anti-reflective coating (BARC) and / or deep ultraviolet (DUV) lithography.

[0119] The switching oxide layer may be conformally fabricated along the sidewalls of the via on a portion of the first etch stop layer surrounding the via and on an exposed portion of the bottom electrode. The fabrication of the switching oxide layer may partially fill the via. The switching oxide layer may be fabricated in accordance with a combination of the above Figure 4E and 5F The above is manufactured.

[0120] In 730, a top electrode layer may be fabricated on the switching oxide layer. For example, fabricating the top electrode layer may involve depositing one or more suitable metal materials that are conductive and reactive to the switching oxide in the switching oxide layer, such as Ta, Hf, Ti, TiN, TaN, etc. The top electrode layer may be fabricated on the switching oxide layer and along the sidewalls of the through hole. The top electrode layer may be a combination of Figure 4F and 5G The top electrode layer 425. In some embodiments, the top electrode layer can be manufactured using an in-situ pre-sputtering etching technique.

[0121] In 735, a second etch stop layer may be fabricated on the top electrode layer. Fabricating the second etch stop layer may involve depositing one or more materials that are resistant to etching of the dielectric layer fabricated on the second etch stop layer. For example, fabricating the second etch stop layer may involve depositing one or more layers of SiN using CVD techniques, ALD techniques, magnetron sputtering techniques, etc. x 、SiO x N y In some embodiments, the second etch stop layer can be formed by completely filling the through hole. Figure 4G and 5H The etch stop layer 450 described in .

[0122] In 740, one or more top electrodes may be fabricated by selectively removing one or more portions of the second etch stop layer and the top electrode layer. For example, the second etch stop layer may be patterned. The second etch stop layer and the top electrode layer may then be etched to fabricate a first top electrode of the first RRAM device and a second top electrode of the second RRAM device. The etching of the second etch stop layer and the top electrode layer may stop on the switching oxide layer or the first etch stop layer. The top electrode may include top electrodes 450a-b and may be formed in accordance with a combination of the above Figure 4H and 5I The above is manufactured.

[0123] In one embodiment, at 745, a portion or portions of the switching oxide layer may be selectively removed to produce a filament formation layer (eg, Figure 4H and 5I In some other embodiments, the switching oxide layer may not be etched and may be used as a filament forming layer of the RRAM device. 745 and 740 may be performed sequentially, simultaneously, or substantially simultaneously.

[0124] In 750, a dielectric layer may be fabricated on the second etch stop layer and the first etch stop layer. Fabricating the dielectric layer may involve depositing one or more suitable materials that may be used as an interlayer dielectric (ILD). For example, fabricating the second isolation layer may involve depositing one or more layers of SiO 2 The ILD material may be deposited on the upper surface of the first etch stop layer and the upper surface of the second etch stop layer. The dielectric layer may be the dielectric layer 460 and may be formed in accordance with the combination of the above Fig. 4I and 5J The above is manufactured.

[0125] In 755, a second interconnect layer may be fabricated. The second interconnect layer may include a plurality of metal pads and / or metal vias. For example, the second interconnect layer may include a first metal via and a second metal via fabricated on the dielectric layer and the second etch stop layer. For another example, the second interconnect layer may include a third metal via fabricated on the dielectric layer and the first etch stop layer. The third metal via may be part of a peripheral circuit that does not include an RRAM device.

[0126] For example, the dielectric layer can be patterned and etched to produce the top of one or more through-hole grooves (e.g., the first part of the first through-hole groove, the first part of the second through-hole groove, the first part of the third through-hole groove, etc.). The etching of the dielectric layer can stop on the etched second etch stop layer and the exposed first etch stop layer. Then the second part of the first through-hole groove and the second part of the second through-hole groove can be produced by patterning and etching the second etch stop layer. The etching of the second etch stop layer can stop on the top electrode (e.g., the first top electrode of the first RRAM device, the second top electrode of the second RRAM device, etc.). The second part of the third through-hole groove can be produced by patterning and etching the first etch stop layer in the peripheral circuit. Suitable metal materials (e.g., Cu, Al, W, etc.) can be deposited in the through-hole groove and patterned to produce one or more metal vias and / or metal pads. The metal material can be deposited using CVD, PVD and / or any other suitable deposition technique. In some embodiments, manufacturing the second interconnect layer may include manufacturing a combination of Figure 4J-4M and metal vias 413a, 413b, 413c and 413d described in 5K-5M.

[0127] Figure 8 is a flow chart illustrating an example process 800 for fabricating one or more interconnect layers according to some embodiments of the present disclosure.

[0128] In 810, a via layer including one or more metal vias may be fabricated. To fabricate the via layer, a first dielectric layer of a first dielectric material may be fabricated in 811. For example, the first dielectric material (e.g., Si 3 N 4 , SiO 2 The layer (etc.) can be deposited using a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), sputtering, etc.

[0129] The first dielectric layer may be patterned to create one or more vias at 813. The first dielectric layer may be patterned using any suitable dry or wet etching technique.

[0130] In 815, one or more suitable metal materials may be deposited on the vias and patterned to produce one or more metal vias. For example, the first vias may be filled by depositing Cu, Al, W, and / or any other suitable metal using CVD, PVD, and / or any other suitable deposition techniques.

[0131] In 817, an annealing process is performed. For example, the first via layer can be annealed at a suitable temperature (e.g., 350° C.-450° C.) in a forming gas environment for a suitable time (e.g., 15-30 minutes). The forming gas may include nitrogen (N 2 ) and hydrogen (H 2 ) in a suitable ratio (e.g. 95:5, 90:10, etc.).

[0132] In 820, a metal layer including one or more metal pads may be fabricated on the via layer. To fabricate the metal layer, a second dielectric layer of a second dielectric material may be fabricated in 821. For example, the second dielectric material (e.g., SiO 2 、Si 3 N 4 ) layer can be deposited on the via layer using a suitable deposition technique, such as chemical vapor deposition (CVD), ALD, sputtering, etc.

[0133] The second dielectric layer may be patterned to create one or more trenches at 823. The second dielectric layer may be patterned using any suitable dry or wet etching technique.

[0134] In 825, one or more suitable metal materials may be deposited in the trenches and patterned to produce one or more metal pads. For example, the second via may be filled by depositing Cu, Al, W, and / or any other suitable metal using CVD, PVD, and / or any other suitable deposition technique.

[0135] In 827, an annealing process is performed. For example, the metal layer can be annealed in a forming gas environment at a suitable temperature (e.g., 350-450°) for a suitable time (e.g., 15-30 minutes). The forming gas can include a mixture of nitrogen (N2) and hydrogen (H2) in a suitable ratio (e.g., 95:5, 90:10, etc.).

[0136] Process 800 can be iteratively performed to manufacture a suitable number of interconnect layers. For example, process 800 can loop back to 810 after performing 820, and manufacture a second via layer on the metal layer in 820. Specifically, a third dielectric layer of a third dielectric material can be manufactured. The third dielectric material can be patterned to generate one or more third vias. One or more suitable metal materials can be deposited in the third via to manufacture one or more metal vias. Then an annealing process can be performed. In some embodiments, a second metal layer can be manufactured on the second via layer. More via layers and / or metal layers can be manufactured by iteratively performing 810 and / or 820.

[0137] Fig. 9A is a flow chart illustrating an example process 900 for fabricating an interconnect structure including metal vias and metal pads in one process. Figure 9B-9G A schematic diagram showing a cross-sectional view of a structure of an interconnect structure 990 manufactured by implementing the process 900 according to some embodiments of the present disclosure.

[0138] As shown, process 900 may begin at 905 by fabricating a dielectric layer on a substrate. The substrate may be and / or include one or more transistors, interconnect layers, etc. The deposition of the dielectric layer may involve deposition of one or more interlayer dielectrics (ILDs), such as SiO 2 、Si 3 N 4 、Al 2 O 3 Etc. For example, Fig. 9B As shown, a dielectric layer 963 can be fabricated on a substrate 961. In some embodiments, a resist 965 can be fabricated on the dielectric layer 963.

[0139] In 910, the dielectric layer may be patterned and partially etched. That is, the dielectric layer is partially deeply etched. For example, Fig. 9C As shown, the through hole 971 can be manufactured by partially etching the dielectric layer 963 and the resist 965.

[0140] In 915, the partially etched dielectric layer may be completely etched to generate vias and / or trenches. Due to conformal etching, the dielectric layer is completely etched in depth, but the etch profiles of the vias and trenches are maintained. For example, Fig.9D As shown, the via 973 and the trench 975 may be generated by etching the partially etched dielectric layer 963 and the resist 965 .

[0141] At 920, a barrier layer may be fabricated. Fig.9E As shown, a barrier layer 967 (eg, a layer containing Ta or TaN) may be deposited on the fully etched dielectric layer and on the sidewalls of the via 973 and the trench 975 .

[0142] In 925, metal may be deposited to generate metal vias and metal pads. For example, a thin Cu crystal layer may be deposited by physical vapor deposition (PVD), followed by electroplating Cu to fill the vias and trenches. The metal deposition may also generate one or more metal wirings. Fig.9E As shown, metal may be deposited (eg, by plating) in via 973 and trench 975 to create metal via 981 and metal pad 983 , respectively.

[0143] At 930, a chemical mechanical polishing (CMP) process is performed. Fig.9F As shown, metal vias 981, metal pads 983, and metal wiring (not shown) may be patterned and processed in a CMP process to remove excess Cu and planarize the surface. Figure 9G As shown, a capping layer 969 (eg, a SiN layer) may be deposited.

[0144] At 935, the metal vias and metal pads may be annealed. For example, Figure 9G The interconnect structure 990 in FIG. 1 may be annealed in a forming gas flow (eg, a mixture of N 2 and H 2 ) at an annealing temperature (eg, 350-450° C.) for an appropriate time (eg, 15-30 minutes).

[0145] For the sake of brevity of explanation, the method of the present disclosure is depicted and described as a series of actions. However, actions according to the present disclosure can occur in various orders and / or simultaneously, and occur together with other actions that are not proposed and described in the present disclosure. In addition, not all actions of explanation can be required to realize the method according to the disclosed subject matter. In addition, those skilled in the art will understand and recognize that the method can be represented as a series of mutual states via state diagrams or events alternatively.

[0146] As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target size in some embodiments, within ±10% of a target size in some embodiments, within ±5% of a target size in some embodiments, within ±2% of a target size in some embodiments, within ±1% of a target size in some embodiments, and within ±0.1% of a target size in some embodiments. The terms "approximately" and "about" may include a target size. Unless otherwise specified or apparent from the context, all numerical values ​​described herein are modified by the term "about."

[0147] As used herein, a range includes all values ​​within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-ranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, and fractions thereof.

[0148] The present disclosure has been described in detail in the above description. However, it is obvious that the present disclosure can be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.

[0149] The terms "first", "second", "third", "fourth", etc. used in this document are marks used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

[0150] The word "example" or "exemplary" as used herein means serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be understood as being more preferred or advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In this application, the term "or" means including "or" rather than excluding "or". That is, unless otherwise specified or as can be seen from the context, "X includes A or B" means any natural inclusive permutation and combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. In addition, "a" and "an" used in this application and the appended claims should generally be understood as "one or more", unless otherwise specified or as can be clearly indicated from the context as being directed to a singular form. "One embodiment" or "an embodiment" mentioned in this specification means that a specific feature, structure or characteristic associated with the embodiment is included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily all refer to the same embodiment.

[0151] As used herein, when an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.

[0152] Although it is obvious to those skilled in the art that additional changes and modifications may be made to the present disclosure after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of various embodiments are not intended to limit the scope of the claims, which themselves merely describe the disclosed technical features.

Claims

1. A device comprising: The first RRAM device, comprising: fabricating a first bottom electrode on the first interconnect layer; a first top electrode; and fabricating a first filament-forming layer between the first bottom electrode and the first top electrode, wherein the first filament-forming layer comprises at least one switching metal oxide, a first filament-forming region in the first filament-forming layer and at least a portion of the first top electrode are fabricated in a first through hole in a first etch stop layer; fabricating a second etch stop layer on the first top electrode; fabricating a dielectric layer on the second etch stop layer; and A first metal via of a second interconnect layer is fabricated in the second etch stop layer and the dielectric layer, wherein the first top electrode is connected to a bit line through the first metal via in the second interconnect layer.

2. The device according to claim 1, wherein: The first bottom electrode is fabricated on a first metal pad in the first interconnect layer, the first metal pad in the first interconnect layer being connected to a first transistor.

3. The device according to claim 1, wherein: The switching oxide includes HfO x 、TaO x 、TiO x 、NbO x 、ZrO x At least one of .

4. The device according to claim 3, wherein: The first RRAM device further includes an interface layer fabricated between the first top electrode and the first filament-forming layer, wherein the interface layer includes at least one of Al2O3, MgO, Y2O3, or La2O3.

5. The device according to claim 3, wherein: The first RRAM device further includes an interface layer fabricated between the first bottom electrode and the first filament-forming layer, wherein the interface layer includes at least one of Al2O3, MgO, Y2O3, or La2O3.

6. The device according to claim 1, wherein: The interface layer includes SiO2.

7. The device according to claim 6, wherein: The first etch stop layer includes at least one of silicon nitride or silicon oxynitride.

8. The device according to claim 6, wherein: The second etch stop layer includes at least one of silicon nitride or silicon oxynitride.

9. The apparatus of claim 1 , further comprising a second RRAM device, the second RRAM device comprising: manufacturing a second bottom electrode on the first interconnect layer; a second top electrode; and A second filament-forming layer is fabricated between the second bottom electrode and the second top electrode, wherein a second filament-forming region of the second filament-forming layer and at least a portion of the second top electrode are fabricated in a second through hole of the first etch stop layer.

10. The device according to claim 9, wherein: The second bottom electrode is fabricated on a second metal pad in the first interconnect layer, and the second metal pad in the first interconnect layer may be connected to a second transistor.

11. The device of claim 9, wherein a second metal via in the second interconnect layer is fabricated on the dielectric layer and the second etch stop layer, and the second bottom electrode can be connected to a bit line through the second metal via of the second interconnect layer.

12. The apparatus according to claim 9, further comprising: Peripheral circuits, including: a third metal pad in the first interconnect layer; and A third metal via in the second interconnect layer, wherein a portion of the first etch stop layer is fabricated on a third metal pad in the first interconnect layer, the third metal via in the second interconnect layer is fabricated in a third via groove located between a dielectric layer and a portion of the first etch stop layer, and the peripheral circuit does not include the second etch stop layer.

13. The apparatus of claim 12, wherein a third metal via in the second interconnect layer connects a third metal pad in the first interconnect layer to a metal pad in a third interconnect layer.

14. A method comprising: fabricating one or more bottom electrodes on a substrate including a first interconnect layer; fabricating a first etch stop layer on the substrate and the one or more bottom electrodes; making one or more through holes in the first etch stop layer to expose a portion of each bottom electrode; fabricating a switching oxide layer on the first etch stop layer, wherein at least a portion of the switching oxide layer is fabricated on an exposed portion of the bottom electrode; fabricating a top electrode layer on the switching oxide layer; fabricating a second etch stop layer on the switching oxide layer; and One or more top electrodes are fabricated by selectively removing one or more portions of the second etch stop layer and the second etch stop layer.

15. The method according to claim 14, wherein: Fabricating the one or more bottom electrodes on the first interconnect layer includes fabricating a first bottom electrode on a first metal pad in the first interconnect layer, and fabricating the one or more through holes on the first etch stop layer includes fabricating a first through hole in the first etch stop layer to expose a portion of the first bottom electrode.

16. The method according to claim 15, wherein: Fabricating one or more top electrodes includes: patterning the second etch stop layer; and The second etch stop layer and the top electrode layer are etched.

17. The method of claim 16, wherein fabricating the one or more bottom electrodes on the first interconnect layer comprises fabricating a second bottom electrode on a second metal pad in the first interconnect layer, and fabricating the one or more through holes in the first etch stop layer comprises fabricating a second through hole in the first etch stop layer to expose a portion of the second bottom electrode.

18. The method according to claim 14, further comprising: fabricating a dielectric layer on the second etch stop layer; and A second interconnect layer is manufactured to connect the first interconnect layer to a third interconnect layer, wherein a first metal via in the second interconnect layer is manufactured in the dielectric layer and the second etch stop layer, and a first metal pad in the first interconnect layer is connected to a first metal pad in the third interconnect layer through the first metal pad in the second interconnect layer.

19. The method according to claim 18, wherein: Producing the second interconnect layer comprises: patterning and etching the dielectric layer to produce a first portion of a first via trench; patterning and etching the second etch stop layer to produce a second portion of the first via trench; A metal material is deposited in the first via trench to produce a first metal via of the second interconnect layer.

20. The method of claim 19, wherein etching of the dielectric layer stops on the second etch stop layer, and etching of the second etch stop layer stops on the top electrode layer.

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