Defect information extraction method of ferroelectric capacitor dielectric layer
By performing polarization state flips and step voltage detection on the ferroelectric capacitor, combined with defect concentration assignment processing, the problem of inability to completely extract ferroelectric capacitor defect information in the prior art is solved, and a more complete defect analysis and optimization effect is achieved.
Patent Information
- Application Number
- CN202510124662.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-26
- Publication Date
- 2025-05-13
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The prior art cannot fully extract defect information inside the ferroelectric capacitor, resulting in unsatisfactory subsequent optimization results.
By flipping the polarization state of the preset number of times to be measured, and applying a gradually increasing step voltage to both ends, detecting leakage current, determining the defect concentration in the relevant response area, and performing assignment processing to extract defect information.
A more complete analysis of the internal defect information of ferroelectric capacitors is achieved, and changes in defect information can be collected in real time, improving the effect of subsequent optimization.
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Figure CN119986455A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of capacitor dielectric performance testing, and in particular to a method for extracting defect information of a ferroelectric capacitor dielectric layer. Background Art
[0002] In the current era of big data, users' demand for memory is constantly increasing, requiring the emergence of non-volatile memory with larger storage capacity, faster speed and lower power consumption. In recent years, emerging memories such as FeRAM (Ferroelectric Random Access Memory), PRAM (Phase-change RAM), RRAM (Resistive RAM), MRAM (Magnetoresistive RAM) are both non-volatile memories and have the high performance characteristics of random access memories. Among them, FeRAM has attracted widespread attention due to its advantages such as low energy consumption, easy miniaturization, good CMOS (Complementary Metal-Oxide-Semiconductor) compatibility, long data retention time, fast write speed and excellent scalability.
[0003] Ferroelectric capacitors are the basic components of ferroelectric memories and ferroelectric transistors. They utilize the spontaneous polarization properties of ferroelectric materials, which can change their polarization state when an electric field is applied, and maintain this state even after the electric field is removed. When reading, if the polarization direction of the ferroelectric capacitor is consistent with the read voltage, the polarization state remains unchanged and the current changes slightly; if the polarization direction is opposite to the read voltage, the polarization state will flip, resulting in a detectable charge flow. The defects of ferroelectric capacitors can come from imperfections in the material itself, errors in the manufacturing process, or damage during use. These defects may affect the key properties of ferroelectric capacitors, such as polarization strength, fatigue characteristics, retention characteristics (data retention ability), etc., thereby affecting the reliability and performance of devices built based on ferroelectric capacitors.
[0004] The existing leakage current defect extraction method of ferroelectric capacitors only analyzes the corresponding area of the test leakage current, and has different pairs of response areas under different relaxation energies and test voltages. However, it cannot analyze the impact of the corresponding area on the leakage current, and cannot fully characterize the contribution of defects in ferroelectric capacitors to the leakage current, making the subsequent optimization effect based on the defect extraction results unsatisfactory. Summary of the invention
[0005] The purpose of the embodiments of the present disclosure is to provide a method for extracting defect information of a dielectric layer of a ferroelectric capacitor, so as to solve the problem in the prior art that the defect information inside the ferroelectric capacitor cannot be completely extracted.
[0006] The embodiments of the present disclosure adopt the following technical scheme: a method for extracting defect information of a ferroelectric capacitor dielectric layer, comprising: flipping the polarization state of the ferroelectric capacitor to be tested a preset number of times; applying a step voltage that gradually increases according to a preset step size to both ends of the ferroelectric capacitor to be tested, and obtaining the leakage current of the ferroelectric capacitor to be tested under each step of the step voltage; determining the relevant response area of each leakage current based on the leakage current of each step of the step voltage; determining the defect concentration of all the relevant response areas, and assigning values to the relevant response areas based on the defect concentration to obtain the defect information of the ferroelectric capacitor to be tested.
[0007] In some embodiments, the step voltage gradually increasing according to a preset step size is applied to both ends of the ferroelectric capacitor to be tested, and the leakage current of the ferroelectric capacitor to be tested under each step voltage is obtained, including: applying a step voltage gradually increasing according to a preset step size to both ends of the ferroelectric capacitor to be tested, and the application time of each step of the step voltage is a preset time length; acquiring the leakage current of the ferroelectric capacitor to be tested under the step voltage in real time, and taking the average value of the leakage current in the tail interval of the preset time length as the leakage current of the ferroelectric capacitor to be tested under the step voltage.
[0008] In some embodiments, the tail interval is from the tth second after the start time of the preset duration to the end of the preset duration.
[0009] In some embodiments, the preset step size is between 0.02V and 0.05V.
[0010] In some embodiments, determining the relevant response area of each leakage current based on the leakage current of each step voltage includes: substituting each leakage current into a thermally activated trapping model, determining the spatial position information and energy level position information of the defect forming each leakage current, and obtaining the relevant response area of the leakage current.
[0011] In some embodiments, determining the defect concentration of all the relevant response regions includes: determining a current density corresponding to each leakage current; and determining the defect concentration of the relevant response region according to the current density.
[0012] In some embodiments, the relevant response area is assigned a value according to the defect concentration to obtain defect information of the ferroelectric capacitor to be tested, including: assigning a value to the relevant response area based on the defect concentration; assigning a value to the overlapping area of the relevant response areas of adjacent leakage currents according to the larger value of the defect concentration according to the defect concentration of the relevant response area, and after forming a new relevant response area, assigning a value to the overlapping area with the relevant response area of the next leakage current, until the assignment of the overlapping areas of the relevant response areas of all leakage currents is completed.
[0013] In some embodiments, after assigning the relevant response area based on the defect concentration, the method further comprises: arranging all the leakage currents in ascending order, and performing the assignment process on the relevant response area of the leakage current in the arranged order.
[0014] In some embodiments, after the overlapping areas of the relevant response areas of all the leakage currents are assigned values, it also includes: establishing a three-dimensional image for display based on the spatial position information, energy level position information and defect concentration of all the relevant response areas, wherein the horizontal axis of the three-dimensional image represents the spatial position information of the defect, the vertical axis represents the energy level position information, and the image color represents the defect concentration.
[0015] In some embodiments, obtaining the leakage current of the ferroelectric capacitor to be measured under each step voltage includes: collecting the leakage current of the ferroelectric capacitor to be measured under each step voltage through an IV sweep module.
[0016] The beneficial effects of the embodiments disclosed herein are as follows: by detecting the leakage current of the ferroelectric capacitor to be tested under gradually increasing step voltages, the changes in the relevant response areas where the defects of the ferroelectric capacitor are located during a complete voltage application process are analyzed, and the relevant response areas are assigned values in combination with the defect concentration to obtain the contribution degree of the defects in each relevant response area to the leakage current, thereby realizing real-time collection of the change information of the internal defect information of the ferroelectric capacitor, achieving the purpose of more complete analysis of the failure behavior of the device, and making the subsequent optimization effect based on the defect extraction results better. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0018] Figure 1A flow chart of a method for extracting defect information of a ferroelectric capacitor dielectric layer provided in one or more embodiments of this specification;
[0019] Figure 2 A schematic diagram of a relevant response area of a leakage current corresponding to a voltage at a stage provided by one or more embodiments of this specification;
[0020] Figure 3 A schematic diagram of the relevant response areas of adjacent leakage currents provided for one or more embodiments of this specification;
[0021] Figure 4 Another schematic diagram of the relevant response area of adjacent leakage current provided for one or more embodiments of the present specification;
[0022] Figure 5 A schematic diagram of the three-dimensional image results of the initial state and 100K polarization state flips provided in one or more embodiments of this specification. DETAILED DESCRIPTION
[0023] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.
[0024] In the current era of big data, users' demand for memory is constantly increasing, requiring the emergence of non-volatile memory with larger storage capacity, faster speed and lower power consumption. In recent years, emerging memories such as FeRAM, PRAM, RRAM, MRAM, etc. are both non-volatile memories and have the high-performance characteristics of random access memory. Among them, FeRAM has attracted widespread attention due to its advantages such as low energy consumption, easy miniaturization, good CMOS compatibility, long data retention time, fast writing speed and excellent scalability.
[0025] Ferroelectric capacitors are the basic components of ferroelectric memories and ferroelectric transistors. They utilize the spontaneous polarization properties of ferroelectric materials, which can change their polarization state when an electric field is applied, and maintain this state even after the electric field is removed. When reading, if the polarization direction of the ferroelectric capacitor is consistent with the read voltage, the polarization state remains unchanged and the current changes slightly; if the polarization direction is opposite to the read voltage, the polarization state will flip, resulting in a detectable charge flow. The defects of ferroelectric capacitors can come from imperfections in the material itself, errors in the manufacturing process, or damage during use. These defects may affect the key properties of ferroelectric capacitors, such as polarization strength, fatigue characteristics, retention characteristics (data retention ability), etc., thereby affecting the reliability and performance of devices built based on ferroelectric capacitors.
[0026] The existing leakage current defect extraction method of ferroelectric capacitors only analyzes the corresponding area of the test leakage current, and has different pairs of response areas under different relaxation energies and test voltages. However, it cannot analyze the impact of the corresponding area on the leakage current, and cannot fully characterize the contribution of defects in ferroelectric capacitors to the leakage current, making the subsequent optimization effect based on the defect extraction results unsatisfactory.
[0027] In order to solve the above problems, the present disclosure provides a method for extracting defect information of a ferroelectric capacitor dielectric layer, and its flow chart is as follows: Figure 1 As shown, it mainly includes steps S10 to S40:
[0028] S10, performing a preset number of polarization state flips on the ferroelectric capacitor to be tested.
[0029] The defects of ferroelectric capacitors come from the imperfections of the material itself, errors in the manufacturing process or damage during use. In order to obtain a stable and complete picture of the defects of ferroelectric capacitors, the polarization state of the ferroelectric capacitor to be tested should be flipped a preset number of times before the actual defect extraction, so that its defects gradually appear and tend to stabilize during the polarization state flipping process.
[0030] In this embodiment, the preset number of times CYCLE can be 1, 10, 100, 1000, 10K and 100K. When actually testing, the defects of the ferroelectric capacitor to be tested that has undergone different preset times of polarization state reversal can be extracted separately to analyze the influence of different polarization state reversal times on the defect situation of the ferroelectric capacitor. It should be noted that in order to avoid the influence of defects in different ferroelectric capacitors on the defect extraction results due to defects in processes and materials, a fixed ferroelectric capacitor can be set to perform polarization state reversal for different preset times, and after each preset number of polarization state reversals is reached, a defect extraction is performed, and then the polarization state of the ferroelectric capacitor is reversed again until the next preset number of times, and the polarization state reversal process and defect extraction operation are repeated in a cycle, and finally the defect information of the ferroelectric capacitor after different preset times of polarization state reversal is obtained.
[0031] S20, applying a step voltage gradually increasing according to a preset step length to both ends of the ferroelectric capacitor to be tested, and obtaining the leakage current of the ferroelectric capacitor to be tested under each step voltage.
[0032] After the polarization state of the ferroelectric capacitor to be tested has been flipped for a preset number of times, a DC step voltage is applied to both ends of the ferroelectric capacitor to be tested, and the leakage current of the ferroelectric capacitor to be tested under the current step voltage is detected. The step voltage in this embodiment is gradually increased according to a preset step length, which can specifically start from 0V until the step voltage increases to a preset maximum value, and the preset step length is between 0.02V and 0.05V. The specific setting can be adjusted according to the actual measurement accuracy. The smaller the preset step length, the higher the measurement accuracy. This embodiment does not limit its specific value.
[0033] In addition, the application duration of each section of step voltage is preset duration, so that the state of ferroelectric capacitor to be measured is stable, and the value of the corresponding leakage current obtained is also more accurate. The preset duration in the present embodiment can be 2 seconds, when each section of step voltage is actually applied, the leakage current of the ferroelectric capacitor to be measured under each section of step voltage can be collected in real time by IV sweep (current-voltage scanning) module in Keysight 1500B series semiconductor parameter analyzer, and the mean of the leakage current in the tail interval in the preset duration is used as the leakage current of the ferroelectric capacitor to be measured under the current step voltage, and the ferroelectric capacitor state is stable in the tail interval, and the mean of the leakage current in this part interval is taken as the extraction result to ensure that the leakage current value is more accurate, which is conducive to the accuracy improvement of subsequent defect analysis results. In this embodiment, the tail interval is from the tth second after the start time of the preset time length to the end of the preset time length. For example, the preset time length is 2 seconds, and the tth second can be 1.4 seconds, that is, the tail interval is from 1.4 seconds to 2 seconds. The leakage current of the ferroelectric capacitor to be tested under the current step voltage is the average of the leakage current in the time period from 1.4 seconds to 2 seconds.
[0034] S30, determining a relevant response region of each leakage current according to the leakage current of each step voltage.
[0035] When ferroelectric capacitors are working, their leakage current may come from the following aspects:
[0036] (1) Intrinsic leakage current: Determined by the physical properties of the ferroelectric material itself, under ideal conditions, there is a tiny intrinsic leakage current even in the absence of defects.
[0037] (2) Defect-related leakage current: caused by point defects (such as vacancies, interstitial atoms), line defects (such as dislocations), or body defects (such as precipitates) in the material. These defects can act as traps or scattering centers for carriers, leading to additional leakage current paths.
[0038] (3) Interface leakage current: occurs at the interface between the ferroelectric layer and the electrode, which may be caused by interface states or poor contact.
[0039] The relevant response region refers to the specific position or range in the ferroelectric capacitor that has a significant impact on the leakage current when a specific voltage is applied. These regions can be divided according to different physical mechanisms, and their spatial distribution and energy level position will affect the behavior of the leakage current, mainly including spatial position information and energy level position information. Among them, the spatial position information mainly refers to the physical position of these response regions in the device, such as close to the electrode interface, located inside the ferroelectric layer, or distributed along the grain boundary. The energy level position information indicates the energy position of the trap state or defect state in these regions relative to the bottom of the conduction band or the top of the valence band. Trap states of different depths will have different degrees of influence on the capture and release of carriers.
[0040] When different stage voltages are applied to a ferroelectric capacitor, the change in its leakage current can reflect the role of each relevant response region. For example, in the low voltage region, the intrinsic leakage current is dominant because the energy provided at this time is not enough to activate most defect states; as the voltage increases, some shallow traps begin to be activated, causing the leakage current to gradually increase; further increasing the voltage will cause deep traps to be activated, and may also trigger other nonlinear effects (such as breakdown), causing the leakage current to rise sharply. Therefore, this application analyzes the leakage current corresponding to the step-by-step increase in voltage in the relevant response region, and uses this as the main basis and data support for the analysis of internal defects of ferroelectric capacitors.
[0041] In actual implementation, all leakage currents at different stages of voltage under the current preset number of times are substituted into the thermally activated trapping model (TAT) to analyze the process of carrier capture and release in the ferroelectric capacitor dielectric layer, so as to determine the spatial position information and energy level position information of the defects that form each leakage current, and finally obtain the relevant response area of the leakage current and present it in the coordinate system.
[0042] Specifically, the electron capture (τ c ) time constant and emission (τ e )Time constant:
[0043]
[0044] Among them, x t is the distance between the defect and the lower electrode, N c is the state density at the bottom of the conduction band, t HK is the capacitor thickness, μ c , μ e is the WKB tunneling probability, which is calculated as follows:
[0045]
[0046] in, is the potential barrier height of the dielectric layer, m is the effective mass of the electron, q is the charge mass of the electron, E T is the defect level.
[0047]
[0048] Among them, E c,j is the activation energy of the relevant potential barrier, E_rel is the relaxation energy, V xt =V*x t / t HK , V is the current step voltage.
[0049] Then, the spatial position information XT and the energy level position information ET are directly solved according to the relevant formula of the leakage current ITAT in the TAT model.
[0050]
[0051] Figure 2 The relevant response area of the leakage current corresponding to a stage voltage is shown, such as Figure 2 As shown in the red circle, Figure 2 The horizontal axis represents the spatial position information XT, the vertical axis represents the energy level position information ET, and the red circle represents the defect contribution in this area. In fact, for a defect extraction process, each leakage current corresponds to a coil representing its related response area, which respectively represents the defect contribution to the leakage current in the response area under different stage voltages.
[0052] S40, determining the defect concentrations of all relevant response regions, and performing value assignment processing on the relevant response regions according to the defect concentrations, so as to obtain defect information of the ferroelectric capacitor to be tested.
[0053] The defect concentration NT refers to the number of defects per unit volume in a semiconductor material. This embodiment calculates the defect concentration of the relevant response area, which can be used to analyze the actual contribution of defects in different relevant response areas to the leakage current. Specifically, when determining the defect concentration of the relevant response area, first determine the current density J of each leakage current, and determine the defect concentration NT based on the current density, or directly use the following formula to parse out the defect concentration of the relevant response area:
[0054]
[0055] Among them, Aer is the electrode area, NT is the defect concentration, and Xc is the physical length of the oxide part with maximum leakage, which is 10nm here.
[0056] Subsequently, the relevant response area is assigned a value according to the defect concentration to describe the changes in the defect at different spatial positions and energy level positions, and finally the contribution to the leakage current is intuitively displayed. Specifically, the current relevant response area is assigned a value according to the defect concentration, that is, Figure 2 The correlation response area shown is assigned a value of NT. In fact, the correlation response areas corresponding to each leakage current have different defect concentration values. Then, according to the defect concentrations of the correlation response areas of adjacent leakage currents, the overlapping areas of the two correlation response areas are assigned a value according to the larger value of their defect concentrations. After a new correlation response area is formed, the overlapping area is assigned a value with the correlation response area of the next leakage current until the overlapping area assignments of the correlation response areas of all leakage currents are completed.
[0057] For example, Figure 3 As shown, for the first leakage current, the first relevant response area ( Figure 3 The defect concentration of the second leakage current is NT1, and the second related response region ( Figure 3 The defect concentration of the first leakage current (indicated by the black dotted line) is NT2, and NT1 is greater than NT2, then the overlapping area of the two correlation response areas is assigned the larger NT2, and the remaining part of the first correlation response area of the first leakage current (that is, the part that does not overlap with the second correlation response area of the second leakage current) is still NT1, forming a new correlation response area with uneven defect concentration; then, the defect concentration of this newly formed correlation response area is compared and assigned with the third correlation response area of the next leakage current, as shown in FIG. Figure 4 As shown, the black line part (including the black solid line and the black dotted line) represents the newly formed correlation response area, and the red line part represents the third correlation response area of the next leakage current, whose defect concentration value is NT3, and NT3 is greater than NT2. Then, the assignment for all areas covered by the red coil (including the overlapping area with the black line part) should be NT3, and the portion of the second correlation response area that only overlaps with the first correlation response area and the portion that does not overlap with other correlation response areas is assigned NT2, and the remaining portion of the first correlation response area is assigned NT1; after assigning the correlation response areas of all leakage currents based on the above assignment method, the changes of defects in different spatial positions and energy level positions of ferroelectric capacitors can be completed, and finally the contribution to the leakage current can be intuitively displayed.
[0058] In some embodiments, after assigning values to the relevant response areas using defect concentrations, all leakage currents can be arranged in ascending order, and the assignment of the relevant response areas of the leakage currents can be performed in the order after the arrangement, so as to reduce the amount of calculation in the assignment process. In addition, after the assignment of the overlapping areas of the relevant response areas of all leakage currents is completed, a three-dimensional image can be established for display based on the spatial position information, energy level position information and defect concentration of all relevant response areas, that is, different defect concentration values are mainly represented by different colors, and presented in the image, such as Figure 5 As shown, the horizontal axis of the three-dimensional image represents the spatial position information of the defect, the vertical axis represents the energy level position information, and the image color represents the defect concentration.
[0059] It should be noted that in this embodiment, the defect information extraction after the polarization state of the ferroelectric capacitor to be tested is flipped for different preset times should have corresponding results of presenting a three-dimensional image representing the defect information at different preset times. Figure 5 That is, a schematic diagram showing the result of a three-dimensional image characterizing defect information in the initial state and after 100K polarization state flips, wherein the Figure 5 The image on the left is a three-dimensional image of defect information in an initial state, and the image on the right is a three-dimensional image of defect information after 100K polarization state flips.
[0060] This embodiment detects the leakage current of the ferroelectric capacitor to be tested under gradually increasing step voltages, analyzes the changes in relevant response areas where defects are located in the ferroelectric capacitor during a complete voltage application process, and assigns values to the relevant response areas in combination with the defect concentration to obtain the contribution of the defects in each relevant response area to the leakage current, thereby realizing real-time collection of change information on the internal defect information of the ferroelectric capacitor, achieving a more complete analysis of the failure behavior of the device, and making the subsequent optimization based on the defect extraction results more effective.
[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A method for extracting defect information of a ferroelectric capacitor dielectric layer, characterized in that: include: Performing a preset number of polarization state flips on the ferroelectric capacitor to be tested; Applying a step voltage gradually increasing according to a preset step length to both ends of the ferroelectric capacitor to be tested, and obtaining the leakage current of the ferroelectric capacitor to be tested under each step voltage; Determine a relevant response area of each leakage current according to the leakage current of each step voltage; The defect concentrations of all the relevant response regions are determined, and the relevant response regions are assigned values according to the defect concentrations to obtain defect information of the ferroelectric capacitor to be tested.
2. The defect information extraction method according to claim 1, characterized in that: The step of applying a step voltage gradually increasing according to a preset step length to both ends of the ferroelectric capacitor to be tested, and obtaining the leakage current of the ferroelectric capacitor to be tested under each step voltage, comprises: Applying a step voltage gradually increasing according to a preset step length to both ends of the ferroelectric capacitor to be tested, wherein the application duration of each step voltage is a preset duration; The leakage current of the ferroelectric capacitor to be tested under the step voltage is acquired in real time, and the average value of the leakage current in the tail interval of the preset time length is used as the leakage current of the ferroelectric capacitor to be tested under the step voltage.
3. The defect information extraction method according to claim 2, characterized in that: The tail interval is from the tth second after the start time of the preset duration to the end of the preset duration.
4. The defect information extraction method according to claim 1, characterized in that: The preset step size is between 0.02V and 0.05V.
5. The defect information extraction method according to claim 1, characterized in that: The determining, according to the leakage current of each step voltage, a relevant response area of each leakage current comprises: Each leakage current is substituted into a thermally activated trapping model to determine the spatial position information and energy level position information of the defect forming each leakage current, and obtain the relevant response area of the leakage current.
6. The defect information extraction method according to claim 5, characterized in that: The determining of defect concentrations of all the relevant response areas comprises: Determining a current density corresponding to each leakage current; The defect concentration of the associated response region is determined based on the current density.
7. The defect information extraction method according to claim 6, characterized in that: The assigning process to the relevant response region according to the defect concentration to obtain defect information of the ferroelectric capacitor to be tested includes: Assigning a value to the relevant response region based on the defect concentration; According to the defect concentration of the related response area, the overlapping area of the related response areas of adjacent leakage currents is assigned according to the larger value of the defect concentration. After a new related response area is formed, the assignment processing of the overlapping area with the related response area of the next leakage current is performed until the assignment of the overlapping areas of the related response areas of all leakage currents is completed.
8. The defect information extraction method according to claim 7, characterized in that: After assigning the relevant response area based on the defect concentration, the method further comprises: All the leakage currents are arranged in ascending order according to their magnitudes, and the assignment processing of the relevant response areas of the leakage currents is performed according to the arranged order.
9. The defect information extraction method according to claim 7, characterized in that: After the overlapping area assignment of all the relevant response areas of the leakage current is completed, the method further includes: Based on the spatial position information, energy level position information and defect concentration of all the relevant response areas, a three-dimensional image is established for display, wherein the horizontal axis of the three-dimensional image represents the spatial position information of the defect, the vertical axis represents the energy level position information, and the image color represents the defect concentration.
10. The defect information extraction method according to any one of claims 1 to 9, characterized in that: The step of obtaining the leakage current of the ferroelectric capacitor to be measured under each step voltage comprises: The leakage current of the ferroelectric capacitor to be tested under each step voltage is collected through an IV sweep module.