Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. A first substrate comprises a first substrate, a transistor array layer, a pixel electrode layer, a common electrode layer, a first inorganic insulating layer and a second inorganic insulating layer; the transistor array layer is arranged on one side of the first substrate, and the pixel electrode layer and the common electrode layer are arranged on the side, away from the first substrate, of the transistor array layer; the transistor array layer comprises a transistor, the pixel electrode layer comprises a pixel electrode, and the common electrode layer comprises a common electrode; the insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is a first inorganic insulating layer; the second inorganic insulating layer is disposed between the pixel electrode layer and the common electrode layer. The insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is set as the inorganic insulating layer, so that the thickness of the display panel can be reduced, the preparation cost of the display panel is reduced, and the process steps are reduced.

Description

[0001] This application is a divisional application of application number 202310423575.3, application date April 19, 2023, and invention name “A display panel and display device”. [Technical field]

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0003] Active matrix flat panel display technology provides strong support for the development of display devices towards thinner, clearer and larger screen-to-body ratio. An important component of active matrix flat panel display technology is the array substrate, which is a substrate including transistors arranged in an array (referred to as array substrate). The array substrate can drive pixels in an orderly and accurate manner.

[0004] Array substrates are widely used in the fields of liquid crystal display, organic light emitting display, micro-LED display, and sub-millimeter light emitting diode (Mini-LED) display. How to optimize the performance and preparation process of existing display panels using array substrates is an important research topic.

[0005]

Application Contents

[0006] In view of this, embodiments of the present application provide a display panel and a display device to optimize the performance and manufacturing process of the existing display panel using an array substrate.

[0007] In a first aspect, an embodiment of the present application provides a display panel, comprising a first substrate; the first substrate comprises a first substrate, a transistor array layer, a pixel electrode layer, a common electrode layer, a first inorganic insulating layer and a second inorganic insulating layer; the transistor array layer is arranged on one side of the first substrate, and the pixel electrode layer and the common electrode layer are both arranged on a side of the transistor array layer away from the first substrate; the transistor array layer comprises transistors, the pixel electrode layer comprises pixel electrodes, and the common electrode layer comprises common electrodes; the insulating layer between one of the pixel electrode layer and the common electrode layer closer to the transistor array layer and the transistor array layer is a first inorganic insulating layer; the second inorganic insulating layer is arranged between the pixel electrode layer and the common electrode layer.

[0008] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0009] In the embodiment of the present application, by setting the insulating layer between the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer as an inorganic insulating layer, the thickness of the display panel can be reduced. At the same time, the inorganic insulating layer has a lower cost and a simpler preparation process than the organic insulating layer, so the preparation cost of the display panel can be reduced. In addition, the insulating layer between the pixel electrode layer and the common electrode layer also includes an inorganic insulating layer, which can reduce the process steps when preparing the vias that penetrate the first inorganic insulating layer and the second inorganic insulating layer, that is, the parts of the vias located in the first inorganic insulating layer and the second inorganic insulating layer can be prepared in one etching process.

Brief Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 A schematic diagram of a first substrate of a display panel provided in an embodiment of the present application;

[0012] Figure 2 For along Figure 1 A schematic cross-sectional view of the M1-M2 direction;

[0013] Figure 3 For along Figure 1 Another cross-sectional schematic diagram in the M1-M2 direction;

[0014] Figure 4 A schematic diagram of a first substrate of another display panel provided in an embodiment of the present application;

[0015] Figure 5 For along Figure 4 A schematic cross-sectional view of the N1-N2 direction;

[0016] Figure 6 A partial schematic diagram of a first substrate in a display panel provided in an embodiment of the present application;

[0017] Figure 7 For along Figure 6 Schematic diagram of the cross section along the S1-S2 direction;

[0018] Figure 8 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0019] Fig. 9 For along Figure 8 Schematic diagram of the cross section along the L1-L2 direction;

[0020] Fig.10 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0021] Fig.11 For along Fig.10 Schematic diagram of the cross section along the K1-K2 direction;

[0022] Fig.12 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0023] Fig.13 along Fig.12 Schematic diagram of the cross section along the V1-V2 direction;

[0024] Fig.14 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0025] Fig.15 along Fig.14 Schematic diagram of the cross section along the F1-F2 direction;

[0026] Fig.16 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0027] Fig.17 For along Fig.16 A schematic cross-sectional view of the T1-T2 direction;

[0028] Fig.18 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0029] Fig.19 For along Fig.18 A schematic cross-sectional view in the I1-I2 direction;

[0030] Fig. 20 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0031] Fig.21 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0032] Fig. 22 For along Fig.21 A schematic cross-sectional view in the D1-D2 direction;

[0033] Fig.23 For along Fig.21 Another cross-sectional schematic diagram in the D1-D2 direction;

[0034] Fig.24For along Fig.21 A schematic cross-sectional view along the J1-J2 direction;

[0035] Fig.25 For along Fig.21 Another cross-sectional schematic diagram in the J1-J2 direction;

[0036] Fig.26 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0037] Fig. 27 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0038] Fig.28 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application;

[0039] Fig.29 A partial schematic diagram of a display panel provided in an embodiment of the present application;

[0040] Fig.30 for Fig.29 A schematic diagram of part of the structure in the X1 region;

[0041] Fig.31 for Fig.30 A schematic cross-sectional view along the A1-A2 direction;

[0042] Fig.32 for Fig.29 Another schematic diagram of part of the structure in the X1 region;

[0043] Fig.33 A partial schematic diagram of another display panel provided in an embodiment of the present application;

[0044] Fig.34 for Fig.33 Schematic diagram of part of the structure in the X2 region;

[0045] Fig.35 A partial schematic diagram of another display panel provided in an embodiment of the present application;

[0046] Fig.36 A partial schematic diagram of another display panel provided in an embodiment of the present application;

[0047] Fig.37 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0048] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0049] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0050] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0051] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0052] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0053] It should be understood that although the terms first, second, third, etc. may be used to describe regions, etc. in the embodiments of the present application, these regions, etc. should not be limited to these terms. These terms are only used to distinguish regions, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first region may also be referred to as the second region, and similarly, the second region may also be referred to as the first region.

[0054] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0055] Figure 1 A schematic diagram of a first substrate of a display panel provided in an embodiment of the present application, Figure 2 For along Figure 1 A cross-sectional diagram along the M1-M2 direction. Figure 3 For along Figure 1 Another cross-sectional schematic diagram along the M1-M2 direction.

[0056] like Figures 1 to 3 As shown, the display panel provided in the embodiment of the present application includes a first substrate 01 , and the first substrate 01 includes a first substrate 11 , a transistor array layer 12 , a pixel electrode layer 13 , a common electrode layer 14 , a first inorganic insulating layer 15 and a second inorganic insulating layer 16 .

[0057] The transistor array layer 12, the pixel electrode layer 13 and the common electrode layer 14 may be disposed on the same side of the first substrate 11. The transistor array layer 12 includes a plurality of transistors 120, the pixel electrode layer 13 includes a plurality of pixel electrodes 130, and the common electrode layer 14 includes a common electrode 140.

[0058] The pixel electrode layer 13 and the common electrode layer 14 are both disposed on a side of the transistor array layer 12 away from the first substrate 11, and the preparation process of the pixel electrode layer 13 and the common electrode layer 14 is performed after the preparation process of the transistor array layer 12. Along a direction Z perpendicular to the surface of the first substrate 11, the common electrode 140 covers at least two pixel electrodes 130, that is, the pixels to which the multiple pixel electrodes 130 belong share the common electrode 140.

[0059] The transistor 120 can function as a switch, combined with Figure 1 and Figure 2 and combination Figure 1 and Figure 3 , the first electrode 121 and the second electrode 122 of at least part of the transistors 120 are electrically connected to the data line DL and the pixel electrode 130 respectively, and the part of the transistors 120 is used as a switch between the data line DL and the pixel electrode 130 .

[0060] The insulating layer between the pixel electrode layer 13 and the common electrode layer 14, which is close to the transistor array layer 12, and the transistor array layer 12 is the first inorganic insulating layer 15. That is, the insulating layer disposed between the pixel electrode layer 13 and the common electrode layer 14, which is close to the transistor array layer 12, and the transistor array layer 12 only includes the inorganic insulating layer.

[0061] The surface of the first inorganic insulating layer 15 close to the first substrate 11 may contact the transistor array layer 12 , and the surface of the first inorganic insulating layer 15 away from the first substrate 11 may contact one of the pixel electrode layer 13 and the common electrode layer 14 close to the transistor array layer 12 .

[0062] For example, Figure 3 As shown, the pixel electrode layer 13 is located on the side of the common electrode layer 14 close to the transistor array layer 12, and the insulating layer between the pixel electrode layer 13 and the transistor array layer 12 is the first inorganic insulating layer 15. Optionally, the surface of the first inorganic insulating layer 15 close to the first substrate 11 can be in contact with the transistor array layer 12, and the surface of the first inorganic insulating layer 15 away from the first substrate 11 can be in contact with the pixel electrode layer 13.

[0063] For example, Figure 2As shown, the common electrode layer 14 is located on the side of the pixel electrode layer 13 close to the transistor array layer 12, and the insulating layer between the common electrode layer 14 and the transistor array layer 12 is the first inorganic insulating layer 15. Optionally, the surface of the first inorganic insulating layer 15 close to the first substrate 11 can be in contact with the transistor array layer 12, and the surface of the first inorganic insulating layer 15 away from the first substrate 11 can be in contact with the common electrode layer 14.

[0064] In the embodiment of the present application, the second inorganic insulating layer 16 is disposed between the pixel electrode layer 13 and the common electrode layer 14. Further, the insulating layer between the pixel electrode layer 13 and the common electrode layer 14 is the second inorganic insulating layer 16, that is, the insulating layer disposed between the pixel electrode layer 13 and the common electrode layer 14 only includes the inorganic insulating layer.

[0065] Among them, one of the surface of the second inorganic insulating layer 16 close to the first substrate 11 and the surface far from the first substrate 11 may be in contact with the pixel electrode layer 13 , and the other may be in contact with the common electrode layer 14 .

[0066] In the embodiment of the present application, the insulating layer between the pixel electrode layer 13 and the common electrode layer 14 close to the transistor array layer 12 and the transistor array layer 12 is set as an inorganic insulating layer. Since the inorganic insulating layer has a thinner thickness than the organic insulating layer, the thickness of the display surface provided by the embodiment of the present application can be thinner. The inorganic insulating layer is usually prepared by chemical deposition and other methods. The inorganic insulating layer has a lower cost and a simpler preparation process than the organic insulating layer, so the preparation cost of the display panel can be reduced; and the preparation method of the inorganic insulating layer will not produce substances that damage the devices in the first substrate, so the preparation yield of the display panel can be improved.

[0067] In addition, the insulating layer between the pixel electrode layer 13 and the common electrode layer 14 also includes an inorganic insulating layer. When preparing a via hole that needs to penetrate the first inorganic insulating layer 15 and the second inorganic insulating layer 16, one etching process can be used to simultaneously etch the first inorganic insulating layer 15 and the second inorganic insulating layer 16, so as to simultaneously form a via hole on the first inorganic insulating layer 15 and a via hole on the second inorganic insulating layer 16. Moreover, when the second inorganic insulating layer 16 also includes a via hole that does not penetrate the via hole in the first inorganic insulating layer 15, the part of the via hole can also be formed together in the above-mentioned etching process, which greatly reduces the etching process.

[0068] In one embodiment of the present application, the first inorganic insulating layer 15 includes at least one of silicon oxide and silicon nitride. The first inorganic insulating layer 15 may be a silicon oxide layer, a silicon nitride layer, or a composite film layer of stacked silicon oxide and silicon nitride. In addition, the first inorganic insulating layer 15 may also be a mixture film layer including silicon oxide and silicon nitride.

[0069] In one embodiment of the present application, the second inorganic insulating layer 16 includes at least one of silicon oxide and silicon nitride. The second inorganic insulating layer 16 may be a silicon oxide layer, a silicon nitride layer, or a composite film layer of stacked silicon oxide and silicon nitride. In addition, the second inorganic insulating layer 16 may also be a mixture film layer including silicon oxide and silicon nitride.

[0070] In one embodiment of the present application, the first inorganic insulating layer 15 and the second inorganic insulating layer 16 both include silicon oxide, or both include silicon nitride. For example, the first inorganic insulating layer 15 is a composite film layer of stacked silicon oxide and silicon nitride, and the second inorganic insulating layer 16 is a silicon oxide layer or a silicon nitride layer.

[0071] Since the preparation process of silicon oxide and silicon nitride is very mature and the patterning process of silicon oxide and silicon nitride is also very mature, when the first inorganic insulating layer 15 and the second inorganic insulating layer 16 include silicon oxide and / or silicon nitride, the difficulty of preparing the display panel can be reduced. In addition, silicon nitride and silicon oxide have good compactness, which can isolate the influence of water and oxygen on the device and can prevent the mutual interference of conductive particles between the transistor array layer and the pixel electrode layer and the common electrode layer.

[0072] In one embodiment of the present application, the thickness of the first inorganic insulating layer 15 is less than or equal to 6000 angstroms. For example, the thickness of the first inorganic insulating layer 15 may be about 3000 angstroms, about 2000 angstroms, or about 1000 angstroms.

[0073] In one embodiment of the present application, the thickness of the second inorganic insulating layer 16 is less than or equal to 6000 angstroms. For example, the thickness of the second inorganic insulating layer 16 may be about 3000 angstroms, about 2000 angstroms, or about 1000 angstroms.

[0074] The thickness of the first inorganic insulating layer 15 and the second inorganic insulating layer 16 is set to be less than 6000 angstroms, which can effectively shorten the preparation period of the display panel. In addition, at least a portion of the via holes respectively included in the first inorganic insulating layer 15 and the second inorganic insulating layer 16 penetrate, and when these penetrating via holes are prepared by an etching process, the process difficulty is low and the process yield is high.

[0075] In one embodiment of the present application, Figure 2 and Figure 3 As shown, the thickness of the first inorganic insulating layer 15 may be greater than the thickness of the second inorganic insulating layer 16. For example, the thickness of the first inorganic insulating layer 15 is about 3000 angstroms, and the thickness of the second inorganic insulating layer 16 is about 1000 angstroms.

[0076] Since the first inorganic insulating layer 15 is disposed on the transistor array layer 12, the thickness of the first inorganic insulating layer 15 is set to be relatively large, so that the surface of the first inorganic insulating layer 15 away from the transistor array layer 12 can be relatively flat, thereby providing a relatively flat bearing surface for the structure disposed thereon.

[0077] The second inorganic insulating layer 15 is set to have a relatively small thickness, which is conducive to realizing a thinner display panel and reducing the preparation cycle of the first substrate. In addition, since the thickness of the pixel electrode layer 13 and the common electrode layer 14 are usually thin, the second inorganic insulating layer 15 is relatively flat on its surface away from the first inorganic insulating layer 15, whether it is prepared after the pixel electrode layer 13 or after the common electrode layer 14, and there is no great risk of process failure.

[0078] In one embodiment of the present application, the transistor 120 includes a polysilicon semiconductor layer. Specifically, the transistors in the transistor array layer 12 may be low temperature polysilicon transistors.

[0079] Figure 4 A schematic diagram of a first substrate of another display panel provided in an embodiment of the present application, Figure 5 For along Figure 4 A schematic cross-sectional view along the N1-N2 direction.

[0080] It should be noted that, for the sake of clarity, the common electrode layer 14 included in the drawings of the following embodiments is located between the pixel electrode layer 13 and the base substrate 11. However, unless otherwise specified, the inventive concepts in the following embodiments are also applicable to display panels in which the pixel electrode layer 13 is located between the common electrode layer 14 and the base substrate 11.

[0081] Combination Figure 4 and Figure 5 The common electrode layer 14 includes a plurality of common electrodes 140, and the common electrodes 140 can be reused as touch electrodes. The common electrodes 140 can be reused as touch electrodes for mutual capacitance touch detection, or can be reused as touch electrodes for self capacitance touch detection.

[0082] In one embodiment of the present application, Figure 4 and Figure 5 As shown, the first substrate 01 further includes a touch line TL, and the touch line TL provides a signal for the common electrode 140. The touch line TL can be electrically connected to the common electrode 140 and provide it with a signal related to touch detection.

[0083] In the embodiment of the present application, the touch line TL is disposed on a side of the common electrode layer 14 close to the first substrate 11. Specifically, the touch line TL can be disposed on a side of the first inorganic insulating layer 15 close to the first substrate 11.

[0084] Figure 6 A partial schematic diagram of a first substrate in a display panel provided in an embodiment of the present application, Figure 7 For along Figure 6 Schematic diagram of the cross section along the S1-S2 direction.

[0085] In a technical solution of the present application, combined with Figure 6 and Figure 7 , at least part of the touch line TL may overlap with the common electrode 140 along a direction Z perpendicular to the surface where the display panel is located. A first slit 141 is provided on the common electrode 140, and along a direction Z perpendicular to the surface where the display panel is located, at least part of the first slit 141 partially overlaps with the touch line TL, that is, at least part of the first slit 141 on the common electrode 140 exposes a part of the touch line TL.

[0086] Since the insulating layer between the touch line TL and the common electrode layer 14 is mainly the first inorganic insulating layer 15 or mainly the first inorganic insulating layer 15 and the second inorganic insulating layer 16, the distance between the touch line TL and the common electrode layer 14 along the direction Z perpendicular to the surface of the display panel is small, so the coupling capacitance between the touch line TL and the common electrode 140 that overlaps and is not electrically connected to it increases and the signal interference is enhanced.

[0087] By forming a first slit 141 partially overlapping the touch line TL on the common electrode 140, the overlapping area between the common electrode 140 and the touch line TL in a direction perpendicular to the surface of the display panel is reduced, the coupling capacitance between the two is reduced, and the signal interference problem between the two is effectively alleviated.

[0088] Figure 8 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig. 9 For along Figure 8 Schematic diagram of the cross section along the L1-L2 direction.

[0089] In a technical solution of the present application, combined with Figure 8 and Fig. 9 , a second slit 142 is included between adjacent common electrodes 140, and along a direction Z perpendicular to the surface where the display panel is located, the second slit 142 at least partially overlaps with at least a portion of the touch trace TL. That is, a portion of the touch trace TL is routed at the location of the second slit 142 and the second slit 142 exposes at least a portion of the portion of the touch trace TL.

[0090] By routing a portion of the touch lines TL at the location of the second slits 142 , the overlapping area between the portion of the touch lines TL and the common electrode 14 can be reduced, thereby reducing the coupling capacitance and signal interference between the portion of the touch lines TL and the common electrode 14 .

[0091] In an implementation of the present technical solution, a portion of the touch trace TL that overlaps with the second slit 142 is completely exposed by the second slit 142 .

[0092] Fig.10 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig.11 For along Fig.10 Schematic diagram of the cross section along the K1-K2 direction.

[0093] In a technical solution of the present application, combined with Fig.10 and Fig.11 A first slit 141 is formed on the common electrode 140 and a second slit 142 is included between adjacent common electrodes 140. Along a direction Z perpendicular to the surface where the display panel is located, at least part of the first slit 141 partially overlaps with the touch line TL and the second slit 142 at least partially overlaps with at least part of the touch line TL.

[0094] Fig.12 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig.13 along Fig.12 Schematic diagram of the cross section along the V1-V2 direction.

[0095] In one embodiment of the present application, Fig.12 and Fig.13 The first substrate 01 further includes a dummy touch line TL′, which is disposed on the same layer as the touch line TL and is electrically insulated from the common electrode 140 .

[0096] In one implementation of this embodiment, Fig.12 As shown, the dummy touch line TL′ may be located in the same column as the touch line TL.

[0097] When the first slit 141 is formed on the common electrode 140, along the direction Z perpendicular to the surface where the display panel is located, part of the first slit 141 partially overlaps with the touch line TL, and part of the first slit 141 partially overlaps with the dummy touch line TL', that is, part of the first slit 141 on the common electrode 140 exposes a part of the touch line TL and part of the first slit 141 on the common electrode 140 exposes at least a part of the dummy touch line TL.

[0098] The lengths of the plurality of touch lines TL in the first substrate 01 are different, and the longer touch lines TL can overlap with more common electrodes 140 than the shorter touch lines TL. Among the plurality of common electrodes 140 arranged along the extension direction of the touch lines TL, at least two common electrodes 140 overlap with different numbers of touch lines TL, and the numbers of first slits 141 respectively opened on the at least two common electrodes 140 and overlapping with the touch lines TL are different, which will result in different loads on the at least two common electrodes 140.

[0099] By providing a dummy touch line TL' and a first slit 141 overlapping with the dummy touch line TL', the above-mentioned problem can be effectively solved. In addition, by providing a dummy touch line TL' and a first slit 141 overlapping with the dummy touch line TL1', the touch line TL and the dummy touch line TL1' can be distributed more evenly as a set, and the number of the first slits 141 on each common electrode 140 is also more uniform, thereby avoiding the problem of uneven display of the display panel caused by uneven setting of the touch line TL and uneven setting of the first slit 141.

[0100] It should be noted that, in some embodiments, along the extension direction of the touch lines TL, different touch lines TL overlap with the same number of common electrodes 140, and it is not necessary to set the dummy touch electrodes TL' in the same column as the touch lines TL. Fig.10 As shown, the touch line TL is not disconnected near the position where it is electrically connected to the first common electrode 140 , and the touch line TL can overlap the uppermost common electrode 140 and the lowermost common electrode 140 in the display panel along the column direction.

[0101] In another implementation of the present embodiment, the dummy touch line TL' can be arranged in the same direction as the multiple touch lines TL, the length of the dummy touch line TL' can be substantially the same as the length of the touch line TL, and the number of common electrodes 140 overlapped by the dummy touch line TL' can be the same as the number of common electrodes 140 overlapped by the touch line TL.

[0102] In addition, the first slits 141 formed on the common electrode 140 may also overlap with the dummy touch lines TL′. Then, the number of first slits 141 overlapped by the dummy touch lines TL′ may be the same as the number of first slits 141 overlapped by the touch lines TL.

[0103] Fig.14 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig.15 along Fig.14 Schematic diagram of the cross section along the F1-F2 direction.

[0104] In one embodiment of the present application, Fig.14 and Fig.15 , a second slit 142 is included between adjacent common electrodes 140, and along a direction Z perpendicular to the surface of the display panel, the second slit 142 at least partially overlaps with at least a portion of the dummy touch trace TL'. Specifically, the dummy touch trace TL' at least partially overlapping with the second slit 142 and the touch trace TL at least partially overlapping with the second slit 142 may be located in the same column.

[0105] Fig.16 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application is shown in FIG. Fig.17 For along Fig.16 A schematic cross-sectional view along the T1-T2 direction.

[0106] In one embodiment of the present application, Fig.16 and Fig.17 The common electrode layer 14 is disposed on a side of the pixel electrode layer 13 close to the transistor array layer 12, and the touch line TL is disposed on a side of the common electrode layer 14 close to the first substrate 11. The pixel electrode layer 13 further includes a bridge electrode 131, which is used to electrically connect the touch line TL and the common electrode 140.

[0107] In an implementation method corresponding to this embodiment, the first inorganic insulating layer 15 is provided with a plurality of first via holes 150, and the second inorganic insulating layer 16 is provided with a plurality of second via holes 160. Part of the second via holes 160 is connected with the first via holes 150, that is, the part of the second via holes 160 overlaps with the first via holes 150 along a direction Z perpendicular to the surface where the display panel is located. Fig.17 As shown, the portion of the second via hole 160 that penetrates the first via hole 150 is marked as the second via hole 161. In addition, part of the second via hole 160 and the first via hole 150 do not overlap along the direction Z perpendicular to the surface where the display panel is located, as shown in FIG. Fig.17 As shown, the portion of the second via 160 that does not overlap with the first via 150 is marked as a second via 162 .

[0108] In this implementation, please combine Fig.16 and Fig.17 , the bridge electrode 131 is electrically connected to the common electrode 140 through the second via hole 160, and the bridge electrode 131 is electrically connected to the touch line TL through the second via hole 160 and the first via hole 150. That is, the bridge electrode 131 is electrically connected to the common electrode 140 through the second via hole 162, and the bridge electrode 131 is electrically connected to the touch line TL through the second via hole 161 and the first via hole 150.

[0109] In the embodiment of the present application, the through first via hole 150 and the through second via hole 161 are obtained by etching the first inorganic insulating layer 15 and the second inorganic insulating layer 16 respectively. Since the first inorganic insulating layer 15 and the second inorganic insulating layer 16 can be formed by the same etching process, the through first via hole 150 and the through second via hole 161 can be completed in one etching process step. In addition, the second via hole 162 can also be completed in one etching process step with the second via hole 161.

[0110] It should be noted that the bridge electrode 131 is electrically connected to the common electrode 140 through the second via hole 160, which means that the bridge electrode 131 is electrically connected to the common electrode 140 through the conductive structure in the second via hole 160. The conductive structure in the second via hole 160 may be a portion deposited in the second via hole 162 when the pixel electrode layer 130 is prepared.

[0111] It should be noted that the bridge electrode 131 is electrically connected to the touch line TL through the through first via hole 150 and the through second via hole 160, which means that the bridge electrode 131 is electrically connected to the common electrode 140 through the through first via hole 150 and the conductive structure in the through second via hole 160. Specifically, the conductive structure in the through first via hole 150 and the through second via hole 160 may be a portion deposited in the second via hole 161 and the first via hole 150 when preparing the pixel electrode layer 130.

[0112] Fig.18 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig.19 For along Fig.18 A schematic cross-sectional view along the I1-I2 direction.

[0113] In a technical solution of the present application, combined with Fig.18 and Fig.19 The common electrode 140 is provided with a first opening 143. Along a direction Z perpendicular to the surface where the display panel is located, the first opening 143 overlaps with the first via hole 150.

[0114] The first via hole 150 overlaps with the first opening 143 on the common electrode 140 , which is equivalent to making an avoidance design for the common electrode 140 in the area where the first via hole 150 is located, thereby reducing the coupling capacitance between the common electrode 140 and the touch line TL.

[0115] Fig. 20 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application.

[0116] In one implementation, Fig. 20 As shown, the opening areas of at least two first openings 143 are different. Fig. 20As shown, the at least two first openings 143 include a first opening 143 a and a first opening 143 b , and the opening area of ​​the first opening 143 a is greater than the opening area of ​​the first opening 143 b .

[0117] In this implementation, the area of ​​the first opening 143 can be flexibly set according to the different positions of the first opening 143. For example, when the first opening 143 needs to be opened at some positions of the common electrode 140, there is no other functional structure (such as a conductive structure) below the position, then the area of ​​the first openings 143 can be set larger; when the first opening 143 needs to be opened at some positions of the common electrode 140, there is a certain area of ​​other functional structures (such as a conductive structure) below the position, then the area of ​​the first openings 143 can be set smaller to avoid damage to the above-mentioned other functional structures. In addition, when the first openings 143 are opened at different positions of the common electrode 140, the surrounding environments of the different positions may be different. For example, the different heights of different positions result in different etching degrees of the first opening 143 by the etching liquid, which in turn results in different areas of the first openings 143 at different positions.

[0118] In one embodiment of the present application, the first substrate 01 further includes a data line DL, and the data line DL provides a signal to the pixel electrode 130. The data line DL can be electrically connected to the pixel electrode 130 through the transistor 120, and the data line DL provides the corresponding electrically connected pixel electrode 130 with a data signal required for the display panel to emit light.

[0119] In the embodiment of the present application, the data line DL is disposed on a side of the common electrode 14 close to the first substrate 11. Specifically, the data line DL is disposed on a side of the first inorganic insulating layer 15 close to the first substrate 11.

[0120] In a technical solution of the present application, combined with Figure 6 and Figure 7 , combined Fig.12 and Fig.13 , at least part of the data line DL may overlap with the common electrode 140 along a direction Z perpendicular to the surface of the display panel. The common electrode 140 is provided with a slit, and along the direction Z perpendicular to the surface of the display panel, the data line DL does not overlap with the slit on the common electrode 140. For example, Figure 6 and Figure 7 , Fig.12 and Fig.13 As shown, the common electrode 140 is provided with a first slit 141, and the data line DL does not overlap with the first slit 141 along a direction Z perpendicular to the surface of the display panel. That is, in this technical solution, the overlapped portion of the data line DL and the common electrode 140 is covered by the physical conductive portion of the common electrode 140.

[0121] Since the insulating layer between the data line DL and the common electrode 140 is mainly the first inorganic insulating layer 15 or mainly the first inorganic insulating layer 15 and the second inorganic insulating layer 16, the distance between the data line DL and the common electrode layer 140 along the direction Z perpendicular to the surface of the display panel is small, the risk of interference of the signal transmitted by the data line DL with the electric field between the pixel electrode 130 and the common electrode 140 is increased.

[0122] For example, refer to Figure 6 and Fig.12 , taking the leftmost data line DL as an example, when the data line DL provides a signal to the pixel electrode 130 located in the first column and the first row, a strong electric field is generated between the signal potential transmitted by the data line DL and the potential of the common electrode 140 due to the reduced distance between the data line DL and the common electrode 140. The strong electric field also exists at the location of the pixel electrode 130 in the first column and the second row, and the risk of the signal transmitted on the data line DL interfering with the display of multiple pixels increases.

[0123] When the electric field between the pixel electrode 130 and the common electrode 140 is used to drive the liquid crystal to deflect, the risk of the liquid crystal being in an erroneous deflection state due to the signal transmitted by the data line DL increases.

[0124] In this technical solution, the overlapping portion of the data line DL and the common electrode 140 is covered by the physical conductive portion of the common electrode 140, so the common electrode 140 can shield the electric field between the data line DL and the common electrode 140 from propagating to the side of the common electrode 140 away from the first substrate 11, effectively solving the above problem.

[0125] In a technical solution of the present application, combined with Figure 8 and Fig. 9 , combined Fig.14 and Fig.15 , there are slits between adjacent common electrodes 140 , and along a direction Z perpendicular to the surface where the display panel is located, the data line DL and at least part of the slits between the adjacent common electrodes 140 do not overlap.

[0126] For example, Figure 8 and Fig. 9 , Fig.14 and Fig.15 As shown, adjacent common electrodes 140 include second slits 142, and along a direction Z perpendicular to the surface of the display panel, the data lines DL do not overlap with the second slits 142. It should be noted that the extension direction of the second slits 142 is substantially parallel to the extension direction of the data lines DL.

[0127] This solution can also effectively solve the interference of the signal transmitted by the data line DL on the electric field between the pixel electrode 130 and the common electrode 140 .

[0128] In one embodiment of the present application, Fig.10 and Fig.11 , along a direction Z perpendicular to the surface of the display panel, the data line DL does not overlap with the slits on the common electrode 140 , and the data line DL does not overlap with at least part of the slits between adjacent common electrodes 140 .

[0129] Fig.21 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig. 22 For along Fig.21 A schematic cross-sectional view along the D1-D2 direction.

[0130] In one embodiment of the present application, Fig.21 and Fig. 22 The first electrode 121 of the transistor 120 is electrically connected to the data line DL and the second electrode 122 of the transistor 120 is electrically connected to the pixel electrode 130. For example, the source of the transistor 120 is the first electrode 121 and the drain of the transistor 120 is the second electrode 122. The data line DL is electrically connected to the plurality of pixel electrodes 130 through the plurality of transistors 120.

[0131] In a technical solution of the present application, combined with Fig.21 and Fig. 22 As shown, a second opening 144 is provided on the common electrode 140, and along a direction Z perpendicular to the surface where the display panel is located, the second opening 144 at least partially overlaps with the first electrode 121 of the transistor 120. That is, along the direction Z perpendicular to the surface where the display panel is located, a hollow portion is provided at a position on the common electrode 140 that overlaps with the first electrode 121 of the transistor 120, thereby reducing interference of the signal on the first electrode 121 of the transistor 120 with the common electrode 140.

[0132] Fig.23 For along Fig.21 Another cross-sectional schematic diagram along the D1-D2 direction.

[0133] In one implementation, Fig. 22 As shown, the common electrode layer 14 is arranged on the side of the pixel electrode layer 13 close to the first substrate 11. The effect of opening the second opening 144 on the common electrode 140 also includes: preventing the common electrode 140 from being electrically conductive with the data line DL when the first pole 121 of the transistor 120 is electrically connected to the data line DL through the via hole.

[0134] In one implementation, Fig.23 As shown, the pixel electrode layer 13 is disposed on a side of the common electrode layer 14 close to the first substrate 11 . At this time, a second opening 144 can still be opened on the common electrode 140 .

[0135] Fig.24 For along Fig.21 A schematic cross-sectional view along the J1-J2 direction.

[0136] In a technical solution of the present application, combined with Fig.21 and Fig.24 As shown, a third opening 145 is provided on the common electrode 140, and along a direction Z perpendicular to the surface where the display panel is located, the third opening 145 at least partially overlaps with the second electrode 122 of the transistor 120. That is, along the direction Z perpendicular to the surface where the display panel is located, a hollow portion is provided at a position on the common electrode 140 that overlaps with the second electrode 122 of the transistor 120, thereby reducing interference of the signal on the second electrode 122 of the transistor 120 on the common electrode 140.

[0137] Fig.25 For along Fig.21 Another cross-sectional schematic diagram along the J1-J2 direction.

[0138] In one implementation, Fig.24 As shown, the common electrode layer 14 is arranged on the side of the pixel electrode layer 13 close to the first substrate 11, and the effect of opening the third opening 145 on the common electrode 140 also includes: preventing the common electrode 140 and the pixel electrode 130 from being electrically connected when the second pole 122 of the transistor 120 is electrically connected to the pixel electrode 130 through the via hole.

[0139] In one implementation, Fig.25 As shown, the pixel electrode layer 13 is disposed on a side of the common electrode layer 14 close to the first substrate 11 . At this time, the third opening 145 can still be opened on the common electrode 140 .

[0140] In a technical solution of the present application, Fig.21 As shown, the common electrode 140 has a second opening 144 and a third opening 145 , and along a direction Z perpendicular to the surface of the display panel, the second opening 144 at least partially overlaps with the first electrode 121 of the transistor 120 , and the third opening 145 at least partially overlaps with the second electrode 122 of the transistor 120 .

[0141] Fig.26 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig. 27 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application, Fig.28 A partial schematic diagram of a first substrate in another display panel provided in an embodiment of the present application.

[0142] In a technical solution of the present application, Fig.26 and Fig.28As shown in FIG. 1 , when the second openings 144 are formed on the common electrode 140, the opening areas of at least two second openings 144 are different. Fig.26 and Fig.28 As shown, the at least two second openings 144 include a second opening 144a and a second opening 144b, wherein the opening area of ​​the second opening 144a is greater than the opening area of ​​the second opening 144b.

[0143] In this implementation, the area of ​​the second opening 144 can be flexibly set according to the different positions of the second opening 144. For example, when the second opening 144 needs to be opened at some positions of the common electrode 140, there is no other functional structure (such as a conductive structure) below the position, then the area of ​​the second openings 144 can be set larger; when the second opening 144 needs to be opened at some positions of the common electrode 140, there is a certain area of ​​other functional structures (such as a conductive structure) below the position, then the area of ​​the second openings 144 can be set smaller to avoid damage to the above-mentioned other functional structures. In addition, when the second openings 144 are opened at different positions of the common electrode 140, the surrounding environments of the different positions may be different. For example, the different heights at different positions result in different etching degrees of the second opening 144 by the etching liquid, which in turn results in different areas of the second openings 144 at different positions.

[0144] In a technical solution of the present application, Fig. 27 and Fig.28 As shown in FIG. 1 , when the third openings 145 are formed on the common electrode 140, the opening areas of at least two third openings 145 are different. Fig. 27 and Fig.28 As shown, the at least two third openings 145 include a third opening 145 a and a third opening 145 b , wherein the opening area of ​​the third opening 145 a is greater than the opening area of ​​the third opening 145 b .

[0145] In this implementation, the area of ​​the third opening 145 can be flexibly set according to the different positions of the third opening 145. For example, when the third opening 145 needs to be opened at some positions of the common electrode 140, there is no other functional structure (such as a conductive structure) below the position, then the area of ​​the third openings 145 can be set larger; when the third opening 145 needs to be opened at some positions of the common electrode 140, there is a certain area of ​​other functional structures (such as a conductive structure) below the position, then the area of ​​the third openings 145 can be set smaller to avoid damage to the above-mentioned other functional structures. In addition, when the third openings 145 are opened at different positions of the common electrode 140, the surrounding environments of the different positions may be different. For example, the different heights at different positions result in different etching degrees of the third opening 145 by the etching liquid, which in turn results in different areas of the third openings 145 at different positions.

[0146] In one embodiment of the present application, Fig.16 and Fig.17 , Fig.18 and Fig.19 As shown, the first substrate 01 includes data lines DL and touch lines TL, and the data lines DL and the touch lines TL are arranged in the same layer. The data lines DL are electrically connected to the pixel electrodes 130 , and the touch lines TL are electrically connected to the common electrodes 140 .

[0147] The data line DL and the touch line TL are arranged in the same film layer, and the insulating layers between the data line DL and the touch line TL and the pixel electrode 130 are all inorganic insulating layers, and the insulating layers between the data line DL and the touch line TL and the common electrode 140 are also all inorganic insulating layers, so the via holes electrically connected between the touch line TL and the common electrode 140 can be prepared by the same process as the via holes electrically connected between the data line DL and the pixel electrode 130, thereby reducing the difficulty of preparation. Furthermore, the via holes electrically connected between the pixel electrode 130 and the data line DL and the via holes electrically connected between the common electrode 140 and the touch line TL can be prepared in the same etching process step. And the touch line TL and the data line DL are arranged in the same film layer, so the touch line TL can be prepared at the same time as the data line DL using the same process and mask plate, thereby reducing the process and saving costs.

[0148] In summary, the common electrode 140 can be reused as a touch electrode, the touch line TL can be prepared at the same time as the data line DL, and the via hole electrically connected between the touch line TL and the common electrode 140 and the via hole electrically connected between the data line DL and the pixel electrode 130 can be prepared at the same time. Therefore, when the structure with a touch function is integrated in the display panel provided by the present application, the process and mask are not increased at all.

[0149] Fig.29 A partial schematic diagram of a display panel provided in an embodiment of the present application, Fig.30 for Fig.29 A schematic diagram of part of the structure in the X1 region, Fig.31 for Fig.30 Schematic diagram of the cross section along the A1-A2 direction.

[0150] In one embodiment of the present application, Fig.29 , Fig.30 and Fig.31 The display panel further includes a second substrate 02 and a support column 03. The second substrate 02 includes a second substrate 21. In addition, the second substrate 02 may also include a black matrix, a color resist and other structures.

[0151] The support column 03 is disposed between the first substrate 11 and the second substrate 21, and is used to form a certain space between the first substrate 01 and the second substrate 02. The support column 03 can be disposed on the first substrate 01, that is, formed during the preparation of the first substrate 01; the support column 03 can also be disposed on the second substrate 02, that is, formed during the preparation of the second substrate 02.

[0152] In addition, the display panel may further include a display medium layer 04, and the display medium layer 04 may be located between the first substrate 01 and the second substrate 02. The display medium layer 04 may include liquid crystal, and the display panel provided in the embodiment of the present application may be a liquid crystal display panel.

[0153] Combination Fig.29 , Fig.30 and Fig.31 The first substrate 01 further includes a scan line SL and a data line DL, and the extending direction of the scan line SL intersects with the extending direction of the data line DL. Fig.29 As shown, the scan line SL extends along the row direction and the data line DL extends along the column direction, and the extending directions of the scan line SL and the data line DL are substantially perpendicular.

[0154] In the embodiment of the present application, along the direction Z perpendicular to the surface of the display panel, the support column 03 does not overlap with at least one of the scan line SL and the data line DL. That is, the support column 03 does not overlap with the scan line SL and the data line DL at the same time, which can be understood as the support column 03 is not arranged at the intersection of the scan line SL and the data line DL.

[0155] The scan line SL is usually electrically connected to the gate of the transistor 120 and the data line DL is electrically connected to the first electrode 12 of the transistor 120. The scan line SL and the data line DL are usually arranged in the same layer as a sub-film layer in the transistor array layer 12, that is, the scan line SL and the data line DL are located on the side of the first inorganic insulating layer 15 facing the first substrate 11. Since the planarization effect of the inorganic insulating layer is effective, although the first inorganic insulating layer 15 and the second inorganic insulating layer 16 are arranged on the side of the scan line SL and the data line DL away from the first substrate 11, the protrusion at the intersection of the scan line SL and the data line DL is still relatively obvious. If the support column 03 is arranged at the intersection of the scan line SL and the data line DL, the stability of the support column 03 is poor.

[0156] In the embodiment of the present application, the support column 03 is disposed at a position avoiding the intersection of the scan line SL and the data line DL, so that the stability of the support column 03 can be guaranteed as much as possible.

[0157] In a technical solution of the present application, combined with Fig.29 , Fig.30 and Fig.31, along the direction Z perpendicular to the surface where the display panel is located, the support column 03 overlaps with at least part of the data line DL and does not overlap with the scanning line SL. By arranging the support column 03 to overlap with the data line DL along the direction Z perpendicular to the surface where the display panel is located, it is avoided that the support column 03 additionally occupies too much area, thereby affecting the opening area of ​​the sub-pixel in the display panel.

[0158] like Fig.30 As shown, in a technical solution of the present application, the minimum distance d1 between the orthographic projection of the support column 03 on the first substrate 11 and the orthographic projection of the scanning line SL on the first substrate 11 is greater than 0 μm, that is, the orthographic projection of the support column 03 on the first substrate 11 and the orthographic projection of the scanning line SL on the first substrate 11 do not overlap. For example, d1 can be 0.5 μm, 1 μm, 1.5 μm, etc.

[0159] For example, when d1 is greater than or equal to 2 μm, the support pillar 03 can be safely prevented from being affected by the protrusion at the intersection of the scan line SL and the data line DL on the position of the support pillar 03 .

[0160] In a technical solution of the present application, Fig.30 As shown, the data line DL includes a first portion DL1 and a second portion DL2, wherein the width of the first portion DL1 along a first direction X is greater than the width of the second portion DL2 along the first direction X, and the first direction X is perpendicular to the extension direction of the data line DL. That is, a portion of the data line DL is widened to form the first portion DL1.

[0161] In the direction Z perpendicular to the surface where the display panel is located, at least part of the support column 03 overlaps with the first part DL1, and at least part of the support column 03 is arranged above the first part DL1 of the data line DL that is widened. Since the width of the first part DL1 is large, the support column 03 overlapping with the first part DL1 can obtain a relatively flat and large bearing surface.

[0162] In addition, since the support column 03 does not overlap with the scan line SL, the first portion DL1 also does not overlap with the scan line SL. Although the width of the first portion DL1 is wider than that of the second portion DL2, the coupling between the scan line SL and the data line DL can be minimized.

[0163] Fig.32 for Fig.29 Another schematic diagram of part of the structure in the X1 region.

[0164] In one implementation, Fig.32 As shown, at least a portion of the first portion DL has a peripheral contour in the shape of a cross.

[0165] The outer contour of the first part DL is set to a "cross" shape. On the one hand, it can ensure that the bearing surface above it for contacting the support column 03 can effectively ensure the stability of the support column 03; on the other hand, it can avoid the problem of sudden resistance change of the data line DL in the first part DL1.

[0166] In one implementation, combining Fig.31 and Fig.30 , Fig.32 When the first electrode 121 of the transistor 120 is electrically connected to the data line DL and the second electrode 122 of the transistor 120 is electrically connected to the pixel electrode 130, along the direction Z perpendicular to the surface where the display panel is located, the first part DL1 overlaps with the first electrode 121 of the transistor 120, and the support column 03 overlapping with the first part DL1 also overlaps with the first electrode 121 of the transistor 120.

[0167] The data line DL is arranged in the same layer as the first electrode 121 of the transistor 120, and the semiconductor layer in the first electrode 121 of the transistor 120 is electrically connected. It can be understood that the portion of the data line DL electrically connected to the semiconductor layer of the transistor 120 through the via hole constitutes the first electrode 121 of the transistor 120. The support column 02 overlaps with the first electrode 121 of the transistor 120 along the direction Z perpendicular to the surface where the display panel is located, which optimizes the station space of the support column 02 and reduces the influence of the support column 02 on the pixel light emitting area.

[0168] Fig.33 A partial schematic diagram of another display panel provided in an embodiment of the present application, Fig.34 for Fig.33 Schematic diagram of part of the structure in the X2 region.

[0169] In a technical solution of the present application, combined with Fig.33 and Fig.34 When the first substrate 01 further includes a touch line TL, the extending direction of the touch line TL is the same as the extending direction of the data line DL. Fig.33 As shown, the touch lines TL and the data lines DL extend along the column direction. Along the direction Z perpendicular to the surface where the display panel is located, the support column 03 overlaps at least a portion of the touch lines TL.

[0170] The touch line TL includes a third portion TL1 and a fourth portion TL2, the width of the third portion TL1 along the first direction X is greater than the width of the fourth portion TL2 along the first direction X, and the first direction X is perpendicular to the extension direction of the touch line TL. That is, a portion of the touch line TL is widened to form the third portion TL1.

[0171] Along the direction Z perpendicular to the surface where the display panel is located, at least part of the support column 02 overlaps with the third part TL3, and at least part of the support column 03 is arranged above the third part TL1 with a widened design in the touch line TL. Since the width of the third part TL1 is large, the support column 03 overlapping with the third part TL1 can obtain a relatively flat and large bearing surface.

[0172] In a technical solution of the present application, combined with Fig.33 and Fig.34 , the touch line TL is arranged adjacent to part of the data line DL, that is, the adjacent touch line TL and the data line DL are located in the same gap between the pixel electrodes 130, and the gap between the pixel electrodes 130 refers to the gap between the adjacent pixel electrodes 130. At this time, the touch line TL and the data line DL arranged adjacent to each other may include a third part TL1 and a first part DL1, respectively, and the same support column 03 may overlap with the third part TL1 and the first part DL1 at the same time along the direction Z perpendicular to the surface where the display panel is located.

[0173] Due to the brittle texture of the inorganic insulating layer, the thickness of the inorganic insulating layer should not be too thick. When the insulating layer between the touch lines TL and the data lines DL and the common electrode 140 and the pixel electrode 130 is an inorganic insulating layer, the thickness of the insulating layer on the side of the touch lines TL and the data lines DL facing the second substrate 02 is thinner, and the thinner insulating layer does not have an excellent flat effect. At this time, the flatness of the surface facing the second substrate 02 in the area where the touch lines TL and the data lines DL are arranged in the first substrate 01 is poor. If the surface facing the second substrate 02 in this area is directly used to support the support column 03, the position of the support column 03 is unstable.

[0174] In the present technical solution, the arrangement of the first portion DL1 is equivalent to widening the portion of the data line DL overlapping with the support column 03, and the arrangement of the third portion DL3 is equivalent to widening the portion of the touch line TL overlapping with the support column 03. The area of ​​the first substrate 01 where the first portion DL1 and the third portion DL3 are arranged and facing the surface of the second substrate 02 with good flatness is increased, so the support column 03 can obtain a stable position.

[0175] Meanwhile, the width of the third portion TL1 of the data line touch trace TL does not need to be increased too much relative to the width of the fourth portion TL2, thereby avoiding a sudden change in resistance on the touch trace TL.

[0176] Fig.35 A partial schematic diagram of another display panel provided in an embodiment of the present application, Fig.36 A partial schematic diagram of another display panel provided in an embodiment of the present application.

[0177] In one embodiment of the present application, Fig.35 and Fig.36 As shown, the first substrate 01 further includes a black matrix 05, and / or the second substrate 02 further includes a black matrix 05. That is, the display panel further includes a black matrix 05, and the black matrix 05 can be arranged on the first substrate 01, and the black matrix 05 can also be arranged on the second substrate 02, or the black matrix 05 includes a portion arranged on the first substrate 01 and the black matrix 05 also includes a portion on the second substrate 02.

[0178] In the direction Z perpendicular to the surface of the display panel, the black matrix 05 covers the scan lines SL, data lines DL and touch lines TL, and the black matrix 05 can prevent these signal lines from being visible and affecting the display effect of the display panel. In addition, the black matrix 05 can prevent light crosstalk between adjacent sub-pixels.

[0179] Please continue to refer to Fig.35 and Fig.36 The black matrix 05 includes a first main body portion 51, and the extension direction of the first main body portion 51 is parallel to the extension direction of the scanning line SL. Fig.35 and Fig.36 As shown, the extending directions of the first main body portion 51 and the scanning line SL are both parallel to the first direction X.

[0180] The first main body 51 includes a first side 511 and a second side 512 opposite to each other. The extension directions of the first side 511 and the second side 512 are parallel to the scanning line SL, and the arrangement direction of the first side 511 and the second side 512 is perpendicular to the extension direction of the scanning line SL. Fig.35 and Fig.36 As shown, the first side 511 and the second side 512 of the first main body portion 51 are the upper and lower sides thereof respectively.

[0181] In addition, the black matrix 05 further includes a plurality of first protrusions 52, which are arranged on a side of the first edge 511 away from the second edge 512 and connected to the first edge 511. Along a direction Z perpendicular to the surface where the display panel is located, the first protrusions 52 at least partially overlap with the support column 03. It can be understood that the first edge 511 in the first main body 51 is closer to the support column 03 than the second edge 512, and the first protrusion 52 overlapping with the support column 03 is arranged on a side of the first edge 511 away from the second edge 512.

[0182] The support column 03 can be covered by the black matrix 05 to prevent the support column 03 from being visible to the human eye and affecting the display effect of the display panel.

[0183] In addition, the black matrix 05 may further include a plurality of second protrusions 53, the second protrusions 53 are arranged on a side of the second edge 512 away from the first edge 511 and the second protrusions 53 are connected to the second edge 512. In addition, along a direction Z perpendicular to the surface where the display panel is located, the second protrusions 53 do not overlap with the support column 03. It can be understood that the second edge 512 in the first main body 51 is farther away from the support column 03 than the first edge 511.

[0184] In the embodiments of the present application, Fig.35 and Fig.36 As shown, along the direction perpendicular to the extension direction of the scan line SL, the width of the first protrusion 52 is greater than the width of the second protrusion 53. That is, the first protrusion 52 overlapping with the support column 03 protrudes toward the region where the support column 03 is located with a wider width, while the second protrusion 52 not overlapping with the support column 03 protrudes away from the region where the support column 03 is located with a narrower width. The wider width of the first protrusion 52 can effectively block the support column 03, and the narrower width of the second protrusion 53 can effectively ensure the opening area of ​​the sub-pixel in the display panel.

[0185] It should be noted that the black matrix 05 also includes a parallel portion 54 extending in a direction parallel to the extending direction of the data line DL and the touch line TL, wherein the difference between the first protrusion 52 and the second protrusion 52 and the parallel portion 54 is that the width of the first protrusion 52 along the first direction X and the width of the second protrusion 52 along the first direction X are both greater than the width of the parallel portion 54 along the first direction X.

[0186] In one implementation, Fig.35 As shown, along the direction perpendicular to the extension direction of the scanning line SL, the width of the second protrusion 53 is equal to 0, that is, no protrusion is provided on the side of the second side 512 away from the first side 511.

[0187] In one implementation, Fig.36 As shown, along the direction perpendicular to the extending direction of the scan line SL, the width of the second protrusion 53 is greater than 0, that is, the protrusion is provided on the side of the second edge 512 away from the first side 511 .

[0188] Fig.37 A schematic diagram of a display device provided in an embodiment of the present application.

[0189] In one embodiment of the present application, Fig.37 As shown, the present application provides a display device, including a display panel 001 as provided in any of the above embodiments. Exemplarily, the display device may be an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and a vehicle-mounted display device, and the embodiments of the present invention are not limited thereto.

[0190] The display device using the inventive concept of the present application can have a thinner body thickness, simple process steps and low preparation cost.

[0191] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a first substrate, wherein the first substrate comprises: a first substrate; A transistor array layer, disposed on one side of the first substrate; the transistor array layer includes transistors; A pixel electrode layer and a common electrode layer are both arranged on a side of the transistor array layer away from the first substrate; the pixel electrode layer includes a pixel electrode, and the common electrode layer includes a common electrode; A first inorganic insulating layer, wherein the insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is the first inorganic insulating layer; A second inorganic insulating layer, disposed between the pixel electrode layer and the common electrode layer; The display panel further includes: a second substrate, the second substrate comprising a second base; A support column, disposed between the first substrate and the second substrate; Wherein, the first substrate further comprises a scan line and a data line, and the extension direction of the scan line intersects with the extension direction of the data line; along a direction perpendicular to the surface where the display panel is located, the support column overlaps with at least a portion of the data line; The first substrate further includes a black matrix, and / or the second substrate further includes a black matrix; the black matrix includes: A first main body portion, wherein the extension direction of the first main body portion is parallel to the extension direction of the scan line; the first main body portion covers the scan line in a direction perpendicular to the surface where the display panel is located; the first main body portion comprises a first side and a second side opposite to each other, the extension directions of the first side and the second side are both parallel to the scan line, and the arrangement direction of the first side and the second side is perpendicular to the extension direction of the scan line; A plurality of first protrusions are arranged on a side of the first edge away from the second edge, and the first protrusions are connected to the first edge; A plurality of second protrusions, arranged on a side of the second edge away from the first edge, the second protrusions being connected to the second edge; Among them, along the direction perpendicular to the surface where the display panel is located, the first protrusion at least partially overlaps with the support column and the second protrusion does not overlap with the support column; along the direction perpendicular to the extension direction of the scanning line, the width of the first protrusion is greater than the width of the second protrusion.

2. The display panel according to claim 1, characterized in that: The film thickness of the first inorganic insulating layer is less than or equal to 6000 angstroms; and / or the film thickness of the second inorganic insulating layer is less than or equal to 6000 angstroms.

3. The display panel according to claim 1, characterized in that: The first inorganic insulating layer includes at least one of silicon oxide and silicon nitride; and / or the second inorganic insulating layer includes at least one of silicon oxide and silicon nitride.

4. The display panel according to claim 1, characterized in that: The transistor includes a polysilicon semiconductor layer.

5. The display panel according to claim 1, characterized in that: The first substrate further includes a touch control wiring, the touch control wiring is arranged on a side of the first inorganic insulating layer close to the first substrate, and the touch control wiring provides a signal for the common electrode; A first slit is formed on the common electrode, and along a direction perpendicular to the surface where the display panel is located, at least a portion of the first slit overlaps with a portion of the touch wiring; and / or, Second slits are provided between adjacent common electrodes, and along a direction perpendicular to the surface where the display panel is located, at least a portion of the second slits at least partially overlaps with at least a portion of the touch wiring.

6. The display panel according to claim 5, characterized in that: The first substrate further includes a dummy touch control wiring, wherein the dummy touch control wiring is arranged on the same layer as the touch control wiring and is electrically insulated from the common electrode; A first slit is provided on the common electrode, and along a direction perpendicular to the surface where the display panel is located, at least a portion of the first slit at least partially overlaps with the dummy touch line; and / or, Second slits are provided between adjacent common electrodes, and along a direction perpendicular to the surface where the display panel is located, at least a portion of the second slits at least partially overlaps with at least a portion of the dummy touch wiring.

7. The display panel according to claim 1, characterized in that: The first substrate further includes a data line, which is disposed on a side of the first inorganic insulating layer close to the first substrate, and provides a signal for the pixel electrode; A first slit is formed on the common electrode, and along a direction perpendicular to the surface where the display panel is located, the data line and the first slit do not overlap; and / or, A second slit is provided between adjacent common electrodes, and along a direction perpendicular to the surface where the display panel is located, the data line and the second slit do not overlap.

8. The display panel according to claim 1, characterized in that: The first substrate further includes a touch wiring, and the touch wiring is arranged on a side of the common electrode layer close to the first substrate; The first inorganic insulating layer is provided with a plurality of first via holes, and the second inorganic insulating layer is provided with a plurality of second via holes; Among them, the common electrode layer is arranged on a side of the pixel electrode layer close to the transistor array layer, and the pixel electrode layer also includes a bridge electrode; the bridge electrode is electrically connected to the common electrode through the second via hole, and the bridge electrode is electrically connected to the touch control trace through the second via hole and the first via hole.

9. The display panel according to claim 8, characterized in that: A first opening is formed on the common electrode; Along a direction perpendicular to a surface where the display panel is located, the first opening overlaps with the first via hole.

10. The display panel according to claim 9, characterized in that: At least two of the first openings have different opening areas.

11. The display panel according to claim 1, characterized in that: The first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode; A second opening is formed on the common electrode; along a direction perpendicular to the surface where the display panel is located, the second opening at least partially overlaps with the first electrode of the transistor; and / or, A third opening is formed on the common electrode; along a direction perpendicular to the surface where the display panel is located, the third opening at least partially overlaps with the second electrode of the transistor.

12. The display panel according to claim 11, characterized in that: When the common electrode is provided with a second opening, at least two of the second openings have different opening areas; and / or, When the common electrode is provided with a third opening, at least two of the third openings have different opening areas.

13. The display panel according to claim 1, characterized in that: Along a direction perpendicular to the surface where the display panel is located, the support column does not overlap with at least one of the scan line and the data line.

14. The display panel according to claim 13, characterized in that: Along a direction perpendicular to the surface where the display panel is located, the support column overlaps with at least a portion of the data line and does not overlap with the scan line.

15. The display panel according to claim 14, characterized in that: The data line comprises a first portion and a second portion, and along a direction perpendicular to the surface where the display panel is located, at least part of the support column overlaps with the first portion; The width of the first portion along a first direction is greater than the width of the second portion along the first direction, and the first direction is perpendicular to an extending direction of the data line.

16. The display panel according to claim 15, characterized in that: The outer contour of at least part of the first portion is in the shape of a cross.

17. The display panel according to claim 15, characterized in that: The first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode; Wherein, along a direction perpendicular to the surface where the display panel is located, the first portion overlaps with the first electrode of the transistor.

18. The display panel according to claim 14, characterized in that: The first substrate further includes a touch line, and the extension direction of the touch line is the same as the extension direction of the data line; along a direction perpendicular to the surface where the display panel is located, the support column overlaps with at least a portion of the touch line; The touch control wiring includes a third portion and a fourth portion, and along a direction perpendicular to the surface where the display panel is located, at least part of the support column overlaps with the third portion; The width of the third portion along a first direction is greater than the width of the fourth portion along the first direction, and the first direction is perpendicular to an extending direction of the touch wiring.

19. The display panel according to claim 14, characterized in that: A minimum distance between an orthographic projection of the support pillar on the first substrate and an orthographic projection of the scanning line on the substrate is greater than or equal to 2 μm.

20. The display panel according to claim 1, characterized in that: The first substrate further includes a data line and a touch line. The data line is electrically connected to the pixel electrode, the touch line is electrically connected to the common electrode, and the touch line and the data line are arranged in the same layer.

21. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-20.

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