Curvature compensation band-gap reference circuit with high power supply rejection ratio

Abstract

The invention discloses a curvature compensation band-gap reference circuit with a high power supply rejection ratio, which is characterized by comprising a pseudo power supply circuit, a starting circuit and a main body circuit, the pseudo power supply circuit is connected with the starting circuit, and the starting circuit is connected with the main body circuit; compared with a traditional band-gap reference circuit, the band-gap reference circuit has the advantages that the power supply rejection ratio of the band-gap reference voltage source is increased by using a pseudo power supply circuit technology, so that the reference voltage source can still keep stable when the power supply voltage changes; the influence of a linear component and a nonlinear component of a temperature coefficient in the circuit on the reference voltage is reduced through the main body circuit, so that the band-gap reference has a relatively low temperature drift coefficient in a wide temperature range, which is crucial for keeping the stability of the reference voltage; and on the premise of not increasing the scale of the circuit, the stability and reliability of the power supply can be effectively improved, and the overall performance of the power supply is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a curvature-compensated bandgap reference circuit with a high power supply rejection ratio. Background Art

[0002] The bandgap reference circuit is a voltage reference source widely used in integrated circuits. It has excellent temperature stability and is often used for high-precision voltage reference. Bandgap reference sources are widely used in analog devices such as motor drives, dynamic storage, and flash memory. As a voltage reference, they output a reference voltage that is independent of temperature. The working principle of the traditional bandgap reference circuit is based on the addition of a positive temperature coefficient voltage and a negative temperature coefficient voltage weight to obtain a voltage quantity that hardly changes with temperature. However, the voltage quantity with a positive temperature coefficient is not first-order, but has certain high-order temperature characteristics. Therefore, the traditional bandgap reference voltage source has poor temperature characteristics and is difficult to meet the requirements of high-performance analog circuits. This shortcoming can be calibrated by high-order compensation.

[0003] The bandgap reference circuit proposed in the patent "Low Voltage Adjustable Bandgap Reference Source Circuit" has two defects. On the one hand, the power supply rejection ratio of this circuit may not be very ideal, and the power supply noise has a great impact on the reference voltage. On the other hand, during the operation of the circuit, the first-order linear component of the temperature coefficient is eliminated by the transistor and the current mirror, and the temperature drift coefficient of the reference voltage is still large, which may not meet the accuracy requirements of some circuits; the bandgap reference circuit proposed in the patent "A Bandgap Reference Circuit Using Current Subtraction Technology" uses a bandgap reference circuit using current subtraction technology, including two negative temperature coefficient current generating circuits and a current subtraction circuit. In the two negative temperature coefficient current generating circuits, Q 2 The emitter is equal to Q 1 N times the emitter area, it converts the base and emitter voltage of the transistor with a negative temperature coefficient into a current with a negative temperature coefficient, and then subtracts the negative temperature coefficient currents with the same temperature coefficient but different amplitudes to obtain the reference current, and the reference current is multiplied by the resistance to obtain the reference voltage. However, this circuit has certain defects, and there is a problem that it is greatly affected by power supply noise, and the power supply suppression is relatively small. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a curvature-compensated bandgap reference circuit with high power supply rejection ratio.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a curvature compensation bandgap reference circuit with a high power supply rejection ratio, comprising: a pseudo power supply circuit, a startup circuit, and a main circuit; the pseudo power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit;

[0007] The pseudo power supply circuit is used to output a pseudo power supply output voltage to the startup circuit to improve the power supply rejection ratio;

[0008] The startup circuit is used to output a startup current to the main circuit according to the pseudo power supply output voltage, so that the main circuit starts to start;

[0009] The main circuit is used to generate a positive temperature coefficient current I after starting according to the starting current PTAT and negative temperature coefficient current I CTAT1 , and according to the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT1 The current I after first-order compensation is obtained CON , and then according to the current I after the first-order compensation CON Get the initial reference voltage V REF ; It is also used to eliminate the nonlinear component and the linear component in the initial reference voltage to obtain the final reference voltage V REF '.

[0010] Optionally, the pseudo power circuit includes: a transistor P M1 , transistor P M2 , transistor P M3 , transistor N M1 , transistor N M2 , transistor N M3 , transistor N M4 , resistor R 1 , resistor R 2 , resistor R 3 , operational amplifier OP1 and capacitor C 1 The transistor P M1 The source of the transistor P is connected to the power supply voltage VCC. M1 The drain of the transistor N M1 The drain of the transistor P M1 The gate of the transistor P M2 The gate of the transistor P M2 The source of the transistor P is connected to the power supply voltage VCC. M2 The drain of the transistor N M2 The drain of the transistor N M1 The gate and the transistor N M2 The gate of the transistor PM3 The source terminal of the transistor P is connected to the power supply voltage VCC. M3 The drain terminal and the capacitor C 1 The lower plate and the resistor R 2 The first terminal of the transistor P M3 The gate and the capacitor C 1 The upper plate of the transistor N is connected to the output terminal of the operational amplifier OP1; M1 The source of the transistor N M3 The drain of the transistor N M2 The source of the operational amplifier OP1 and the negative input terminal of the resistor R 1 The first end of the transistor N M4 The gate of the transistor N M3 The source of the transistor N is connected to GND. M3 The drain of the transistor N M1 The source of the transistor N M3 The gate and the resistor R 1 The second terminal of the transistor N M4 The drain of the transistor N M4 The source of the transistor N is connected to the GND. M4 The gate and the resistor R 1 The first end of the operational amplifier OP1, the negative input end of the operational amplifier OP1 and the transistor N M2 The source end is connected; the resistor R 2 The second end is connected to the positive input terminal of the operational amplifier OP1 and the resistor R 3 The first end of the resistor R 3 The second end is connected to the GND.

[0011] Optionally, the startup circuit includes: a transistor P M4 , transistor P M5 With capacitor C 2 The transistor P M4 The source and pseudo power supply output voltage V REG connection, the transistor P M4 The drain and the capacitor C 2 The upper plate and the transistor P M5 The gate of the transistor P is connected M4 The gate of the transistor P is connected to GND; M5 The source and the pseudo power supply output voltage V REG connection, the transistor P M5 The gate and the capacitor C 2 The upper plate and the transistor PM4 Drain connection.

[0012] Optionally, the main circuit includes a transistor P M6 , transistor P M7 , transistor P M8 , transistor P M9 , transistor P M10 , transistor P M11 , transistor P M12 , transistor Q 1 , transistor Q 2 , transistor Q 3 , operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, resistor R 4 , resistor R 5 , resistor R 6 , resistor R 7 , resistor R 8 and transistor N M5 The transistor P M6 The source and the pseudo power supply output voltage V REG connection, the transistor P M6 The drain of the operational amplifier OP2 is connected to the positive input terminal and the resistor R 4 The first terminal of the transistor P M6 The gate of the transistor P M5 The drain of the transistor P M7 The gate of the transistor P M8 The gate of the transistor P M12 The gate of the transistor P M7 The source and the pseudo power supply output voltage V REG connection, the transistor P M7 The drain of the operational amplifier OP2 is connected to the negative input terminal of the operational amplifier OP3 and the negative input terminal of the transistor Q 2 The emitter of the transistor P is connected; M8 The source and the pseudo power supply output voltage V REG connection, the transistor P M8 The drain of the transistor P M9 The drain of the operational amplifier OP4 and the positive input terminal of the transistor Q 3 The emitter of the transistor P is connected; M9 The source and the pseudo power supply output voltage V REG connection, the transistor P M9 The gate of the operational amplifier OP3 and the output terminal of the transistor P M10 The gate of the transistor PM11 The gate of the transistor P M10 The source and the pseudo power supply output voltage V REG connection, the transistor P M10 The drain of the operational amplifier OP3 and the positive input terminal of the resistor R 5 The first end of the transistor P is connected; M11 The source and the pseudo power supply output voltage V REG connection, the transistor P M11 The drain of the transistor N M5 The drain and the resistor R 7 The first end of the transistor P is connected; M12 The source and the pseudo power supply output voltage V REG connection, the transistor P M12 The drain and the resistor R 7 The second end and the resistor R 8 The first end of the transistor N is connected; M5 The source of the operational amplifier OP4 and the negative input terminal of the resistor R 6 The first terminal of the transistor N M5 The drain of the transistor P M11 The drain and the resistor R 7 The first terminal of the transistor N M5 The gate of the capacitor C is connected to the output terminal of the operational amplifier OP4; 2 The lower plate is connected to the GND, the resistor R 4 The second end of the transistor Q 1 The emitter connection, the resistor R 5 The second end of the resistor R 6 The second end of the resistor R 8 The second end of the transistor Q is connected to the GND. 1 The base and collector of the transistor Q are connected to the GND. 2 The base and collector of the transistor Q are connected to GND. 3 The base and collector are both connected to the GND.

[0013] Optionally, the positive temperature coefficient current I PTAT It is expressed as follows:

[0014]

[0015] Among them, I PTAT Represents the positive temperature coefficient current I PTAT, k is the Boltzmann constant, T is the absolute temperature, N 1 Indicates the transistor Q 1 and the transistor Q 2 The ratio of the emitter area, q is the electron charge, R 4 Represents the resistance R 4 resistance value.

[0016] Optionally, the negative temperature coefficient current I CTAT1 It is expressed as follows:

[0017]

[0018] Among them, I CTAT1 Represents the negative temperature coefficient current I CTAT1 , V BE2 The transistor Q 2 The base-emitter voltage, R 5 The resistance R 5 resistance value.

[0019] Optionally, the transistor Q 2 The base-emitter voltage V BE2 It is expressed as follows:

[0020]

[0021] Among them, V BE2 (T) represents the transistor Q when the temperature is T 2 The base-emitter voltage V BE2 , V g0 Represents the bandgap voltage of silicon at 0K, V BE2 (T r ) represents the temperature T r When the transistor Q 2 The base-emitter voltage V BE2 , η is the temperature constant, T r is the reference temperature.

[0022] Optionally, the initial reference voltage V REF It is expressed as follows:

[0023] V REF =I NPTAP ×(R 7 +R 8 )+I PTAT ×R 8 ;

[0024] Among them, V REF represents the initial reference voltage V REF , I NPTAPAccording to the negative temperature coefficient current I CTAT1 The resulting characteristic current, I PTAT is the positive temperature coefficient current I PTAT , R 7 The resistor R 7 The resistance value, R 8 The resistor R 8 resistance value.

[0025] Optionally, the final reference voltage V REF ' means as follows:

[0026]

[0027] Among them, V REF ' is the final reference voltage V REF ', R 6 The resistor R 6 resistance value.

[0028] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0029] In the above technical scheme, compared with the traditional bandgap reference circuit, the present invention improves the power supply rejection ratio of the bandgap reference voltage source by using pseudo power supply circuit technology, so that the reference voltage source can remain stable when the power supply voltage changes; and reduces the influence of the linear component and nonlinear component of the temperature coefficient in the circuit on the reference voltage through the main circuit, so that the bandgap reference has a lower temperature drift coefficient within a wide temperature range, which is crucial for maintaining the stability of the reference voltage; and without increasing the scale of the circuit, it can effectively improve the stability and reliability of the power supply and improve the overall performance of the power supply.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The invention is a schematic structural diagram of a curvature-compensated bandgap reference circuit with a high power supply rejection ratio provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0033] Figure 1 is a schematic diagram of the structure of a curvature compensation bandgap reference circuit with high power supply rejection ratio provided by an embodiment of the present invention, such as Figure 1 As shown, it includes: a pseudo power supply circuit, a startup circuit, and a main circuit; the pseudo power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit; as shown Figure 1 As shown, the part within the green dashed box is the pseudo power supply circuit, the part within the purple dashed box is the startup circuit, and the part within the red dashed box is the main circuit.

[0034] As Figure 1 shown, the pseudo power supply circuit includes: transistor P M1 , transistor P M2 , transistor P M3 , transistor N M1 , transistor N M2 , transistor N M3 , transistor N M4 , resistor R 1 , resistor R 2 , resistor R 3 , operational amplifier OP1 and capacitor C 1 ; the source of transistor P M1 is connected to the power supply voltage VCC, and the drain of transistor P M1 is connected to the drain of transistor N M1 , the gate of transistor P M1 , and the gate of transistor P M2 ; the source of transistor P M2 is connected to the power supply voltage VCC, and the drain of transistor P M2 is connected to the drain of transistor N M2 , the gate of transistor N M1 , and the gate of transistor N M2 ; the source terminal of transistor P M3 is connected to the power supply voltage VCC, and the drain terminal of transistor P M3 is connected to the lower plate of capacitor C 1 and the first end of resistor R 2 ; the gate of transistor P M3 is connected to the upper plate of capacitor C 1 and the output terminal of operational amplifier OP1; the source of transistor N M1 is connected to the drain of transistor N M3 ; the source of transistor N M2 is connected to the negative input terminal of operational amplifier OP1, the first end of resistor R 1 , and the gate of transistor N M4 ; the source of transistor N M3 is connected to GND, the drain of transistor N M3 is connected to the source of transistor N M1 , and the gate of transistor N M3 is connected to resistor R 1The second terminal of the transistor N M4 The drain of the transistor N M4 The source of the transistor N is connected to the GND. M4 The gate and the resistor R 1 The first end of the operational amplifier OP1, the negative input end of the operational amplifier OP1 and the transistor N M2 The source end is connected; the resistor R 2 The second end is connected to the positive input terminal of the operational amplifier OP1 and the resistor R 3 The first end of the resistor R 3 The second end is connected to the GND.

[0035] like Figure 1 As shown, the startup circuit includes: a transistor P M4 , transistor P M5 With capacitor C 2 The transistor P M4 The source and pseudo power supply output voltage V REG connection, the transistor P M4 The drain and the capacitor C 2 The upper plate and the transistor P M5 The gate of the transistor P is connected M4 The gate of the transistor P is connected to GND; M5 The source and the pseudo power supply output voltage V REG connection, the transistor P M5 The gate and the capacitor C 2 The upper plate and the transistor P M4 Drain connection.

[0036] like Figure 1 As shown, the main circuit includes a transistor P M6 , transistor P M7 , transistor P M8 , transistor P M9 , transistor P M10 , transistor P M11 , transistor P M12 , transistor Q 1 , transistor Q 2 , transistor Q 3 , operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, resistor R 4 , resistor R 5 , resistor R 6 , resistor R 7 , resistor R 8 and transistor N M5 The transistor P M6The source of is connected to the pseudo power supply output voltage V REG The drain of the transistor P M6 is connected to the positive input terminal of the operational amplifier OP2 and the first terminal of the resistor R 4 The source of the transistor P M6 The gate of is connected to the output terminal of the operational amplifier OP2, the drain of the transistor P M5 The gate of the transistor P M7 The gate of the transistor P M8 The gate of the transistor P M12 The gate of the transistor P M7 The source of the transistor P REG is connected to the pseudo power supply output voltage V M7 The drain of the transistor P 2 is connected to the negative input terminal of the operational amplifier OP2, the negative input terminal of the operational amplifier OP3 and the emitter of the triode Q M8 The source of the transistor P REG is connected to the pseudo power supply output voltage V M8 The drain of the transistor P M9 is connected to the drain of the transistor P 3 The positive input terminal of the operational amplifier OP4 and the emitter of the triode Q M9 The source of the transistor P REG is connected to the pseudo power supply output voltage V M9 The gate of the transistor P M10 The gate of the transistor P M11 The gate of the transistor P M10 The source of the transistor P REG is connected to the pseudo power supply output voltage V M10 The drain of the transistor P 5 is connected to the positive input terminal of the operational amplifier OP3 and the first terminal of the resistor R M11 The source of the transistor P REG is connected to the pseudo power supply output voltage V M11 The drain of the transistor P M5 is connected to the drain of the transistor N 7 The first terminal of the resistor R M12 The source of the transistor P REG is connected to the pseudo power supply output voltage V M12 The drain of the transistor P 7 The second terminal of the resistor R and the first terminal of the resistor R 8 The first terminal of the transistor NM5 The source of the operational amplifier OP4 and the negative input terminal of the resistor R 6 The first terminal of the transistor N M5 The drain of the transistor P M11 The drain and the resistor R 7 The first terminal of the transistor N M5 The gate of the capacitor C is connected to the output terminal of the operational amplifier OP4; 2 The lower plate is connected to the GND, the resistor R 4 The second end of the transistor Q 1 The emitter connection, the resistor R 5 The second end of the resistor R 6 The second end of the resistor R 8 The second end of the transistor Q is connected to the GND. 1 The base and collector of the transistor Q are connected to the GND. 2 The base and collector of the transistor Q are connected to GND. 3 The base and collector are both connected to the GND.

[0037] The pseudo power supply circuit is used to output a pseudo power supply output voltage to the startup circuit to improve the power supply rejection ratio.

[0038] It can be understood that the two PMOS tubes P in the pseudo power circuit M1 , P M2 And four NMOS tubes N M1 、N M2 、N M3 、N M4 It forms an auxiliary bandgap and can provide bias for the operational amplifier. The pseudo power supply technology can increase the power supply rejection ratio of the bandgap reference by nearly A1 times, where A1 is the gain of the operational amplifier OP1 in the pseudo power supply circuit.

[0039] The startup circuit is used to output a startup current to the main circuit according to the pseudo power supply output voltage, so that the main circuit starts to start.

[0040] It can be understood that the transistor P M4 , transistor P M5 and capacitor C2 form the startup part of the current-type bandgap; at the beginning of power-on, transistor P M4 conduction, to the capacitor C 2 Start charging, at this time transistor P M5 The gate of transistor P is low, so M5When the capacitor is fully charged, transistor P M5 The gate of transistor P is high. M5 The shutdown and startup circuits ensure the stability and reliability of the overall circuit.

[0041] The main circuit is used to generate a positive temperature coefficient current I after starting according to the starting current PTAT and negative temperature coefficient current I CTAT1 , and according to the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT1 The current I after first-order compensation is obtained CON , and then according to the current I after the first-order compensation CON Get the initial reference voltage V REF ; It is also used to eliminate the nonlinear component and the linear component in the initial reference voltage to obtain the final reference voltage V REF '.

[0042] It is understandable that if Figure 1 As shown, through the clamping effect of operational amplifier OP2, operational amplifier OP3 and operational amplifier OP4 and transistor Q 1 , transistor Q 2 And transistor Q 3 The temperature characteristics of the positive temperature coefficient current I PTAT and negative temperature coefficient current I CTAT1 The generation of the current is achieved by adding two currents with opposite temperature coefficients at point C and setting the resistor R 4 and resistor R 5 resistance value, the positive temperature coefficient current I PTAT With negative temperature coefficient current I CTAT1 The current I after superposition is obtained after first-order compensation CON .

[0043] Optionally, the positive temperature coefficient current I PTAT It is expressed as follows:

[0044]

[0045] Among them, I PTAT Represents the positive temperature coefficient current I PTAT , k is the Boltzmann constant, T is the absolute temperature, N 1 Indicates the transistor Q 1 and the transistor Q 2 The ratio of the emitter area, q is the electron charge, R 4 Represents the resistance R 4 resistance value.

[0046] Negative temperature coefficient current I CTAT1 is expressed as follows:

[0047]

[0048] wherein, I CTAT1 represents the negative temperature coefficient current I CTAT1 , V BE2 is the base-emitter voltage of the triode Q 2 , R 5 is the resistance value of the resistor R 5 .

[0049] The base-emitter voltage V of the triode Q 2 is expressed as follows: BE2 is expressed as follows:

[0050]

[0051] wherein, V BE2 (T) represents the base-emitter voltage V of the triode Q at temperature T 2 , V BE2 , V g0 represents the bandgap voltage of silicon at 0K, V BE2 (T r ) represents the base-emitter voltage V of the triode Q at temperature T r , η is the temperature constant, T 2 is the reference temperature. BE2 , η is the temperature constant, T r is the reference temperature.

[0052] Since the base-emitter voltage V of the triode Q 3 is generated by the current I injected into the emitter of the triode Q BE3 , the base-emitter voltage of the triode Q can be expressed as follows: 3 is generated by the current I injected into the emitter of the triode Q CON , the base-emitter voltage of the triode Q can be expressed as follows: 3 is expressed as follows:

[0053]

[0054] wherein, V BE3 (T) represents the base-emitter voltage V of the triode Q at temperature T 3 , V BE3 , V BE3 (T r ) represents the base-emitter voltage V of the triode Q at temperature T r , V 3 is the base-emitter voltage V of the triode Q BE3 .

[0055] Figure 1The second negative temperature coefficient current I CTAT2 It is expressed as follows:

[0056]

[0057] Among them, R 6 is the resistance R 6 resistance value.

[0058] According to Kirchhoff's current law, the characteristic current I NPTAT The expression is as follows:

[0059] I NPTAP =I CTAT1 -I CTAT2 ;

[0060] According to the above formula, the characteristic current I NPTAT The expression is as follows:

[0061]

[0062] Since the initial reference voltage V REF It is expressed as follows:

[0063] V REF =I NPTAP ×(R 7 +R 8 )+I PTAT ×R 8 ;

[0064] Among them, V REF represents the initial reference voltage V REF , I NPTAP According to the negative temperature coefficient current I CTAT1 The resulting characteristic current, I PTAT is the positive temperature coefficient current I PTAT , R 7 The resistor R 7 The resistance value, R 8 The resistor R 8 resistance value.

[0065] The positive temperature coefficient current I PTAT and characteristic current I NPTAT Substitute the formula into it and get the initial reference voltage V REF Further statement:

[0066]

[0067] If the nonlinear component representing temperature in the above equation is If it is equal to 0, the nonlinear component in the formula can be eliminated, and the initial reference voltage V after eliminating the nonlinear componentREF The expression is as follows:

[0068]

[0069] make Equal to, the linear component in the formula can be eliminated to obtain a stable final reference voltage V that is not affected by temperature. REF ' means as follows:

[0070]

[0071] Among them, V REF ' is the final reference voltage V REF ', R 6 The resistance R 6 resistance value.

[0072] In the above technical scheme, compared with the traditional bandgap reference circuit, the present invention improves the power supply rejection ratio of the bandgap reference voltage source by using pseudo power supply circuit technology, so that the reference voltage source can remain stable when the power supply voltage changes; and reduces the influence of the linear component and nonlinear component of the temperature coefficient in the circuit on the reference voltage through the main circuit, so that the bandgap reference has a lower temperature drift coefficient within a wide temperature range, which is crucial for maintaining the stability of the reference voltage; and without increasing the scale of the circuit, it can effectively improve the stability and reliability of the power supply and improve the overall performance of the power supply.

[0073] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0075] Although the present invention has been described in connection with various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the accompanying drawings and the disclosure. In the description of the present invention, the term "comprising" does not exclude other components or steps, the indefinite article "a" or "an" does not exclude a plurality, and the meaning of "plurality" is two or more unless otherwise specifically defined. In addition, certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0076] The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A curvature-compensated bandgap reference circuit with high power supply rejection ratio, characterized in that: include: Pseudo power supply circuit, startup circuit, main circuit; The pseudo power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit; The pseudo power supply circuit is used to output a pseudo power supply output voltage to the startup circuit to improve the power supply rejection ratio; The startup circuit is used to output a startup current to the main circuit according to the pseudo power supply output voltage, so that the main circuit starts to start; The main circuit is used to generate a positive temperature coefficient current I after starting according to the starting current PTAT and negative temperature coefficient current I CTAT1 , and according to the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT1 The current I after first-order compensation is obtained CON , and then according to the current I after the first-order compensation CON Get the initial reference voltage V REF ; It is also used to eliminate the nonlinear component and the linear component in the initial reference voltage to obtain the final reference voltage V REF '.

2. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 1, characterized in that: The pseudo power supply circuit comprises: a transistor P M1 , transistor P M2 , transistor P M3 , transistor N M1 , transistor N M2 , transistor N M3 , transistor N M4 , resistor R1, resistor R2, resistor R3, operational amplifier OP1 and capacitor C1; the transistor P M1 The source of the transistor P is connected to the power supply voltage VCC. M1 The drain of the transistor N M1 The drain of the transistor P M1 The gate of the transistor P M2 The gate of the transistor P M2 The source of the transistor P is connected to the power supply voltage VCC. M2 The drain of the transistor N M2 The drain of the transistor N M1 The gate and the transistor N M2 The gate of the transistor P M3 The source terminal of the transistor P is connected to the power supply voltage VCC. M3 The drain end of the transistor P is connected to the lower plate of the capacitor C1 and the first end of the resistor R2. M3 The gate of the transistor N is connected to the upper plate of the capacitor C1 and the output end of the operational amplifier OP1; M1 The source of the transistor N M3 The drain of the transistor N M2 The source of the operational amplifier OP1, the negative input terminal of the operational amplifier OP1, the first terminal of the resistor R1, the transistor N M4 The gate of the transistor N M3 The source of the transistor N is connected to GND. M3 The drain of the transistor N M1 The source of the transistor N M3 The gate of the transistor N M4 The drain of the transistor N M4 The source of the transistor N is connected to the GND. M4 The gate of the transistor N1 is connected to the first end of the resistor R1, the negative input end of the operational amplifier OP1 and the M2 The second end of the resistor R2 is connected to the positive input end of the operational amplifier OP1 and the first end of the resistor R3; the second end of the resistor R3 is connected to the GND.

3. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 1, characterized in that: The startup circuit includes: a transistor P M4 , transistor P M5 and capacitor C2; the transistor P M4 The source and pseudo power supply output voltage V REG connection, the transistor P M4 The drain of the capacitor C2 and the upper plate of the transistor P M5 The gate of the transistor P is connected M4 The gate of the transistor P is connected to GND; M5 The source and the pseudo power supply output voltage V REG connection, the transistor P M5 The gate of the transistor P M4 Drain connection.

4. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 3, characterized in that: The main circuit includes a transistor P M6 , transistor P M7 , transistor P M8 , transistor P M9 , transistor P M10 , transistor P M11 , transistor P M12 , transistor Q1, transistor Q2, transistor Q3, operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8 and transistor N M5 The transistor P M6 The source and the pseudo power supply output voltage V REG connection, the transistor P M6 The drain of the transistor P is connected to the positive input terminal of the operational amplifier OP2 and the first end of the resistor R4. M6 The gate of the transistor P M5 The drain of the transistor P M7 The gate of the transistor P M8 The gate of the transistor P M12 The gate of the transistor P M7 The source and the pseudo power supply output voltage V REG connection, the transistor P M7 The drain of the transistor P is connected to the negative input terminal of the operational amplifier OP2, the negative input terminal of the operational amplifier OP3 and the emitter of the transistor Q2; M8 The source and the pseudo power supply output voltage V REG connection, the transistor P M8 The drain of the transistor P M9 The drain of the transistor P is connected to the positive input terminal of the operational amplifier OP4 and the emitter of the transistor Q3; M9 The source and the pseudo power supply output voltage V REG connection, the transistor P M9 The gate of the operational amplifier OP3 and the output terminal of the transistor P M10 The gate of the transistor P M11 The gate of the transistor P M10 The source and the pseudo power supply output voltage V REG connection, the transistor P M10 The drain of the transistor P is connected to the positive input terminal of the operational amplifier OP3 and the first end of the resistor R5; M11 The source and the pseudo power supply output voltage V REG connection, the transistor P M11 The drain of the transistor N M5 The drain of the transistor P is connected to the first end of the resistor R7; M12 The source and the pseudo power supply output voltage V REG connection, the transistor P M12 The drain of the transistor N is connected to the second end of the resistor R7 and the first end of the resistor R8; M5 The source of the transistor N is connected to the negative input terminal of the operational amplifier OP4 and the first end of the resistor R6. M5 The drain of the transistor P M11 The drain of the transistor N is connected to the first end of the resistor R7. M5 The gate of the transistor is connected to the output end of the operational amplifier OP4; the lower plate of the capacitor C2 is connected to the GND, the second end of the resistor R4 is connected to the emitter of the transistor Q1, the second end of the resistor R5 is connected to the GND, the second end of the resistor R6 is connected to the GND, the second end of the resistor R8 is connected to the GND, the base and collector of the transistor Q1 are both connected to the GND, the base and collector of the transistor Q2 are both connected to the GND, and the base and collector of the transistor Q3 are both connected to the GND.

5. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 4, characterized in that: The positive temperature coefficient current I PTAT It is expressed as follows: Among them, I PTAT Represents the positive temperature coefficient current I PTAT , k is the Boltzmann constant, T is the absolute temperature, N1 represents the ratio of the emitter area of ​​the transistor Q1 to the emitter area of ​​the transistor Q2, q is the amount of electron charge, and R4 represents the resistance value of the resistor R4.

6. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 5, characterized in that: The negative temperature coefficient current I CTAT1 It is expressed as follows: Among them, I CTAT1 Represents the negative temperature coefficient current I CTAT1 , V BE2 is the base-emitter voltage of the transistor Q2, and R5 is the resistance value of the resistor R5.

7. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 6, characterized in that: The base-emitter voltage V of the transistor Q2 BE2 It is expressed as follows: Among them, V BE2 (T) represents the base-emitter voltage V of the transistor Q2 when the temperature is T BE2 , V g0 Represents the bandgap voltage of silicon at 0K, V BE2 (T r ) represents the temperature T r When the base-emitter voltage V BE2 , η is the temperature constant, T r is the reference temperature.

8. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 6, characterized in that: The initial reference voltage V REF It is expressed as follows: V REF =I NPTAP ×(R7+R8)+I PTAT ×R8; Among them, V REF represents the initial reference voltage V REF , I NPTAP According to the negative temperature coefficient current I CTAT1 The resulting characteristic current, I PTAT is the positive temperature coefficient current I PTAT , R7 is the resistance value of the resistor R7, and R8 is the resistance value of the resistor R8.

9. The curvature compensated bandgap reference circuit with high power supply rejection ratio according to claim 8, characterized in that: The final reference voltage V REF ' means as follows: Among them, V REF ' is the final reference voltage V REF ', R6 is the resistance value of the resistor R6.

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