Deep learning oriented coarse-grained reconfigurable array system and computing method

Abstract

The disclosure provides a coarse-grained reconfigurable array system and a computing method for deep learning, which can be applied to the technical field of reconfigurable array. The system comprises a controller configured to determine input information input to at least one processing unit, wherein the input information comprises to-be-computed data, operation instructions and mode control instructions; and a processing unit group comprising a plurality of processing units, the plurality of processing units forming a reconfigurable array, and each processing unit being configured to perform floating point operation or integer operation on the to-be-computed data based on the mode control instructions and the operation instructions to obtain an operation result. The processing unit comprises an operand selector configured to determine first operation data and second operation data from neighbor operation results, weight data and input data based on the operation instructions; and an arithmetic logic subunit configured to perform floating point operation or integer operation on the first operation data and the second operation data based on operation sub-instructions corresponding to the mode control instructions to obtain the operation result.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of reconfigurable array, in particular to a coarse-grained reconfigurable array system and a computing method for deep learning. BACKGROUND

[0002] Coarse-grained reconfigurable array (CGRA) is an architecture that performs computing tasks according to data flow configuration of instruction and data information. In existing coarse-grained reconfigurable arrays, most architectures only support integer data computing in consideration of high energy efficiency of computing and precision of supporting target network. However, in scenarios with relatively high precision requirements, such as training scenarios of deep learning models, floating-point data needs to be used to improve training precision.

[0003] In related technologies, the following method is usually used to realize computing of CGRA on floating-point data, such as directly embedding a special floating-point processing unit (FPU) in a processing unit of CGRA. However, this method will greatly increase hardware overhead and reduce energy efficiency advantage of the coarse-grained reconfigurable array, thereby limiting application. SUMMARY

[0004] In view of the above problems, the present disclosure provides a coarse-grained reconfigurable array system and a computing method for deep learning.

[0005] According to an aspect of the present disclosure, a coarse-grained reconfigurable array system for deep learning is provided, the system comprising:

[0006] a controller configured to determine input information input to at least one processing unit, wherein the input information comprises to-be-computed data, operation instructions and mode control instructions; and a processing unit group comprising a plurality of processing units, the plurality of processing units forming a reconfigurable array, each processing unit being configured to perform floating-point operation or integer operation on the to-be-computed data based on the mode control instructions and the operation instructions to obtain an operation result; wherein the to-be-computed data comprises input data and weight data, and the processing unit comprises an operand selector and an arithmetic logic subunit; the operand selector is configured to receive neighbor operation results output by neighbor processing units, and determine first operation data and second operation data from the neighbor operation results, the weight data and the input data based on the operation instructions, wherein the neighbor processing units are processing units adjacent to the processing unit; and the arithmetic logic subunit is configured to determine an operation subinstruction corresponding to the mode control instructions from the operation instructions, so as to perform floating-point operation or integer operation on the first operation data and the second operation data based on the operation subinstruction to obtain the operation result.

[0007] Another aspect of the present disclosure provides a deep learning oriented coarse-grained reconfigurable array computing method, comprising: determining, by a controller, input information input to at least one processing unit, wherein the input information comprises to-be-computed data, operation instructions and mode control instructions; inputting, by an input bus, the to-be-computed data to the at least one processing unit; inputting, by a configuration bus, the operation instructions to the at least one processing unit; performing, by each processing unit, floating point operation or integer operation on the to-be-computed data based on the mode control instructions and the operation instructions to obtain operation results; and outputting, by an output bus, the operation results.

[0008] According to the deep learning oriented coarse-grained reconfigurable array system of the present disclosure, the mode control instructions and the operation instructions are input by the controller, so that the processing unit group can perform floating point operation or integer operation on the to-be-computed data based on the mode control instructions and the operation instructions. Specifically, the processing unit comprises an operand selector and an arithmetic logic subunit. When performing the computation, the operand selector is used to select the first operation data and the second operation data, and the arithmetic logic subunit is used to determine the operation subinstruction corresponding to the mode control instruction from the operation subinstruction, so as to perform floating point operation or integer operation on the first operation data and the second operation data based on the operation subinstruction. Thus, the technical problem of large hardware overhead caused by directly embedding a floating point processing unit in the CGRA architecture for only integer computation in the related art is solved, that is, the computing effect of being able to perform computation on both integer data and floating point data is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of the deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure is schematically shown;

[0011] Figure 2 A schematic diagram of the floating point operation data BF16 format according to an embodiment of the present disclosure is schematically shown;

[0012] Figure 3 A schematic diagram of the processing unit of the deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure is schematically shown;

[0013] Figure 4 A schematic diagram of the arithmetic logic subunit of the deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure is schematically shown;

[0014] Figure 5FIG. 6(a) schematically illustrates a first reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0015] FIG. 6(a) schematically illustrates a first reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0016] FIG. 6(b) schematically illustrates a second reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0017] FIG. 6(c) schematically illustrates a third reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0018] FIG. 6(d) schematically illustrates a fourth reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0019] Figure 7 FIG. 6(d) schematically illustrates a fourth reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0020] Figure 8 FIG. 6(d) schematically illustrates a fourth reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure;

[0021] Figure 9 FIG. 6(d) schematically illustrates a fourth reconfiguration schematic of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure; DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present disclosure, and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it would be apparent to one skilled in the art that the present disclosure can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present disclosure.

[0023] The terms used herein are merely used to describe specific embodiments, and are not intended to limit the present disclosure. The terms "include" and "have" and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be further noted that the use of any terms herein should not be interpreted to exclude from the scope of the specification other embodiments that would benefit from being within the scope of the present disclosure.

[0025] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should generally be interpreted that the meaning of the expression includes each and every combination of one of the items from the group consisting of A, B, and C.

[0026] It should be noted that the deep learning-oriented coarse-grained reconfigurable array system and computing method of the present disclosure can be used in the field of reconfigurable array technology, and can also be used in any field other than the field of reconfigurable array technology, such as the field of artificial intelligence technology. The application field of the deep learning-oriented coarse-grained reconfigurable array system and computing method of the present disclosure is not limited.

[0027] In the research process, it is found that in the existing coarse-grained reconfigurable array, considering the high energy efficiency of the calculation and the accuracy of the support target network, most architectures only support integer data calculation. When higher precision is required or other networks are to be supported, the calculation results of such architecture are insufficient to support real-world applications. BF16 (Brain Floating Point 16-bit, 16-bit floating point) format is a floating point data representation mainly for deep learning, which has the same exponent bits as FP32, but only 7 bits of mantissa. Many modern hardware architectures have provided native support for BF16, including Google TPU, NVIDIA A100 GPU, which can greatly improve AI performance while ensuring neural network accuracy. If a dedicated floating point processing unit (FPU) is directly embedded in the processing unit of the array, it will greatly increase the hardware overhead (about 25%), which will reduce the energy efficiency advantage of the coarse-grained reconfigurable array, thereby limiting the application. If the instruction reconstruction method is used to complete the floating point calculation, although there is no hardware overhead, it takes more than 100 clock cycles to complete an average floating point operation, which cannot support the computing power demand of neural networks.

[0028] In view of this, the embodiment of the present disclosure provides a deep learning oriented coarse-grained reconfigurable array system, comprising: a controller configured to determine input information input to at least one processing unit, wherein the input information comprises to-be-computed data, operation instructions and mode control instructions; and a processing unit group comprising a plurality of processing units, the plurality of processing units forming a reconfigurable array, and each processing unit being configured to perform floating point operation or integer operation on the to-be-computed data based on the mode control instructions and the operation instructions to obtain an operation result; wherein the to-be-computed data comprises input data and weight data, and each processing unit comprises: an operand selector and an arithmetic logic subunit; the operand selector is configured to receive neighbor operation results output by neighbor processing units, and determine first operation data and second operation data from the neighbor operation results, the weight data and the input data based on the operation instructions, wherein the neighbor processing units are processing units adjacent to the processing unit; and the arithmetic logic subunit is configured to determine operation sub-instructions corresponding to the mode control instructions from the operation instructions, so as to perform floating point operation or integer operation on the first operation data and the second operation data based on the operation sub-instructions to obtain the operation result.

[0029] Figure 1 An illustrative diagram of a deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure is shown schematically.

[0030] As Figure 1 shown, the system comprises a controller 11, a processing unit group 12, an input storage unit 13, an output storage unit 14, an input bus 15, a configuration bus 16 and an output bus 17.

[0031] The controller 11 is configured to determine input information input to at least one processing unit, wherein the input information comprises to-be-computed data, operation instructions and mode control instructions.

[0032] The processing unit group 12 comprises a plurality of processing units, the plurality of processing units forming a reconfigurable array, and each processing unit being configured to perform floating point operation or integer operation on the to-be-computed data based on the mode control instructions and the operation instructions to obtain an operation result; wherein the to-be-computed data comprises input data and weight data, and each processing unit comprises: an operand selector and an arithmetic logic subunit; the operand selector is configured to receive neighbor operation results output by neighbor processing units, and determine first operation data and second operation data from the neighbor operation results, the weight data and the input data based on the operation instructions, wherein the neighbor processing units are processing units adjacent to the processing unit; and the arithmetic logic subunit is configured to determine operation sub-instructions corresponding to the mode control instructions from the operation instructions, so as to perform floating point operation or integer operation on the first operation data and the second operation data based on the operation sub-instructions to obtain the operation result.

[0033] According to an embodiment of the present disclosure, the controller 11 is configured to control the start and end of the operation, data loading, and array computing mode according to the configuration information delivered by the data stream.

[0034] According to an embodiment of the present disclosure, the configuration information includes instruction information such as state instructions and mode control instructions. The state instructions are used to control the related operations of the operation instructions, and can include the number of operation instructions, the execution order of the operation instructions, the number of state instructions, the number of weights, the number of small outer loops, the number of large outer loops, the small outer loop weight base address increment, the parameter of the large outer loop weight base address increment, and the like. The mode control instructions are used to control the operation mode of the current operation.

[0035] According to an embodiment of the present disclosure, the operation instructions are instructions used to control the processing units to perform operations.

[0036] According to an embodiment of the present disclosure, in some embodiments, the controller 11 configures the processing unit group 12 with the number of operation instructions, the number of state instructions, the number of weights, the number of small outer loops, the number of large outer loops, the small outer loop weight base address increment, the parameter of the large outer loop weight base address increment, and the mode control instructions in the order of the instructions in the configuration information.

[0037] According to an embodiment of the present disclosure, the processing unit group 12 forms an array, and the length and width of the array can be configured according to parameters. Each processing unit can be interconnected with the processing units above, below, left, and right thereof. Each processing unit initially receives configuration information from the controller 11, such as the number of loops, floating point control, and loading of operation instructions, loading of weight data, and output of result data. The processing unit array shares an output bus 17 by row and an input bus 15 by column to reduce wiring pressure.

[0038] According to an embodiment of the present disclosure, the processing unit group 12 includes a plurality of processing units, each of which performs operations on specified data according to operation instructions stored therein, and each of which supports two sets of instruction sets for integer and BF16 format data.

[0039] According to an embodiment of the present disclosure, the input storage unit 13 and the output storage unit 14 are composed of a group of input / output FIFOs. The input storage unit 13 is used to buffer input data, and the bus and the top-level controller 11 are used to configure the working mode of the processing unit, instruction data, and weight data, and output the final calculation result.

[0040] According to an embodiment of the present disclosure, the input bus 15 is used to input weight data and input data to at least one processing unit. The configuration bus 16 is used to input configuration information and operation instructions to at least one processing unit. The output bus 17 is used to output operation results by at least one processing unit.

[0041] According to embodiments of the present disclosure, the array adopts distributed storage to reduce dynamic power consumption, each processing unit has local register to store instructions and weight data to support deep learning-oriented computation.

[0042] According to embodiments of the present disclosure, the array needs to prepare operation instructions and weight data of each processing unit before starting to perform a computation task, the controller 11 controls the data input FIFO and the instruction FIFO to pre-load operation instructions and weight data and configuration information to the processing units, the configuration information can include whether each processing unit performs floating-point operation to perform computation according to different instruction sets.

[0043] According to embodiments of the present disclosure, each processing unit has two operands, i.e. first operation data and second operation data, when computing in a single cycle. The instruction computation on the first operation data and the second operation data can be determined as integer operation or floating-point operation according to the mode control instruction. The BF16 format floating-point computation in a single cycle is realized by multiplexing the integer computation resources in the conventional coarse-grained reconfigurable array.

[0044] According to embodiments of the present disclosure, at the beginning of computation, the data to be computed, operation instructions and mode control instructions are pre-loaded to the processing unit group 12 through the input FIFO. The configuration information is arranged as shown in Table 1, in the case of 24 processing units in the processing unit group 12, fp_ctrl[23:0] is the mode control instruction of each processing unit, when fp_ctrl is high, the corresponding processing unit is converted from integer data type computation to BF16 data type computation.

[0045] Table 1

[0046]

[0047] According to embodiments of the present disclosure, the instruction information and the weight data information can be first loaded from the FIFO to the corresponding processing unit according to the configuration information of the controller 11, i.e. pre-loading is realized, when the pre-loading process is completed, the controller 11 controls the processing unit group 12 to start computation. At this time, each processing unit in the processing unit group 12 starts computation according to the operation instruction stored in the processing unit itself. When the processing unit reads the instruction indicating the output request, the result of this computation is output to the output storage unit 14. After all processing units execute the control logic configured according to the configuration information, the coarse-grained reconfigurable array system sends a computation end signal to wait for the next round of computation.

[0048] Figure 2 The schematic diagram of the floating-point operation data BF16 format according to embodiments of the present disclosure is shown schematically.

[0049] As Figure 2As shown, the BF16 format is a floating point data representation mainly facing deep learning. The data identification of the BF16 format is shown as formula (1) below.

[0050] (1)

[0051] wherein, is a representation form of a sign bit, is a representation form of an exponent bit, and Mantissa_true is a representation form of a mantissa bit.

[0052] According to an embodiment of the present disclosure, the binary representation of Mantissa_true is . As shown in formula (2), when Value_BF16 is 4.5, the sign bit is 0, the exponent bit is 8’b10000001, i.e., 129 in decimal, and the mantissa bit is 7’b0010000. The binary {1’b1, 7’b0010000} is equal to 1.125 in decimal, so the represented numerical value is shown as formula (2). Figure 2

[0053] (2)

[0054] Figure 3 An illustrative diagram of a processing unit of a deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure is shown.

[0055] As shown in formula (3), the processing unit includes an operand selector 31, an arithmetic logic subunit 32, an instruction register subunit 33, a weight register subunit 34, a local register subunit 35, and an output register subunit 36. Figure 3 According to an embodiment of the present disclosure, the operand selector 31 can be represented by two selectors, i.e., MUX, the arithmetic logic subunit 32 can be represented by ALU, the instruction register subunit 33 can be represented by CTRL, the weight register subunit 34 can be represented by WRF, the local register subunit 35 can be represented by LRF, and the output register subunit 36 can be represented by OUT REG.

[0056] According to an embodiment of the present disclosure, the instruction register subunit 33 is configured to store operation instructions, state instructions, and mode control instructions. The weight register subunit 34 is configured to store weight data or input data. The local register subunit 35 is configured to store intermediate data generated in an operation process. The output register subunit 36 is configured to store a final operation result of the processing unit.

[0057]

[0058] ​​According to embodiments of this disclosure, each processing unit decodes and retrieves operation data according to the operation instruction within the current clock cycle. The sources of the operation data are the outputs of the processing units above, below, to the left, and to the right, the data bus, the output of the weight register, the output of the local register, etc.

[0059] According to embodiments of this disclosure, the internal design of the arithmetic logic subunit 32 in the processing unit is optimized as much as possible for the critical path, so as to achieve two BF16 multiplications or one BF16 addition in each cycle, thereby improving computational efficiency.

[0060] According to embodiments of this disclosure, the array employs distributed storage to reduce dynamic power consumption, and each processing unit has local registers to store instructions and weight data to support deep learning-oriented computations.

[0061] According to embodiments of this disclosure, in each processing unit, two different instruction formats are implemented based on the high and low levels of a mode control instruction. When the mode control instruction is high, the operation is a floating-point calculation; when the mode control instruction is low, integer operations are performed on the same instruction.

[0062] According to embodiments of this disclosure, the processing unit receives a 32-bit input from the data bus and control instructions from the controller 11, which controls whether the current data bus information is used for preloading. When not used for preloading, the data bus information serves as one of the sources of operation data selection for the arithmetic logic unit. When the controller 11 controls the processing unit to perform preloading, it first stores the corresponding operation instructions of the processing unit in the local storage of the processing unit. With an operation instruction width of 20 bits, 32 instructions can be stored.

[0063] According to embodiments of this disclosure, when the controller 11 controls the processing unit to preload weights, it stores the information of the data bus in the weight register, totaling 32 32-bit data entries. When the calculation task begins, the arithmetic logic unit (ALU) receives information from the local instruction storage, and the operand selector 31 selects the corresponding operation data according to the operation instruction. The ALU calculation result is stored in the 32-bit output register subunit 36 ​​and provided to the adjacent processing unit. The ALU selects whether to write the result to the local register subunit 35 according to the operation instruction, and writes it to the data output FIFO when there is an output requirement. The ALU receives mode control instructions to select and execute different operation instructions.

[0064] According to embodiments of this disclosure, Table 2 shows the format of the operation instructions. `mux_ctrl1` and `mux_ctrl2` respectively control the operand selection of two selectors in operand selector 31 within the processing unit. The weight register subunit 34 outputs weight data based on the address provided by `WRF_addr` as one of the operand sources for the data selector.

[0065] According to an embodiment of the present disclosure, there is no mode control instruction in the instruction format in Table 2, because the mode control instruction has been given by the initial configuration information, and adding floating point control in the operation instruction will increase the instruction storage cost. The first row represents control information, and the second row represents address information.

[0066] Table 2

[0067]

[0068] According to an embodiment of the present disclosure, the op_code is an operation sub-instruction for controlling the arithmetic logic sub-unit 32, wherein different op_codes can be selected by different mode control instructions, wherein Table 3 represents the operation sub-instruction when the mode control instruction represents integer operation, and Table 4 represents the operation sub-instruction when the mode control instruction represents floating point operation.

[0069] Table 3

[0070]

[0071] Table 4

[0072]

[0073] Figure 4 A schematic diagram of an arithmetic logic sub-unit of a deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure is schematically shown.

[0074] As shown in Figure 4 The arithmetic logic sub-unit 32 includes a multiplier group 41, a first adder circuit 42, a second adder circuit 43, a normalization circuit 44, a third adder circuit 45, a fourth adder circuit 46, a result selector 47, a logic operator group 48, a consistency operator 49, and a sign bit selector 50. The multiplier group 41 includes a first multiplier 411, a second multiplier 412, a third multiplier 413, and a fourth multiplier 414.

[0075] The first adder circuit 42, the first input end of the first adder circuit 42 is connected with the first multiplier 411, the second input end of the first adder circuit 42 is connected with the output end of the second adder circuit 43, the third input end of the first adder circuit 42 is connected with the second multiplier 412, and the output end of the first adder circuit 42 is connected with the input end of the normalization circuit 44, the first input end of the third adder circuit 45, and the input end of the result selector 47 respectively.

[0076] The normalization circuit 44, the output end of the normalization circuit 44 is connected with the second input end of the third adder circuit 45.

[0077] A second adder circuit 43, a first input of the second adder circuit 43 is connected with the third multiplier 413, a second input of the second adder circuit 43 is connected with the fourth multiplier 414, and an output of the second adder circuit 43 is connected with a second input of the first adder circuit 42, a third input of the third adder circuit 45, a first input of the fourth adder circuit 46 and an input of the result selector 47 respectively.

[0078] A third adder circuit 45, an output of the third adder circuit 45 is connected with the result selector 47.

[0079] A fourth adder circuit 46, an output of the fourth adder circuit 46 is connected with the result selector 47.

[0080] Among them, the first adder circuit 42, the second adder circuit 43, the third adder circuit 45 and the fourth adder circuit 46 respectively include at least one selector and an adder, and the input of the adder is selected by the at least one selector based on the operation sub-instruction.

[0081] According to the embodiment of the present disclosure, each processing unit contains a basic structure of four 8bit multipliers, one 8bit adder, two 16bit adders, one 17bit adder, one 35bit adder and right shift, left shift, or, and, exclusive or and other operation units. By adding reasonable data selectors (MUX) to the input of each basic structure, the multiplexing of the module can be realized, and more functions can be realized while reducing the hardware overhead.

[0082] According to the embodiment of the present disclosure, the normalization circuit 44 is used to provide the result of the floating point operation which needs to be shifted.

[0083] According to the embodiment of the present disclosure, in the traditional CGRA, four 8bit multipliers, one 8bit adder, two 16bit adders, one 17bit adder and one 35bit adder can also be included. By adding the normalization circuit 44 with small cost and adding selectors, the above operation units can be multiplexed to reduce the hardware overhead to realize floating point operation, thereby avoiding the overhead caused by adding an additional floating point processor FPU.

[0084] According to the embodiment of the present disclosure, the arithmetic logic subunit 32 further includes a consistency operation unit 49 and a logic operation unit group 48. The logic operation unit group 48 can include a plurality of logic operation units such as a comparator, a shift, an exclusive or, an inverter and the like. The input end of the consistency operation unit 49 can be connected with the output end of the logic operation unit group 48. The consistency operation unit 49 is used to compare the input data with the preset data bit by bit, and if the two data are exactly the same, 1 is output, otherwise 0 is output.

[0085] According to an embodiment of the present disclosure, the arithmetic logic subunit 32 further comprises a consistency operator 49; the first adder circuit 42 comprises a first selector 421, a second selector 422, a first adder 423, a first exclusive OR operator 424, a second exclusive OR operator 425, a first shift operator 426, a bit number expander 427, a third selector 428 and a third exclusive OR operator 429.

[0086] The first input terminal of the first selector 421 is connected with the output terminal of the first multiplier, and the output terminal of the first selector 421 is connected with the first input terminal of the first adder 423.

[0087] The first input terminal of the second selector 422 is connected with the output terminal of the first exclusive OR operator 424, the second input terminal of the second selector 422 is connected with the second multiplier, and the output terminal of the second selector 422 is connected with the second input terminal of the first adder 423.

[0088] The first input terminal of the first exclusive OR operator 424 is connected with the output terminal of the first shift operator 426, and the second input terminal of the first exclusive OR operator 424 is connected with the output terminal of the bit number expander 427.

[0089] The output terminal of the second exclusive OR operator 425 is connected with the third input terminal of the first adder 423.

[0090] The output terminal of the first adder 423 is connected with the input terminal of the normalization circuit 44 and the first input terminal of the third adder circuit 45 respectively.

[0091] The first input terminal of the first shift operator 426 is connected with the third selector 428, and the second output terminal of the first shift operator 426 is connected with the output terminal of the second adder circuit 43.

[0092] The first input terminal of the third selector 428 is connected with the output terminal of the consistency operator 49.

[0093] The input terminal of the bit number expander 427 is connected with the second input terminal of the third exclusive OR operator 429.

[0094] According to an embodiment of the present disclosure, the arithmetic logic subunit 32 further comprises a consistency operator 49; the second adder circuit 43 comprises a fourth selector 431, a second adder 432, a first NOT operator 433, a fifth selector 434, a sixth selector 435, a seventh selector 436 and an eighth selector 437.

[0095] The first input terminal of the fourth selector 431 is connected to the output terminal of the third multiplier, the second input terminal of the fourth selector 431 is connected to the output terminal of the first NOT operator 433, and the output terminal of the fourth selector 431 is connected to the first input terminal of the second adder 432.

[0096] The input terminal of the first NOT operator 433 is connected to the output terminal of the fifth selector 434.

[0097] The input terminal of the fifth selector 434 is connected to the output terminal of the consistency operator 49.

[0098] The first input terminal of the sixth selector 435 is connected to the fourth multiplier, and the output terminal of the sixth selector 435 is connected to the second input terminal of the second adder 432.

[0099] The input terminal of the seventh selector 436 is connected to the output terminal of the consistency operator 49, and the output terminal of the seventh selector 436 is connected to the input terminal of the eighth selector 437.

[0100] The output terminal of the eighth selector 437 is connected to the third input terminal of the second adder 432.

[0101] According to an embodiment of the present disclosure, the arithmetic logic subunit 32 further comprises a sign bit selector 50. The third adder circuit 45 comprises a second NOT operator 451, a ninth selector 452, an AND logic operator 453, a third adder 454, a tenth selector 455, an eleventh selector 456, a twelfth selector 457, a thirteenth selector 458, and a second shift operator 459.

[0102] The input terminals of the second NOT operator 451 are respectively connected to the output terminal of the normalization circuit 44 and the output terminal of the second XOR operator 425 in the first adder circuit 42, and the output terminal of the second NOT operator 451 is respectively connected to the first input terminal of the ninth selector 452 and the first input terminal of the AND logic operator 453;

[0103] The second input terminal of the ninth selector 452 is connected to the output terminal of the first adder circuit 42, and the output terminal of the ninth selector 452 is connected to the first input terminal of the third adder 454;

[0104] The second input terminal of the third adder 454 is connected to the output terminal of the tenth selector 455, the third input terminal of the third adder 454 is connected to the output terminal of the eleventh selector 456, and the output terminal of the third adder 454 is connected to the first input terminal of the twelfth selector 457;

[0105] The second input terminal of the logic unit 453 is connected to the output terminal of the first adder circuit 42, and the output terminal of the logic unit 453 is connected to the first input terminal of the thirteenth selector 458 and the second input terminal of the twelfth selector 457 respectively.

[0106] The second input of the thirteenth selector 458 is connected to the output of the second shift operator 459;

[0107] The first input terminal of the second shifter 459 is connected to the output terminal of the normalization circuit 44, and the second input terminal of the second shifter 459 is connected to the output terminal of the first adder circuit 42.

[0108] According to embodiments of this disclosure, the selectors in the arithmetic logic subunit 32 can all be used to determine the input sub-data at a preset data address from the first operation data and the second operation data based on the instruction signal corresponding to the selector in the operation sub-instruction, and to determine the output data from the input sub-data.

[0109] Figure 5 The illustration schematically shows a reconstruction diagram of the arithmetic logic sub-units of a coarse-grained reconfigurable array system for deep learning according to an embodiment of the present disclosure during floating-point multiplication.

[0110] like Figure 5 As shown, when floating-point operations are floating-point multiplication, the calculation processes of the following structures in the first adder circuit 42 are as follows, based on the operation sub-instructions.

[0111] The first multiplier is used to perform multiplication on the first mantissa sub-data in the first operation data and the second mantissa sub-data in the second operation data to obtain the multiplication result. The first mantissa sub-data and the second mantissa sub-data are the output data of two selectors connected to the input of the first multiplier.

[0112] The first selector 421 is used to output the first exponent bit data in the first data.

[0113] The second selector 422 is used to output the second exponent bit data in the second data.

[0114] The first adder 423 is used to add the first exponent bit data and the second exponent bit data to obtain the first exponent bit result.

[0115] The second XOR operator 425 is used to perform a bitwise XOR operation on the sign bit data of the first operation data and the sign bit data of the second operation data to obtain the output sign bit result.

[0116] According to an embodiment of the present disclosure, in the case of floating point operation being floating point multiplication, the calculation processes of the following structures in the third adder circuit 45 are as follows based on the operation sub-instruction.

[0117] The ninth selector 452 is configured to receive the first exponent bit result output by the first adder circuit 42 and output the first exponent bit result.

[0118] The tenth selector 455 is configured to output the second preset value.

[0119] The eleventh selector 456 is configured to receive the multiplication calculation result output by the first multiplier and output a sub-result in the first range of data addresses in the multiplication calculation result.

[0120] The third adder 454 is configured to perform addition calculation on the first exponent bit result, the second preset value and the sub-result to obtain an output exponent bit result.

[0121] According to an embodiment of the present disclosure, the second preset value is 8’d129, and the first range can be the 15th bit.

[0122] According to an embodiment of the present disclosure, in the case of floating point operation being floating point multiplication, the calculation processes of the following structures in the third adder circuit 45 are as follows based on the operation sub-instruction. Figure 5 The inputs of the first multiplier, the first adder 423 and the third adder 454 are all selected by their respective selectors.

[0123] According to an embodiment of the present disclosure, data1 and data2 are operation data selected by the data selectors MUX1 and MUX2 in the processing unit structure respectively, data1[15:0] and data2[15:0] represent two BF16 format data to be calculated respectively, data1[14:7] is the first exponent bit sub-data in the first operation data, data1[6:0] is the first mantissa bit sub-data, and data1

[15] is the first sign bit sub-data. The second operation data is the same. The numbers in the brackets represent the range of the data address of the data, and the data address can be the data bit number.

[0124] According to an embodiment of the present disclosure, in the case of floating point operation being floating point multiplication, the calculation processes of the following structures in the third adder circuit 45 are as follows based on the operation sub-instruction.

[0125] According to an embodiment of the present disclosure, as Figure 5As shown, data1[14:7] and data2[14:7] are added as two inputs of an 8-bit adder, which represents the addition of the exponent bits of two operation data in the BF16 format. The mantissa bits {1'b1, data1[6:0]} and {1'b1, data2[6:0]} multiplex an 8-bit multiplier, and output the 16-bit multiplication result product0.

[0126] According to the embodiment of the present disclosure, for the multiplication of the BF16 format floating point numbers, the normalization result can only be one bit more or remain unchanged. In order to obtain the exponent bits of the final multiplication result, 127 should be subtracted from the addition result of the two BF16 format data exponent bits, which is reflected on the binary 8-bit adder as inverting and adding 1, i.e. 8'd129. Therefore, in order to perform the normalization processing, another adder is multiplexed to add the addition result of the exponent bits and 8'd129, and the input carry is product0

[15] , i.e. the exponent bit sub-data in the multiplication result, which is used to determine whether the normalization result needs to carry, so as to obtain the final output exponent bit result.

[0127] According to the embodiment of the present disclosure, the result selector 47 can be multiplexed to select the sub-data with the data address in the preset address range from the multiplication result as the final output bit number result.

[0128] According to the embodiment of the present disclosure, the second exclusive OR operator 425 can be multiplexed, and the second exclusive OR operator 425 is connected with the result selector 47, so as to obtain the final output sign bit result.

[0129] According to the embodiment of the present disclosure, the result selector 47 can be used to splice and output the output exponent bit result, the output bit number result and the output sign bit result, so as to obtain the final operation result of the floating point multiplication.

[0130] According to the embodiment of the present disclosure, in some embodiments, other multipliers and adders of the integer calculation module are multiplexed to realize the multiplication calculation of two groups of BF16 format data, such as data1[15:0]*data2[15:0] and data1[31:16]*data2[31:16].

[0131] FIG. 6(a) schematically shows a first reconfiguration diagram of the arithmetic logic sub-unit of the deep learning oriented coarse-grained reconfigurable array system when performing floating point addition according to the embodiment of the present disclosure.

[0132] As shown in FIG. 6(a), the comparator, i.e., CMP, can be one device in the logic operator group 48. The absolute values of the first operation data and the second operation data are compared by the comparator to obtain a comparison result, i.e., data1_cmp_data2. The comparison result is sent to the identity operator. The identity operator 49 compares the larger operation data in the comparison result with the first operation data or the second operation data bit by bit, so as to obtain an input signal, i.e., op1_biggger in the figure, representing the comparison result between the first operation data and the second operation data.

[0133] According to an embodiment of the present disclosure, the sign bit selector 50 can output the sign bit sub-data of the maximum data between the first operation data and the second operation data as an output sign bit result based on the above input signal.

[0134] FIG. 6(b) schematically shows a second reconfiguration diagram of the arithmetic logic subunit when performing floating point addition of the deep learning oriented coarse-grained reconfigurable array system according to an embodiment of the present disclosure.

[0135] According to an embodiment of the present disclosure, in the case of floating point addition, the calculation processes of the following structures in the second adder circuit 43 are as follows based on the operation sub-instruction.

[0136] The fifth selector 434 is configured to select the exponent bit sub-data of the minimum data from the first exponent bit sub-data of the first operation data and the second mantissa bit sub-data of the second operation data based on the input signal representing the comparison result between the first operation data and the second operation data output by the identity operator 49.

[0137] The first NOT operator 433 is configured to perform NOT processing on the exponent bit sub-data of the minimum data to obtain a first NOT sub-data.

[0138] The fifth selector 434 is configured to output the first NOT sub-data to the second adder 432.

[0139] The sixth selector 435 is configured to output empty data.

[0140] The seventh selector 436 is configured to select the exponent bit sub-data of the maximum data from the first exponent bit sub-data and the second mantissa bit sub-data based on input information.

[0141] The eighth selector 437 is configured to output the exponent bit sub-data of the maximum data and a preset sub-data to the second adder 432.

[0142] The second adder 432 is configured to perform addition calculation on the exponent bit sub-data of the maximum data, the preset sub-data and the first NOT sub-data to obtain a target order difference between the first exponent bit sub-data and the second exponent bit sub-data.

[0143] According to an embodiment of the present disclosure, in the case of the floating point operation being floating point addition, the calculation processes of the following structures in the first adder circuit 42 are as follows based on the operation sub-instruction.

[0144] The third selector 428 is configured to select the mantissa bit sub-data of the maximum data from the first mantissa bit sub-data and the second mantissa bit sub-data based on the input signal output by the consistency operator 49 and representing the comparison result between the first operation data and the second operation data, wherein the maximum data is the maximum of the first operation data and the second operation data.

[0145] The first shift operator 426 is configured to move the mantissa bit sub-data of the minimum data by the target exponent difference bits to obtain the first shift sub-data, wherein the target exponent difference is used to represent the exponent difference between the first exponent bit sub-data and the second exponent bit sub-data, and the target exponent difference is the output data of the second adder circuit 43.

[0146] The third XOR operator 429 is configured to perform bitwise XOR operation on the sign bit sub-data of the first operation data and the sign bit sub-data of the second operation data to obtain the first XOR sub-data.

[0147] The bit number expander 427 is configured to expand the data bit number of the first XOR sub-data to the target bit to obtain the expanded sub-data.

[0148] The first XOR operator 424 is configured to perform bitwise XOR operation on the first shift sub-data and the expanded sub-data to obtain the target input sub-data.

[0149] The second selector 422 is configured to output the target input sub-data to the first adder 423.

[0150] The second XOR operator 425 is configured to perform bitwise XOR operation on the sign bit sub-data of the first operation data and the sign bit sub-data of the second operation data to obtain the second XOR sub-data.

[0151] The first adder 423 is configured to perform addition calculation on the second XOR sub-data, the target input sub-data and the mantissa bit sub-data of the minimum data to obtain the intermediate mantissa bit sub-data, wherein the minimum data is the minimum of the first operation data and the second operation data, and the mantissa bit sub-data of the minimum data is the output data of the third selector 428.

[0152] According to an embodiment of the present disclosure, the maximum data is the maximum of the two operation data, and the minimum data is the minimum of the two operation data.

[0153] According to an embodiment of the present disclosure, the preset sub-data can be 1’b1.

[0154] According to an embodiment of the present disclosure, based on the input signal of the comparison result between the first operation data and the second operation data, the index bit sub-data of the minimum data can be selected and inverted. And the index bit sub-data of the maximum data is selected, and the index bit sub-data of the minimum data after inversion and the index bit sub-data of the maximum data are added, so as to obtain the target order difference between the first operation data and the second operation data.

[0155] According to an embodiment of the present disclosure, the minimum data is shifted by the target order difference, so as to align the orders of the minimum data and the maximum data, for example, 8.0 and 4.0 are added, and the mantissas of both are 8' b10000000, and the mantissa of 4.0 needs to be shifted during the addition process, and the mantissa part representing 4.0 is shifted to 8' b01000000, and then added with the mantissa part representing 8.0, which is 8' b10000000.

[0156] According to an embodiment of the present disclosure, whether the mantissa part of the data with smaller absolute value is subtracted or not can be determined according to whether the sign bit sub-data of the two operation data is the same. If the sign bits are different, the mantissa part of the smaller absolute value data is subtracted from the shifted result of the larger absolute value data when calculating the mantissa of the addition result; if the sign bits are the same, the addition result after shifting can be calculated.

[0157] According to an embodiment of the present disclosure, specifically, the sign bits of the two operation numbers can be processed by the third exclusive or operator 429, that is, data1

[15] xor data2

[15] ; and the exclusive or result is extended by 8 bits, and then is exclusive or with the shifted result of the mantissa bit of the minimum data, so as to realize the inversion operation. If the sign bits of the two operation data are opposite, that is, subtraction is needed, the mantissa of the smaller operation number is exclusive or with all 1, to complete the inversion operation. If the sign bits are the same, addition is needed, and the mantissa of the smaller operation number is exclusive or with all 0, that is, remains unchanged. The output result of the first exclusive or operator 424 is added with the mantissa bit sub-data of the maximum data, and the carry input of the adder is the exclusive or result of the third exclusive or operator 429. So as to realize that if the sign bits are opposite, subtraction is performed, that is, the shifted result of the mantissa bit of the smaller operation number is inverted and added with 1, and the 1 is reflected on the carry input of the adder; if the sign bits are the same, addition is performed, that is, the carry input remains 0.

[0158] According to an embodiment of the present disclosure, the above processing process can be realized, which avoids more data selection processing according to the sign bit result, saves multiple selectors, for example, an additional selector is not needed before the adder after the mantissa shifting processing, saves the area and timing overhead, and shortens the critical path.

[0159] FIG. 6(c) schematically shows a third reconfiguration diagram of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system when performing floating point addition, according to an embodiment of the present disclosure.

[0160] According to an embodiment of the present disclosure, in the case of floating point addition, the calculation processes of the following structures in the third adder circuit 45 are as follows.

[0161] The second NOT operator 451 is configured to perform a NOT operation on the shift data output by the normalization circuit 44 to obtain second NOT sub-data, and perform a NOT operation on the second XOR sub-data output by the second XOR operator 425 to obtain third NOT sub-data, wherein the shift data represents the number of shift bits of the intermediate mantissa bit sub-data output by the first adder circuit 42.

[0162] The tenth selector 455 is configured to output the exponent bit sub-data of the maximum data.

[0163] The eleventh selector 456 is configured to output a third preset value.

[0164] The third adder 454 is configured to add the second NOT sub-data, the exponent bit sub-data of the maximum data, and the third preset value to obtain a third exponent bit result.

[0165] The AND logic operator 453 is configured to perform an AND logic operation on the intermediate mantissa bit sub-data output by the first adder circuit 42 and the third NOT sub-data to obtain processing sub-data.

[0166] The twelfth selector 457 is configured to determine an output exponent bit result from the third exponent bit result and a preset input based on the operation sub-data and the processing sub-data, wherein the preset input is a sum of the exponent bit sub-data of the maximum data and a fourth preset value.

[0167] The second shift operator 459 is configured to shift the sub-data with a second range of data addresses in the intermediate mantissa bit sub-data based on the processing sub-data to obtain second shift sub-data.

[0168] The thirteenth selector 458 is configured to select and output a mantissa bit result from the second shift sub-data and the sub-data with a third range of data addresses in the intermediate mantissa bit sub-data based on the processing sub-data.

[0169] According to an embodiment of the present disclosure, the second NOT operator 451 can be multiplexed, so as to respectively perform a NOT operation on the shift data and the second XOR sub-data.

[0170] According to an embodiment of the present disclosure, data1_cmp_data2[14:7] is the exponent bit sub-data of the maximum data, the third preset value can be binary 1, the preset input can be data1_cmp_data2[14:7]+1b1', which represents adding 1 to the exponent bit sub-data of the maximum data, and the fourth preset value can be binary 1.

[0171] According to an embodiment of the present disclosure, the normalization circuit 44 is configured to ensure that the highest bit of the final output mantissa bit sub-data is 1, i.e., to maintain the format of , so that the normalization circuit 44 determines how many bits the intermediate mantissa bit sub-data output by the first adder 423 needs to be shifted to maintain the format of . For example, if the input is 8'b01000000, the normalization circuit 44 outputs 1, so that 8'b01000000 is left shifted by 1 bit. The shift data output by the normalization circuit 44 can be represented by norm_code.

[0172] According to an embodiment of the present disclosure, when determining the output exponent bit sub-data of the floating point multiplication, if the shift data is to shift the intermediate mantissa bit sub-data psuml8 left by n bits, the exponent bit data of the maximum data should be reduced by n; and if the shift data is to perform a carry operation on the intermediate mantissa bit data, the exponent bit sub-data of the maximum data should be added by 1. Thus, the exponent bit sub-data of the above two schemes is calculated respectively, and whether there is a carry operation is determined based on the processing sub-data output by the AND logic operator 453, and the output exponent bit result is determined from the exponent bit sub-data output from the above two schemes.

[0173] According to an embodiment of the present disclosure, and by determining whether there is a carry operation, the shift result of the intermediate mantissa bit sub-data and the mantissa bit result from the sub-data with the data address in the third range in the intermediate mantissa bit sub-data are selected.

[0174] According to an embodiment of the present disclosure, the third range can be the first 7 bits of the intermediate mantissa bit sub-data.

[0175] According to an embodiment of the present disclosure, the arithmetic logic subunit 32 of the present disclosure can achieve parallel processing for different sign bit conditions, and the final output result is obtained by selection of the selector, so that the critical path delay can be reduced.

[0176] FIG. 6(d) schematically shows a fourth reconfiguration diagram of an arithmetic logic subunit of a deep learning-oriented coarse-grained reconfigurable array system when performing floating point addition according to an embodiment of the present disclosure.

[0177] As shown in FIG. 6(d), in the floating-point addition, the final output sign bit result is output by the sign bit selector 50, the output exponent bit result and the output mantissa bit result are output by the twelfth selector 457 and the thirteenth selector 458 respectively, and the above three output results are received by the result selector 47 and integrated.

[0178] According to embodiments of the present disclosure, the outputs of the adders in FIGS. 6(a)-6(c) are selected by selectors, and some selectors are not drawn for the convenience of drawing.

[0179] Figure 7 A schematic diagram of a normalization circuit of a deep learning oriented coarse-grained reconfigurable array system according to the present disclosure is schematically shown.

[0180] As shown in FIG. 6(d), in the floating-point addition, the final output sign bit result is output by the sign bit selector 50, the output exponent bit result and the output mantissa bit result are output by the twelfth selector 457 and the thirteenth selector 458 respectively, and the above three output results are received by the result selector 47 and integrated. Figure 7

[0181] The first OR logic operator 223 is configured to perform logical OR operation on the sub-data with the fourth range of data addresses in the intermediate mantissa bit sub-data to obtain a first selection signal, wherein the intermediate mantissa bit sub-data is the output data of the first adder circuit 42.

[0182] The fourteenth selector 441 is configured to determine first output data from the sub-data with the fifth range of data addresses and the sub-data with the sixth range of data addresses in the intermediate mantissa bit sub-data based on the first selection signal.

[0183] The second OR logic operator 444 is configured to perform logical OR operation on the first output data to obtain a second selection signal.

[0184] The fifteenth selector 442 is configured to determine second output data from the sub-data with the seventh range of data addresses and the sub-data with the eighth range of data addresses in the first output data based on the second selection signal.

[0185] The third OR logic operator 445 is configured to perform logical OR operation on the second output data to obtain a third selection signal.

[0186] The non-logic operator group 446 is configured to convert the first selection signal, the second selection signal and the third selection signal respectively to obtain shift data.

[0187] According to embodiments of the present disclosure, the normalization circuit 44 can process the intermediate mantissa bit sub-data into a standard BF16 format mantissa form. As shown in FIG. 6(d), the normalization circuit 44 includes a fourteenth selector 441, a fifteenth selector 442, a first OR logic operator 223, a second OR logic operator 444, a third OR logic operator 445 and a non-logic operator group 446. Figure 7 ​As shown, when normalizing the intermediate mantissa bit sub-data Data[7:0], Mux0[3:0] can be obtained from the intermediate mantissa bit sub-data Data[7:4] and Data[3:0] according to the instruction signal corresponding to the fourteenth selector 441 and the first selection signal in the operation sub-instruction, and Mux0[1:0] can be determined from Mux0[3:2] and Mux0[1:0].

[0188] According to an embodiment of the present disclosure, the non-logic operator group 446 can include a plurality of non-logic operators, and the shift data can be obtained by inputting the first selection signal, the second selection signal and the third selection signal into the corresponding non-logic operators.

[0189] According to an embodiment of the present disclosure, for example, input 8’b01000000, the shift data Result=3’b001 indicates that only 1 bit needs to be shifted to become 8’b10000000, which is the standard mantissa form, and the final output mantissa is 7’b0000000.

[0190] According to an embodiment of the present disclosure, the deep learning oriented coarse-grained reconfigurable array system of the present disclosure can implement floating point data multiplication and addition calculation and integer data multiplication and accumulation calculation, and reuse hardware resources for implementing integer calculation as much as possible to complete multiplication and addition operation of format floating point data, thereby reducing hardware overhead, and the calculation result is obtained in one period. Each processing unit can support instructions suitable for different data type calculation by using flexible data flow configuration, and the number of instructions executable by the processing unit is increased to perform multi-precision operation without increasing the instruction length and instruction logic control cost.

[0191] According to an embodiment of the present disclosure, the deep learning oriented coarse-grained reconfigurable array system of the present disclosure, in the BF16 multiplication and addition, reuses the existing integer multiplier and adds a normalization module to complete the deep learning oriented BF16 format floating point multiplication and addition under the general CGRA architecture, and the precision is consistent with the C language compiler. The implementation efficiency is greatly improved compared with the instruction reconstruction method.

[0192] According to an embodiment of the present disclosure, the deep learning oriented coarse-grained reconfigurable array system of the present disclosure, while implementing the above multi-precision operation, has only 3.9% additional hardware overhead. Without increasing the instruction width, i.e. without increasing the instruction data storage cost, the dynamic configuration of the instruction type executed by each processing unit is met.

[0193] Figure 8 An illustrative diagram of an arithmetic logic subunit of a deep learning oriented coarse-grained reconfigurable array system according to another embodiment of the present disclosure is shown.

[0194] AsFigure 8 As shown, the arithmetic logic subunit 32 includes 4 8-bit multipliers, two 16-bit adders, one 17-bit adder and one 35-bit adder, a logic operator group 48, a plurality of selectors and a plurality of logic operators. The basic logic module is the logic operator group 48 including shift, XOR, inverter and other modules.

[0195] According to an embodiment of the present disclosure, Figure 8 The circuit or device included in the arithmetic logic subunit 32 and the connection relationship between the related devices are schematically shown in the figure. The arithmetic logic subunit 32 includes a multiplier group 41, a first adder circuit 42, a second adder circuit 43, a normalization circuit 44, a third adder circuit 45, a fourth adder circuit 46, a result selector 47, a logic operator group 48, a consistency operator 49 and a sign bit selector 50.

[0196] According to an embodiment of the present disclosure, the fourth adder circuit 46 can include a sixteenth selector 461 and a fourth adder 462.

[0197] According to an embodiment of the present disclosure, Figure 8 The connection relationship between the individual devices is not marked in the figure. If the input of a certain device is the output of another device, it can be considered that there is a connection relationship between the two devices, for example: psuml8 is the output of the first adder 423 when performing floating point addition, therefore the devices with psuml8 as input are connected to the output of the first adder 423.

[0198] Figure 9 A flowchart of the coarse-grained reconfigurable array computing method for deep learning according to an embodiment of the present disclosure is schematically shown.

[0199] As Figure 9 shown, the method includes operations S910-S950.

[0200] In operation S910, the input information input to the at least one processing unit is determined by the controller 11, wherein the input information includes to-be-computed data, operation instructions and mode control instructions.

[0201] In operation S920, the to-be-computed data is input to the at least one processing unit through the input bus 15.

[0202] In operation S930, the operation instructions are input to the at least one processing unit through the configuration bus 16.

[0203] In operation S940, the to-be-computed data is subjected to floating point operation or integer operation according to the mode control instructions and the operation instructions by each processing unit, and an operation result is obtained.

[0204] In operation S950, the operation result is output through the output bus 17.

[0205] According to embodiments of the present disclosure, program code for implementing the computer programs provided by embodiments of the present disclosure can be written in any combination of one or more programming languages, and specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The programming languages include, but are not limited to, such as Java, C++, python, “C” language, or similar programming languages. The program code can be executed entirely on a user computing device, partially on a user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case involving a remote computing device, the remote computing device can be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, connected through the Internet by using an Internet service provider).

[0206] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a portion of code that contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in a different order than that noted in the accompanying drawings. For example, two blocks that are represented in succession can actually be executed in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams or flowcharts, and the combination of blocks in the block diagrams or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0207] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0208] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A coarse-grained reconfigurable array system oriented to deep learning, characterized in that, The system comprises: a controller configured to determine input information input to at least one processing unit, wherein the input information comprises to-be-calculated data, operation instructions, and mode control instructions; a set of processing units comprising a plurality of processing units, the plurality of processing units forming a reconfigurable array, and each processing unit being configured to perform floating-point operation or integer operation on the to-be-calculated data based on the mode control instructions and the operation instructions to obtain an operation result; wherein the to-be-calculated data comprises input data and weight data, and the processing unit comprises an operand selector and an arithmetic logic subunit; the operand selector is configured to receive neighbor operation results output by neighbor processing units adjacent to the processing unit, and determine first operation data and second operation data from the neighbor operation results, the weight data, and the input data based on the operation instructions; the arithmetic logic subunit is configured to determine an operation subinstruction corresponding to the mode control instruction from the operation instructions, and perform floating-point operation or integer operation on the first operation data and the second operation data based on the operation subinstruction to obtain an operation result; the arithmetic logic subunit comprises: a first adder circuit, a first input terminal of the first adder circuit being connected with a first multiplier, a second input terminal of the first adder circuit being connected with an output terminal of a second adder circuit, a third input terminal of the first adder circuit being connected with a second multiplier, and an output terminal of the first adder circuit being connected with an input terminal of a normalization circuit, a first input terminal of a third adder circuit, and an input terminal of a result selector, respectively; the normalization circuit, an output terminal of the normalization circuit being connected with a second input terminal of the third adder circuit; the second adder circuit, a first input terminal of the second adder circuit being connected with a third multiplier, a second input terminal of the second adder circuit being connected with a fourth multiplier, and an output terminal of the second adder circuit being connected with a second input terminal of the first adder circuit, a third input terminal of the third adder circuit, a first input terminal of a fourth adder circuit, and an input terminal of the result selector, respectively; the third adder circuit, an output terminal of the third adder circuit being connected with the result selector; the fourth adder circuit, an output terminal of the fourth adder circuit being connected with the result selector; wherein the first adder circuit, the second adder circuit, the third adder circuit, and the fourth adder circuit each comprise at least one selector and an adder, and an input of the adder is selected based on the operation subinstruction by the at least one selector.

2. The system of claim 1, wherein, the arithmetic logic subunit further comprises a consistency operator; the first adder circuit comprises a first selector, a second selector, a first adder, a first exclusive-OR operator, a second exclusive-OR operator, a first shift operator, a bit number expander, a third selector, and a third exclusive-OR operator; The first input end of the first selector is connected with the output end of the first multiplier, and the output end of the first selector is connected with the first input end of the first adder; The first input end of the second selector is connected with the output end of the first exclusive OR operator, the second input end of the second selector is connected with the second multiplier, and the output end of the second selector is connected with the second input end of the first adder; The first input end of the first exclusive OR operator is connected with the output end of the first shift operator, and the second input end of the first exclusive OR operator is connected with the output end of the bit number extender; The output end of the second exclusive OR operator is connected with the third input end of the first adder; The output end of the first adder is connected with the input end of the normalization circuit and the first input end of the third adder circuit respectively; The first input end of the first shift operator is connected with the third selector, and the second output end of the first shift operator is connected with the output end of the second adder circuit; The first input end of the third selector is connected with the output end of the consistency operator; The input end of the bit number extender is connected with the second input end of the third exclusive OR operator.

3. The system of claim 2, wherein, in a case where the floating point operation is floating point multiplication, the first multiplier is configured to perform multiplication operation on first mantissa bit sub-data in the first operation data and second mantissa bit sub-data in the second operation data to obtain a multiplication result, wherein the first mantissa bit sub-data and the second mantissa bit sub-data are output data of two selectors connected with input ends of the first multiplier; the first selector is configured to output first exponent bit sub-data in the first data; the second selector is configured to output second exponent bit sub-data in the second data; the first adder is configured to perform addition operation on the first exponent bit sub-data and the second exponent bit sub-data to obtain a first exponent bit result; the second exclusive OR operator is configured to perform bit-wise exclusive OR operation on sign bit sub-data of the first operation data and sign bit sub-data of the second operation data to obtain an output sign bit result; in a case where the floating point operation is floating point addition, the third selector is configured to select mantissa bit sub-data of a maximum data from the first mantissa bit sub-data and the second mantissa bit sub-data based on an input signal output by the consistency operator and representing a comparison result between the first operation data and the second operation data, wherein the maximum data is a maximum of the first operation data and the second operation data; the first shift operator is configured to move the mantissa bit sub-data of the minimum data by a target order difference to obtain a first shift sub-data, wherein the target order difference is used to represent an order difference between the first exponent bit sub-data and the second exponent bit sub-data, and the target order difference is output data of the second adder circuit. The third exclusive OR operator is configured to perform bitwise exclusive OR operation on the sign bit sub-data of the first operation data and the sign bit sub-data of the second operation data to obtain first exclusive OR sub-data; The bit number extender is configured to extend the data bit number of the first exclusive OR sub-data to a target bit number to obtain extended sub-data; The first exclusive OR operator is configured to perform bitwise exclusive OR operation on the first shift sub-data and the extended sub-data to obtain target input sub-data; The second selector is configured to output the target input sub-data to the first adder; The second exclusive OR operator is configured to perform bitwise exclusive OR operation on the sign bit sub-data of the first operation data and the sign bit sub-data of the second operation data to obtain second exclusive OR sub-data; The first adder is configured to perform addition calculation on the second exclusive OR sub-data, the target input sub-data and the mantissa bit sub-data of the minimum data to obtain intermediate mantissa bit sub-data, wherein the minimum data is the minimum one of the first operation data and the second operation data, and the mantissa bit sub-data of the minimum data is the output data of the third selector.

4. The system of claim 3, wherein, The arithmetic logic sub-unit further comprises a consistency operator; and the second adder circuit comprises a fourth selector, a second adder, a first NOT operator, a fifth selector, a sixth selector, a seventh selector and an eighth selector; The first input end of the fourth selector is connected with the output end of the third multiplier, the second input end of the fourth selector is connected with the output end of the first NOT operator, and the output end of the fourth selector is connected with the first input end of the second adder; The input end of the first NOT operator is connected with the output end of the fifth selector; The input end of the fifth selector is connected with the output end of the consistency operator; The first input end of the sixth selector is connected with the fourth multiplier, and the output end of the sixth selector is connected with the second input end of the second adder; The input end of the seventh selector is connected with the output end of the consistency operator, and the output end of the seventh selector is connected with the input end of the eighth selector; The output end of the eighth selector is connected with the third input end of the second adder.

5. The system of claim 4, wherein, in a case where the floating point operation is floating point addition, the fifth selector is configured to select, from the first exponent bit sub-data of the first operation data and the second mantissa bit sub-data of the second operation data, an exponent bit sub-data of a minimum data based on an input signal output by the consistency operator and representing a comparison result between the first operation data and the second operation data; the first NOT operator is configured to perform NOT operation on the exponent bit sub-data of the minimum data to obtain first NOT sub-data; the fourth selector is configured to output the first NOT sub-data to the second adder; the sixth selector is configured to output empty data; and the seventh selector is configured to select, from the first exponent bit sub-data and the second mantissa bit sub-data, an exponent bit sub-data of a maximum data based on the input information. The eighth selector is configured to output the index bit sub-data of the maximum data and preset sub-data to the second adder. The second adder is configured to perform addition calculation on the index bit sub-data of the maximum data, the preset sub-data and the first complement sub-data to obtain a target order difference between the first index bit sub-data and the second index bit sub-data.

6. The system of claim 1, wherein, The third adder circuit comprises a second complement operator, a ninth selector, an AND logic operator, a third adder, a tenth selector, an eleventh selector, a twelfth selector, a thirteenth selector and a second shift operator. An input end of the second complement operator is connected with an output end of the normalization circuit and an output end of the second XOR operator in the first adder circuit respectively, and an output end of the second complement operator is connected with a first input end of the ninth selector and a first input end of the AND logic operator respectively. A second input end of the ninth selector is connected with an output end of the first adder circuit, and an output end of the ninth selector is connected with a first input end of the third adder. A second input end of the third adder is connected with an output end of the tenth selector, a third input end of the third adder is connected with an output end of the eleventh selector, and an output end of the third adder is connected with a first input end of the twelfth selector. A second input end of the AND logic operator is connected with an output end of the first adder circuit, and an output end of the AND logic operator is connected with a first input end of the thirteenth selector and a second input end of the twelfth selector respectively. A second input end of the thirteenth selector is connected with an output end of the second shift operator. A first input end of the second shift operator is connected with an output end of the normalization circuit, and a second input end of the second shift operator is connected with an output end of the first adder circuit.

7. The system of claim 6, wherein, in a case where the floating point operation is floating point multiplication, the ninth selector is configured to receive the first index bit result output by the first adder circuit and configured to output the first index bit result; the tenth selector is configured to output a second preset value; the eleventh selector is configured to receive a multiplication result output by the first multiplier and configured to output a sub-result in the multiplication result with a data address in a first range; the third adder is configured to perform addition calculation on the first index bit result, the second preset value and the sub-result to obtain an output index bit result; in a case where the floating point operation is floating point addition, the second complement operator is configured to perform complement operation on shift data output by the normalization circuit to obtain second complement sub-data, and perform complement operation on second XOR sub-data output by the second XOR operator to obtain third complement sub-data, wherein the shift data represents a shift bit number of intermediate mantissa bit sub-data output by the first adder circuit; the tenth selector is configured to output index bit sub-data of maximum data; the eleventh selector is configured to output a third preset value; and the twelfth selector is configured to output the second index bit result. The third adder is configured to add the second complement data, exponent bit data of the maximum data and the third preset value to obtain a third exponent bit result; The AND logic operator is configured to perform AND logic processing on the intermediate mantissa bit data output by the first adder circuit and the third complement data to obtain processing data; The twelfth selector is configured to determine an output exponent bit result from the third exponent bit result and preset input based on operation data and the processing data, wherein the preset input is a sum of the exponent bit data of the maximum data and a fourth preset value; The second shift operator is configured to perform shift on the data with a second range in the intermediate mantissa bit data based on the processing data to obtain second shift data; The thirteenth selector is configured to select the mantissa bit result from the second shift data and the data with a third range in the intermediate mantissa bit data based on the processing data.

8. The system of claim 1, wherein, The normalization circuit comprises a fourteenth selector, a fifteenth selector, a first OR logic operator, a second OR logic operator, a third OR logic operator and a NOT logic operator group; The first OR logic operator is configured to perform OR logic processing on the data with a fourth range in the intermediate mantissa bit data to obtain a first selection signal, wherein the intermediate mantissa bit data is output data of the first adder circuit; The fourteenth selector is configured to determine first output data from the data with a fifth range and the data with a sixth range in the intermediate mantissa bit data based on the first selection signal; The second OR logic operator is configured to perform OR logic processing on the first output data to obtain a second selection signal; The fifteenth selector is configured to determine second output data from the data with a seventh range and the data with an eighth range in the first output data based on the second selection signal; The third OR logic operator is configured to perform OR logic processing on the second output data to obtain a third selection signal; The NOT logic operator group is configured to convert the first selection signal, the second selection signal and the third selection signal respectively to obtain shift data.

9. A deep learning-oriented coarse-grained reconfigurable array computing method applied to the deep learning-oriented coarse-grained reconfigurable array system of any one of claims 1-8, comprising: determining input information input to at least one processing unit through a controller, wherein the input information comprises to-be-computed data, operation instructions and mode control instructions; inputting the to-be-computed data to at least one processing unit through an input bus; inputting the operation instructions to at least one processing unit through a configuration bus; performing floating point operation or integer operation on the to-be-computed data through each processing unit based on the mode control instructions and the operation instructions to obtain an operation result; outputting the operation result through an output bus.

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