System loading method and device and electronic equipment

Abstract

The invention provides a loading method and device of a system and electronic equipment, the system comprises a programmable chip and a first memory, and the loading method of the system comprises the following steps: when the system enters an initialization state, controlling the programmable chip to enter an analog memory state; when the system completes the initialization state, sending a program loading instruction to the programmable chip; and according to the program loading instruction, controlling the programmable chip to cache the program data in the first memory, and loading the program data to the system. The first memory supported by the first processor is simulated through the programmable chip, interface configuration is completed, program data is loaded to the system, the support range of the processor guiding device is expanded, and the processor guiding device is suitable for providing a wider-range guiding FLASH memory for a specific processor and expanding the support range of the specific processor.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer data processing, and in particular relates to a system loading method, device and electronic equipment. Background Art

[0002] Some processors use the QSPI (Queued Serial Peripheral Interface, a serial peripheral interface technology) interface boot method, but since the command words or access timings of QSPI FLASH (full name Quad Serial Peripheral Interface Flash, a high-speed serial flash memory) devices from different manufacturers are different, the built-in boot program of this type of processor is usually only adapted for specific types of FLASH (full name Flash EEPROM, flash memory). Since there are currently few types of domestically produced QSPI FLASH and some of its command words are incompatible with imported products, there are very few FLASH memories to choose from when conducting domestic design, and its cost, delivery time and other aspects often bring constraints to product development.

[0003] With the increasing demand for domestic production of weapons and equipment, when using processors that adopt QSPI interface boot mode in projects, there is an urgent need for a method to expand the support range of FLASH memory to support a wider range of domestic FLASH chips.

[0004] Therefore, when the processor adopts the QSPI interface boot mode, there are very few FLASH memories to choose from. How to expand the support range of FLASH memories is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In a first aspect, the present invention provides a system loading method, the system includes a programmable chip and a first memory, the system loading method includes: when the system enters an initialization state, controlling the programmable chip to enter a simulation memory state; when the system completes the initialization state, sending a program loading instruction to the programmable chip; according to the program loading instruction, controlling the first memory to cache program data, and loading the program data into the system.

[0006] In a second aspect, the present invention provides a loading device for a system, comprising: a control module, used to control a programmable chip to enter an analog memory state when the system enters an initialization state; a processor transceiver module, used to send a program loading instruction to the programmable chip when the system completes the initialization state; and a loading module, used to control a first memory to cache program data according to the program loading instruction, and load the program data into the system.

[0007] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, the memory storing programs or instructions that can be run on the processor, and the program or instructions, when executed by the processor, implements the steps of the system loading method as in any one of the above embodiments.

[0008] The beneficial effects brought by the present invention are as follows:

[0009] It can be seen from the above scheme that an embodiment of the present invention provides a system loading method, wherein the programmable chip simulates the first memory supported by the first processor according to the initialization process of the first processor. When the system is initialized, the programmable chip first completes the interface configuration, and performs command parsing according to the processor loading instruction, caches the program data stored in the first memory into the inside thereof, and then loads the program data into the system. The support range of the processor boot device is expanded, which is suitable for providing a wider range of boot FLASH memory for a specific processor, expanding its support range, and realizing the sharing of FPGA (Field Programmable Gate Array) configuration FLASH and processor boot FLASH memory, which can effectively reduce product costs while solving the problem of difficult selection of domestic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram showing a flow chart of a method for loading a system according to an embodiment of the present invention;

[0011] Figure 2 A second flow chart showing a method for loading a system according to an embodiment of the present invention;

[0012] Figure 3 A third flowchart diagram showing a method for loading a system according to an embodiment of the present invention;

[0013] Figure 4 A fourth flowchart of a method for loading a system according to an embodiment of the present invention;

[0014] Figure 5 A schematic block diagram showing the structure of a programmable chip according to an embodiment of the present invention;

[0015] Figure 6 A schematic block diagram showing the structure of a loading device of a system according to an embodiment of the present invention;

[0016] Figure 7 A schematic block diagram showing the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] like Figure 1 As shown, the present invention provides a system loading method, the system includes a programmable chip and a first memory, and the system loading method includes:

[0019] Step 102: When the system enters the initialization state, the programmable chip is controlled to enter the analog memory state;

[0020] Step 104: When the system completes the initialization state, a program loading instruction is sent to the programmable chip;

[0021] Step 106: According to the program loading instruction, control the programmable chip to cache the program data in the first memory, and load the program data into the system.

[0022] A loading method of a system provided by the present invention, the system includes a first processor, when the system enters the initialization state, the programmable chip is controlled to enter the simulated memory state, that is, in the processor loading program initialization stage, the programmable chip simulates the first memory supported by the first processor according to its initialization process, when the system completes the initialization state, the programmable chip first completes the interface configuration, and performs command parsing according to the program loading instruction of the first processor, and controls the programmable chip to cache the program data stored in the first memory to the dual-port RAM (Random Access Memory) in the programmable chip according to the program loading instruction, and loads the program data to the system. The programmable chip simulates the first memory supported by it, and when it enters the simulated memory state, the program data stored in the first memory is cached in the programmable chip, and the program data is loaded into the system, so that the support range of the processor boot device is expanded, which is suitable for providing a wider range of boot FLASH memory for a specific processor, and expanding its support range. It also realizes that the FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chip configuration FLASH and the processor boot FLASH program are shared, while solving the problem of difficult selection of domestic devices, it can also effectively reduce product costs.

[0023] The system includes a first processor, the first processor has a QSPI boot interface, the programmable chip is an FPGA chip, and the first memory is a FLASH memory, including a FLASH program. In the above embodiment, further, when the system enters the initialization state, the programmable chip is controlled to enter the simulated memory state, including: when the system enters the initialization state, the programmable chip is controlled to enter the simulated memory state according to a preset initialization process.

[0024] In this embodiment, when the system enters the initialization state, the programmable chip enters the simulated memory state according to the preset initialization process, that is, simulates the first memory supported by the first processor to complete the interface configuration. By controlling the programmable chip to enter the simulated memory state according to the preset initialization process, the interface configuration and the parsing of the command sent by the system can be completed, and the program data can be loaded into the system, effectively expanding the support range of the processor boot FLASH memory.

[0025] The specific principle of the programmable chip entering the simulated memory state according to the preset initialization process is that according to the interface timing requirements of the first processor for the FLASH memory and the analysis of the command word, the program data in the external FLASH memory is read through data preloading, and the first processor responds according to the timing and results required by the first processor, so that the first processor believes that what is read is the FLASH memory it supports.

[0026] In the above embodiment, further, Figure 2 As shown, according to the program loading instruction, the first memory is controlled to cache the program data, and the program data is loaded into the system, including:

[0027] Step 202: In an idle cycle, control the programmable chip to cache program data in the first memory according to the read timing in the program loading instruction;

[0028] Step 204: After the idle period ends, the programmable chip is controlled to send the cached program data to the system according to the read timing.

[0029] In this embodiment, during the idle cycle, the programmable chip is controlled to cache the program data in the first memory according to the read timing in the program loading instruction, that is, the QSPI idle cycle (DUMMYCycle) is used to preload and cache the program data according to the read timing of the newly extended FLASH, so that it is cached in the programmable chip; after the idle cycle ends, while the program data is preloaded, the programmable chip is controlled to send the cached program data to the system according to the read timing until the loading is completed, thereby completing the loading of the FLASH program.

[0030] In the above embodiment, further, when the system enters the initialization state, the programmable chip is controlled to enter the emulation memory state according to a preset initialization process: the programmable chip is controlled to load to start the programmable chip.

[0031] In this embodiment, when the system is initialized, the programmable chip is controlled to load to start the programmable chip. Specifically, the programmable chip is loaded starting from address 0. This ensures that the programmable chip can be started and configured normally.

[0032] In the above embodiment, further, after controlling the programmable chip to load and start the programmable chip, it also includes: according to the system startup process, controlling the programmable chip to perform the first communication mode conversion.

[0033] In this embodiment, according to the system startup process, the programmable chip is controlled to perform the first communication mode conversion, that is, the programmable chip is initialized to the single-line SPI mode (Serial Peripheral Interface) to implement the command issued by the parsing system. This ensures the stability of communication and prepares for subsequent data loading.

[0034] Specifically, since the QSPI interface can operate in different modes such as single-line SPI and four-line QSPI, the first processor has a built-in loader that will configure the first processor's single QSPI controller to single-line SPI mode. Therefore, in the initial stage of the programmable chip, in order to be able to normally parse the commands of the first processor, the programmable chip needs to be initialized to single-line SPI mode.

[0035] In the above embodiment, further, Figure 3 As shown, according to the system startup process, after controlling the programmable chip to perform the first communication mode conversion, it also includes:

[0036] Step 302: The system sends an idle cycle instruction to the programmable chip;

[0037] Step 304: The programmable chip performs a second communication mode conversion according to the idle cycle instruction.

[0038] In this embodiment, the programmable chip receives the idle cycle instruction sent by the system and starts to perform a second communication mode conversion on the programmable chip, that is, the programmable chip is updated from the single-wire SPI mode to the four-wire QSPI mode. The four-wire QSPI mode can support more efficient data transmission and improve system performance.

[0039] It is understandable that in order for the programmable chip to normally parse the command of the first processor, the programmable chip needs to be initialized and updated to the four-wire QSPI mode. The four-wire QSPI mode can transmit data more efficiently and improve system performance.

[0040] In the above embodiment, further, after the programmable chip performs the second communication mode conversion according to the idle cycle instruction, the method further includes: initializing the first memory.

[0041] In this embodiment, the first memory is initialized according to the QSPI boot process of the first processor and the selected FLASH type. If QSPI FLASH is used, its interface width, read delay, etc. are configured.

[0042] After the first processor of the system initializes its own QSPI interface, the programmable chip changes the communication mode through programming, and then the first processor completes its configuration according to the corresponding command of the selected QSPI FLASH chip so that it can adapt to subsequent read and write operations.

[0043] In the above embodiment, further, Figure 4 As shown, after sending the program loading instruction to the programmable chip, the following steps are included:

[0044] Step 402: the programmable chip parses the program loading instruction;

[0045] Step 404: If the program loading instruction is a boot instruction, remap the system address.

[0046] In this embodiment, the programmable chip parses the program loading instruction, and if the program loading instruction is a boot instruction, the system address is remapped. The boot instruction means starting the boot phase, and the system will parse the command according to the preset command table. Each command corresponds to a specific operation or function. When parsed to 0xB, it indicates the start of the boot phase.

[0047] Specifically, the system's processor address starts at 0, and the programmable chip remaps it to the boot base address by adding a boot offset address. The programmable chip will add a boot offset address and remap the first processor address from 0 to the boot base address, so that the first processor can correctly access and configure the FLASH memory without conflicting with the configuration of the programmable chip, ensuring the stability and reliability of the system.

[0048] like Figure 5 As shown, a schematic diagram of the structure of the programmable chip 520 is shown. A specific embodiment of the system loading method provided by the present invention, the programmable chip is connected to the first processor 510 and the first memory 530 respectively, wherein the first processor has a QSPI boot interface, the programmable chip is an FPGA chip, the first memory is a FLASH memory, including a FLASH program, and the programmable chip includes a dual-port RAM, a FLASH read-write module and a QSPI command parsing module.

[0049] For the first processor with QSPI boot interface, the boot loading process can generally be divided into three stages:

[0050] Stage 1: QSPI FLASH initialization;

[0051] The first processor initializes the configuration of the first memory, such as the interface bit width, the number of idle cycles, etc.

[0052] The second stage: boot program loading stage.

[0053] Stage 3: Bootloader execution, loading and executing the application.

[0054] The following is a detailed description by taking the first processor with a QSPI boot interface and the boot FLASH memory selecting a general parallel FLASH and sharing it with the FPGA chip configuration FLASH as an example.

[0055] The startup process of the first processor is shown in Table 1.

[0056] Table 1 First processor QSPI startup process

[0057] step processor The CPU issues a command 1 Chip select low 2 SCK=25M 3 Send FLASH write enable command in single-line mode 06H 4 SCK=12.5M 5 Send "switch to four-wire mode" command in single-wire mode 61H+1FH 6 Four-wire mode is set to fast read, 10 DUMMY 81H+AFH 7 Read Data 0BH+address (starting from address 0) 8 Receive 256 bytes 9 Address + 100H, repeat steps 7 to 9 18 times

[0058] Since the boot FLASH memory and the FPGA chip configuration FLASH program are loaded from address 0 by default, in order to achieve the common use of the two, the FLASH address needs to be remapped through the FPGA chip. The QSPI command (i.e. program loading command) parsing process is as follows:

[0059] 1. Initialization phase

[0060] 1) Complete FPGA loading from address 0;

[0061] 2) According to the processor startup process, initialize to single-line SPI mode;

[0062] 3) Wait for the command to switch to four-wire QSPI mode;

[0063] 4) After receiving the set idle (DUMMY) cycle command, QSPI output is enabled.

[0064] 2. Bootstrapping

[0065] 1) Parse the QSPI command according to Table 2 and initiate the corresponding data transmission. Among them, the 0xB command corresponds to the boot phase, the processor address starts from 0, and the FPGA chip remaps it to the boot base address (such as 0x400000) by adding the boot offset address;

[0066] 2) The FLASH read / write module completes the FLASH data reading and writing into the cache dual-port RAM according to the transmission command and the general FLASH access timing;

[0067] 3) After the idle cycle ends, data is read from the cache according to the QSPI read timing to achieve data loading.

[0068] Table 2 FLASH memory transfer commands

[0069]

[0070] Table 2 shows the transfer request of the FLASH memory. The corresponding transfer request is initiated by parsing the commands in the table.

[0071] 3. Boot program execution phase

[0072] 1) The boot program uses a custom read FLASH command (0xC) to read the remaining program data. The read address is the actual address (no address remapping is required). The remaining address space after the FPGA chip configuration storage is used as the program data storage of the first processor. By address mapping, it is ensured that there is no storage space conflict between the two, thereby achieving sharing of the two.

[0073] 2) Repeat reading until loading is complete;

[0074] 3) Execute the application.

[0075] 4. Other FLASH read and write access

[0076] 1) Read operation: Initiate a read transfer through the read FLASH command; the FLASH read / write module preloads data into the cache; after the idle cycle ends, the read data is obtained from the dual-port RAM and output according to the QSPI timing;

[0077] 2) Erase operation: The erase transmission is initiated through the custom erase command (0x10), and the FLASH read / write module completes the actual erase according to the actually selected FLASH chip.

[0078] 3) Write operation: It is executed in two steps: writing buffer (0x20) and programming FLASH (0x21). First, write data to dual-port RAM for buffering, and then start programming through 0x21.

[0079] 4) Status register operation: The status register can be accessed to obtain the FLASH BUSY status (FLASH busy status) or write protection and other operations.

[0080] According to a specific embodiment of the present invention, a method for extending the support range of a processor-guided FLASH memory is proposed, and the specific steps are as follows:

[0081] 1) Load FPGA chip configuration from address 0;

[0082] 2) After loading is completed, the first processor is reset;

[0083] 3) According to the QSPI boot process of the first processor and the selected FLASH memory, the first processor initializes the FLASH memory, and if QSPI FLASH is used, configures its interface width, read delay, etc.;

[0084] The process of the first processor initializing the FLASH memory is to configure the extended FLASH. If QSPI FLASH is used, it needs to be configured according to the processor boot process, such as idle cycle, interface bit width, etc., and complete its configuration according to the corresponding commands of the selected QSPIFLASH chip so that it can adapt to subsequent read and write operations; if BPI FLASH is used, reset processing is performed to ensure that it is in read mode.

[0085] 4) canceling the first processor reset signal;

[0086] 5) parsing the boot command of the first processor until initialization is completed;

[0087] 6) Entering the boot phase, responding to the FLASH read command of the first processor;

[0088] 7) Add an offset address through the FPGA chip, remap the load address, and adjust the load address to the location of the boot data;

[0089] 8) Using the idle cycle when the QSPI boot interface is read, the program data in the FLASH memory is read and cached into the dual-port RAM;

[0090] The idle period refers to the time the first memory needs to wait before receiving the next command.

[0091] 9) After the DUMMY cycle ends, read data from the cache according to the QSPI read timing to achieve data loading;

[0092] 10) After loading is completed, use custom QSPI commands to implement operations such as reading, erasing, programming, BUSY status acquisition and write protection of program data in the FLASH memory through the FPGA chip and dual-port RAM cache.

[0093] The system loading method provided in this embodiment involves the expansion of the support range of processor boot devices, which is suitable for providing a wider range of boot FLASH memory for a specific processor to expand its support range. Through the FPGA chip preloading method, the first processor boot process simulation is realized to meet its boot timing, command and other related requirements, thereby expanding its FLASH boot device range and realizing the sharing of FPGA configuration memory and processor boot FLASH.

[0094] like Figure 6 As shown, a loading device 600 of a system provided by the present invention includes: a control module 610, which is used to control the programmable chip to enter an emulated memory state when the system enters an initialization state; a processor transceiver module 620, which is used to send a program loading instruction to the programmable chip when the system completes the initialization state; and a loading module 630, which is used to control the first memory to cache program data according to the program loading instruction and load the program data into the system.

[0095] The present invention provides a loading device for a system, the system includes a programmable chip and a first memory, the loading device of the system includes a control module, a processor transceiver module and a loading module, wherein the programmable chip simulates the first memory supported by the first processor according to the initialization process of the first processor, when the system is initialized, the programmable chip first completes the interface configuration, and performs command parsing according to the processor loading instruction, caches the program data stored in the first memory into the inside thereof, and then loads the program data into the system. The support range of the processor boot device is expanded, which is suitable for providing a wider range of boot FLASH memories for specific processors to expand their support range. It also realizes the sharing of FPGA configuration FLASH and processor boot FLASH programs, which can effectively reduce product costs while solving the problem of difficult selection of domestic devices.

[0096] like Figure 7 As shown, an electronic device 700 provided in an embodiment of the present invention includes: a processor 710 and a memory 720, the memory 720 stores programs or instructions that can be run on the processor 710, and when the programs or instructions are executed by the processor 710, the steps of the system loading method as in any one of the above embodiments are implemented.

[0097] An electronic device provided by the present invention includes: a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the system loading method in any one of the above embodiments are implemented. Therefore, the electronic device has all the beneficial effects of the system loading method in any one of the above embodiments.

[0098] In order to meet the loading and booting requirements of some processors with QSPI interfaces, the present invention extends the FLASH program through the FPGA chip, and the processor interacts with the FPGA chip, so that the FLASH program can use general FLASH, including QSPIFLASH, SPI FLASH (full name Serial Peripheral Interface Flash, a non-volatile memory based on the serial peripheral interface protocol) or parallel FLASH. When a FLASH program that supports FPGA chip configuration is selected, the FPGA chip configuration FLASH memory and the first processor boot FLASH program can also be shared.

[0099] In the initialization phase of the first processor loader, the FPGA chip simulates the FLASH program supported by the processor according to its initialization process and completes the interface configuration, such as converting SPI single-line access to QSPI four-line access; after the initialization is completed, the FPGA chip responds to the processor's FLASH read command, uses the QSPI idle cycle, and preloads and caches data according to the read timing of the newly extended FLASH program; when the idle cycle ends, while preloading the data, it outputs the cached program data according to the QSPI command read timing issued by the processor until the loading is completed, thus completing the FLASH program loading.

[0100] The FPGA chip-based boot FLASH program expansion method proposed in the present invention effectively expands the support range of the processor boot FLASH program with the QSPI interface, and realizes the sharing of the FPGA chip configuration FLASH memory and the first processor boot FLASH program. While solving the problem of difficult selection of domestically produced devices, it can also effectively reduce product costs.

[0101] The above are preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A system loading method, characterized in that: The system includes a programmable chip and a first memory, and the loading method of the system includes: When the system enters the initialization state, controlling the programmable chip to enter the analog memory state; When the system completes the initialization state, sending a program loading instruction to the programmable chip; According to the program loading instruction, the programmable chip is controlled to cache the program data in the first memory and load the program data into the system.

2. The system loading method according to claim 1, characterized in that: When the system enters the initialization state, controlling the programmable chip to enter the emulation memory state specifically includes: When the system enters the initialization state, the programmable chip is controlled to enter the emulation memory state according to a preset initialization process.

3. The system loading method according to claim 1, characterized in that: The step of controlling the programmable chip to cache the program data in the first memory and load the program data into the system according to the program loading instruction includes: In an idle cycle, controlling the programmable chip to cache program data in the first memory according to a read timing in the program loading instruction; After the idle period ends, the programmable chip is controlled to send the cached program data to the system according to the read timing.

4. The system loading method according to claim 1, characterized in that: When the system enters the initialization state, controlling the programmable chip to enter the analog memory state according to a preset initialization process includes: The programmable chip is controlled to load to start the programmable chip.

5. The system loading method according to claim 4, characterized in that: After the programmable chip is controlled to load and start the programmable chip, the method further includes: According to the startup process of the system, the programmable chip is controlled to perform the first communication mode conversion.

6. The system loading method according to claim 5, characterized in that: After controlling the programmable chip to perform the first communication mode conversion according to the startup process of the system, the method further includes: The system sends an idle cycle instruction to the programmable chip; The programmable chip performs a second communication mode conversion according to the idle cycle instruction.

7. The system loading method according to claim 6, characterized in that: After the programmable chip performs the second communication mode conversion according to the idle cycle instruction, the programmable chip further includes: The system initializes the first memory.

8. The system loading method according to claim 1, characterized in that: After sending the program loading instruction to the programmable chip, the method further comprises: The programmable chip parses the program loading instruction; If the program loading instruction is a boot instruction, the address of the system is remapped.

9. A loading device of a system, characterized in that: The system includes a programmable chip and a first memory, and the loading device includes: A control module, used for controlling the programmable chip to enter a simulation memory state when the system enters an initialization state; A processor transceiver module, used for sending a program loading instruction to the programmable chip when the system completes the initialization state; The loading module is used to control the programmable chip to cache the program data in the first memory and load the program data into the system according to the program loading instruction.

10. An electronic device, characterized in that: include: A processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the system loading method according to any one of claims 1 to 8 are implemented.

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