Memory allocation for benchmark

Abstract

The invention relates to memory allocation for benchmark testing. A memory system may be configured to allocate and deallocate portions of volatile memory for a particular use based on detecting an occurrence of a benchmark test operation. For example, the memory system may be configured to detect an occurrence of a benchmark operation based on an occurrence of one or more conditions. After detecting the benchmark test operation, the memory system may deallocate a portion of the volatile memory associated with a multi-level cell access and may allocate (e.g., reallocate) the portion for storing additional logical-to-physical mappings.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 929,369, filed by Porzio et al. on October 28, 2024, entitled “MEMORY ALLOCATION FOR A BENCHMARK TEST,” which claims priority to U.S. patent application No. 63 / 548,320, filed by Porzio et al. on November 13, 2023, entitled “MEMORY ALLOCATION FOR ABENCHMARK TEST,” each of which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates to one or more systems for memory, including memory allocation for benchmark testing. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, etc. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose a stored state when disconnected from an external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a memory system including a volatile memory and a nonvolatile memory; and a controller coupled to the memory system and configured to cause the apparatus to: determine whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory, a second portion associated with writing to single-level memory cells of the nonvolatile memory, and a third portion associated with writing to multi-level memory cells of the nonvolatile memory; and based at least in part on determining that the plurality of read commands are associated with the benchmark test operation, allocate the third portion of the volatile memory for storing the one or more mappings between logical addresses and physical addresses of the nonvolatile memory for a duration associated with performing the benchmark test operation.

[0007] A non-transitory computer-readable medium storing code including instructions is described. The non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: determine, by a memory system including a volatile memory and a non-volatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory, a second portion associated with writing to single-level memory cells of the non-volatile memory, and a third portion associated with writing to multi-level memory cells of the non-volatile memory; and based at least in part on determining that the plurality of read commands are associated with the benchmark test operation, allocate the third portion of the volatile memory for storing the one or more mappings between logical addresses and physical addresses of the non-volatile memory for a duration associated with performing the benchmark test operation.

[0008] A method is described. The method may include: determining, by a memory system including a volatile memory and a nonvolatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory, a second portion associated with writing to single-level memory cells of the nonvolatile memory, and a third portion associated with writing to multi-level memory cells of the nonvolatile memory; and allocating the third portion of the volatile memory for storing the one or more mappings between logical addresses and physical addresses of the nonvolatile memory for a duration associated with performing the benchmark test operation based at least in part on determining that the plurality of read commands are associated with the benchmark test operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting memory allocation for benchmarking according to examples as disclosed herein is presented.

[0010] Figure 2A and 2B An example of a system supporting memory allocation for benchmarking according to examples as disclosed herein is presented.

[0011] Figure 3 An example of a process flow supporting memory allocation for benchmarking according to examples as disclosed herein is presented.

[0012] Figure 4 A block diagram of a memory system supporting memory allocation for benchmarking is shown according to examples as disclosed herein.

[0013] Figure 5 A flow chart illustrating one or several methods of supporting memory allocation for benchmarking according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0014] A benchmark test may be performed on a memory system to test one or more parameters. For example, a benchmark test may test parameters such as latency, bandwidth, temperature, and power consumption while accessing one or more non-volatile memory cells of a memory system. To access the non-volatile memory cells, a memory system (e.g., a memory system controller) may utilize a table that stores mappings between logical addresses and physical addresses of the memory system. In some cases, a portion of the mapping table may be stored in a volatile memory of the memory system to reduce latency when accessing the mapping.

[0015] However, when performing a benchmark test, a relatively large amount of data stored to the non-volatile memory may be accessed, resulting in a relatively large number of mappings being transferred between the non-volatile memory and the volatile memory. Because the volatile memory may be relatively small, the portion of the mapping table stored to the volatile memory may store a relatively small subset of the mappings associated with the benchmark test. Increasing the size of the volatile memory to store the larger number of mappings associated with the benchmark test may be relatively expensive, or may occupy an undesirable large portion of the memory system. Therefore, it may be desirable to have a memory system (e.g., volatile memory) that is capable of storing a relatively large number of mappings associated with the benchmark test without adding undesirable costs or occupying an undesirable large portion of the system.

[0016] A memory system having a volatile memory is described herein that is configured to store a relatively large number of mappings associated with a benchmark test while reducing undesirable costs or without occupying an undesirable large portion of the system. In some examples, the memory system may include volatile memory and non-volatile memory. The non-volatile memory may include memory cells for storing a single bit of data (e.g., single-level cells (SLC)) and memory cells for storing two or more bits of data (e.g., multi-level cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC)). The memory system may include one or more cursors for managing access to the SLC and multi-level cells. For example, when data is read from or written to an SLC or multi-level cell, the data may be temporarily stored in a dedicated portion of the volatile memory before being read to a host system or written to the SLC or multi-level cell.

[0017] The memory system may include a component (e.g., a benchmark detector) configured to detect when a benchmark operation is performed. For example, the benchmark detector may detect that a random read benchmark is being performed based on the occurrence of one or more conditions. When a benchmark operation is detected, the memory system may deallocate a portion of the volatile memory dedicated to multi-level cell access by refreshing its contents. The memory system may then allocate the same portion of the volatile memory for storing address mappings between logical addresses and physical addresses. Thus, the volatile memory may then be able to store a relatively large number of mappings without the system incurring additional costs or occupying an undesirable large portion of the memory system. Furthermore, by increasing the size of the volatile memory used to store the address mappings, the latency and overall performance of the system may be improved during benchmark testing.

[0018] In addition to applicability in memory systems as described herein, techniques for memory allocation for benchmarking may also be implemented generally to improve the performance of various electronic devices and systems, including games. Some electronic device applications, including games and other high-performance applications, may be associated with relatively high processing requirements while also benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve the performance of electronic devices. Implementation of the techniques described herein may improve the performance of electronic devices by detecting benchmarks and reconfiguring volatile memory to support relatively high performance during benchmarks, which may result in reduced processing or latency times, improved response times, or otherwise improved user experience, among other benefits.

[0019] refer to Figures 1 to 3 , initially describe the features of the present disclosure in the context of systems, devices, and process flows. Figure 4 and 5 These and other features of the present disclosure are further illustrated and described in the context of a device diagram and flow chart involving memory allocation for benchmark testing.

[0020] Figure 1 An example of a system 100 supporting memory allocation for benchmarking according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled with a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or any other computing device including a memory and a processing device.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM) or a non-volatile DIMM (NVDIMM), among other devices.

[0022] System 100 may include a host system 105, which may be coupled to a memory system 110. In some examples, such coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to examples as described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] Memory system 110 may include a memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples as described herein. The memory system controller 115 may also be coupled and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130—as well as other such operations—which may generally be referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to perform such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, such as for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to the memory device 130, the data may be stored in the local memory 120, and the data may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in has been illustrated as including the memory system controller 115, but in some cases, the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 (which may each be internal to the memory device 130) to perform the functions attributed herein to the memory system controller 115. In general, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, the memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetically controlled RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include a local controller 135 (e.g., on the same die or within the same package) that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells. Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells if configured to store two bits of information each, three-level cells (TLC) if configured to store three bits of information each, quad-level cells (QLC) if configured to store four bits of information each, or more generally, multi-level memory cells. Relative to SLC memory cells, multi-level memory cells may provide greater storage density, but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a group of blocks 170 and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170 as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof), but may be erased at a second granularity (e.g., at a block granularity). That is, a page 175 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), while a block 170 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they are overwritten with new data. Thus, for example, in some cases, a used page 175 is not updated until the entire block 170 containing the page 175 has been erased.

[0037] In some cases, to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise designate the data remaining in the old block 170 as invalid or obsolete, and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) of the data with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed rather than erasing and rewriting the entire old block 170, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., stored within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations (e.g., as part of one or more media management algorithms) for the memory device 130, such as wear leveling, background flushing, trash collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. In order to avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "trash collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Trash collection may refer to a set of media management operations including, for example, selecting a block 170 containing valid and invalid data, selecting a page 175 in the block containing valid data, copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected page 175 as invalid, and erasing the selected block 170. Thus, the number of blocks 170 that have been erased may be increased so that more blocks 170 are available to store subsequent data (eg, data subsequently received from the host system 105).

[0039] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0040] The system 100 may include any number of non-transitory computer-readable media that support memory allocation for benchmark testing. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system 110 (e.g., by the memory system controller 115), or by the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0041] In some examples, the memory system 110 may include volatile memory and non-volatile memory. For example, the memory device 130-a may include both volatile memory and non-volatile memory. The non-volatile memory may include memory cells (e.g., SLC) for storing a single bit of data and memory cells (e.g., multi-level cells) for storing two or more bits of data. The memory system 110 may include one or more cursors for managing access to the SLC and multi-level cells. For example, when data is read from or written to an SLC or multi-level cell, the data may be temporarily stored in a dedicated portion of the volatile memory before being read to the host system 105 or written to the SLC or multi-level cell.

[0042] The memory system 110 may include a component (e.g., a benchmark detector) configured to detect when a benchmark operation is performed. For example, the benchmark detector may detect that a random read benchmark is being performed based on the occurrence of one or more conditions. When a benchmark operation is detected, the memory system 110 may deallocate a portion of the volatile memory dedicated to multi-level cell accesses by refreshing its contents. The memory system 110 may then allocate the same portion of the volatile memory for storing the L2P map. Thus, the volatile memory may then be able to store a relatively large number of maps without the memory system 110 incurring additional costs or occupying an undesirable large portion of the memory system 110. Furthermore, by increasing the size of the volatile memory used to store the address map, the latency and overall performance of the memory system 110 may be improved during benchmark testing.

[0043] Figure 2A and 2B An example of a system 200 that supports memory allocation for benchmarking according to examples as disclosed herein is shown. The system 200 may implement aspects of the system 100, as described with reference to FIG. Figure 1 For example, the system 200 may include a host system 205 and a memory system 210. The host system 205 and the memory system 210 may be as described in reference Figure 1 Examples of host system 105 and memory system 110 are described. Figure 2A An example of system 200 is illustrated prior to detecting a benchmark test at memory system 210, and Figure 2B An example of system 200 is illustrated after reconfiguring volatile memory 235 to support execution of a benchmark test.As described herein, by increasing the size of volatile memory 235 used to store address maps, latency and overall performance of memory system 210 may be improved during benchmark operations.

[0044] The system 200 may include a memory system 210 coupled to the host system 205. The memory system 210 may include a memory system controller 215, which may be a memory system controller such as the one shown in FIG. Figure 1 2. An example of a memory system controller 115 is described. The memory system controller 215 may be configured to perform operations on the memory system 210 according to commands received from the host system 205. The memory system 210 may include a benchmark detector, which may be included within the memory system controller 215 (e.g., as firmware) or may be coupled with the memory system controller 215 (e.g., as a separate hardware component, which is not shown). The benchmark detector may be configured to determine whether a benchmark test has been initiated at the memory system 210. In some cases, the host system 205 may initiate a benchmark test to test one or more performance characteristics of the memory system 210, and the benchmark detector may detect the occurrence of the test operation based on one or more characteristics of the data received from the host system 205.

[0045] In some cases, the benchmark detector may determine whether the system 200 is performing a benchmark test based on commands received from the host system 205. For example, the benchmark detector may compare the number of read commands received from the host system 205 to the number of write commands to determine whether a benchmark test is being performed. In some such instances, the benchmark detector may detect the occurrence of a benchmark test based on determining that a difference between the number of read commands and the number of write commands satisfies a threshold or that the number of read commands or the number of write commands satisfies a respective threshold. For example, if a relatively large number of read commands (e.g., relative to the number of write commands received) is received from the host system 205, a random read benchmark test operation may be detected.

[0046] In other examples, the benchmark detector may detect the occurrence of a benchmark based on identifying the absence of a write command. In some examples, the benchmark detector may detect a benchmark based on determining that the data size (e.g., data transfer size, chunk size) associated with a read command is within a threshold range (e.g., each read command is the same size). For example, if the command sizes received from the host system 205 are similar, a benchmark operation may be detected.

[0047] In some cases, the benchmark detector may detect which type of benchmark test the system 200 is performing based on the commands received from the host system 205. For example, a random read benchmark test may be associated with non-sequential read operations (e.g., read operations associated with non-sequential addresses of the memory system 210), and a sequential read benchmark test may be associated with sequential read operations (e.g., read operations associated with sequential addresses of the memory system 210). Thus, the benchmark detector may detect a random read benchmark test based on determining that the number of read commands is non-sequential. Alternatively, the benchmark detector may detect a sequential read benchmark test based on determining that the number of read commands is sequential.

[0048] In some cases, the benchmark detector may detect the occurrence of a benchmark test based on determining a power state of the memory system 210. For example, the benchmark detector may determine whether the memory system 210 is in a high power state (e.g., a normal power state, an on state) or a low power state (e.g., a sleep state, a power off state, an off state). In some cases, the benchmark detector may detect the occurrence of a benchmark test based on determining that the memory system 210 is not in a low power state (e.g., the memory system 210 is in a high power state). In some examples, the benchmark detector may detect the benchmark test based on determining that the memory system 210 has not received a command to enter a low power state.

[0049] Figure 2A The memory system 210 includes a non-volatile memory 220 (eg, NAND memory). The non-volatile memory 220 may be a memory system 210 as described in reference to FIG. Figure 1 An example of a memory device 130 is described. The non-volatile memory 220 may include a memory array 225 (e.g., a NAND array), which may include an array of non-volatile memory cells (e.g., NAND memory cells). The non-volatile memory 220 may include a mapping table 230-a, which may include address information for the memory array 225. For example, the mapping table 230-a may be an example of an L2P table that includes mappings between logical addresses (e.g., logical block addresses) and physical addresses (e.g., physical block addresses) of the memory array 225.

[0050] Figure 2A The memory system 210 includes a volatile memory 235 (eg, SRAM memory, DRAM memory). The volatile memory 235 may be as described in reference Figure 1An example of a memory device 130 is described. The volatile memory 235 may include one or more cursors 240 (e.g., a second portion), which may be SLC cursors for accessing the SLCs of the memory array 225. For example, the volatile memory 235 may include a cursor 240-a and a cursor 240-b, which may each act as a buffer for access commands associated with reading data from and writing data to the SLCs of the memory array 225. The volatile memory 235 may additionally include one or more cursors 245 (e.g., a third portion), which may be multi-level cell cursors associated with reading data from and writing data to the multi-level cells of the memory array 225. As used herein, a multi-level cell wiper can read data from or write data to a memory cell associated with storing two or more bits of information, which can include MLC, TLC, and QLC. In some examples, one or more wipers 245 can be associated with a redundant array of independent NAND (RAIN) operation.

[0051] For example, cursor 245 may be a cursor associated with reading data from or writing data to a TLC of memory array 225. In some implementations, cursor 245 may be associated with a relatively large size of volatile memory 235. Volatile memory 235 may also include mapping table 230-b (e.g., a first portion), which may include address mapping information of memory array 225. Mapping table 230-b may be a portion of mapping table 230-a, such that mapping table 230-b may be an example of an L2P table that includes mappings between logical addresses (e.g., logical block addresses) and physical addresses (e.g., physical block addresses) of memory array 225. In some implementations, mapping table 230-b may be associated with a relatively small size of volatile memory 235.

[0052] Figure 2A An example of system 200 during normal operation is illustrated (eg, no benchmark testing is performed at system 200), while Figure 2B An example of system 200 during a benchmark test operation is illustrated. For example, Figure 2B The system 200 is illustrated after the benchmark detector has detected that a benchmark test is being performed, such that Figure 2B Volatile memory 235 is illustrated being reconfigured to support execution of a benchmark test. In some cases, after a benchmark test is detected, cursor 245 (eg, or one of cursors 240) may be temporarily deallocated.

[0053] When a cursor 245 is deallocated, its contents may be stored (e.g., temporarily stored) to non-volatile memory 220, which may free up space in volatile memory 235. That is, cursor 245 may be temporarily deallocated from volatile memory 235 and allocated to non-volatile memory 220. In some such cases, deallocating cursor 245 may include disassociating a logical partition associated with cursor 245 from a portion of volatile memory 235, and reallocating cursor 245 may include allocating a logical partition in non-volatile memory 220 for cursor 245. In some implementations, reallocating cursor 245 to non-volatile memory 220 may have a negligible effect on the storage capacity of non-volatile memory 220.

[0054] In some cases, after the cursor 245 is deallocated from the volatile memory 235, the size of the mapping table 230-b stored in the volatile memory 235 may be increased to support a relatively larger amount of address information. For example, a portion of the volatile memory 235 previously associated with storing the cursor 245 may be reallocated to the mapping table 230-b. In some embodiments, the size of the mapping table 230-b may be increased by an amount corresponding to the size of the cursor 245.

[0055] In some such cases, increasing the size of mapping table 230-b may support storing a relatively larger number of mappings, thereby supporting accessing a relatively larger amount of data from memory array 225 during benchmarking operations. Reconfiguring volatile memory 235 to support accessing a relatively larger amount of data may result in relatively higher performance of memory system 210 during benchmarking. For example, volatile memory 235 may support relatively low latency for accessing data associated with mapping table 230-b (e.g., compared to accessing data using mapping table 230-a in non-volatile memory 220), and thus memory system 210 may have the ability to access a relatively larger amount of data during execution of a benchmark while maintaining the low latency associated with using volatile memory 235.

[0056] In other cases, the benchmark detector may determine that the benchmark test is a sequential benchmark test. For example, the benchmark detector may determine that the LBAs of the read command received from the host system 205 are sequential. In some examples, this determination may be made based on receiving a certain number (e.g., a threshold number) of sequential LBAs. While the sequential benchmark test is in progress, the memory system controller 215 may begin preloading mappings into the mapping table 230-b (e.g., after deallocating the cursor 245 from the volatile memory 235).

[0057] Preloading the mapping may refer to the memory system controller 215 loading the mapping associated with the subsequent sequential LBA into the mapping table 230-b before receiving the associated command from the host system 205. Thus, when the associated command is received, the mapping may have been stored to the mapping table 230-b, and the associated data may be read with relatively low latency to the host system 205. As described herein, by increasing the size of the volatile memory 235 used to store the address mapping, the latency and overall performance of the memory system 210 may be improved during benchmarking operations.

[0058] Figure 3 An example of a process flow 300 for supporting memory allocation for benchmarking according to an example as disclosed herein is shown. The process flow 300 may illustrate aspects or operations of the system 200, as respectively referred to in Figure 2A and 2B For example, process flow 300 may depict operations at host system 205 and memory system 210, memory system 210 including memory system controller 215, volatile memory 235, and non-volatile memory 220, as described in reference Figure 2A and 2B As described herein, by increasing the size of the volatile memory 235 used to store address maps, the latency and overall performance of the memory system 210 may be improved during benchmarking operations.

[0059] In the following description of process flow 300, methods, techniques, processes, and operations may be performed in a different order or at different times. In addition, some operations may be omitted from process flow 300, or other operations may be added to process flow 300. Process flow 300 illustrates operations associated with detecting a benchmark test and reconfiguring volatile memory 235 to support performing the benchmark test, as described in reference to FIG. Figure 2A and 2B described.

[0060] At 305, a number of read commands can be transmitted to the memory system controller 215. In some examples, the number of read commands can be transmitted by the host system 205.

[0061] At 310, one or more conditions associated with performing a benchmark test may be detected. In some examples, the conditions may be detected by the memory system controller 215. For example, a benchmark detector associated with the memory system controller 215 may determine that one or more conditions associated with performing a benchmark test have been met. Figure 2AAs described, the benchmark detector may detect a benchmark test based on comparing the command type (e.g., the number of read commands compared to the number of write commands) received at the memory system, the command size (e.g., the data transfer size), the power state of the memory system (e.g., sleep), or a combination thereof. For example, the benchmark detector may determine that the number of read commands received at 305 satisfies a threshold, each of the read commands is the same size, no write commands are received, the memory system 210 is not in a sleep state, or a combination thereof, to determine whether a benchmark test is being performed.

[0062] At 315, it may be determined whether the benchmark test is a random benchmark test or a sequential benchmark test. In some examples, the determination may be made by the memory system controller 215 (e.g., by a benchmark detector). For example, the benchmark detector may determine that the read command received at 305 is associated with a sequential address and the benchmark detector may determine that the benchmark test is a sequential benchmark test. In another example, the benchmark detector may determine that the read command received at 305 is associated with a non-sequential address and the benchmark detector may determine that the benchmark test is a random benchmark test. Figure 3 , the benchmark detector may have determined that the benchmark test is a random benchmark test. Additionally or alternatively, during the benchmark test operation, data associated with the received read command may be read from the non-volatile memory 220 to the host system 205 (eg, by the memory system controller 215).

[0063] At 320, the cursor 245 may be deallocated from the volatile memory 235, as shown in FIG. Figure 2A For example, the cursor 245 (eg, a logical partition associated with the cursor 245) may be removed from a portion of the volatile memory 235. The cursor 245 may be associated with a multi-level cell that writes data to the non-volatile memory 220.

[0064] At 325, the wiper 245 may be transferred to the non-volatile memory 220. That is, the data associated with the wiper 245 may be written (eg, temporarily written) to one or more multi-level cells of the non-volatile memory 220.

[0065] At 330, a portion of the mapping table may be allocated to the volatile memory 235 so that the volatile memory 235 may store the portion of the mapping table. The portion of the mapping table may be a mapping table (e.g., mapping table 230-b, as shown in FIG. 230). Figure 2A An addition to a portion of the data already stored in the volatile memory 235 (described above).

[0066] At 335, a portion of the mapping table (eg, a portion of mapping table 230-a, as shown in FIG. 230-1) may be forwarded to the corresponding mapping table. Figure 2A305 ) to volatile memory 235. In some cases, a portion of the mapping table may be associated with address information of the read command received at 305.

[0067] At 340, one or more write commands may be received at the memory system controller 215. In some examples, the write commands may be received from the host system 205 and may be received while the random read benchmark operation is ongoing. That is, the random read benchmark operation may continue despite receiving the one or more write commands.

[0068] At 345, data associated with the one or more write commands may be written to the nonvolatile memory 220 using the cursor 240. In some examples, the data may be written by the memory system controller 215. The cursor 240 may be associated with writing the data to the SLC of the nonvolatile memory 220. In some cases, the data associated with the one or more write commands may have been written to the multi-level cells of the nonvolatile memory 220 in other ways, such that the cursor 245 would be used to write the data. However, due to the deallocation of the cursor 245, the memory system controller 215 may use the cursor 240 to write the data to the SLC of the nonvolatile memory 220. In some examples, the memory system controller 215 may store an indication (e.g., with the data) to move the data to the one or more multi-level cells during a maintenance operation (e.g., during a garbage collection operation).

[0069] At 350, it may be determined that the benchmark test is complete. In some examples, the determination may be made by the memory system controller 215. For example, the benchmark detector may determine that the conditions for performing the benchmark test are no longer met, and therefore the benchmark test is complete.

[0070] At 355, one or more maintenance operations may be performed on the data stored in the non-volatile memory 220. In some examples, the one or more maintenance operations may be performed by the memory system controller 215 based on using the cursor 240 to write the data to the non-volatile memory 220. In some cases, performing the maintenance operations may include performing a garbage collection process to read the data from the SLC and write the data to the multi-level cells of the non-volatile memory 220.

[0071] At 360, portions of the mapping table may be deallocated from volatile memory 235. In some cases, a portion of the mapping table may remain stored to volatile memory 235 and other portion(s) may be transferred to a mapping table stored to non-volatile memory 220.

[0072] At 365 , the portion of the mapping table that was deallocated from the volatile memory 235 may be transferred to the non-volatile memory 220 .

[0073] At 370, the cursor 245 may be assigned (e.g., reallocated) to the volatile memory 235. Thus, subsequent access operations associated with the multi-level cell may be performed using the cursor 245. For example, after the cursor 245 is reallocated to the volatile memory, the memory system 210 may receive a write command (e.g., a second write command). In some examples, the second write command may be assigned to the cursor 245 for writing data to the multi-level cell of the non-volatile memory 220.

[0074] At 375, the portion of the mapping table may be stored to the non-volatile memory 220. In some cases, storing the portion of the mapping table may include reallocating a portion of the non-volatile memory 220 to store the portion of the mapping table. As described herein, by increasing the size of the volatile memory 235 used to store the address mapping, the latency and overall performance of the memory system 210 may be improved during benchmarking operations.

[0075] Figure 4 A block diagram 400 is shown of a memory system 420 that supports memory allocation for benchmarking according to examples as disclosed herein. The memory system 420 may be as described in reference Figures 1 to 3 4. The memory system 420 or its various components may be examples of means for performing various aspects of memory allocation for benchmarking as described herein. For example, the memory system 420 may include a determination component 425, an allocation component 430, a storage component 435, a reading component 440, a receiving component 445, an assignment component 450, a transfer component 455, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0076] The determining component 425 may be configured to or otherwise support means for determining, by a memory system including a volatile memory and a non-volatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory, a second portion associated with writing to single-level memory cells of the non-volatile memory, and a third portion associated with writing to multi-level memory cells of the non-volatile memory. The allocating component 430 may be configured to or otherwise support means for allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory for a duration associated with performing the benchmark test operation based at least in part on determining that the plurality of read commands are associated with the benchmark test operation.

[0077] In some examples, the allocation component 430 may be configured to or otherwise support means for deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory for the duration based at least in part on determining that the plurality of read commands are associated with the benchmark operation, wherein allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory is based at least in part on deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory.

[0078] In some examples, to support deallocation of the third portion of the volatile memory from being associated with the multi-level memory cells that write data to the nonvolatile memory, the storage component 435 may be configured as or otherwise support means for storing data associated with the third portion of the volatile memory to the nonvolatile memory.

[0079] In some examples, the allocating component 430 may be configured to or otherwise support means for deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory after the duration. In some examples, the allocating component 430 may be configured to or otherwise support means for allocating the third portion of the volatile memory to be associated with writing data to the multi-level memory cells of the non-volatile memory based at least in part on deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory.

[0080] In some examples, the storage component 435 can be configured to or otherwise support means for storing mappings between logical addresses associated with the plurality of read commands and corresponding physical addresses of the non-volatile memory to the third portion of the volatile memory based at least in part on allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory. In some examples, the read component 440 can be configured to or otherwise support means for reading data from the corresponding physical addresses of the non-volatile memory based at least in part on storing mappings between logical addresses associated with the plurality of read commands and corresponding physical addresses of the non-volatile memory.

[0081] In some examples, the determining component 425 can be configured to or otherwise support means for determining that the plurality of read commands are sequential read commands. In some examples, the allocating component 430 can be configured to or otherwise support means for preloading a mapping between one or more subsequent logical addresses and corresponding physical addresses of the non-volatile memory to the third portion of the volatile memory based at least in part on determining that the plurality of read commands are sequential read commands.

[0082] In some examples, receiving component 445 can be configured to or otherwise support means for receiving, by the memory system, a first write command during the duration. In some examples, assigning component 450 can be configured to or otherwise support means for assigning the first write command to the second portion of the volatile memory based at least in part on receiving the first write command during the duration, wherein first data associated with the first write command is written to one or more single-level memory cells of the non-volatile memory based at least in part on assigning the first write command to the second portion of the volatile memory.

[0083] In some examples, the transfer component 455 can be configured to or otherwise support means for transferring the first data from the one or more single level memory cells of the nonvolatile memory to one or more multi-level memory cells of the nonvolatile memory during a sustain operation occurring after the duration.

[0084] In some examples, receiving component 445 can be configured to or otherwise support means for receiving, by the memory system, a second write command after the duration. In some examples, assigning component 450 can be configured to or otherwise support means for assigning the second write command to the third portion of the volatile memory based at least in part on receiving the second write command after the duration, wherein second data associated with the second write command is written to one or more multi-level memory cells of the non-volatile memory based at least in part on assigning the second write command to the third portion of the volatile memory.

[0085] In some examples, to support determining that the plurality of read commands are associated with the benchmarking operation, the determining component 425 can be configured or otherwise support means for determining that a threshold number of read commands are received within the second duration.

[0086] In some examples, to support determining that the plurality of read commands are associated with the benchmarking operation, the determining component 425 may be configured or otherwise support means for determining that the logical block addresses associated with each of the plurality of read commands are non-contiguous.

[0087] In some examples, to support determining that the plurality of read commands are associated with the benchmarking operation, the determining component 425 can be configured or otherwise support means for determining that each of the plurality of read commands is associated with data of the same size.

[0088] In some examples, to support determining that the multiple read commands are associated with the benchmark operation, the determination component 425 may be configured to or otherwise support means for determining that the multiple read commands were received without write commands, power management commands, or both being interleaved among the multiple read commands.

[0089] In some examples, the third portion of the volatile memory is associated with writing to a redundant array of independent non-volatile memory cells.

[0090] In some examples, the size of the third portion of the volatile memory is greater than the size of the second portion of the volatile memory.

[0091] Figure 5 A flowchart illustrating a method 500 for supporting memory allocation for benchmarking according to an example as disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The memory system described herein performs. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0092] At 505, the method may include determining, by a memory system including a volatile memory and a nonvolatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory, a second portion associated with writing to single-level memory cells of the nonvolatile memory, and a third portion associated with writing to multi-level memory cells of the nonvolatile memory. The operations of 505 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 505 may be performed as described in reference to Figure 4 The described determination component 425 performs.

[0093] At 510, the method may include allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory for a duration associated with performing the benchmarking operation based at least in part on determining that the plurality of read commands are associated with the benchmarking operation. The operations of 510 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 510 may be performed as described in reference to Figure 4 The described allocation component 430 performs.

[0094] In some examples, an apparatus as described herein may perform one or several methods, such as method 500. The apparatus may include operations, features, circuit systems, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0095] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: determining, by a memory system comprising a volatile memory and a non-volatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory comprises a first portion for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory, a second portion associated with writing to single-level memory cells of the non-volatile memory, and a third portion associated with writing to multi-level memory cells of the non-volatile memory; and allocating, based at least in part on determining that the plurality of read commands are associated with the benchmark test operation, the third portion of the volatile memory for storing the one or more mappings between logical addresses and physical addresses of the non-volatile memory for a duration associated with performing the benchmark test operation.

[0096] Aspect 2: A method, apparatus, or non-transitory computer-readable medium according to aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: based at least in part on determining that the plurality of read commands are associated with the benchmark operation, de-allocating the third portion of the volatile memory for the duration so that it is not associated with writing data to the multi-level memory cells of the non-volatile memory, wherein allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory is based at least in part on de-allocating the third portion of the volatile memory so that it is not associated with writing data to the multi-level memory cells of the non-volatile memory.

[0097] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein deallocating the third portion of the volatile memory so that it is not associated with the multi-level memory cells that write data to the non-volatile memory includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: storing data associated with the third portion of the volatile memory to the non-volatile memory.

[0098] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: deallocating the third portion of the volatile memory after the duration so that it is not associated with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory; and allocating the third portion of the volatile memory so that it is associated with writing data to the multi-level memory cells of the non-volatile memory based at least in part on deallocating the third portion of the volatile memory so that it is not associated with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory.

[0099] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: storing mappings between logical addresses associated with the multiple read commands and corresponding physical addresses of the non-volatile memory to the third portion of the volatile memory based at least in part on allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory; and reading data from the corresponding physical addresses of the non-volatile memory based at least in part on storing mappings between logical addresses associated with the multiple read commands and corresponding physical addresses of the non-volatile memory.

[0100] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: determining that the multiple read commands are sequential read commands; and preloading a mapping between one or more subsequent logical addresses and corresponding physical addresses of the non-volatile memory into the third portion of the volatile memory based at least in part on determining that the multiple read commands are sequential read commands.

[0101] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a first write command by the memory system during the duration; and assigning the first write command to the second portion of the volatile memory based at least in part on receiving the first write command during the duration, wherein first data associated with the first write command is written to one or more single-level memory cells of the non-volatile memory based at least in part on assigning the first write command to the second portion of the volatile memory.

[0102] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of Aspect 7, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transferring the first data from the one or more single-level memory cells of the non-volatile memory to one or more multi-level memory cells of the non-volatile memory during a maintenance operation occurring after the duration.

[0103] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a second write command by the memory system after the duration; and assigning the second write command to the third portion of the volatile memory based at least in part on receiving the second write command after the duration, wherein second data associated with the second write command is written to one or more multi-level memory cells of the non-volatile memory based at least in part on assigning the second write command to the third portion of the volatile memory.

[0104] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein determining that the plurality of read commands are associated with the benchmark operation comprises operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that a threshold number of read commands are received within a second duration.

[0105] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 10, wherein determining that the multiple read commands are associated with the benchmark operation includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that the logical block addresses associated with each of the multiple read commands are discontinuous.

[0106] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, wherein determining that the multiple read commands are associated with the benchmark operation includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that each of the multiple read commands is associated with data of the same size.

[0107] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 12, wherein determining that the multiple read commands are associated with the benchmark operation includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that the multiple read commands are received without write commands, power management commands, or both being interleaved among the multiple read commands.

[0108] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 13, wherein the third portion of the volatile memory is associated with writing to a redundant array of independent non-volatile memory cells.

[0109] Aspect 15: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 14, wherein the size of the third portion of the volatile memory is greater than the size of the second portion of the volatile memory.

[0110] It should be noted that the described techniques include possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, portions from two or more methods may be combined.

[0111] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0112] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication (or conductive contact or connected or coupled) with each other if there is any conductive path between the components that can readily support signal flow between the components. At any given time, the conductive path between components that are in electronic communication (or conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0113] The term "coupled" (e.g., "electrically coupled") may refer to a condition that moves from an open circuit relationship between components (where signals cannot currently be communicated between components via conductive paths) to a closed circuit relationship between components (where signals can be communicated between components via conductive paths). If a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0114] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, then the components are isolated from each other. For example, if a switch positioned between the components is open, then the two components separated by the switch are isolated from each other. If a controller isolates two components, then the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0115] The terms "if", "when", "based on", or "based at least in part on" are used interchangeably. In some instances, the terms "if", "when", "based on", or "based at least in part on" may be interchangeable if they are used to describe a connection between conditional actions, conditional processes, or parts of processes.

[0116] The term "responsive to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a prior condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the prior condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0117] In addition, the term "directly in response to or in direct response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of the occurrence of a previous condition or action, so that no other intermediate conditions or actions occur between an earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between an earlier condition or action and the second condition or action. Any condition or action described herein as "based on", "at least partially based on" or "in response to" some other step, action, event or condition and performed may be performed in addition or alternatively (e.g., in an alternative instance) "directly in response to (in direct response to or directly in response to)" this other condition or action, unless otherwise specified.

[0118] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0119] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0120] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details to provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0121] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0122] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0123] For example, the various illustrative blocks and components described in connection with the present disclosure may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0124] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0125] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or may be used to carry or store desired program code components in the form of instructions or data structures and any other non-transitory media that can be accessed by a general or special computer or a general or special processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0126] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: A memory system including a volatile memory and a non-volatile memory; and a controller coupled to the memory system and configured to cause the apparatus to: determining whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory, a second portion associated with writing to single level memory cells of the nonvolatile memory, and a third portion associated with writing to multi-level memory cells of the nonvolatile memory; and Based at least in part on determining that the plurality of read commands are associated with the benchmark operation, allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory for a duration associated with performing the benchmark operation.

2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: Based at least in part on determining that the plurality of read commands are associated with the benchmark operation, deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory for the duration, wherein allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory is based at least in part on deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory.

3. The apparatus of claim 2, wherein deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory is configured to cause the apparatus to: Data associated with the third portion of the volatile memory is stored to the non-volatile memory.

4. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory after the duration; and The third portion of the volatile memory is allocated to be associated with writing data to the multi-level memory cells of the nonvolatile memory based at least in part on deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory.

5. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: storing mappings between logical addresses associated with the plurality of read commands and corresponding physical addresses of the nonvolatile memory in the third portion of the volatile memory based at least in part on allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory; and Based at least in part on storing a mapping between logical addresses associated with the plurality of read commands and corresponding physical addresses of the nonvolatile memory, data is read from the corresponding physical addresses of the nonvolatile memory.

6. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: determining that the plurality of read commands are sequential read commands; and Based at least in part on determining that the plurality of read commands are sequential read commands, a mapping between one or more subsequent logical addresses and corresponding physical addresses of the non-volatile memory is preloaded into the third portion of the volatile memory.

7. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receiving, by the memory system, a first write command during the duration; and Based at least in part on receiving the first write command during the duration, the first write command is assigned to the second portion of the volatile memory, wherein based at least in part on assigning the first write command to the second portion of the volatile memory, first data associated with the first write command is written to one or more single-level memory cells of the non-volatile memory.

8. The apparatus of claim 7, wherein the controller is further configured to cause the apparatus to: During a sustain operation occurring after the duration, the first data is transferred from the one or more single level memory cells of the nonvolatile memory to one or more multi-level memory cells of the nonvolatile memory.

9. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receiving, by the memory system, a second write command after the duration; and Based at least in part on receiving the second write command after the duration, the second write command is assigned to the third portion of the volatile memory, wherein based at least in part on assigning the second write command to the third portion of the volatile memory, second data associated with the second write command is written to one or more multi-level memory cells of the non-volatile memory.

10. The apparatus of claim 1, wherein determining that the plurality of read commands are associated with the benchmark operation is configured to cause the apparatus to: It is determined that a threshold number of read commands are received within a second duration.

11. The apparatus of claim 1 , wherein determining that the plurality of read commands are associated with the benchmark operation is configured to cause the apparatus to: A logical block address associated with each read command of the plurality of read commands is determined to be non-contiguous.

12. The apparatus of claim 1 , wherein determining that the plurality of read commands are associated with the benchmark operation is configured to cause the apparatus to: It is determined that each read command of the plurality of read commands is associated with data of a same size.

13. The apparatus of claim 1 , wherein determining that the plurality of read commands are associated with the benchmark operation is configured to cause the apparatus to: It is determined that the plurality of read commands are received without write commands, power management commands, or both being interleaved among the plurality of read commands.

14. The apparatus of claim 1, wherein the third portion of the volatile memory is associated with writing to a redundant array of independent non-volatile memory cells.

15. The apparatus of claim 1, wherein a size of the third portion of the volatile memory is greater than a size of the second portion of the volatile memory.

16. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: determining, by a memory system including a volatile memory and a nonvolatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory, a second portion associated with writing to single-level memory cells of the nonvolatile memory, and a third portion associated with writing to multi-level memory cells of the nonvolatile memory; and Based at least in part on determining that the plurality of read commands are associated with the benchmark operation, allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory for a duration associated with performing the benchmark operation.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Based at least in part on determining that the plurality of read commands are associated with the benchmark operation, deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory for the duration, wherein allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory is based at least in part on deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory.

18. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory after the duration; and The third portion of the volatile memory is allocated to be associated with writing data to the multi-level memory cells of the nonvolatile memory based at least in part on deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory.

19. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: storing mappings between logical addresses associated with the plurality of read commands and corresponding physical addresses of the nonvolatile memory in the third portion of the volatile memory based at least in part on allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory; and Based at least in part on storing a mapping between logical addresses associated with the plurality of read commands and corresponding physical addresses of the nonvolatile memory, data is read from the corresponding physical addresses of the nonvolatile memory.

20. A method comprising: determining, by a memory system including a volatile memory and a nonvolatile memory, whether a plurality of read commands are associated with a benchmark test operation for testing latency of the memory system, wherein the volatile memory includes a first portion for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory, a second portion associated with writing to single-level memory cells of the nonvolatile memory, and a third portion associated with writing to multi-level memory cells of the nonvolatile memory; and Based at least in part on determining that the plurality of read commands are associated with the benchmark operation, allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory for a duration associated with performing the benchmark operation.

21. The method according to claim 20, further comprising: Based at least in part on determining that the plurality of read commands are associated with the benchmark operation, deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory for the duration, wherein allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the non-volatile memory is based at least in part on deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cells of the non-volatile memory.

22. The method of claim 21 , wherein deallocating the third portion of the volatile memory from being associated with writing data to the multi-level memory cell of the non-volatile memory comprises: Data associated with the third portion of the volatile memory is stored to the non-volatile memory.

23. The method of claim 20, further comprising: deallocating the third portion of the volatile memory from association with storing one or more mappings between logical addresses and physical addresses of the non-volatile memory after the duration; and The third portion of the volatile memory is allocated to be associated with writing data to the multi-level memory cells of the nonvolatile memory based at least in part on deallocating the third portion of the volatile memory from being associated with storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory.

24. The method of claim 20, further comprising: storing mappings between logical addresses associated with the plurality of read commands and corresponding physical addresses of the nonvolatile memory in the third portion of the volatile memory based at least in part on allocating the third portion of the volatile memory for storing one or more mappings between logical addresses and physical addresses of the nonvolatile memory; and Based at least in part on storing a mapping between logical addresses associated with the plurality of read commands and corresponding physical addresses of the nonvolatile memory, data is read from the corresponding physical addresses of the nonvolatile memory.

25. The method of claim 20, further comprising: determining that the plurality of read commands are sequential read commands; and Based at least in part on determining that the plurality of read commands are sequential read commands, a mapping between one or more subsequent logical addresses and corresponding physical addresses of the non-volatile memory is preloaded into the third portion of the volatile memory.

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