A self-repairing method of a processor chip, a processor chip, a medium and an apparatus

Abstract

The application discloses a self-repairing method of a processor chip, a processor chip, a medium and equipment. The method comprises the following steps: determining a target redundant PE group according to the position of a faulty PE core in a faulty functional PE block of the processor chip; dividing a PE array of the processor chip into a plurality of self-repairing PE array blocks; each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group; the faulty functional PE block and the target redundant PE group belong to the same self-repairing PE array block; configuring an interconnection selection control signal; the interconnection selection control signal is used for instructing the target redundant PE group to replace a PE group in which the faulty PE core is located, so as to realize the interconnection between a self-repairing PE array block to which the faulty functional PE block belongs and an adjacent self-repairing PE array block; the redundant PE group and the PE group in which the faulty PE core is located comprise a PE row, and / or the redundant PE group and the PE group in which the faulty PE core is located comprise a PE column.

Description

Technical Field

[0001] This invention relates to the field of chip PE core repair technology, and more specifically, to a self-repair method for processor chips, a processor chip, a medium, and an apparatus. Background Technology

[0002] With the rapid development of deep learning and artificial intelligence (AI) technologies, the parameter scale of AI models is becoming increasingly large. The computing and memory bandwidth resources of traditional AI processors are no longer sufficient to meet the training and inference needs of AI models with current parameter scales. In order to solve the bottleneck problems of large model training, such as the limited computing power and memory bandwidth, various new processor architectures have been proposed by academia and industry. Among them, wafer-level processor chips, due to their unique architecture design, have computing power and memory bandwidth far exceeding those of traditional AI chips. This makes them stand out among many new processor architectures and attract widespread research in the industry.

[0003] Wafer-level processors (WPS) are an advanced concept that utilizes an entire silicon wafer as a single processor. A large number of processor cores are designed and manufactured within a single chip, uniformly arranged in an array and interconnected via a communication network (such as a 2DMesh network), thereby improving computing performance and energy efficiency. Due to process variations, environmental factors, and other factors, wafer-level processors are prone to various defects during manufacturing and packaging. These defects can lead to performance degradation or even malfunctions in some processor cores, directly reducing the yield of wafer-level processors. Chip redundancy design is a method to improve system reliability and fault tolerance. By adding extra hardware components, redundant replacement strategies can be employed to ensure the chip's continued functionality when some components fail. Therefore, researching the redundancy architecture design of wafer-level processors is of great significance for improving chip yield. Summary of the Invention

[0004] To improve chip yield, this invention provides a self-repair method for processor chips, a processor chip, a medium, and an apparatus.

[0005] According to one aspect of the present invention, a self-repair method for a processor chip is provided, comprising:

[0006] Based on the location of the faulty PE core in the faulty PE block of the processor chip, the target redundant PE group is determined. The PE array of the processor chip is divided into several self-repairing PE array blocks. Each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group. The faulty functional PE block and the target redundant PE group belong to the same self-repairing PE array block.

[0007] Configure interconnection selection control signals. Interconnection selection control signals are used to instruct the target redundant PE group to replace the PE group where the faulty PE core is located, so as to realize the interconnection between the self-healing PE array block to which the faulty functional PE block belongs and the adjacent self-healing PE array block; the redundant PE group and the PE group where the faulty PE core is located include PE rows, and / or, the redundant PE group and the PE group where the faulty PE core is located include PE columns.

[0008] Optionally, if the redundant PE group includes PE rows, and adjacent self-healing PE array blocks in the row direction are interconnected through a first multiplex interconnection structure, the interconnection selection control signal is configured, including: configuring the interconnection selection control signal of the first multiplex interconnection structure between the self-healing PE array block to which the faulty PE block belongs and the adjacent self-healing PE array blocks in the row.

[0009] Optionally, each PE core in the functional PE block is provided with a second multiplex interconnection structure on the interconnection link of the PE cores adjacent in the column direction, and the interconnection selection control signal is configured. It also includes: configuring the interconnection selection control signal of the second multiplex interconnection structure of each PE core in the PE group where the faulty PE core is located, so that the PE group where the faulty PE core is located is skipped in the column direction.

[0010] or,

[0011] The configuration of interconnection selection control signals also includes: configuring the interconnection selection control signals of the routing modules of each PE core in the PE group where the faulty PE core is located, indicating that the routing modules are in fixed routing mode so that the PE group where the faulty PE core is located is skipped in the column direction.

[0012] Optionally, if the redundant PE group includes PE columns, and adjacent PE array blocks in the column direction are interconnected through a third multiplex interconnection structure, the interconnection selection control signal is configured, including: configuring the interconnection selection control signal of the third multiplex interconnection structure between the self-healing PE array block to which the fault function PE block belongs and the repair PE array block of the adjacent column group.

[0013] Optionally, each PE core in the functional PE block is provided with a fourth multiplex interconnection structure on the interconnection link of the PE cores adjacent to the row direction, and the interconnection selection control signal is configured. It also includes: configuring the interconnection selection control signal of the fourth multiplex interconnection structure of each PE core in the PE group where the faulty PE core is located, so that the PE group where the faulty PE core is located is skipped in the row direction.

[0014] or,

[0015] The configuration of interconnection selection control signals also includes: configuring the interconnection selection control signals of the routing modules of each PE core in the PE group where the faulty PE core is located, indicating that the routing modules are in fixed routing mode so that the PE group where the faulty PE core is located is skipped in the row direction.

[0016] Optionally, based on the location of the faulty PE core in the faulty PE block of the processor chip, a target redundant PE group is determined, including:

[0017] Select the redundant PE group closest to the faulty PE core from the redundant PE group of the self-healing PE array block to which the faulty PE block belongs as the target redundant PE group.

[0018] According to another aspect of the present invention, a processor chip is provided, comprising: a PE array, the PE array being divided into a plurality of self-healing PE array blocks, each self-healing PE array block being further divided into a functional PE block and at least one redundant PE group, wherein a faulty functional PE block and a target redundant PE group belong to the same self-healing PE array block.

[0019] Optionally, a redundant PE group includes PE rows, and / or, a redundant PE group includes PE columns.

[0020] According to another aspect of the present invention, a computer-readable storage medium is provided, the storage medium storing a computer program for performing the methods described in any of the above aspects of the present invention.

[0021] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising the processor chip described above.

[0022] Therefore, this invention divides the entire PE array in a wafer-level processor chip into multiple small array blocks; each small array block has an independent redundant structure, and these redundant structures are not shared with other small array blocks. This effectively controls the scope of redundancy replacement. Furthermore, it proposes a selection logic for switching redundant structures and a redundancy switching strategy, which can effectively reduce the hardware resources of redundant design and simplify redundancy switching control and configuration. Attached Figure Description

[0023] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures:

[0024] Figure 1 This is a flowchart illustrating a self-repair method for a processor chip provided in an exemplary embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the row selection logic of the row redundancy PE group provided in an exemplary embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the selection logic provided in an exemplary embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the replacement rules for a faulty PE core provided in an exemplary embodiment of the present invention. Detailed Implementation

[0028] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is obvious that the described embodiments are merely some embodiments of the present invention, and not all embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0029] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0030] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of the present invention are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0031] It should also be understood that in the embodiments of the present invention, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0032] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more unless explicitly defined or given contrary instructions in the context.

[0033] Furthermore, the term "and / or" in this invention is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this invention generally indicates that the preceding and following related objects have an "or" relationship.

[0034] It should also be understood that the description of the various embodiments in this invention emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0035] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0036] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0037] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0038] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0039] Figure 1 This is a flowchart illustrating a self-repair method for a processor chip provided in the first aspect of an embodiment of the present invention. This embodiment can be applied to electronic devices, such as... Figure 1 As shown, the self-repair method 100 for a processor chip includes the following steps:

[0040] Step 101: Determine the target redundant PE group based on the location of the faulty PE core in the faulty function PE block of the processor chip. The PE array of the processor chip is divided into several self-healing PE array blocks. Each self-healing PE array block is further divided into a functional PE block and at least one redundant PE group. The faulty function PE block and the target redundant PE group belong to the same self-healing PE array block.

[0041] Step 102: Configure the interconnection selection control signal. The interconnection selection control signal is used to instruct the target redundant PE group to replace the PE group where the faulty PE core is located, so as to realize the interconnection between the self-healing PE array block to which the faulty functional PE block belongs and the adjacent self-healing PE array block.

[0042] The redundant PE group and the PE group containing the faulty PE core include PE rows, and / or the redundant PE group and the PE group containing the faulty PE core include PE columns. That is, a PE group is one or more rows of PEs, or a PE group is one or more columns of PEs.

[0043] Specifically, this invention proposes an architecture design for row or column redundancy replacement, which minimizes the resource consumption caused by redundancy design while also simplifying the control logic for redundancy switching.

[0044] Specifically, the entire PE array in the processor chip is divided into multiple self-healing PE array blocks. Each self-healing PE array block has an independent redundant structure, and these redundant structures are not shared with other self-healing PE array blocks, effectively controlling the impact range of redundancy replacement. A selection logic for switching redundant structures and a redundancy switching strategy are designed, which can effectively reduce the hardware resources of redundant design and simplify redundancy switching control and configuration.

[0045] In one embodiment of the present invention, taking a wafer-level processor chip as an example, the specific implementation of the processor chip's self-healing is as follows: (Refer to...) Figure 2As shown, the entire wafer processor is first divided into multiple self-healing PE array blocks (RA). Each self-healing PE array block contains functional PE blocks and multiple redundant PE groups. Functional PE blocks are used for chip functionality when there are no faults, while redundant PE groups are used as replacement PE blocks when a faulty PE core exists in a functional PE block. There are three types of self-healing PE array blocks: only row redundant PE groups, only column redundant PE groups, and both row and column redundant PE groups exist simultaneously. When a self-healing PE array block contains only row redundant PE groups, adjacent left and right self-healing arrays need to be interconnected through multiplexing logic (first multiplexing interconnection structure), while adjacent top and bottom self-healing arrays can be directly interconnected through PE. Accordingly, the interconnection selection control signal configuration includes: an interconnection selection control signal configuring the first multiplexing interconnection structure between the self-healing PE array block of the faulty functional PE block and the row-adjacent self-healing PE array blocks. When a self-healing PE array block contains only column-redundant PE groups, adjacent self-healing arrays need to be interconnected via multi-selection logic (third multi-selection interconnection structure), while adjacent self-healing arrays can be directly interconnected via PEs. Accordingly, the interconnection selection control signals include: configuring the interconnection selection control signals for the third multi-selection interconnection structure between the self-healing PE array block to which the fault-function PE block belongs and the column-adjacent repair PE array block. When both row and column-redundant PE groups exist in a self-healing PE array block, adjacent self-healing arrays need to be interconnected via multi-selection logic, and adjacent self-healing arrays also need to be interconnected via multi-selection logic. Generally, in row-redundant PE groups, the number of rows in a redundant PE group can be one or more; in column-redundant PE groups, the number of columns in a redundant PE group can be one or more. However, the number of rows / columns only affects the complexity of the internal connections of the multi-selection logic and has no impact on the redundancy architecture scheme.

[0046] Since the row-redundant PE group design architecture and the column-redundant PE group design architecture are symmetrically similar, this invention takes the row-redundant PE group design as an example, and the row-redundant PE group has 1 row, such as... Figure 2As shown: The self-healing PE array block contains two sets of row redundant PE groups and one set of functional array blocks. The two sets of row redundant PE groups are located above and below the functional array blocks, respectively. Vertically adjacent self-healing PE array blocks are directly connected through their adjacent PE cores. Horizontally adjacent self-healing PE array blocks need to be interconnected using row multiplexing logic (i.e., the first multiplexing interconnection structure mentioned above). The row multiplexing logic adopts a CrossBar-like structure. The input ports in the row multiplexing logic can be connected to three output ports, namely the output ports directly opposite the input port on the left and right, and the two output ports adjacent to the input port vertically (for input ports at the upper and lower boundaries, they can only be connected to two of the output ports). The configuration register is used to store the selection control signals of the row multiplexing logic (i.e., the interconnection selection control signals of the first multiplexing interconnection structure), thereby controlling the connection relationship between the input ports and output ports of the multiplexing logic.

[0047] In one embodiment of the present invention, the multiplexing logic can realize the row (or column) replacement function of the faulty PE core row (or column) of the functional array, thereby ensuring the normal routing in the left and right directions of the functional array. However, since the row where the faulty PE is located needs to be bypassed, the routing in the up and down directions also needs to realize the function of cross-row connection. Figure 3 Two implementation schemes are given. Taking the row redundancy PE group as an example, there are two schemes: PE core bypass scheme A and PE core bypass scheme B.

[0048] 1) PE Core Bypass Solution A: Add PE multiplexing logic (second multiplexing interconnection structure) to the interconnection links between the PE core and its adjacent PE cores to implement the bypass function of the PE core. The control signal of the PE multiplexing logic (i.e., the interconnection selection control signal of the second multiplexing interconnection structure) is controlled by the configuration signal. Solution A requires additional logic and routing resources, but it can handle situations where the router itself is faulty.

[0049] 2) PE Core Bypass Solution B: Since the PE core itself contains a Router module, all Routers in the row containing the faulty PE can be configured to fixed routing mode, thus enabling the PE core to bypass. Solution B leverages the Router's built-in functionality, requiring no additional logical or routing resources, but it cannot handle situations where the Router itself is faulty. Accordingly, configuring the interconnection selection control signals includes: configuring the interconnection selection control signals of the routing modules of each PE core in the PE group containing the faulty PE core, indicating that the routing modules are in fixed routing mode, so that the PE group containing the faulty PE core is skipped in the column direction.

[0050] Furthermore, the selection logic for column redundancy PE groups is similar to that for row redundancy PE groups, and will not be elaborated here.

[0051] In one embodiment of the present invention, the row or column replacement rules are as follows:

[0052] For example, if row-redundant PE groups are distributed on the top and bottom sides, when a PE core in a row of the functional array block fails, the redundancy replacement direction is selected based on the distance between the failed row and the two redundant PE groups, following the principle of proximity. The replacement rules for column-redundant PE groups are the same as those for row-redundant PE groups.

[0053] by Figure 4 For example, in self-healing PE array block 0 (SR-A0), a faulty PE core exists in row 0 (F-R0) of the functional array block. Since this faulty row is closer to the upstream redundant PE group (R-U0), the row above the faulty PE is selected to replace the faulty row. At this time, row F-R0 of self-healing PE array block 1 (SR-A1) is connected to R-U0 via row selection logic. Similarly, in self-healing PE array block 1 (SR-A1), a faulty PE core exists in row x (F-Rx) of the functional array block. Since this faulty row is closer to the downstream redundant PE group (R-D0), the row below the faulty PE is selected to replace the faulty row. At this time, row F-Rx of self-healing PE array block 0 (SR-A0) is connected to R-D0 via row selection logic. In self-healing PE array block 2 (SR-A2), there are faulty PE cores in both row 0 (F-R0) and row 1 (F-R1) of the functional array block, requiring the simultaneous use of the up-row redundant PE group (R-U0) and the down-row redundant PE group (R-D0). At this time, row F-R0 of self-healing PE array block 3 (SR-A3) is connected to R-U0 through row multiplexing logic. At this time, (F-R1~F-Rx) of self-healing PE array block 3 (SR-A3) needs to be connected to (F-R2~F-Rx, R-D0) through row multiplexing logic.

[0054] Furthermore, since the faulty PE core needs to be replaced entirely in its row, the faulty PE row has bypass capability in the vertical direction, which means that the adjacent rows above and below the faulty row can be directly interconnected. This invention provides two solutions, PE core bypass scheme A and PE core bypass scheme B, which can be selected according to actual needs.

[0055] The technical solution provided by this invention can be applied to processor chips, effectively improving the yield of such processor chips. Main application scenarios include wafer-level processor chips, wafer-level processor boards, and wafer-level processor servers and clusters; large-array many-core processor chips, large-array many-core processor boards, and large-array many-core processor servers and clusters.

[0056] Therefore, this invention divides the entire PE array in the processor chip into multiple small array blocks; each small array block has an independent redundant structure, and these redundant structures are not shared with other small array blocks. This effectively controls the scope of redundancy replacement. Furthermore, it proposes a selection logic for switching redundant structures and a redundancy switching strategy, which can effectively reduce the hardware resources of redundant design and simplify redundancy switching control and configuration.

[0057] Furthermore, a second aspect of the present invention provides a processor chip, comprising: a PE array, wherein the PE array is divided into a plurality of self-healing PE array blocks, and each self-healing PE array block is further divided into a functional PE block and at least one redundant PE group.

[0058] Among them, the target redundant PE group is used to replace the PE group where the faulty PE core of the functional PE block in the self-healing PE array block is located.

[0059] The target redundant PE group is determined based on the location of the faulty PE core.

[0060] The self-healing PE array block of the fault function PE block realizes the replacement of the PE group where the faulty PE core is located by the target redundant PE group according to the configured interconnection selection control signal, thereby realizing interconnection with the adjacent self-healing PE array block.

[0061] Wherein, the redundant PE group and the PE group containing the faulty PE core include PE rows (i.e., row redundancy), and / or, the redundant PE group and the PE group containing the faulty PE core include PE columns (i.e., column redundancy).

[0062] If the redundant PE group includes PE rows, and adjacent self-healing PE array blocks in the row direction are interconnected through a first multiplex interconnection structure, the interconnection selection control signal includes the interconnection selection control signal of the first multiplex interconnection structure.

[0063] Furthermore, in one implementation, each PE core in the functional PE block has a second multiplexed interconnection structure on the interconnection link with the PE cores adjacent in the column direction, and the interconnection selection control signal also includes the interconnection selection control signal for the second multiplexed interconnection structure. In another implementation, the interconnection selection control signal also includes the interconnection selection control signal for the routing module of the PE core. By configuring the interconnection selection control signals of the routing modules of each PE core in the PE group containing the faulty PE core, the routing module is instructed to be in a fixed routing mode, so that the PE group containing the faulty PE core is skipped in the column direction.

[0064] If the redundant PE group includes PE columns, and adjacent PE array blocks in the column direction are interconnected through a third multiplex interconnection structure, the interconnection selection control signal includes the interconnection selection control signal of the third multiplex interconnection structure.

[0065] Furthermore, in one implementation, each PE core in the functional PE block has a fourth multiplexed interconnection structure on the interconnection link with the PE cores adjacent in the row direction, and the interconnection selection control signal further includes the interconnection selection control signal of the fourth multiplexed interconnection structure. In another implementation, the interconnection selection control signal further includes the interconnection selection control signal of the routing module of the PE core. By configuring the interconnection selection control signals of the routing modules of each PE core in the PE group containing the faulty PE core, the routing module is instructed to be in a fixed routing mode, so that the PE group containing the faulty PE core is skipped in the row direction.

[0066] Furthermore, a third aspect of the present invention provides a computer-readable storage medium storing a computer program for performing the methods described in any of the above aspects of the present invention.

[0067] Furthermore, a fourth aspect of the present invention provides an electronic device, which includes the processor chip described above.

[0068] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the invention to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method of self-repairing a processor chip, the method comprising: The method comprises the following steps: According to the location of the faulty PE core in the faulty functional PE block of the processor chip, a target redundant PE group is determined, the PE array of the processor chip is divided into a plurality of self-repairing PE array blocks, each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group, the faulty functional PE block and the target redundant PE group belong to the same self-repairing PE array block, the functional PE block is divided into a plurality of PE groups, and each PE group comprises a plurality of PE cores; An interconnection selection control signal is configured, which is used to instruct the target redundant PE group to replace the PE group in which the faulty PE core is located, so as to realize the interconnection between the self-repairing PE array block to which the faulty functional PE block belongs and the adjacent self-repairing PE array block; the redundant PE group and the PE group in which the faulty PE core is located comprise a PE row, and / or the redundant PE group and the PE group in which the faulty PE core is located comprise a PE column; wherein, The method comprises the following steps: A redundant PE group closest to the faulty PE core is selected from the redundant PE groups of the self-repairing PE array block to which the faulty functional PE block belongs as the target redundant PE group; If the redundant PE group comprises a PE row, the self-repairing PE array blocks adjacent in the row direction are interconnected through a first multiplexing interconnection structure, and the configuration of the interconnection selection control signal comprises the following steps: configuring the interconnection selection control signal of the first multiplexing interconnection structure between the self-repairing PE array block to which the faulty functional PE block belongs and the self-repairing PE array block adjacent in the row direction; If the redundant PE group comprises a PE column, the self-repairing PE array blocks adjacent in the column direction are interconnected through a third multiplexing interconnection structure, and the configuration of the interconnection selection control signal comprises the following steps: configuring the interconnection selection control signal of the third multiplexing interconnection structure between the self-repairing PE array block to which the faulty functional PE block belongs and the self-repairing PE array block adjacent in the column direction.

2. The method of claim 1, wherein, Each PE core in the functional PE block is provided with a second multiplexing interconnection structure on the interconnection link with the PE core adjacent in the column direction, and the configuration of the interconnection selection control signal further comprises the following steps: configuring the interconnection selection control signal of the second multiplexing interconnection structure of each PE core in the PE group in which the faulty PE core is located, so that the PE group in which the faulty PE core is located is skipped in the column direction; Or, The configuration of the interconnection selection control signal further comprises the following steps: configuring the interconnection selection control signal of the routing module of each PE core in the PE group in which the faulty PE core is located, and instructing the routing module to be in a fixed routing mode, so that the PE group in which the faulty PE core is located is skipped in the column direction.

3. The method of claim 1, wherein, Each PE core in the functional PE block is provided with a fourth multiplexing interconnection structure on the interconnection link with the PE core adjacent in the row direction, and the configuration of the interconnection selection control signal further comprises the following steps: configuring the interconnection selection control signal of the fourth multiplexing interconnection structure of each PE core in the PE group in which the faulty PE core is located, so that the PE group in which the faulty PE core is located is skipped in the row direction; Or, The configuration interconnection selection control signal further comprises: configuration of interconnection selection control signals of routing modules of each PE core in the PE group where the faulty PE core is located, instructing the routing modules to be in a fixed routing mode, so that the PE group where the faulty PE core is located is skipped in a row direction.

4. A processor chip which is self-repairable by the method of any one of claims 1 to 3, characterized in that Comprise: The PE array is divided into a plurality of self-repairing PE array blocks, and each self-repairing PE array block is further divided into a functional PE block and at least one redundant PE group.

5. The processor chip of claim 4, wherein, The redundant PE group comprises a PE row, and / or the redundant PE group comprises a PE column.

6. A computer-readable storage medium, characterized in that, The storage medium stores a computer program for executing the method of any one of claims 1-3.

7. An electronic device, comprising: The electronic device comprises the processor chip of claim 4.

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