Data transmission method and device based on enhanced serial peripheral interface, equipment and medium

Abstract

The application discloses a data transmission method and device based on an enhanced serial peripheral interface, equipment and a medium, relates to the technical field of data transmission, and is applied to a target function component. The target function component is a function component determined from a first function component, a second function component, a third function component and a fourth function component according to the type of to-be-transmitted data and used for executing a data transmission task. First data carried by a write request sent by a preset host is written into a local first preset cache, a first interrupt signal is generated to a target processor, so that the target processor writes data in the first preset cache into a baseboard management controller. Second data sent by the baseboard management controller is received by using a local second preset cache, and a target message is sent to the preset host, so that, in response to a read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host. The transmission of special information between the host and the baseboard management controller is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method and device based on an enhanced serial peripheral interface, an apparatus and a medium. BACKGROUND

[0002] Currently, an eSPI (Enhanced Serial Peripheral Interface) bus is mainly used as a dedicated interface between low-speed peripherals and a host. The eSPI bus borrows and reuses the electrical clock specification of an SPI (Serial Peripheral Interface) bus, but uses a brand-new definition at the protocol layer. In addition to the functions and roles of an LPC (Low Pin Count) bus, the eSPI bus also converts the OOB (out of band) SMBUS (System Management Bus) and SideBand GPIO (General - Purpose Input / Output) into in-band information that can be transmitted on the eSPI bus. In addition, the eSPI bus can also share a cache with a chipset in real time.

[0003] However, the related art only implements the functions of the eSPI protocol, and does not extend the transmission of some special information between the host and the baseboard management controller.

[0004] To sum up, how to extend the functions of the eSPI protocol to realize the transmission of some special information between the host and the baseboard management controller is a problem to be solved at present. SUMMARY

[0005] Therefore, the present application aims to provide a data transmission method and device based on an enhanced serial peripheral interface, an apparatus and a medium, which can extend the functions of the eSPI protocol to realize the transmission of some special information between the host and the baseboard management controller. The specific solutions are as follows:

[0006] In a first aspect, the present application discloses a data transmission method based on an enhanced serial peripheral interface, applied to a target functional component, the target functional component being a functional component determined from a first functional component, a second functional component, a third functional component and a fourth functional component according to the type of data to be transmitted for executing a data transmission task, and the method comprises:

[0007] When the write request sent by the preset host is acquired, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller;

[0008] The second data sent by the baseboard management controller is received by using the second preset cache locally, and a target message is sent to the preset host, so that the second data in the second preset cache is sent to the preset host in response to the read request sent by the preset host based on the target message.

[0009] Optionally, the functional component used for executing the data transmission task is determined from the first functional component, the second functional component, the third functional component and the fourth functional component according to the type of the to-be-transmitted data, and the method comprises the following steps.

[0010] If the to-be-transmitted data is a command and data corresponding to system management software, the first functional component is determined as the functional component used for executing the data transmission task.

[0011] If the total amount of the to-be-transmitted data is greater than a preset threshold, the second functional component is determined as the functional component used for executing the data transmission task.

[0012] If the to-be-transmitted data is preset information data, the third functional component is determined as the functional component used for executing the data transmission task.

[0013] If the to-be-transmitted data is interactive data corresponding to the preset host and external equipment, the fourth functional component is determined as the functional component used for executing the data transmission task.

[0014] Optionally, if the target functional component is the first functional component, the first preset cache is a first register, and the second preset cache is a second register.

[0015] Correspondingly, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, and the method comprises the following steps.

[0016] The first data carried by the write request is written into the first register.

[0017] The level state of the first flag signal corresponding to the first register is set to a high level, so as to generate a first interrupt signal to the target processor, so that the target processor writes the first data stored in the first register to the baseboard management controller.

[0018] Correspondingly, the second data sent by the baseboard management controller is received by the local second preset cache, and a target message is sent to the preset host, so that the second data in the second preset cache is sent to the preset host in response to a read request sent by the preset host based on the target message, comprising:

[0019] The second data sent by the baseboard management controller is received by the second register, and the level state of the second flag signal corresponding to the second register is set to high level, so that the second data in the second register is sent to the preset host in response to a read request sent by the preset host based on the high level signal.

[0020] Optionally, if the target function component is a second function component, the first preset cache is a first random memory, and the second preset cache is a second random memory;

[0021] Correspondingly, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, comprising:

[0022] The first data carried by the write request is written into a first position in the first random memory according to the current first write pointer, and a one operation is performed on the current first write pointer to update the current first write pointer;

[0023] After the first data is written, a first interrupt signal is generated to the target processor, so that the target processor generates a read enable signal and writes the data in the first random memory to the baseboard management controller;

[0024] Correspondingly, the second data sent by the baseboard management controller is received by the local second preset cache, and a target message is sent to the preset host, so that the second data in the second preset cache is sent to the preset host in response to a read request sent by the preset host based on the target message, comprising:

[0025] The second data sent by the baseboard management controller is received by the second random memory according to the current second write pointer;

[0026] After the second data is received, a target message is sent to the preset host, so that the preset host generates a read enable signal and reads the second data from the second random memory.

[0027] Optionally, if the target function component is a third function component, the first preset cache is any first data register in the set of data registers, and the second preset cache is any second data register in the set of data registers;

[0028] Correspondingly, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, including:

[0029] The first data carried by the write request is written into the first data register, and the flag bit corresponding to the first data register in the preset state register is set to the target value; wherein the preset state register is used to record the storage state of each data register;

[0030] A first interrupt signal is generated to the target processor, so that the target processor reads the first data from the corresponding first data register to the baseboard management controller based on the flag bit being the target value in the preset state register;

[0031] Correspondingly, the second data sent by the baseboard management controller is received by the second preset cache locally, and a target message is sent to the preset host, so that in response to the read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host, including:

[0032] The second data sent by the baseboard management controller is received by the second data register, and the flag bit corresponding to the second data register in the preset state register is set to the target value;

[0033] A target message is sent to the preset host, so that the preset host sends a read request based on the target message, to read the second data from the corresponding second data register based on the flag bit being the target value in the preset state register.

[0034] Optionally, if the target functional component is a fourth functional component, the data transmission method based on the enhanced serial peripheral interface of the application further comprises:

[0035] Based on the preset state machine, a target external device interacting with the preset host is determined, so that the first data is forwarded to the target external device through the baseboard management controller, and the second data sent by the target external device is received through the baseboard management controller.

[0036] Optionally, the preset state machine includes a first state for indicating that the fourth functional component is idle, a second state for indicating that the fourth functional component is to be unlocked, a third state for indicating that the fourth functional component is to select an external device, and a fourth state for indicating that the fourth functional component is to determine an external device;

[0037] Correspondingly, based on the preset state machine, a target external device interacting with the preset host is determined, including:

[0038] When the signal input by the preset host is a first preset signal, the preset state machine is controlled to enter the second state from the first state;

[0039] when the signal input by the preset host is a second preset signal, control the preset state machine to enter a third state from the second state;

[0040] when the signal input by the preset host is a third preset signal, control the preset state machine to enter a fourth state from the third state;

[0041] obtain a device number input by the preset host, so as to determine an external device corresponding to the device number as a target external device for interaction with the preset host.

[0042] In a second aspect, the application discloses a data transmission device based on an enhanced serial peripheral interface, which is applied to a target function component, the target function component being a function component for executing a data transmission task determined from a first function component, a second function component, a third function component and a fourth function component according to a type of to-be-transmitted data, and the device comprises:

[0043] a data writing module, configured to write first data carried by a write request into a first preset cache locally when the write request sent by the preset host is acquired, and generate a first interrupt signal to the target processor, so that the target processor writes the data in the first preset cache into a baseboard management controller;

[0044] a data reading module, configured to receive second data sent by the baseboard management controller by using a second preset cache locally, and send a target message to the preset host, so that the second data in the second preset cache is sent to the preset host in response to a read request sent by the preset host based on the target message;

[0045] The first function component is a function component set based on a keyboard controller interface, the second function component is a function component set based on an IPMI block transmission interface, the third function component is a function component set based on a mailbox message, and the fourth function component is a function component set based on an input / output interface.

[0046] In a third aspect, the application discloses an electronic device, which comprises:

[0047] a memory, configured to save a computer program;

[0048] a processor, configured to execute the computer program to realize the steps of the data transmission method based on the enhanced serial peripheral interface disclosed above.

[0049] In a fourth aspect, the application discloses a computer readable storage medium, configured to store a computer program; when the computer program is executed by a processor, the steps of the data transmission method based on the enhanced serial peripheral interface disclosed above are realized.

[0050] It can be seen that the application discloses a data transmission method based on an enhanced serial peripheral interface applied to a target function component, the target function component is a function component for performing a data transmission task determined from a first function component, a second function component, a third function component and a fourth function component according to the type of to-be-transmitted data, and the method comprises the following steps: when a write request sent by a preset host is acquired, first data carried by the write request is written into a first preset cache locally, and a first interrupt signal is generated to a target processor, so that the target processor writes the data in the first preset cache into a baseboard management controller; second data sent by the baseboard management controller is received by using a second preset cache locally, and a target message is sent to the preset host, so that, in response to a read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host; wherein the first function component is a function component based on a keyboard controller interface setting, the second function component is a function component based on an IPMI block transmission interface setting, the third function component is a function component based on a mailbox message setting, and the fourth function component is a function component based on an input and output interface setting.

[0051] Beneficial effects: the application further expands the function of the eSPI protocol, and specifically sets four function components, the first function component is a function component based on a keyboard controller interface setting, the second function component is a function component based on an IPMI block transmission interface setting, the third function component is a function component based on a mailbox message setting, and the fourth function component is a function component based on an input and output interface setting; when data transmission is needed, the target function component for performing the data transmission task is first determined from the first function component, the second function component, the third function component and the fourth function component according to the type of to-be-transmitted data. When the target function component acquires a write request sent by a preset host, first data carried by the write request is written into a first preset cache locally, and a first interrupt signal is generated to a target processor, so that the target processor writes the data in the first preset cache into a baseboard management controller, thereby realizing host write operation. Further, the target function component receives second data sent by the baseboard management controller by using a second preset cache locally, and sends a target message to the preset host, so that, in response to a read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host, thereby realizing host read operation. Through the above scheme, transmission of some special information data between the host and the baseboard management controller is realized, and the function of the baseboard management controller is increased. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute a part of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0053] Figure 1 A flow chart of a data transmission method based on an enhanced serial peripheral interface is disclosed in the present application.

[0054] Figure 2 A system architecture diagram suitable for a data transmission method based on an enhanced serial peripheral interface is disclosed in the present application.

[0055] Figure 3 A state change schematic diagram of a state machine is disclosed in the present application.

[0056] Figure 4 A structural schematic diagram of a data transmission device based on an enhanced serial peripheral interface is disclosed in the present application.

[0057] Figure 5 A structural diagram of an electronic device is disclosed in the present application. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments only constitute a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0059] Currently, the eSPI bus is mainly used as a dedicated interface between low-speed peripherals and a host. However, in the related art, only the functions of the eSPI protocol are implemented, and the transmission of some dedicated information between the host and the baseboard management controller is not extended. Therefore, the embodiments of the present application disclose a data transmission method, device, equipment and medium based on an enhanced serial peripheral interface, which can extend the functions of the eSPI protocol to realize the transmission of some dedicated information between the host and the baseboard management controller.

[0060] Referring to Figure 1 As shown in the figure, the embodiments of the present application disclose a data transmission method based on an enhanced serial peripheral interface, applied to a target functional component, the target functional component being a functional component for executing a data transmission task determined from a first functional component, a second functional component, a third functional component and a fourth functional component according to the type of the data to be transmitted, and the method comprises:

[0061] Step S11: When the write request sent by the preset host is acquired, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller.

[0062] In the embodiment, the functions of the eSPI protocol are further expanded, and four function components are specifically set. The first function component is a function component set based on a keyboard controller interface. The second function component is a function component set based on an IPMI (Intelligent Platform Management Interface) block transmission interface. The third function component is a function component set based on a mailbox message. The fourth function component is a function component set based on an input / output interface. When data transmission is needed, the target function component for executing the data transmission task is first determined from the first function component, the second function component, the third function component, and the fourth function component according to the type of the data to be transmitted.

[0063] Specifically, when the target function component acquires the write request sent by the preset host, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation.

[0064] In the specific embodiment, the function component for executing the data transmission task is determined from the first function component, the second function component, the third function component, and the fourth function component according to the type of the data to be transmitted, including: if the data to be transmitted is a command and data corresponding to system management software, the first function component is determined as the function component for executing the data transmission task; if the total amount of data of the data to be transmitted is greater than a preset threshold, the second function component is determined as the function component for executing the data transmission task; if the data to be transmitted is preset information data, the third function component is determined as the function component for executing the data transmission task; and if the data to be transmitted is interactive data corresponding to the preset host and external equipment, the fourth function component is determined as the function component for executing the data transmission task.

[0065] Specifically as Figure 2As shown, the first function component is specifically kcs (keyboard controller style interface), which is a communication protocol for transmitting information between the BMC and the BIOS (Basic Input Output System). The kcs interface is the interface between the BMC and the system management software (SMS), and the kcs interface mainly implements the transmission of SMS messages, i.e., is used to transmit commands and data corresponding to the system management software. The second function component is specifically ibt (IPMI block transfer interface, IPMI is an intelligent platform management interface), which can only transmit 1 byte at a time and is used for transmission of small amounts of data. The ibt is mainly used for bulk data transmission, i.e., if the total amount of data to be transmitted is greater than a preset threshold, the second function component is used to perform the data transmission task. The third function component is specifically mbox (mailbox message), which is mainly used to transmit message information between the host and the baseboard management controller, i.e., to transmit preset information data. The fourth function component is superio (super input / output), which is mainly used to transmit interaction data corresponding to the preset host and external device, i.e., to implement information interaction between the host and low-speed peripherals, mainly including uart (universal asynchronous receiver transmitter), gpio (general purpose input / output port), system wake-up controller, mailbox, etc. However, the related art only implements the function of the espi protocol and does not extend it. The functions of kcs, ibt, mbox, superio, etc. are implemented based on LPC (Low Pin Count), and only simple read and write designs are performed without the participation of control signals. The present application extends the function of the espi protocol and uses espi to implement the functions of kcs, ibt, mbox, superio, etc., to implement the transmission of some special information between the host and the bmc, and to increase the function of the bmc.

[0066] Step S12: receiving the second data transmitted by the baseboard management controller using the local second preset cache, and transmitting a target message to the preset host, so as to transmit the second data in the second preset cache to the preset host in response to a read request transmitted by the preset host based on the target message.

[0067] In the embodiment, the target functional component receives the second data sent by the baseboard management controller through the local second preset cache, and sends a target message to the preset host, so as to send the second data in the second preset cache to the preset host in response to a read request sent by the preset host based on the target message, thereby realizing the host read operation. Through the above scheme, the transmission of some special information data between the host and the baseboard management controller is realized, and the function of the baseboard management controller is increased.

[0068] It should be further pointed out that, in order to optimize the data transmission mechanism between the host and the baseboard management controller, a data compression and decompression algorithm can also be introduced in the target functional component, that is, the data sending end transmits the data after compression, and correspondingly, the receiving end needs to decompress after receiving the data, thereby reducing the amount of transmitted data and improving the transmission efficiency, and the specific compression algorithm and decompression algorithm are not limited here. For example, in the host write operation stage, the host transmits data after compression using a selected compression algorithm, and the compressed data is transmitted to the BMC. After receiving the compressed data, the BMC restores the data using a corresponding decompression algorithm. In this way, the data transmission time can be reduced, the system response speed can be improved, and more data can be transmitted under limited bandwidth.

[0069] In a specific embodiment, if the target functional component is the first functional component, the first preset cache is the first register, and the second preset cache is the second register; correspondingly, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, including: the first data carried by the write request is written into the first register; the level state of the first flag signal corresponding to the first register is set to high level, so as to generate the first interrupt signal to the target processor, so that the target processor writes the first data stored in the first register to the baseboard management controller; correspondingly, the second data sent by the baseboard management controller is received through the local second preset cache, and a target message is sent to the preset host, so as to send the second data in the second preset cache to the preset host in response to a read request sent by the preset host based on the target message, including: the second data sent by the baseboard management controller is received by the second register, and the level state of the second flag signal corresponding to the second register is set to high level, so as to send the second data in the second register to the preset host in response to a read request sent by the preset host based on the high level signal.

[0070] That is, in the kcs module, two preset buffers are a first register and a second register, wherein the first register is specifically an IBR register (Input Buffer Register, input buffer register), and the second register is specifically an OBR register (Output Buffer Register, output buffer register). The IBR register is used to receive data sent by the host for reading by the BMC, and the OBR register is used to receive data sent by the BMC for reading by the host. The two registers each have a flag signal. As long as there is data in the register, the corresponding flag signal is pulled high, and as long as there is no data, the flag signal is pulled low. The IBR register is 9 bits in size, wherein the highest 1 bit is used to distinguish whether the data sent by the host is a command or data, and the other 8 bits are the content of the transmission; and the OBR register is 8 bits, and only the data read by the host from the BMC is transmitted.

[0071] The host write process of the kcs module is specifically as follows: the preset host first queries whether there is data in the IBR register. Only when there is no data in the register can the host send data or a command. Otherwise, the host will continue to query. When the host can send, the host sends a write request carrying data to be written and an address. The kcs module judges the address sent. If the address sent is a command address, it indicates that the data transmitted this time is a command. The data is placed in the low 8 bits of the IBR register, and the 9th bit is set to 1, indicating that it is a command. The corresponding first flag signal is pulled high, and a corresponding first interrupt signal is generated and sent to the target processor. The target processor in the embodiment is specifically an ARM (Advanced RISC Machines) processor. After receiving the first interrupt signal, the ARM processor obtains the data written by the host to the BMC by reading the IBR register. In addition, if the address sent is a data address, the data transmitted this time is data. The data is directly placed in the low 8 bits of the KCS IBR register, and the 9th bit is set to 0, indicating that it is data. The corresponding first flag signal is pulled high, and a first interrupt signal is generated and sent to the ARM processor. After receiving the interrupt, the ARM processor reads the data away. After reading away, the flag signal of the IBF register is automatically pulled low.

[0072] The host read flow of the kcs module is as follows: the host first needs to query whether there is data in the OBR register, if there is data, it indicates that the ARM has written data into the OBR register, at this time the host can go to perform the read operation, otherwise the host cannot initiate the read operation. When the OBR register in the kcs module has no data, the ARM can write data into the register, that is, the OBR register receives the data written by the BMC, when the writing is successful, the second flag signal corresponding to the register is pulled high, indicating that there is data in the register, at this time, the preset host can initiate the read operation, sends the address of the OBR register, and reads the data in the OBR register, after the data is read, the flag signal of the OBF register is automatically pulled low.

[0073] In a specific embodiment, if the target function component is the second function component, the first preset cache is the first random memory and the second preset cache is the second random memory; correspondingly, writing the first data carried by the write request into the first preset cache locally and generating a first interrupt signal to the target processor so that the target processor writes the data in the first preset cache into the baseboard management controller, comprises: writing the first data carried by the write request into a first position in the first random memory according to the current first write pointer, and performing an add-one operation on the current first write pointer to update the current first write pointer; after the first data is written, generating a first interrupt signal to the target processor so that the target processor generates a read enable signal and writes the data in the first random memory into the baseboard management controller; correspondingly, using the second preset cache locally to receive the second data sent by the baseboard management controller, and sending a target message to the preset host so as to send the second data in the second preset cache to the preset host in response to the read request sent by the preset host based on the target message, comprises: receiving the second data sent by the baseboard management controller using a second position in the second random memory according to the current second write pointer; after the second data is received, sending a target message to the preset host so that the preset host generates a read enable signal and reads the second data from the second random memory.

[0074] That is, the kcs module has two RAM (Random Access Memory) cache spaces, namely host2bmc buffer (i.e. the first random memory) and bmc2host buffer (i.e. the second random memory), and the size of each is 256 bytes. When the host intends to perform a write operation, the host sends a write enable and write data, and the kcs module stores the data in the corresponding first position of the host2bmc buffer according to the current first write pointer position, and simultaneously increments the corresponding current first write pointer by one for the next write operation. When the host has written all the data to be transmitted, the kcs module generates a first interrupt signal to the target processor (i.e. ARM). After the ARM receives the interrupt signal, it reads the data in the host2bmc buffer, generates a read enable to read, and increments the read pointer by one for each read until all the data is read out, after which all the pointers are cleared. The host read operation is the same. First, the ARM writes corresponding data into the bmc2host buffer. After the data is written, the kcs module notifies the host, and then the host initiates a read operation, generates a read enable signal, and reads the data in the bmc2host buffer. For each read, the corresponding read pointer is incremented by one, and after all the data is read, the pointer is cleared.

[0075] In a specific embodiment, if the target function component is a third function component, the first preset cache is any first data register in the set of data registers, and the second preset cache is any second data register in the set of data registers; accordingly, writing the first data carried by the write request into the first preset cache locally and generating a first interrupt signal to the target processor so that the target processor writes the data in the first preset cache to the baseboard management controller includes: writing the first data carried by the write request into the first data register and setting a flag corresponding to the first data register in the preset status register to a target value; wherein the preset status register is used to record the storage state of each data register; generating a first interrupt signal to the target processor so that the target processor reads the first data from the corresponding first data register to the baseboard management controller based on the flag being the target value in the preset status register; accordingly, using the second preset cache locally to receive the second data sent by the baseboard management controller and sending a target message to the preset host so that, in response to the read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host, which includes: using the second data register to receive the second data sent by the baseboard management controller and setting the flag corresponding to the second data register in the preset status register to the target value; sending a target message to the preset host so that the preset host sends a read request based on the target message to read the second data from the corresponding second data register based on the flag being the target value in the preset status register.

[0076] It should be noted that the mbox module has 32 data registers, each of which can cache 8 bits of data, and the mbox module has a total of 4 status registers, each of which is 8 bits, for a total of 32 bits. In this way, each 1-bit status register corresponds to a data register. When the host performs a write operation, the host writes the first data carried by the write request into the corresponding first data register and sets the flag corresponding to the first data register in the preset status register to a target value. After the mbox module receives the first data, an interrupt signal is generated to the target processor ARM. After the ARM receives the interrupt signal, it reads the preset status register to check the corresponding state change. According to the change of the status register, the data register corresponding to the status register is found, and then the data is read out. Finally, the interrupt is cleared. The mbox module mainly implements the caching of data on the hardware and the corresponding relationship between the data registers and the status registers. The process of the host read operation is the same as that of the write operation. First, the ARM writes the data into the second data register of the mbox module, and the corresponding status register is set high. The mbox module notifies the host that the data can be read. Then the host reads the status register and reads the data from the corresponding second data register according to the status of the status register. Finally, the interrupt is cleared.

[0077] In a specific implementation, if the target function component is the fourth function component, the enhanced serial peripheral interface based data transmission method further comprises: determining, based on a preset state machine, a target external device interacting with the preset host, so as to forward the first data to the target external device by the baseboard management controller, and receiving second data sent by the target external device by the baseboard management controller.

[0078] That is, the superio module mainly implements the parsing logic device function through the state machine. Specifically, the target external device selected currently interacting with the preset host is determined based on the preset state machine, so as to realize the data transmission between the baseboard management controller and the target external device.

[0079] Specifically, the preset state machine comprises a first state for indicating that the fourth function component is idle, a second state for indicating that the fourth function component is to be unlocked, a third state for indicating that the fourth function component is to select an external device, and a fourth state for indicating that the fourth function component is to determine an external device. Correspondingly, the target external device interacting with the preset host is determined based on the preset state machine, comprising: when the signal input by the preset host is a first preset signal, controlling the preset state machine to enter the second state from the first state; when the signal input by the preset host is a second preset signal, controlling the preset state machine to enter the third state from the second state; when the signal input by the preset host is a third preset signal, controlling the preset state machine to enter the fourth state from the third state; and acquiring the device number input by the preset host, so as to determine the external device corresponding to the device number as the target external device interacting with the preset host.

[0080] That is, as Figure 3As shown, the preset state machine in the superio module mainly includes four states, which are a first state SIOR_IDLE, a second state SIOR_UNLOCK, a third state SIOR_X, and a fourth state SIOR_LDN. The SIOR_IDLE state is an idle state without operation. If the host wants to operate any logical device under the superio, the first preset signal 0xA5 is written first, and then the state machine enters the SIOR_UNLOCK state from the idle state, which is equivalent to entering a password stage, i.e., an unlocked state. If the host wants to continue, the second preset signal 0xA5 needs to be written in the unlocked state, and then the state machine enters a stage of selecting an external logical device, i.e., the SIOR_X state. In the SIOR_X state, the host writes the third preset signal 0x07, and then the state machine continues to jump to the SIOR_LDN state, which indicates that the logical device register is selected. The register is a device number of an external logical device (referred to as an external device), which represents which external device the host wants to select for data transmission. In the SIOR_LDN state, the host writes the device number of the selected external device into the register, and then the host can operate the corresponding register in the selected external device. After the host completes the operation, 0xAA is directly sent, and then the state machine returns to the idle state, and the host can perform the next logical device operation. In the state machine, as long as the jump condition is not met, the state machine remains in the current state. Each time the data of the selected logical device is transmitted, the operation needs to be performed in the SIOR_LDN state.

[0081] It can be seen that the application further expands the functions of the eSPI protocol, and specifically sets four function components, the first function component is a function component set based on a keyboard controller interface, the second function component is a function component set based on an IPMI block transmission interface, the third function component is a function component set based on a mailbox message, and the fourth function component is a function component set based on an input / output interface. When data transmission is required, the target function component for performing the data transmission task is first determined from the first function component, the second function component, the third function component and the fourth function component according to the type of the data to be transmitted. When the target function component obtains a write request sent by the preset host, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation. Further, the target function component receives second data sent by the baseboard management controller using the local second preset cache, and sends a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, thereby realizing the host read operation. Through the above scheme, the transmission of some special information data between the host and the baseboard management controller is realized, and the function of the baseboard management controller is increased.

[0082] Referring to Figure 4 It is shown that the application embodiment discloses a data transmission device based on an enhanced serial peripheral interface, applied to a target function component, the target function component being a function component for performing a data transmission task determined from a first function component, a second function component, a third function component and a fourth function component according to the type of the data to be transmitted, and the device comprises:

[0083] The data write module 11 is configured to write the first data carried by the write request into the local first preset cache and generate a first interrupt signal to the target processor when the write request sent by the preset host is obtained, so that the target processor writes the data in the first preset cache to the baseboard management controller.

[0084] The data read module 12 is configured to receive second data sent by the baseboard management controller using the local second preset cache, and send a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host.

[0085] The first function component is a function component set based on a keyboard controller interface, the second function component is a function component set based on an IPMI block transmission interface, the third function component is a function component set based on a mailbox message, and the fourth function component is a function component set based on an input / output interface.

[0086] It can be seen that the application further expands the function of the eSPI protocol, and specifically sets four function components, the first function component is a function component set based on a keyboard controller interface, the second function component is a function component set based on an IPMI block transmission interface, the third function component is a function component set based on a mailbox message, and the fourth function component is a function component set based on an input / output interface. When data transmission is required, the target function component for performing the data transmission task is first determined from the first function component, the second function component, the third function component and the fourth function component according to the type of the data to be transmitted. When the target function component obtains a write request sent by the preset host, the first data carried by the write request is written into the local first preset cache, and a first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache to the baseboard management controller, thereby realizing the host write operation. Further, the target function component receives second data sent by the baseboard management controller using the local second preset cache, and sends a target message to the preset host, so as to respond to the read request sent by the preset host based on the target message, and send the second data in the second preset cache to the preset host, thereby realizing the host read operation. Through the above scheme, the transmission of some special information data between the host and the baseboard management controller is realized, and the function of the baseboard management controller is increased.

[0087] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part are described with reference to the embodiments of the method part, which are not described here. Moreover, the embodiments have the same beneficial effects as the above-mentioned data transmission method based on the enhanced serial peripheral interface.

[0088] Figure 5 A structural schematic diagram of an electronic device provided in the embodiments of the application is shown. Specifically, it can include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the related steps of the data transmission method based on the enhanced serial peripheral interface executed by the electronic device disclosed in any of the preceding embodiments.

[0089] In the embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 is any communication protocol applicable to the technical solution of the application, which is not limited here; the input / output interface 25 is used to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not limited here.

[0090] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 21 can also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also referred to as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing content required to be displayed by the display screen. In some embodiments, the processor 21 can further include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0091] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a magnetic disk, an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222, and data 223, etc. The storage mode can be temporary storage or permanent storage.

[0092] The operating system 221 is used to manage and control each hardware device on the electronic device 20 and the computer program 222, so as to realize the operation and processing of the processor 21 on the mass data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222 can further include computer programs for completing other specific work in addition to the computer program for completing the enhanced serial peripheral interface-based data transmission method executed by the electronic device 20 disclosed in any of the preceding embodiments. The data 223 can include data transmitted by an external device received by the electronic device, data collected by the self input / output interface 25, etc.

[0093] Further, the embodiments of the present application also disclose a computer readable storage medium, the storage medium storing a computer program, the computer program being loaded and executed by the processor to implement the steps of the enhanced serial peripheral interface-based data transmission method disclosed in any of the preceding embodiments.

[0094] Further, the embodiment of the present application further discloses a computer program product, comprising computer programs / instructions, which, when executed by a processor, implement the steps of the enhanced serial peripheral interface based data transmission method disclosed in any of the foregoing embodiments.

[0095] The various embodiments are described in the present specification in progressive manner, each embodiment focusing on differences from other embodiments, and the same or similar parts among the various embodiments can be mutually referred to. For the apparatus disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0096] Those skilled in the art can further understand that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present specification can be realized in electronic hardware, computer software or combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in general in the foregoing description. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0097] The steps of the method or algorithm described in combination with the embodiments disclosed in the present specification can be directly implemented by hardware, software modules executed by a processor, or combination of both. The software modules can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0098] Finally, it needs to be pointed out that, in this article, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0099] The above provides a detailed description of the data transmission method, device, equipment and storage medium based on the enhanced serial peripheral interface provided by the application. The principles and implementation modes of the application are described in this article by applying specific examples. The above example is only used to help understand the method and core idea of the application. Meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the application.

Claims

1. A data transmission method based on enhanced serial peripheral interface, characterized in that, The method is applied to a target function component, which is determined from a first function component, a second function component, a third function component and a fourth function component according to a type of data to be transmitted, and is used for performing a data transmission task, and the method comprises the following steps: When a write request sent by a preset host is acquired, first data carried by the write request is written into a first preset cache locally, and a first interrupt signal is generated to a target processor, so that the target processor writes data in the first preset cache into a baseboard management controller; Second data sent by the baseboard management controller is received by using a second preset cache locally, and a target message is sent to the preset host, so that, in response to a read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host; The first function component is a function component set based on a keyboard controller interface, the second function component is a function component set based on an IPMI block transmission interface, the third function component is a function component set based on a mailbox message, and the fourth function component is a function component set based on an input / output interface.

2. The enhanced serial peripheral interface based data transfer method according to claim 1, wherein, The function component used for performing the data transmission task is determined from the first function component, the second function component, the third function component and the fourth function component according to the type of data to be transmitted, and the method comprises the following steps: If the data to be transmitted is a command and data corresponding to system management software, the first function component is determined as the function component used for performing the data transmission task; If a total amount of the data to be transmitted is greater than a preset threshold, the second function component is determined as the function component used for performing the data transmission task; If the data to be transmitted is preset information data, the third function component is determined as the function component used for performing the data transmission task; If the data to be transmitted is interactive data corresponding to the preset host and an external device, the fourth function component is determined as the function component used for performing the data transmission task.

3. The enhanced serial peripheral interface based data transfer method according to claim 2, wherein, If the target function component is the first function component, the first preset cache is a first register, and the second preset cache is a second register; Correspondingly, the first data carried by the write request is written into the first preset cache locally, and the first interrupt signal is generated to the target processor, so that the target processor writes the data in the first preset cache into the baseboard management controller, and the method comprises the following steps: The first data carried by the write request is written into the first register; A level state of a first flag signal corresponding to the first register is set to a high level, so as to generate the first interrupt signal to the target processor, so that the target processor writes the first data stored in the first register into the baseboard management controller; Correspondingly, the second data sent by the baseboard management controller is received by using the second preset cache locally, and the target message is sent to the preset host, so that, in response to the read request sent by the preset host based on the target message, the second data in the second preset cache is sent to the preset host, and the method comprises the following steps: The second register is used to receive the second data sent by the baseboard management controller, and a level state of a second flag signal corresponding to the second register is set to a high level, so that the second data in the second register is sent to the preset host in response to a read request sent by the preset host based on the high level signal.

4. The enhanced serial peripheral interface based data transfer method according to claim 2, wherein, If the target function component is the second function component, the first preset cache is a first random memory, and the second preset cache is a second random memory. Correspondingly, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to a target processor, so that the target processor writes the data in the first preset cache into the baseboard management controller, including: The first data carried by the write request is written into a first position in the first random memory according to a current first write pointer, and a one operation is performed on the current first write pointer to update the current first write pointer; After the first data is written, a first interrupt signal is generated to a target processor, so that the target processor generates a read enable signal and writes the data in the first random memory into the baseboard management controller; Correspondingly, the second data sent by the baseboard management controller is received by using a second preset cache locally, and a target message is sent to the preset host, so that the second data in the second preset cache is sent to the preset host in response to a read request sent by the preset host based on the target message, including: The second data sent by the baseboard management controller is received by using a second position in the second random memory according to a current second write pointer; After the second data is received, a target message is sent to the preset host, so that the preset host generates a read enable signal and reads the second data from the second random memory.

5. The enhanced serial peripheral interface based data transfer method according to claim 2, wherein, If the target function component is the third function component, the first preset cache is any first data register in a set of data registers, and the second preset cache is any second data register in the set of data registers. Correspondingly, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to a target processor, so that the target processor writes the data in the first preset cache into the baseboard management controller, including: The first data carried by the write request is written into the first data register, and a flag bit corresponding to the first data register in a preset state register is set to a target value; wherein the preset state register is used to record storage states of each data register; A first interrupt signal is generated to a target processor, so that the target processor reads the first data from the corresponding first data register to the baseboard management controller based on the flag bit with the target value in the preset state register; and Correspondingly, the first data carried by the write request is written into the first preset cache locally, and a first interrupt signal is generated to a target processor, so that the target processor writes the data in the first preset cache into the baseboard management controller, including: The first data carried by the write request is written into the first data register, and a flag bit corresponding to the first data register in a preset state register is set to a target value; wherein the preset state register is used to record storage states of each data register; A first interrupt signal is generated to a target processor, so that the target processor reads the first data from the corresponding first data register to the baseboard management controller based on the flag bit with the target value in the preset state register; and Correspondingly, the receiving, by the second preset cache locally, of the second data sent by the baseboard management controller and the sending, to the preset host, of a target message so as to respond to a read request sent by the preset host based on the target message and send the second data in the second preset cache to the preset host, comprises: receiving, by the second data register, of the second data sent by the baseboard management controller and setting a flag bit corresponding to the second data register in the preset state register to the target value; sending, to the preset host, of a target message so as to send a read request by the preset host based on the target message and read the second data from the corresponding second data register based on the flag bit in the preset state register being the target value.

6. The enhanced serial peripheral interface based data transfer method according to claim 2, wherein, If the target function component is the fourth function component, the method further comprises: determining, based on a preset state machine, of a target external device interacting with the preset host so as to forward, by the baseboard management controller, the first data to the target external device and receive, by the baseboard management controller, of the second data sent by the target external device.

7. The enhanced serial peripheral interface based data transfer method according to claim 6, wherein, The preset state machine comprises a first state for indicating that the fourth function component is idle, a second state for indicating that the fourth function component is to be unlocked, a third state for indicating that the fourth function component is to select an external device and a fourth state for indicating that the fourth function component is to determine an external device; Correspondingly, the determining, based on a preset state machine, of a target external device interacting with the preset host comprises: when the signal input by the preset host is a first preset signal, controlling the preset state machine to enter the second state from the first state; when the signal input by the preset host is a second preset signal, controlling the preset state machine to enter the third state from the second state; when the signal input by the preset host is a third preset signal, controlling the preset state machine to enter the fourth state from the third state; acquiring a device number input by the preset host so as to determine an external device corresponding to the device number as the target external device interacting with the preset host.

8. An enhanced serial peripheral interface based data transfer apparatus, characterized by, Applied to a target function component, the target function component being a function component for performing a data transmission task determined from a first function component, a second function component, a third function component and a fourth function component according to a type of data to be transmitted, the apparatus comprises: a data write module for, when a write request sent by a preset host is acquired, writing first data carried by the write request into a first preset cache locally and generating a first interrupt signal to a target processor so as to write data in the first preset cache to a baseboard management controller by the target processor; a data read module for receiving, by a second preset cache locally, of second data sent by the baseboard management controller and sending, to the preset host, of a target message so as to respond to a read request sent by the preset host based on the target message and send the second data in the second preset cache to the preset host; The first function component is a function component based on a keyboard controller interface setting, the second function component is a function component based on an IPMI block transmission interface setting, the third function component is a function component based on a mailbox message setting, and the fourth function component is a function component based on an input / output interface setting.

9. An electronic device, comprising: Comprise: a memory for saving a computer program; a processor for executing the computer program to implement the steps of the data transmission method based on the enhanced serial peripheral interface according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, a computer program for storage; wherein the computer program is executed by a processor to implement the steps of the data transmission method based on the enhanced serial peripheral interface according to any one of claims 1 to 7.

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