Semiconductor device and semiconductor system

Abstract

The invention relates to a semiconductor device and a semiconductor system. The core particle comprises an I3C controller used for receiving a processing request transmitted through an I3C bus and sending an interruption notification to a DMA module; the DMA module is used for reading response data corresponding to the processing request from a response queue cache in the I3C controller under the condition that the interrupt notification is received, and reading payload data from a receiving data cache in the I3C controller according to the response data to serve as DMA data; and executing a corresponding command according to the DMA data. The data transmission between the semiconductor devices can be realized through the I3C bus, and the internal data transmission can be realized through a DMA (Direct Memory Access) mode, so that the master semiconductor device can directly send the CPU mirror image file to the slave semiconductor device, and a storage device does not need to be externally hung on the slave semiconductor device to store the CPU mirror image file. Therefore, the problem that low-speed interfaces defined by different manufacturers are incompatible can be solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a semiconductor system. Background Art

[0002] There are many types of high-speed interfaces used for interconnecting chiplets. These high-speed interface buses generally require a complex configuration and initialization process. At present, different manufacturers use different methods for low-speed interface access before high-speed interface initialization, and there is no standard low-speed interface defined for communication between chiplets. This makes each manufacturer use its own defined low-speed interface, resulting in only controlled access between chiplets produced by itself, and unable to control access between chiplets produced by different manufacturers. In order to enable the chiplets produced by each manufacturer to control access to each other through the low-speed interface, it is necessary to adjust the low-speed interfaces defined by different manufacturers, which will extend the development time of the chip and increase the design cost. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device and a semiconductor system that can improve the incompatibility problem of low-speed interfaces between different semiconductor devices in order to address the above technical problems.

[0004] In a first aspect, the present application provides a semiconductor device, comprising:

[0005] An I3C controller is used to receive processing requests transmitted via the I3C bus and send interrupt notifications to the DMA module;

[0006] The DMA module is used to read the response data corresponding to the processing request from the response queue buffer in the I3C controller when receiving the interrupt notification, and read the payload data from the receiving data buffer in the I3C controller as DMA data according to the response data; and execute the corresponding command according to the DMA data.

[0007] In a specific embodiment, the DMA module includes an interrupt processing unit and an execution unit;

[0008] The interrupt processing unit is used to receive the interrupt notification sent by the I3C controller, read the interrupt from the interrupt register in the I3C controller, and if the read interrupt is a response interrupt corresponding to the processing request, send the response interrupt corresponding to the processing request to the execution unit;

[0009] The execution unit is used for, after receiving a response interrupt corresponding to the processing request, reading response data corresponding to the processing request from a response queue buffer in the I3C controller, obtaining a length of payload data in the processing request according to the response data, and reading data from a receiving data buffer in the I3C controller according to the payload length as DMA data;

[0010] The execution unit is also used to execute commands in the DMA data.

[0011] In a specific implementation, the DMA module further includes:

[0012] The verification unit is used to verify the DMA data after reading the data from the receiving data buffer in the I3C controller as DMA data; if the verification fails, the interrupt processing flow is triggered; if the verification passes, the execution unit continues to execute the subsequent flow.

[0013] In a specific implementation, the verification unit is specifically configured to send an interrupt message for indicating a verification error to the I3C controller when the verification fails;

[0014] The I3C controller is further used to send an interrupt message to the semiconductor device at the opposite end; according to the command count carried by the interrupt message, delete the data cached after the data corresponding to the command count in the received data cache, and delete the data cached after the response data corresponding to the command count in the response queue cache;

[0015] The I3C controller is also used to send an interrupt message to the semiconductor device at the other end to indicate that the semiconductor device at the other end can resend data if no new data is cached in the received data cache for a preset period of time after sending the interrupt message to the semiconductor device at the other end.

[0016] In a specific implementation, the execution unit is specifically configured to write the payload data in the DMA data into the corresponding storage space through the AXI bus according to the write command when the command to be executed in the DMA data is a write command.

[0017] In a specific embodiment, the DMA module further includes a read processing unit;

[0018] The execution unit is further configured to send at least part of the fields in the read command to the read processing unit when the command to be executed in the DMA data is a read command;

[0019] A read processing unit, configured to send at least part of the fields in the read command to a send command buffer in the I3C controller; read corresponding data through the AXI bus according to the read command, and send the data to the send data buffer in the I3C controller;

[0020] The I3C controller is also used to send the data cached in the send command cache and the send data cache to the semiconductor device at the opposite end.

[0021] In a specific embodiment, the I3C controller is further used to store the execution status of the command as response data in the response queue buffer after the command in the DMA data is executed, and send an interrupt notification to the interrupt processing unit;

[0022] The interrupt processing unit is further used to receive the interrupt notification sent by the I3C controller, read the interrupt from the interrupt register in the I3C controller; if the read interrupt is a response interrupt corresponding to the command, send the response interrupt corresponding to the command to the execution unit;

[0023] The execution unit is used to read the execution status of the command from the response queue buffer in the I3C controller after receiving the response interrupt corresponding to the command, and send an interrupt message for indicating the command execution error to the I3C controller when the execution status indicates that the command execution error occurs;

[0024] The I3C controller is used to send an interrupt message to a semiconductor device at the other end.

[0025] In a specific embodiment, the I3C controller is also used to reply a negative confirmation message to the semiconductor device at the other end for data sent by the semiconductor device at the other end through the I3C bus, clear the data in the internal cache, and clear the device error status when the command to be executed in the DMA data is a write command and the execution status of the write command indicates an execution error of the write command.

[0026] In a specific implementation, the execution unit is specifically configured to send a cache clearing command to the I3C controller after sending an interrupt message for notifying the peer end of a read command execution error to the I3C controller when the command to be executed in the DMA data is a read command;

[0027] The I3C controller is also used to receive a cache clearing command, clear the data in the internal cache according to the cache clearing command, and send an interrupt message to the semiconductor device at the opposite end to indicate that the semiconductor device at the opposite end can resend data.

[0028] In a second aspect, the present application further provides a semiconductor system, comprising at least two semiconductor devices provided in any specific embodiment of the first aspect; wherein data is transmitted between different semiconductor devices via an I3C bus.

[0029] In a specific embodiment, the semiconductor device is a die or a chip.

[0030] In the semiconductor device and semiconductor system, before initializing the high-speed interface between the master semiconductor device and the slave semiconductor device, data can be transmitted between the semiconductor devices through the I3C bus, and data can be transmitted inside the semiconductor device through the DMA method, so that the master semiconductor device can directly send the CPU image file to the slave semiconductor device to boot the slave semiconductor device, without the need for the slave semiconductor device to store the CPU image file through an external storage device. Therefore, the packaging and use costs can be reduced, and the problem of incompatibility between low-speed interfaces defined by different manufacturers can also be solved.

[0031] In addition, since the master semiconductor device can be connected to multiple slave semiconductor devices, the storage space inside all slave semiconductor devices can be uniformly managed through one master semiconductor device, which facilitates management and simplifies software programming. Since data is transmitted between different semiconductor devices through the I3C bus, and the I3C bus only has two signal lines, the serial clock line and the serial data line, the semiconductor device only needs two more bumps to achieve the connection requirements through the two signal lines, which makes the manufacturing cost of the semiconductor device lower and occupies less area on the chip. In the case of high-speed interface abnormalities, testing can be performed through the I3C path to ensure the stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of an application environment of a semiconductor system in one embodiment;

[0034] Figure 2 A schematic diagram of the interaction between the CPU subsys and the I3C DMA module in one embodiment;

[0035] Figure 3 is a schematic structural diagram of a semiconductor device in one embodiment;

[0036] Figure 4 A schematic diagram of the format of a write command in one embodiment;

[0037] Figure 5 A schematic diagram of the format of an interrupt message in one embodiment;

[0038] Figure 6 A schematic diagram of the format of a read command in one embodiment;

[0039] Figure 7 FIG. 1 is a schematic diagram of a process of processing a request sent by a master semiconductor device in one embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] The common multi-chip interconnection structure generally has one master chip and multiple slave chips. The slave chips generally do not have a separate external memory to store the CPU image file, otherwise it will form a chip with many flash memories and many more pins on the package, which greatly increases the packaging and use costs. At present, the industry's unified practice is to store the CPU image files of all slave chips and the CPU image files of the master chip in an external memory. After the chip is powered on, the master chip first loads the corresponding CPU image file for startup. Then the master chip configures the slave chips, that is, the master chip sends the corresponding CPU image file to each slave chip to guide the slave chip to start.

[0042] The high-speed interface bus for interconnecting chiplets, such as UCIe (Universal Chiplet Interconnect Express), generally requires a complex configuration and initialization process. For the slave chiplet, it needs to rely on the above-mentioned CPU image file sent by the master chiplet before the slave chiplet can start to further initialize the high-speed interface. Therefore, there needs to be a low-speed interface between the master chiplet and the slave chiplet compared to the high-speed interface, so that the slave chiplet can receive the CPU image file sent by the master chiplet for startup.

[0043] However, currently, different manufacturers use different methods to access the low-speed interface before the high-speed interface is initialized, and a standard low-speed interface for communication between chiplets has not yet been defined. This forces each manufacturer to use its own defined low-speed interface, resulting in only controlled access between chiplets produced by itself, and unable to achieve mutual control of access between chiplets produced by different manufacturers. In order to enable the chiplets produced by each manufacturer to control access to each other through the low-speed interface, the low-speed interfaces defined by different manufacturers need to be adjusted, which will extend the chip development time and increase the design cost.

[0044] Based on the above description, the embodiment of the present application provides a semiconductor device, which can realize data transmission through DMA mode inside the semiconductor device, and can realize data transmission through I3C bus between semiconductor devices, which can be specifically applied to Figure 1 In the application environment shown. Figure 1 In the context of the term CPU subsys, CPU subsys is the abbreviation or abbreviation of CPU subsystem. In computer architecture, the CPU subsystem is a key part that includes the CPU (central processing unit) and its related components and interfaces, which are used to execute instructions in computer programs and process data. Bus refers to the bus, which can be the Advanced Peripheral Bus (APB) for connecting low-speed peripherals. DMA refers to Direct Memory Access (DMA). I3C controller refers to the improved I2C (I3C, Improved Inter-Integrated Circuit) controller. APB 2to1 refers to the 1-to-2 interconnection bridge realized through APB, and Intr means interrupt notification. The I3C DMA module is used to implement data access paths between different semiconductor devices.

[0045] The I3C controller can work in master mode or slave mode. Figure 1 In the embodiment, the I3C controller in the master semiconductor device operates in the master mode, and the I3C controller in the slave semiconductor device operates in the slave mode. When the I3C controller operates in the master mode, the CPU in the master semiconductor device can be started first, and then the I3C controller is configured, and the common command code (CCC) is sent through the I3C controller to initialize the I3C mode of the I3C controller in the slave semiconductor device and configure the dynamic address.

[0046] Thus, the I3C controller in the slave semiconductor device can operate in slave mode. In slave mode, the I3C DMA function can be enabled by default in the slave semiconductor device, that is, the I3C DMA module interacts with the I3C controller. At this time, the CPU in the slave semiconductor device may not work. If the CPU is required to control the I3C controller, the I3CDMA module can be disabled after the CPU is started. At this time, the CPU can interact with the I3C controller. The master semiconductor device can access the storage space in the slave semiconductor device through the internal I3C controller to specifically implement the initialization of the slave semiconductor device, send the CPU image file to the CPU of the slave semiconductor device, and guide the CPU in the slave semiconductor device to start.

[0047] Further, the interaction between the CPU subsys and the I3C DMA module can be referred to Figure 2 .exist Figure 2 In the I3CDMA module, the I3C interface submodule can be further divided into the I3C interface submodule and the DMA control submodule. The I3C interface submodule corresponds to the I3Cif wrap; and the DMA control submodule corresponds to the dma ctrl wrap, which is the I3C DMA module. ABP IF represents the APB interface, and AXI IF represents the AXI interface. APB4 represents the use of the fourth revision of the APB protocol, AXI4 represents the use of the fourth revision of the AXI protocol, and cfg write represents the writing of configuration information between the CPU and the I3C DMA module. Figure 2 For other contents, please refer to the above explanation.

[0048] As mentioned above, when the I3C controller works in master mode, the CPU can directly control the I3C controller. When the I3C controller works in slave mode, the CPU can directly control the I3C controller, or the I3C DMA module can directly control it. Figure 2 It can be seen that if the CPU controls the I3C controller, no matter whether the I3C controller works in master mode or slave mode, the data transmission path and control path can be the same, and a general DMA mechanism can be used. Among them, the I3C DMA module mainly works when the I3C controller works in slave mode. The I3C DMA module and the CPU share the interface for accessing the I3C controller. In order to enable the CPU and the I3C DMA module to reuse the APB interface, APB 2to1 can be used to enable APB to achieve 1 to 2.

[0049] In addition, as can be seen from the above content, the I3C controller in the master semiconductor device can initialize the I3C mode of the I3C controller in the slave semiconductor device by sending CCC. In addition, whether the I3C controller in the slave semiconductor device is controlled by the CPU or the I3C DMA module in the slave semiconductor device, the data sent by the master semiconductor device to the I3C controller of the slave semiconductor device uses the same data structure, so that the master semiconductor device cannot perceive whether the slave semiconductor device is controlled by the CPU or the I3C DMA module.

[0050] After receiving the interrupt notification sent by the I3C controller, the I3C DMA module can read data from the I3C controller through the APB interface to obtain the commands to be executed and the data to be processed; the I3C DMA module can also send data to the I3C controller through the APB interface, thereby realizing bidirectional data transmission. After receiving the command sent by the master semiconductor device, the I3C DMA module in the slave semiconductor device can perform read and write operations on the internal storage space. Specifically, the I3C DMA module can convert the command into accessing the storage space in the slave semiconductor device through the AXI bus.

[0051] In combination with the above description, the semiconductor device provided in the embodiment of the present application can refer to Figure 3 The semiconductor device can be used as a master semiconductor device or a slave semiconductor device. For example, when two semiconductor devices transmit data to each other, one of the semiconductor devices acts as a master semiconductor device and the other chip acts as a slave semiconductor device. Figure 3 , the semiconductor device may include: an I3C controller 302 and a DMA module 304, wherein:

[0052] The I3C controller 302 is used to receive a processing request transmitted via the I3C bus and send an interrupt notification to the DMA module 304;

[0053] The DMA module 304 is used to read the response data corresponding to the processing request from the response queue cache in the I3C controller 302 when receiving the interrupt notification, and read the payload data from the receiving data cache in the I3C controller 302 as DMA data according to the response data; and execute the corresponding command according to the DMA data.

[0054] Among them, the I3C controller 302 corresponds to Figure 3 The I3C controller in the DMA module 304 corresponds to Figure 3 The I3C DMA module in Figure 3 Taking the corresponding semiconductor device in the master semiconductor device as an example, the I3C controller in the master semiconductor device can send a processing request to the I3C controller 302 in the slave semiconductor device through the I3C bus. After receiving the processing request, the I3C controller 302 in the slave semiconductor device can send an interrupt notification to the DMA module 304, that is, Figure 3 Send Intr to DMA module 304.

[0055] After receiving the interrupt notification, the DMA module 304 can read the response data corresponding to the processing request from the response queue buffer in the I3C controller. Among them, the response queue buffer can be specifically a response queue buffer, abbreviated as response queue; the response data is an entry in the response queue. The data sent by the main semiconductor device through the I3C bus each time is an I3C data packet sent through the I3C bus. The I3C data packet may include an I3C header and payload data. The I3C controller 302 can generate an entry in the response queue according to the I3C header as the corresponding response data. The length of the payload data in the processing request can be stored in the response data, and the payload data can be stored in the receiving data buffer in the I3C controller 302. The receiving data buffer can be specifically an rx data buffer, and the payload data can be read from the rx data buffer in the I3C controller 302 according to the payload length in the response data.

[0056] The payload data read from the rx data buffer can be used as DMA data, and the DMA data can carry specific commands to be executed. For example, the DMA data can carry a read command or a write command; if it carries a write command, it can further carry data to be written. Thus, the DMA module 304 can execute corresponding commands according to the DMA data, which can specifically be writing data to the storage space in the slave semiconductor device or reading data from the storage space in the slave semiconductor device. The storage space in the slave semiconductor device can be a memory or a register, and the embodiments of the present application do not specifically limit this.

[0057] In the semiconductor device, before initializing the high-speed interface between the master semiconductor device and the slave semiconductor device, data can be transmitted between the semiconductor devices through the I3C bus, and data can be transmitted inside the semiconductor device through the DMA method, so that the master semiconductor device can directly send the CPU image file to the slave semiconductor device to guide the slave semiconductor device to start, without the need for the slave semiconductor device to hang an external storage device to store the CPU image file. Therefore, the packaging and use costs can be reduced, and the problem of incompatibility between low-speed interfaces defined by different manufacturers can also be solved.

[0058] In addition, since the master semiconductor device can be connected to multiple slave semiconductor devices, the storage space inside all slave semiconductor devices can be uniformly managed through one master semiconductor device, which facilitates management and simplifies software programming. Since data is transmitted between different semiconductor devices through the I3C bus, and the I3C bus only has two signal lines, the serial clock line and the serial data line, the semiconductor device only needs two more bumps to achieve the connection requirements through the two signal lines, which makes the manufacturing cost of the semiconductor device lower and occupies less area on the chip. In the case of high-speed interface abnormalities, testing can be performed through the I3C path to ensure the stability of the semiconductor device.

[0059] In an exemplary embodiment, the DMA module 304 includes an interrupt processing unit 3042 and an execution unit 3044;

[0060] The interrupt processing unit 3042 is used to receive the interrupt notification sent by the I3C controller 302, read the interrupt from the interrupt register in the I3C controller 302, and if the read interrupt is a response interrupt corresponding to the processing request, send the response interrupt corresponding to the processing request to the execution unit 3044;

[0061] The execution unit 3044 is used for, after receiving the response interrupt corresponding to the processing request, reading the response data corresponding to the processing request from the response queue buffer in the I3C controller 302, obtaining the length of the payload data in the processing request according to the response data, and reading the data from the receiving data buffer in the I3C controller 302 according to the payload length as DMA data;

[0062] The execution unit 3044 is also used to execute commands in the DMA data.

[0063] For the specific process, please refer to Figure 3 , the I3C controller 302 can send Intr to the interrupt processing unit 3042. After receiving the interrupt notification, the interrupt processing unit 3042 can read the interrupt register in the I3C controller 302. It can be understood that the interrupt register can store multiple types of interrupts, but only the response interrupt corresponding to the processing request, that is, the response interrupt, will be sent to the execution unit 3044. Among them, Figure 3 The intr in the command is the interrupt processing unit 3042, and the cmd / respexecute is the execution unit 3044.

[0064] After receiving the response interrupt corresponding to the processing request, the execution unit 3044 can read the response data corresponding to the processing request from the response queue cache in the I3C controller 302, that is, the response queue. As can be seen from the previous content, each time the data sent by the main semiconductor device through the I3C bus is an I3C data packet sent through the I3C bus. The I3C data packet may include an I3C header and payload data. The I3C controller 302 can generate an entry in the response queue as the corresponding response data according to the I3C header. The length of the payload data in the processing request can be stored in the response data, and the payload data can be stored in the receiving data cache in the I3C controller 302.

[0065] Thus, the execution unit 3044 can obtain the length of the payload data in the processing request according to the response data, and read the payload data from the receiving data buffer in the I3C controller according to the payload length as DMA data. As mentioned above, the DMA data can carry specific commands to be executed. Thus, the execution unit 3044 can execute the commands in the DMA data.

[0066] In this embodiment, since the I3C controller can send an interrupt notification to the interrupt processing unit, and then the interrupt processing unit reads the response interrupt that needs to be processed by the execution unit and sends it to the execution unit, the execution unit can be able to specifically process the processing request sent by the master semiconductor device. In addition, since data transmission can be achieved between semiconductor devices through the I3C bus, data transmission can be achieved inside the semiconductor device through DMA, so that the master semiconductor device can directly send the CPU image file to the slave semiconductor device to guide the slave semiconductor device to start, without the need for the slave semiconductor device to plug in an external storage device to store the CPU image file. Therefore, the packaging and use costs can be reduced, and the problem of incompatibility between low-speed interfaces defined by different manufacturers can also be solved.

[0067] In an exemplary embodiment, the execution unit 3044 is specifically configured to write the payload data in the DMA data into the corresponding storage space through the AXI bus according to the write command when the command to be executed in the DMA data is a write command.

[0068] Specifically, when the command to be executed in the DMA data is a write command, the format of the DMA data can refer to Figure 4 .exist Figure 4In the write command, the 0th to 31st bits represent addr, that is, the write address. The 32nd to 39th bits represent reserved, that is, the reserved bit. The 40th to 51st bits represent data length, that is, the data length of payload. The 52nd to 55th bits represent Rnw, that is, it is used to indicate whether the command is a write command or a read command. It should be noted that the reason why four bits are used to indicate the type of command is mainly because a fault-tolerant mechanism is adopted. For example, if 0000 represents a read command and 1111 represents a write command, even if the transmitted Rnw is 1110, because only 1 bit is transmitted incorrectly, it can still be interpreted as the command being a write command, thereby achieving a certain degree of fault tolerance. The specific fault-tolerant method can be set according to the actual situation, and the embodiments of the present application do not make specific limitations on this.

[0069] The 56th to 63rd bits represent crc parity, i.e., cyclic check bits and parity check bits. The payload data in the DMA data can be multiple copies, each of which can be 32 bits, which is not specifically limited in the embodiment of the present application. When the execution unit 3044 interprets the command in the DMA data as a write command, it can write the payload data in the DMA data into the storage space determined by addr according to the write command.

[0070] In this embodiment, since data can be transmitted between semiconductor devices through the I3C bus, data can be written inside the semiconductor device through the DMA method, so that the master semiconductor device can directly send the CPU image file to the slave semiconductor device to guide the slave semiconductor device to start, without the need for the slave semiconductor device to hang an external storage device to store the CPU image file. Therefore, the packaging and use costs can be reduced, and the problem of incompatibility between low-speed interfaces defined by different manufacturers can also be solved.

[0071] In an exemplary embodiment, the DMA module 304 further includes:

[0072] The verification unit 3046 is used to verify the DMA data after reading the data from the receiving data buffer in the I3C controller 302 as DMA data; if the verification fails, the interrupt processing flow is triggered; if the verification passes, the execution unit 3044 continues to execute the subsequent flow.

[0073] Specifically, after obtaining the DMA data, the execution unit 3044 may send the DMA data to the verification unit 3046 for verification. Figure 3 In the example, Addr crc is the verification unit. As can be seen from the previous content, for Figure 4The write instruction shown in the figure has a cyclic check bit and a parity check bit in the write instruction, which can be used for verification. If the DMA data passes the verification, the execution unit 3044 can continue to execute the subsequent process, that is, execute the command in the DMA data. If the DMA data does not pass the verification, it means that there may be an error in the DMA data during the transmission process. Figure 3 , then the verification unit 3046 can send a message to an in-band interrupt (IBI), that is, send an IBI interrupt message to the I3C controller 302 to trigger an interrupt processing flow. The specific interrupt processing flow can refer to the description in the subsequent embodiments.

[0074] In this embodiment, since the DMA data can be verified by the verification unit, the integrity and accuracy of the data transmission process can be improved.

[0075] In an exemplary embodiment, the verification unit 3046 is specifically configured to send an interrupt message indicating a verification error to the I3C controller 302 when the verification fails;

[0076] The I3C controller 302 is further configured to send an interrupt message to the semiconductor device at the opposite end; delete the data cached after the data corresponding to the command count in the received data cache according to the command count carried in the interrupt message, and delete the data cached after the response data corresponding to the command count in the response queue cache;

[0077] The I3C controller 302 is also used to, after sending an interrupt message to the semiconductor device at the other end, if no new data is cached in the received data cache for a preset period of time, after clearing the device error state at the local end and restoring to a normal state, send an interrupt message to the semiconductor device at the other end to indicate that the semiconductor device at the other end can resend data.

[0078] Specifically, no matter whether the DMA data carries a write command or a read command, there may be a situation where the verification fails. Therefore, the verification unit 3046 can send an interrupt message indicating the verification error to the I3C controller 302, and the I3C controller 302 can send the interrupt message to the main semiconductor device, that is, the semiconductor device at the opposite end. The format of the interrupt message can be referred to Figure 5 .

[0079] exist Figure 5In the write command, bits 0 to 7 represent the IBI vector, that is, the type of interrupt message. Bits 8 to 23 represent count, that is, the command count, which is used to indicate which command has a check error in the corresponding DMA data, resulting in the generation of an interrupt message. Among them, the execution unit 3044 in the DMA module 304 in the semiconductor device reads a response data from the response cache queue in the I3C control 302 each time, which is equivalent to reading a command, and the command count corresponding to the command counter can be increased by 1. Therefore, when a check error occurs in the DMA data corresponding to a certain command, the check unit 3046 can obtain the command count corresponding to the command, and fill it into the corresponding interrupt message. Bits 24 to 26 represent the transaction identifier (TID, Transaction ID), which is mainly a field specified by the I3C protocol, and can also be used to represent the command count; but since there are only three bits, the range of command counts that can be represented is relatively limited. In actual implementation, the command count can be mainly represented by count. Bits 27 to 31 represent reserved, that is, reserved bits.

[0080] In addition, the types of interrupt messages mentioned above can be specifically referred to in the following Table 1:

[0081] Table 1

[0082] IBI vector data illustrate 0x0 count and TID Notify the main semiconductor device to temporarily stop sending numbers, and use count to indicate where the main semiconductor device will start sending numbers again. 0x1 reserved Notify the main semiconductor device that it can resend data 0x2 count Notify the main semiconductor device that the read data is wrong and can be read again

[0083] In the above Table 1, 0x in 0x0, 0x1 and 0x2 represents that the following number is a hexadecimal number. 0x0, 0x1 and 0x2 are all specific values ​​of IBI vector to represent different types of interrupt messages. Among them, 0x0 mainly indicates that an error occurred when the master semiconductor device sent a number to the slave semiconductor device. For example, a check error is one of them. If a check error occurs, it means that an error has occurred in the data sent by the master semiconductor device. Therefore, the master semiconductor device must clearly know which data to start sending again. Combined with the previous description of count, count can indicate which command's corresponding DMA data has a check error, that is, it corresponds to which processing request sent by the master semiconductor device has a data error, so that the master semiconductor device can be instructed to resend the data.

[0084] In some cases, the slave semiconductor device may fail to receive data due to an error. At this time, the slave semiconductor device may reply with all negative acknowledgment messages (NAK) for the data sent by the master semiconductor device, and the master semiconductor device may stop sending data. In order for the master semiconductor device to resume sending data, the slave semiconductor device can send an interrupt message to the master semiconductor device to indicate that the master semiconductor device can resend data. That is, the interrupt message can carry 0x1, and the reserved bit can be used for expansion.

[0085] As for 0x2, it mainly indicates that an error occurred when the slave semiconductor device sent a number to the master semiconductor device. For example, when the master semiconductor device reads data from the slave semiconductor device and the slave semiconductor device sends the data to be read, an error occurred. At this time, the master semiconductor device may need to resend the processing request carrying the read command. Therefore, the corresponding interrupt message may carry 0x2 and count to indicate which processing request carrying which read command the master semiconductor device needs to resend.

[0086] The above content is only a description of several types of interrupt messages. Figure 5 The number of bits of the IBI vector is 8, so that more interrupt message types can be represented. In actual implementation, it can be expanded according to needs, and the embodiment of the present application does not make specific limitations on this.

[0087] For the aforementioned process, that is, after the verification unit 3046 sends an interrupt message for characterizing the verification error to the I3C controller 302, the I3C controller 302 can send an interrupt message to the semiconductor device at the opposite end to instruct the semiconductor device at the opposite end to resend the number. At the same time, because the count in the interrupt message can represent which processing request sent by the semiconductor device at the opposite end has a data error, and a data error occurs in a certain processing request, such as an error in the data length, it may cause all the data read after the data corresponding to count in the receive data buffer (rx data buffer) and the response queue buffer (response queue) to be wrong. Therefore, the I3C controller 302 can delete the data cached after the data corresponding to the command count in the receive data buffer, and delete the data cached after the response data corresponding to the command count in the response queue buffer.

[0088] After the I3C controller 302 sends an interrupt message to the semiconductor device at the other end, the semiconductor device at the other end may stop sending data. At this time, if the received data cache in the I3C controller 302 has not cached new data for a preset period of time, the I3C controller 302 can send an interrupt message to the semiconductor device at the other end to indicate that the semiconductor device at the other end can resend data; combined with the previous content, an interrupt message carrying 0x1 can be sent. Among them, the preset duration can be 256 clock cycles, and the embodiment of the present application does not specifically limit this.

[0089] In this embodiment, when the data sent by the master semiconductor device fails to pass the verification, the I3C controller in the slave semiconductor device can send an interrupt message to the master semiconductor device to instruct the master semiconductor device to resend the erroneous data and the data sent after the erroneous data. At the same time, the I3C controller can also delete the cached erroneous data and the data sent after the erroneous data. Therefore, the accuracy of data transmission between the master semiconductor device and the slave semiconductor device can be improved. In addition, when the slave semiconductor device does not receive the data sent by the master semiconductor device for a long time, the I3C controller in the slave semiconductor device can also send an interrupt message to the semiconductor device at the opposite end to indicate that the data can be resent, thereby also improving the stability of data processing.

[0090] In an exemplary embodiment, the DMA module 304 also includes a read processing unit 3048;

[0091] The execution unit 3044 is further configured to send at least part of the fields in the read command to the read processing unit 3048 when the command to be executed in the DMA data is a read command;

[0092] The read processing unit 3048 is used to send at least part of the fields in the read command to the send command buffer in the I3C controller 302; read the corresponding data through the AXI bus according to the read command, and send it to the send data buffer in the I3C controller 302;

[0093] The I3C controller 302 is further used to send the data cached in the send command cache and the send data cache to the semiconductor device at the opposite end.

[0094] like Figure 3 As shown, Figure 3 The read handle in the read handle is the read processing unit 3048. Since the execution process of the read command is more complicated than that of the write command, a separate read processing unit 3048 can be set in the embodiment of the present application to process the read command. Of course, in actual implementation, the read command can also be executed by the execution unit 3044 without setting up a separate read processing unit 3048, and the embodiment of the present application does not make specific limitations on this.

[0095] In the case where the command to be executed in the DMA data is a read command, the execution unit 3044 may send at least some of the fields in the read command to the read processing unit 3048. Among them, at least some of the fields may include the length of the data to be read and the address to be read, which is not specifically limited in the embodiment of the present application. The format of the read command can be specifically referred to Figure 6 . Figure 6 The meaning of each field can be referred to in the previous explanation. addr represents the read address, and data length represents the length of the data to be read.

[0096] In order to inform the semiconductor device at the opposite end of the relevant information of the read data, the read processing unit 3048 can send at least part of the fields in the read command to the send command buffer in the I3C controller 302, such as the read data length. The read processing unit 3048 can read data from the storage space corresponding to the read address through the AXI bus according to the read command, and send it to the send data buffer in the I3C controller 302. The I3C controller 302 can send the data cached in the send command buffer and the send data buffer to the semiconductor device at the opposite end, thereby completing the data reading process.

[0097] In this embodiment, since data transmission between semiconductor devices can be achieved through the I3C bus, data reading can be achieved inside the semiconductor device through the DMA method, thereby solving the problem of incompatibility between low-speed interfaces defined by different manufacturers.

[0098] In an exemplary embodiment, the I3C controller 302 is further configured to store the execution status of the command as response data in the response queue buffer after the command in the DMA data is executed, and send an interrupt notification to the interrupt processing unit 3042;

[0099] The interrupt processing unit 3042 is further used to receive the interrupt notification sent by the I3C controller 302, read the interrupt from the interrupt register in the I3C controller 302; if the read interrupt is a response interrupt corresponding to the command, send the response interrupt corresponding to the command to the execution unit 3044;

[0100] The execution unit 3044 is used to read the execution status of the command from the response queue buffer in the I3C controller 302 after receiving the response interrupt corresponding to the command, and send an interrupt message indicating the command execution error to the I3C controller 302 when the execution status indicates that the command execution error occurs;

[0101] The I3C controller 302 is used to send an interrupt message to a semiconductor device at the opposite end.

[0102] The above process is mainly the corresponding processing process when the command execution error occurs. Specifically, after the command in the DMA data is executed, the I3C controller 302 can obtain the execution status of the command. Among them, for both read and write commands, the execution status of the command can be sent to the I3C controller 302 by the execution unit 3044. After obtaining the execution status of the command, the I3C controller 302 can store the execution status of the command as response data in the response queue buffer, and refer to the interrupt processing mechanism mentioned above for processing the corresponding response data of the request, and the interrupt processing unit 3042 notifies the execution unit 3044 to process the corresponding response interrupt.

[0103] After receiving the response interrupt sent by the interrupt processing unit 3042, the execution unit 3044 can read the execution status of the command from the response queue cache in the I3C controller 302. In the case where the execution status indicates a command execution error, an interrupt message for indicating the command execution error is sent to the I3C controller 302, and the I3C controller 302 sends it to the semiconductor device at the opposite end. For example, if it is a write command execution error, an interrupt message carrying 0x0 can be sent to indicate that there may be a number transmission error in the semiconductor device at the opposite end, and the semiconductor device at the opposite end is instructed to resend the number. If it is a read command execution error, an interrupt message carrying 0x2 can be sent to instruct the semiconductor device at the opposite end to resend the read command.

[0104] In this embodiment, when a command sent by the master semiconductor device is executed incorrectly, the I3C controller in the slave semiconductor device can send an interrupt message to the master semiconductor device to instruct the retransmission number, thereby improving the accuracy of data transmission between the master semiconductor device and the slave semiconductor device, and also improving the stability of data processing.

[0105] In an exemplary embodiment, the I3C controller 302 is also used to reply a negative confirmation message to the semiconductor device at the other end for data sent by the semiconductor device at the other end through the I3C bus, clear the data in the internal cache, and clear the device error status when the command to be executed in the DMA data is a write command and the execution status of the write command indicates an execution error of the write command.

[0106] The above process is mainly the corresponding processing process of the I3C controller 302 in the case of a write command execution error. Specifically, due to the write command execution error, the length of the data to be written carried in the write command may be wrong, which may cause the data cached after the erroneous data in the internal cache to be erroneous, so that the I3C controller 302 can clear the data in the internal cache, such as the data in the receiving data cache and the response queue cache. At the same time, in order to avoid continuing to receive data that cannot be correctly received, the I3C controller 302 can also reply to the semiconductor device at the opposite end with a negative acknowledgment message (NAK) to allow the semiconductor device at the opposite end to temporarily stop sending data.

[0107] Before the I3C controller 302 clears the data in the internal cache, the I3C controller 302 may also update the device status of the slave semiconductor device stored in its own register, that is, CCC_DEVICE_STATUS, to a device error status. After the I3C controller 302 clears the data in the internal cache, the I3C controller 302 may clear the device error status. The master semiconductor device may obtain the device status CCC_DEVICE_STATUS of the slave semiconductor device through the protocol standard command GETSTATUS CCC. After obtaining that the device error status has been cleared, the master semiconductor device may resend the number. Of course, as mentioned in the previous content, by sending an interrupt message carrying 0x1, the master semiconductor device may be instructed to resend the number, and the embodiments of the present application do not specifically limit this.

[0108] In this embodiment, in the case of an execution error of a write command sent by the master semiconductor device, the I3C controller in the slave semiconductor device can send a negative confirmation message to the master semiconductor device to instruct the master semiconductor device to stop sending data, and can clear the data in the internal cache, thereby improving the accuracy of data transmission between the master semiconductor device and the slave semiconductor device. In addition, after clearing the data in the internal cache, the device error state can also be cleared, so that the master semiconductor device restarts sending data after querying that the slave semiconductor device has cleared the device error state, thereby improving the stability of data processing.

[0109] In an exemplary embodiment, the execution unit 3044 is specifically configured to send a cache clearing command to the I3C controller 302 after sending an interrupt message for notifying the peer end of a read command execution error to the I3C controller 302 when the command to be executed in the DMA data is a read command;

[0110] The I3C controller 302 is further configured to receive a cache clearing command, clear the data in the internal cache according to the cache clearing command, and send an interrupt message to the semiconductor device at the opposite end to indicate that the semiconductor device at the opposite end can resend data.

[0111] The above process is mainly the corresponding processing process of the I3C controller 302 in the case of a read command execution error. Specifically, after the I3C controller 302 replies to the data that the main semiconductor device needs to read, it can refer to the previous process and store the corresponding execution status of the read command as the response data in the response queue cache, and then the interrupt processing unit 3042 sends the corresponding response interrupt of the read command to the execution unit 3044. The execution unit 3044 can send an interrupt message to the I3C controller 302 to characterize the read command execution error, and the I3C controller 302 sends the interrupt message to the semiconductor device at the opposite end. In addition to sending an interrupt message to the I3C controller 302, the execution unit 3044 can also send a cache clear command to the I3C controller 302. The I3C controller 302 can clear the data in the internal cache, and can send an interrupt message to the semiconductor device at the opposite end to indicate that the data can be resent, such as an interrupt message carrying 0x1.

[0112] In this embodiment, in the case of an execution error of a read command sent by the master semiconductor device, the I3C controller in the slave semiconductor device can send an interrupt message to the master semiconductor device to instruct the master semiconductor device to stop sending data, and can clear the data in the internal cache, thereby improving the accuracy of data transmission between the master semiconductor device and the slave semiconductor device. In addition, after clearing the data in the internal cache, the master semiconductor device can also be instructed to restart sending data, thereby improving the stability of data processing.

[0113] The previous embodiments mainly illustrate the data transmission process between the master semiconductor device and the slave semiconductor device, as well as the processing process inside the slave semiconductor device. In an exemplary embodiment, a semiconductor system is also provided, comprising at least two semiconductor devices as provided in the previous embodiments; wherein data is transmitted between different semiconductor devices via an I3C bus.

[0114] In an exemplary embodiment, the semiconductor device is a core particle or a chip. That is, the above solution can be used between chips or between core particles, and the embodiment of the present application does not specifically limit this.

[0115] Among them, the method process executed from inside the semiconductor device can be referred to Figure 7 .exist Figure 7In the example, the execution unit in the semiconductor device can wait for the response interrupt. If the response interrupt is received, it can be determined whether it is a response interrupt corresponding to the command execution error. If it is, the branch to the error direction is executed and the interrupt processing is performed; if not, that is, the response interrupt corresponding to the processing request, the execution can continue. Specifically, the command in the processing request can be obtained and verified. If the verification fails, the branch to the error direction can be executed and the interrupt processing can be performed; if not, the execution can continue.

[0116] Commands can be divided into read commands and write commands. If it is a write command, it can be written directly through the AXI bus. If it is a read command, data can be read through the AXI bus, at least part of the fields in the read command can be sent to the tx command queue buffer for storage, and the read data can be sent to the tx data buffer for storage. After executing the command, you can refer to the previous content and further wait for the response interrupt. If it is a response interrupt of a command execution error, you can perform interrupt processing.

[0117] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0118] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: An I3C controller is used to receive processing requests transmitted via the I3C bus and send interrupt notifications to the DMA module; The DMA module is used to read the response data corresponding to the processing request from the response queue cache in the I3C controller when an interrupt notification is received, and read the payload data from the receiving data cache in the I3C controller as DMA data according to the response data; and execute the corresponding command according to the DMA data.

2. The semiconductor device according to claim 1, wherein: The DMA module includes an interrupt processing unit and an execution unit; The interrupt processing unit is used to receive an interrupt notification sent by the I3C controller, read an interrupt from an interrupt register in the I3C controller, and if the read interrupt is a response interrupt corresponding to the processing request, send the response interrupt corresponding to the processing request to the execution unit; The execution unit is configured to, after receiving a response interrupt corresponding to the processing request, read response data corresponding to the processing request from a response queue buffer in the I3C controller, obtain a length of payload data in the processing request according to the response data, and read data from a receive data buffer in the I3C controller according to the payload length as DMA data; The execution unit is also used to execute the commands in the DMA data.

3. The semiconductor device according to claim 2, characterized in that The DMA module also includes: The verification unit is used to verify the DMA data after reading the data from the receiving data buffer in the I3C controller as DMA data; if the verification fails, an interrupt processing flow is triggered; if the verification passes, the execution unit continues to execute subsequent flows.

4. The semiconductor device according to claim 3, characterized in that The verification unit is specifically configured to send an interrupt message indicating a verification error to the I3C controller when the verification fails; The I3C controller is further configured to send the interrupt message to the semiconductor device at the opposite end; according to the command count carried by the interrupt message, delete the data cached after the data corresponding to the command count in the received data cache, and delete the data cached after the response data corresponding to the command count in the response queue cache; The I3C controller is also used to, after sending the interrupt message to the semiconductor device at the other end, if the received data cache has not cached new data for a preset period of time, after clearing the device error state at the local end and restoring to a normal state, send an interrupt message to the semiconductor device at the other end to indicate that the semiconductor device at the other end can resend data.

5. The semiconductor device according to claim 2, wherein: The execution unit is specifically used to write the payload data in the DMA data into the corresponding storage space through the AXI bus according to the write command when the command to be executed in the DMA data is a write command.

6. The semiconductor device according to claim 2, wherein: The DMA module also includes a read processing unit; The execution unit is further configured to send at least part of the fields in the read command to the read processing unit when the command to be executed in the DMA data is a read command; The read processing unit is used to send at least part of the fields in the read command to the send command buffer in the I3C controller; According to the read command, corresponding data is read through the AXI bus and sent to the send data buffer in the I3C controller; The I3C controller is further used to send the data cached in the sending command cache and the sending data cache to the semiconductor device at the opposite end.

7. The semiconductor device according to claim 2, characterized in that The I3C controller is further configured to store the execution status of the command as response data in the response queue buffer after the command in the DMA data is executed, and send an interrupt notification to the interrupt processing unit; The interrupt processing unit is further configured to receive an interrupt notification sent by the I3C controller, read an interrupt from an interrupt register in the I3C controller, and send a response interrupt corresponding to the command to the execution unit when the read interrupt is a response interrupt corresponding to the command; The execution unit is configured to read the execution status of the command from the response queue buffer in the I3C controller after receiving the response interrupt corresponding to the command, and send an interrupt message indicating the command execution error to the I3C controller when the execution status indicates that the command execution error occurs; The I3C controller is used to send the interrupt message to the semiconductor device at the opposite end.

8. The semiconductor device according to claim 7, characterized in that The I3C controller is also used to reply a negative confirmation message to the semiconductor device at the other end for data sent by the semiconductor device at the other end through the I3C bus, clear the data in the internal cache, and clear the device error status when the command to be executed in the DMA data is a write command and the execution status of the write command indicates an execution error of the write command.

9. The semiconductor device according to claim 7, characterized in that The execution unit is specifically configured to send a cache clearing command to the I3C controller after sending an interrupt message for notifying the other end of an execution error of the read command to the I3C controller when the command to be executed in the DMA data is a read command; The I3C controller is further configured to receive the cache clearing command, clear the data in the internal cache according to the cache clearing command, and send an interrupt message to the semiconductor device at the opposite end to indicate that the semiconductor device at the opposite end can resend data.

10. A semiconductor system, characterized in that: The method comprises at least two semiconductor devices according to any one of claims 1 to 9; wherein data are transmitted between different semiconductor devices via an I3C bus.

11. The semiconductor system according to claim 10, characterized in that The semiconductor device is a core particle or a chip.

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