Digital soft start circuit with feedback regulation function

Abstract

The invention discloses a digital soft start circuit with a feedback regulation function, and relates to the field of network security. Four paths of DDQ-APUF circuits of the response processing unit DDQ-APUF unit generate delay deviation on excitation signals input by the excitation unit and carry out quantization output; the response processing unit respectively calculates and outputs single-bit stable response according to the signal values of the response signals; the dynamic reconfigurable unit determines a reconstruction sequence in combination with the high-order excitation signal output by the excitation unit, and performs sequential reconstruction on each path of single-bit stable response; and the DRXOR unit performs exclusive-or calculation on each path of single-bit stable response according to the reconstruction sequence, and outputs an exclusive-or result signal. According to the scheme, a DRXOR-APUF mechanism is introduced, the input sequence responded by an embedded basic APUF unit is dynamically adjusted through a control signal, time-varying dynamic XOR operation is achieved under the condition that a large amount of extra hardware overhead is not generated, and machine learning modeling attack resistance is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of network security, and in particular to an image alignment method, apparatus, device and storage medium. Background Art

[0002] With the increasing severity of information technology and network security issues, traditional cryptographic methods (such as symmetric encryption, asymmetric encryption, etc.) face many incentives when facing hardware attacks, cloning attacks, and physical attacks. For example, hardware tampering, copying, key leakage and other problems will lead to the loss of security of traditional cryptographic systems. The foundation of traditional encryption is the key. If users want to pass authentication or decrypt messages, they must master the key. In this way, the relevant keys must be effectively protected, because this is the premise for protecting information security. In actual operation, non-volatile memory is the main place for designers to store keys, or they will also be stored in random access memory with continuous battery power supply. However, this storage method is not safe and is easily vulnerable to non-invasive attacks, which are also called side channel attacks. Under this circumstance, developing a hardware-based, non-clonable and random security mechanism has become a hot topic in today's research.

[0003] PUF (Physical Unclonable Functions) is a new security mechanism that relies on physical hardware characteristics and has unique advantages. Utilizing the inconsistency of manufacturing processes between gate circuits or wires within integrated circuits, PUF technology uses these random differences to generate an unpredictable response (encrypted signal). However, due to the inherent linear relationship within strong PUF, it is very vulnerable to modeling attacks based on machine learning. Therefore, researching and designing strong PUF circuits with high reliability, low overhead, and strong resistance to machine learning modeling attacks has high academic and engineering value. Summary of the invention

[0004] The embodiment of the present application provides a digital soft start circuit with a feedback regulation function, which is used to solve the problem of low resistance of strong PUF when it is attacked by a machine learning model.

[0005] On the one hand, the present application provides a digital soft start circuit with feedback regulation function, the circuit comprising:

[0006] An excitation unit generates an n-bit excitation signal, and sends the n-bit excitation signal to a delayed differential quantization-physical unclonable function DDQ-APUF unit, and sends the high-bit excitation signal to a dynamically reconfigurable unit;

[0007] The DDQ-APUF unit includes four identical n-order DDQ-APUF circuits, which are respectively used to generate delay deviation for the input n-bit excitation signal and quantize and output the delay deviation;

[0008] A response processing unit receives each response signal quantized and output by the DDQ-APUF unit, and calculates and outputs a single-bit stable response according to the signal value of each response signal;

[0009] The dynamically reconfigurable unit receives the single-bit stable response output by the response processing unit, determines the reconstruction order in combination with the high-bit excitation signal output by the excitation unit, and sequentially reconstructs the single-bit stable responses of each channel;

[0010] The dynamically reconfigurable XOR DRXOR unit receives the sequentially reconstructed single-bit stable responses, performs XOR calculation on the single-bit stable responses of each channel according to the reconstruction order, and outputs the XOR result signal R final .

[0011] Specifically, the DDQ-APUF circuit includes n-stage cascaded crossbar switch blocks, quantization delay blocks, and an arbiter;

[0012] The switch bolck includes two paths, upper and lower paths, and the excitation signals are sequentially input into the n-order switch bolck through the two paths respectively. The two-path excitation signals are sent to different paths according to the switch signal, and a delay deviation is generated;

[0013] The delay block includes two symmetrical delay circuits, each of which includes m delay branches, and different delay branches include different numbers of secondary inverters for quantizing and outputting the delay deviation;

[0014] The two quantized outputs of the delay block are connected to an arbitrator, and the quantized values ​​are output through arbitration by the arbitrator.

[0015] Specifically, the switch bolck includes parallel transmission paths and cross transmission paths between the upstream and downstream ports, and each stage of the switch bolck selects a target transmission path to transmit a signal according to a switch signal;

[0016] In each delay circuit, the S0th delay branch to the S m The number of the second-stage inverters in the delay branches decreases to 0 one by one; the delayed signal generated by each delay branch is input to the corresponding arbiter port.

[0017] Specifically, the upper port and the lower port of the arbiter sequentially generate quantized output signals of 2m-1 bits according to the sequence of signals; and the four DDQ-APUF units respectively output four quantized output signals.

[0018] Specifically, the response processing unit counts the number Nr of high-level bit signals in each quantized output signal based on a counter circuit, and determines a single-bit stable response value based on a normal distribution and the value of Nr.

[0019] Specifically, the quantized output signal contains 13 bits, and the two-segment segmentation method or the three-segment segmentation method is determined according to the value of Nr; when Nr = [0, 3], [6, 7] or [10, 13], the three-segment segmentation method is used to determine the single-bit stable response value; when Nr = 4, 5, 8, 9, the two-segment segmentation method is used to determine the single-bit stable response value;

[0020] Among them, under the three-segment segmentation method, when Nr takes the value of [0,3] or [10,13], the output single-bit stable response value is 0; when Nr takes the value of 6 or 7, the output single-bit stable response value is 1;

[0021] Under the two-segment segmentation method, when Nr is 4 or 5, the output single-bit stable response value is 0; when Nr is 8 or 9, the output single-bit stable response value is 1.

[0022] Specifically, the dynamic reconfigurable unit includes two XOR gates and four dynamic reconfiguration blocks; the four-way single-bit stable response output by the response processing unit outputs a first selection signal Sel0 through a first XOR gate; the first k bits of the excitation signal output a second selection signal Se11 through a second XOR gate;

[0023] The four-way single-bit stable responses are input into four dynamic reconstruction blocks respectively, and the reconstruction order is determined according to the Sel0 and Se11 signals.

[0024] Specifically, the four-way single-bit stable response sequences before reconstruction are R0, R1, R2, and R3;

[0025] When Sel0 Se11=00, O r =R1, R2, R3, R0;

[0026] When Sel0 Se11=01, O r =R2, R0, R3, R1;

[0027] When Sel0 Se11=10, O r =R0, R3, R1, R2;

[0028] When Sel0 Se11=11, O r=R0, R1, R2, R3;

[0029] O r It represents the reconstructed four-way single-bit stable response sequence.

[0030] Specifically, the DRXOR unit includes three XOR gates and a selector; the first two bits of the reconstructed stable response sequence are input to one input end of the selector through the third XOR gate, the second and third bits of the signal are input to the other input end of the selector through the fourth XOR gate, and the fourth bit of the signal is input to the selector end as a select signal;

[0031] The output terminal of the selector and the selection signal are output through the fifth XOR gate to output the result signal R final .

[0032] Specifically, the first 4 bits of the excitation signal are output through the second XOR gate to output the second selection signal Se11. Each delay circuit includes 7 delay branches, and S0 delay branches include 6 cascaded two-stage inverters.

[0033] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: in view of the problem that the strong PUF in the related technical solution has low resistance to modeling attacks based on machine learning, the technical solution introduces a dynamic XOR circuit to achieve strong resistance to machine learning modeling attacks without significantly increasing hardware overhead. In view of the reliability problem of stimulus response, the response division combining the two-segment segmentation method and the three-segment segmentation method in the response processing unit is used to determine the single-bit stable response. Compared with the traditional 4-XOR APUF, the use of the DRXOR unit has stronger nonlinear operations and obtains stronger resistance to modeling attacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural diagram of LFSR-APUF in the related technical solution 1;

[0035] Figure 2 This is a schematic diagram of the structure of the mutual protection between the traditional strong PUF and P-RNG in the related technical solution 2;

[0036] Figure 3 It is a schematic diagram of the structure of FLAM-PUF in the related technical solution three;

[0037] Figure 4 It is a structural schematic diagram of a digital soft start circuit with feedback regulation function provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the structure of the DDQ-APUF circuit is shown;

[0039] Figure 6A schematic diagram showing a DDQ-APUF circuit outputting a single-bit signal;

[0040] Figure 7 A schematic diagram showing the response division of a single-bit stable response value by a two-segment segmentation method and a three-segment segmentation method is shown;

[0041] Figure 8 is a schematic diagram of a local structure of a dynamically reconfigurable unit;

[0042] Fig. 9 This is a comparison chart between DRXOR-APUF and traditional XOR-APUF;

[0043] Fig.10 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0045] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0046] Before describing this application solution, we first introduce the relevant mainstream PUF technologies:

[0047] Technology 1: The technology published in "A Lightweight Authentication Protocol Against Modeling Attacks Based on a Novel LFSR-APUF" (IEEE Internet of Things Journal, 2024). Its technical solution is as follows Figure 1 As shown, the LFSR-APUF can be divided into five parts:

[0048] 1) Challenge Segmentation: This module divides the (n+4)-bit challenge data into two parts, n-bit C1 and 4-bit C2, and sends them to the LFSR and control unit respectively.

[0049] 2) APUF: A traditional APUF (Arbiter PUF) circuit with n-level symmetric delay blocks.

[0050] 3) LFSR: Linear Shift Register, used to confuse external stimuli.

[0051] 4) Control Unit: This unit controls the LFSR according to external stimuli and controls the APUF to generate a response.

[0052] 5) Voting & Dark-bit Masking Unit: Voting and dark-bit masking scheme is used on the proposed APUF to improve reliability.

[0053] The stimulus generator generates (n+4)-bit stimulus C, where n-bit C1 and the remaining 4-bit stimulus C2 are regarded as inputs of the n-stage LFSR unit and the control unit, respectively. The n-stage LFSR unit receives the n-bit C1 generated by the stimulus generator and uses it as the initial value. Then waits for the shift signal SL sent by the control unit. The control unit receives the remaining 4-bit C2 and determines the shift number of the LFSR, and its final output is used as the n-bit obfuscated stimulus CO. Finally, after the control unit sends the shift signal SL a specific number of times, it sends a pulse signal SA, i.e., a rising edge jump signal, to the n-stage APUF. The n-stage APUF receives the n-bit obfuscated stimulus CO generated by the LFSR and the pulse signal SA of the control unit. When the pulse signal is transmitted from the beginning to the last D flip-flop through two delay chains, the APUF generates a response RO. The voting and dark bit masking unit screens out unreliable CRP and outputs a reliable response R. The LFSR-APUF extracts several bits from the external stimulus and applies them to the mapping before the external stimulus obfuscation. The mapping of the obfuscated module is then determined using the real-time specific external stimulus. This is equivalent to changing a fixed mapping into a mapping that varies with external stimuli, changing the obfuscation mechanism from "time-invariant" to "time-varying", thereby greatly reducing the attacker's ability to crack it through modeling attacks.

[0054] In short, the disadvantage of the first technical solution is that the incentive and response confusion strategy cannot effectively defend against white-box attacks.

[0055] Technology 2: Published in "A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER" ​​(IEEE Transactions on Circuits and Systems I: Regular Papers, 2022), its technical solution is as follows Figure 2As shown, the device-specific P-RNG configured by the weak PUF array is designed to generate a unique random key stream (K) that bit-wise encrypts the original response from the traditional strong PUF. Although each manufactured PUF chip has the same schematic and layout, they have a large number of P-RNGs with unique configurations due to the randomness and uniqueness of the weak PUF array. When each authentication task comes, a P-RNG configuration is randomly selected to bit-wise encrypt the original response of the traditional strong PUF. Since the remote authentication server has registered all the responses of the weak PUF array, it can effectively calculate the generated key stream of the selected P-RNG to complete the authentication task. Weak PUF is inherently immune to modeling attacks because each weak PUF unit is independent of other units and has no correlation. At the same time, each generated bit of the P-RNG depends entirely on all previous states and the initial seed. Therefore, there is no mapping relationship between input and output like the stimulus-response process of strong PUF. Ultimately, no input feature information can be used for machine learning or deep learning-based algorithms to train the P-RNG model. However, cryptanalysis can crack the P-RNG because it follows a specific mathematical algorithm to generate random bits. But this can only be done if the adversary obtains a sufficiently long and continuous keystream to perform cryptanalysis. Figure 2 In the structure of , the attacker can only obtain the final encrypted response (R) and cannot derive the key stream without knowing the original response. Therefore, the key stream can also be considered as a bit-by-bit encryption of the original response of the strong PUF. Figure 2 The traditional strong PUF and P-RNG in the proposed method protect each other to enhance the resistance to modeling attacks.

[0056] In short, the disadvantage of the second technique is that the combination of strong PUF and weak PUF will generate a lot of hardware overhead. In addition, since weak PUF is relatively easy to be destroyed, the divide-and-conquer approach will make the weak PUF ineffective.

[0057] Technology 3: Published in "FLAM-PUF: A Response–Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF" (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022), its technical solution is as follows Figure 3 As shown, the APUF combined with the reconfigurable LFSR can form a closed-loop structure for CRP obfuscation. The key features of FLAM-PUF (Lightweight Anti-Machine Learning Attack PUF Based on Response Feedback) are as follows:

[0058] First, FLAM-PUF feeds back a 1-bit response in each cycle to intentionally poison the data of the CRP set for training. It is worth noting that the 1-bit response can randomly update a coefficient of the feedback polynomial, implanting problematic correlations into the model that the attacker wants to build to resist modeling attacks based on machine learning.

[0059] Second, FLAM-PUF exploits a reconfigurable Galois LFSR controlled by n-bit response feedback to expand the original stimulus space of APUF. In this way, FLAM-PUF can combine circuit obfuscation with timing obfuscation, but obtains a significant degree of CRP obfuscation at the expense of a simple loop structure.

[0060] In short, the disadvantage of the third approach is that it significantly reduces data throughput. Moreover, due to its single APUF and limited XOR operations in LFSR, its resistance to white-box attacks is also quite limited.

[0061] In view of the shortcomings of the above-mentioned various technologies, the present application has re-improved and designed a level shift circuit.

[0062] Figure 4 : is a structural diagram of a digital soft start circuit with feedback regulation function provided in an embodiment of the present application, including the following structure:

[0063] The Challenge Unit has a structure similar to that of related technologies and is used to generate an n-bit Challenge and send the Challenge to the Delayed Differential Quantization-Physical Unclonable Function DDQ-APUF unit, while sending the high-bit stimulus signal to the Dynamic Reconfigurable Unit. The high-bit stimulus signal here is selected according to the actual situation, for example, the highest four-bit bit signal C0 to C3 is selected.

[0064] The DDQ-APUF unit includes four identical n-stage DDQ-APUF circuits, namely, n-stage DDQ-APUF0 to DDQ-APUF3 circuits. The four circuits are respectively used to generate delay deviation for the input n-bit Challenge and quantize the delay deviation for output.

[0065] The response processing unit Response Processing Unit is used to receive each response signal (multi-bit signal) quantized and output by the DDQ-APUF unit, and calculate and output a single-bit stable response according to the signal value of each response signal.

[0066] The dynamic reconfigurable unit receives the single-bit stable response output by the response processing unit, determines the reconstruction order in combination with the high-bit excitation signal output by the excitation unit, and sequentially reconstructs the single-bit stable responses of each channel;

[0067] The dynamically reconfigurable XOR DRXOR unit receives the sequentially reconstructed single-bit stable responses, performs XOR calculation on the single-bit stable responses of each channel according to the reconstruction order, and outputs the XOR result signal R final .

[0068] The following focuses on the structural composition and functions of each unit module:

[0069] Figure 5 The schematic diagram of the structure of the DDQ-APUF circuit is shown, and the DDQ-APUF circuit includes an n-stage cascaded cross switch block switch bolck, a quantization delay block delay block, and an arbiter. Each switch bolck includes an upper and lower input and output port, and the upper and lower ports include a parallel transmission path and a cross transmission path. Each stage of the switch bolck selects the target transmission path to transmit the signal according to the switch signal. The n-stage excitation signal passes through the dual-path port in turn, and the dual-path excitation signal is sent to different paths according to the switch signal, and finally an excitation signal with a delay deviation is output. The delay deviation introduced here is generated based on the parallel and path. In theory, the time to pass through the two paths is the same, and the two signals will not generate delays. However, in fact, due to physical factors such as process and resistance, obvious delay deviation will be generated under the action of multi-stage switch blocks.

[0070] After the delay deviation is generated, it needs to be quantized for subsequent judgment and use. At this time, the excitation signal output from the nth-order switch block will be quantized through the delay block.

[0071] The delay block contains two symmetrical delay circuits, which are connected to the upper and lower paths of the switch block respectively. Each delay circuit contains m delay branches, and different delay branches contain different numbers of secondary inverters for quantizing the delay deviation. m The number of secondary inverters in the delay branches decreases to 0 one by one. The delayed signal generated by each delay branch is input to the corresponding arbiter port. The delay branches of the upper and lower paths are in parallel and finally sent to the two input ports of the arbiter, that is, the two quantized outputs of the delay block are connected to the arbiter, and the quantized values ​​are output through arbitration by the arbiter.

[0072] by Figure 5Taking the output of 13-bit quantized response as an example, the Response Processing Unit is 13-1 response processing unit. Each delay circuit contains 7 delay branches, the S0th delay branch contains 6 cascaded two-level inverters, the S5th delay branch contains 1 cascaded two-level inverter, and the S6th delay branch does not contain a two-level inverter; the delayed signal generated by each delay branch is input to the corresponding arbiter port. The purpose of using a two-level inverter here is to ensure that the signal value does not change, otherwise it will affect subsequent judgments. It should be noted that due to the symmetrical structure, the delay branch of the lower path is completely symmetrical with the upper path, and also contains a delay branch without a two-level inverter ( Figure 4 The two delay branches without the secondary inverter are collectively referred to as the S6th delay branch), and the remaining S7 to S 12 The number of secondary inverters in the circuit increases successively.

[0073] The function of the arbitrator is to generate 2m-1 bit quantized output signals in sequence according to the order of the signals from the upper port and the lower port, and the four DDQ-APUF units output four quantized output signals respectively. Taking the 13-bit quantized response output as an example, each quantized output signal outputs R[0]-R

[12] , a total of 13 bits of data.

[0074] Figure 6 The schematic diagram of the DDQ-APUF circuit outputting a single-bit signal is shown, because the switch bolck contains parallel and cross paths, and each switch bolck determines the output or cross output based on the switch signal. For example, C0=1 indicates cross output, C1=0, C2=0, indicates parallel output, and so on. The rising edges of the two paths will generate a Δtv time difference in this process, and then enter the Arbiter. Here, it can be stipulated that if the upper path signal is input into the arbiter first, the Response will output a low level, otherwise it will output a high level. According to this logic, multi-bit signals can be output. As for the quantization step, it is assumed that the upper path is delayed by 10 time units than the lower path, that is, the upper path is 10 units and the lower path is 0 units. In the upper path S0 delay block, it is changed to 16 units, and the S1 delay block is changed to 15 units. Comparing with the lower path 0 unit as the basis, assuming that no jump occurs under the action of 16 units, it means that the delay of the upper path is much larger than that of the lower path. Taking S 12 To illustrate, the delay block is changed to 6 units. Assuming the upper channel has 10 units, the result of the lower channel with 6 units will not jump, which further shows that the delay of the upper channel is much larger than that of the lower channel. This quantification can concretely determine the delay difference between the two channels.

[0075] Furthermore, in order to improve accessibility, the quantized output is sent to the response processing unit, which counts the number Nr of high-level bit signals in each quantized output signal based on the counter circuit, and determines the single-bit stable response value based on the normal distribution and the Nr value. Figure 4 For example, quantization outputs 13-bit R0~R3, and the 13-bit R0~R3 are input into the 13-1 response processing unit, and the 13-1 response processing unit processes them to obtain 1-bit R0~R3.

[0076] For the convenience of description, it is still described as 13-bit. When the quantized output signal contains 13-bit and Nr=4, 5, 8 or 9, the single-bit stable response value is determined based on the two-segment segmentation method; when Nr selects other values, the single-bit stable response value is determined based on the three-segment segmentation method.

[0077] Figure 7 The schematic diagram of the two-segment division method and the three-segment division method for dividing the single-bit stable response value is shown. In the case of 13-bit output, Figure 7 The horizontal axis ΔD of the normal distribution diagram in represents the number of “0” or “1”. The present application uses the Nr value (the number of “1”) for statistics.

[0078] Traditionally, the two-segment segmentation method is used to stabilize the single-bit stable response value, that is, R = 0 (Nr takes the value [0,6]) on the left side of the normal curve, and R = 1 (Nr takes the value [9,13]) on the right side. However, Nr = 6 or 7 in the middle indicates that the number of high and low levels is balanced. This situation occurs when the sum of delay deviations is small, and this small deviation itself will affect the accuracy of the result. Based on this, the application uses the three-segment segmentation method to determine the general direction, and combines the two-segment segmentation method for auxiliary judgment.

[0079] First, determine whether to use the two-segment segmentation method or the three-segment segmentation method based on the value of Nr. When Nr = [0, 3], [6, 7], [10, 13], the three-segment segmentation method is used; when Nr = 4, 5, 8, 9, the two-segment segmentation method is used. Under the three-segment segmentation method, when Nr takes a value in the range of [0, 3] or [10, 13], the output single-bit stable response value is 0 (i.e. Figure 7 When Nr is 6 or 7, the single-bit stable response value is directly output as 1 (in this state, no left-right distinction is made and the default value is 1, i.e. Figure 7 In the two-segment segmentation method, when Nr is 4, 5, 8 or 9, it is determined according to the original two-segment segmentation method. Figure 7 In the figure above, when Nr is 4 or 5, the output R = 0; when Nr is 8 or 9, the output R = 1. The function expression is as follows:

[0080]

[0081] The single-bit stable response R is then fed into the dynamically reconfigurable unit, such as Figure 8 As shown, the dynamic reconfigurable unit includes two XOR gates and four dynamic reconfiguration blocks. The four-way single-bit stable response R0-R4 output by the response processing unit passes through the first XOR gate to output the first selection signal Sel0 ( Figure 4 and Figure 8 The first k bits of the excitation signal pass through the second XOR gate to output the second selection signal Se11 ( Figure 4 and Figure 8 The four-way single-bit stable responses are input into four dynamic reconstruction blocks respectively, and the reconstruction order is determined according to the Sel0 and Se11 signals.

[0082] The setting of the selection signal S1S0 should ensure that the probability of these four combinations is equal, all 25%. Under these conditions, DRXOR-APUF can achieve the best resistance to modeling attacks. Therefore, the relationship between the setting of the selection signal Se11 Sel0 and the response sequence in this paper is as follows:

[0083] Assume that the four-way single-bit stable response sequence before reconstruction is R0, R1, R2 and R3;

[0084] When Se11 Sel0=00, O r =R1, R2, R3, R0;

[0085] When Se11 Sel0=01, O r =R2, R0, R3, R1;

[0086] When Se11 Sel0=10, O r =R0, R3, R1, R2;

[0087] When Se11 Sel0=11, O r =R0, R1, R2, R3;

[0088] O r It represents the reconstructed four-way single-bit stable response sequence.

[0089] In some other embodiments, other reconstruction sequences may be set according to specific functional requirements.

[0090] The DRXOR unit includes three XOR gates and a selector. The first two bits of the reconstructed stable response sequence are input to one input of the selector through the third XOR gate, the second and third bits are input to the other input of the selector through the fourth XOR gate, and the fourth bit is used as the selection signal R. sThe selector input terminal; the selector output terminal R MUX and the selection signal R s The result signal R is output through the fifth XOR gate final , which is expressed as follows:

[0091]

[0092] Compared with the traditional 4-XOR APUF, the dynamic XOR unit in the DRXOR-APUF achieves stronger nonlinear operations. Consider the following scenario: When the 4-APUF responses generated by three different n-bit challenges are (1, 0, 1, 0) and (0, 1, 0, 1), the final response of the traditional 4-XOR APUF is the same. This is because the final response of the traditional 4-XOR APUF depends only on the value of the 4-APUF response (the number of "1"s in the 4-bit response). Each of these two sets of responses has two "1s", resulting in a final XOR response of "0". However, the DRXOR-APUF response is different. According to the structure of the dynamic XOR unit, the final responses corresponding to the two different challenges are "1" and "0", respectively. This shows that DRXOR-APUF is more resistant to modeling attacks.

[0093] refer to Figure 4 From the structure, it can be seen that the structure adopts a level shift circuit design to form a DRXOR-APUF circuit structure. The output calculated by the XOR gate is independent of the input order of the response data of its four basic APUF circuits (i.e., DDQ-APUF units). For the DRXOR-APUF structure, changing the order of the output signals of its four internal APUF units will result in different final responses. Please note that the main hardware overhead of XOR-APUF and DRXOR-APUF lies in their multiple underlying APUF units, so their overall hardware overhead is very similar. Without incurring a lot of additional hardware overhead, DRXOR-APUF can dynamically adjust the input order of the responses from the embedded basic APUF units through control signals to achieve time-varying dynamic XOR operations.

[0094] Fig. 9is a comparison chart between DRXOR-APUF and traditional XOR-APUF. Intuitively, DRXOR-APUF is more resistant to modeling attacks than traditional XOR-APUF. When attacking k-XOR APUF, the machine learning (ML) algorithm can use the correlation between the reliability of stimulus response pairs (CRPs) and the corresponding delay differences to obtain the Pearson correlation coefficient to train the ML model, and then use the divide-and-conquer approach to reduce the complexity introduced by the final XOR gate. However, the effectiveness of the divide-and-conquer approach is mainly based on the assumption that all APUF primitives contribute equally to the reliability of the final response. For the proposed DRXOR-APUF, it is difficult for an attacker to accurately understand the sorting rules of the dynamic reconstruction unit's responses to the four APUFs. Therefore, it is unlikely that the adversary will accurately obtain the model of the dynamic reconstruction unit, which is crucial for calculating the Pearson correlation coefficient.

[0095] Fig.10 The block diagram of a computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or in other ways. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various chips.

[0096] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0097] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0098] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.

[0099] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0100] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, arranged on the front panel of the computer device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the computer device or in a folding design; in other embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device. Even, the display screen can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.

[0101] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0102] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0103] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0104] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A digital soft start circuit with feedback regulation function, characterized in that: The circuit comprises: An excitation unit generates an n-bit excitation signal, and sends the n-bit excitation signal to a delayed differential quantization-physical unclonable function DDQ-APUF unit, and sends the high-bit excitation signal to a dynamically reconfigurable unit; The DDQ-APUF unit includes four identical n-order DDQ-APUF circuits, which are respectively used to generate delay deviation for the input n-bit excitation signal and quantize and output the delay deviation; A response processing unit receives each response signal quantized and output by the DDQ-APUF unit, and calculates and outputs a single-bit stable response according to the signal value of each response signal; The dynamically reconfigurable unit receives the single-bit stable response output by the response processing unit, determines the reconstruction order in combination with the high-bit excitation signal output by the excitation unit, and sequentially reconstructs the single-bit stable responses of each channel; The dynamically reconfigurable XOR DRXOR unit receives the sequentially reconstructed single-bit stable responses, performs XOR calculation on the single-bit stable responses of each channel according to the reconstruction order, and outputs the XOR result signal R final .

2. The digital soft start circuit with feedback regulation function according to claim 1, characterized in that: The DDQ-APUF circuit includes n-stage cascaded crossbar switch blocks, quantization delay blocks, and an arbiter; The switch bolck includes two paths, upper and lower paths, and the excitation signals are sequentially input into the n-order switch bolck through the two paths respectively. The two-path excitation signals are sent to different paths according to the switch signal, and a delay deviation is generated; The delay block includes two symmetrical delay circuits, each of which includes m delay branches, and different delay branches include different numbers of secondary inverters for quantizing and outputting the delay deviation; The two quantized outputs of the delay block are connected to an arbitrator, and the quantized values ​​are output through arbitration by the arbitrator.

3. The digital soft start circuit with feedback regulation function according to claim 2, characterized in that: The switch bolck includes parallel transmission paths and cross transmission paths between the upstream and downstream ports, and each stage of the switch bolck selects a target transmission path to transmit a signal according to a switch signal; In each delay circuit, the S0th delay branch to the S m The number of the second-stage inverters in the delay branches decreases to 0 one by one; the delayed signal generated by each delay branch is input to the corresponding arbiter port.

4. The digital soft start circuit with feedback regulation function according to claim 3, characterized in that: The upper port and the lower port of the arbiter sequentially generate 2m-1 bit quantized output signals according to the sequence of the signals; and the four DDQ-APUF units respectively output four quantized output signals.

5. The digital soft start circuit with feedback regulation function according to any one of claims 1 to 4, characterized in that: The response processing unit counts the number Nr of high-level bit signals in each quantized output signal based on a counter circuit, and determines a single-bit stable response value based on a normal distribution and the value of Nr.

6. The digital soft start circuit with feedback regulation function according to claim 5, characterized in that: The quantized output signal contains 13 bits, and the two-segment segmentation method or the three-segment segmentation method is determined according to the value of Nr; when Nr = [0, 3], [6, 7] or [10, 13], the three-segment segmentation method is used to determine the single-bit stable response value; when Nr = 4, 5, 8, 9, the two-segment segmentation method is used to determine the single-bit stable response value; Among them, under the three-segment division method, when Nr takes the value of [0,3] or [10,13], the output single-bit stable response value is 0; when Nr takes the value of 6 or 7, the output single-bit stable response value is 1; Under the two-segment segmentation method, when Nr is 4 or 5, the output single-bit stable response value is 0; when Nr is 8 or 9, the output single-bit stable response value is 1.

7. The digital soft start circuit with feedback regulation function according to claim 3, characterized in that: The dynamic reconfigurable unit includes two XOR gates and four dynamic reconfiguration blocks; the four-way single-bit stable response output by the response processing unit outputs a first selection signal Sel0 through a first XOR gate; the first k bits of the excitation signal output a second selection signal Se11 through a second XOR gate; The four-way single-bit stable responses are input into four dynamic reconstruction blocks respectively, and the reconstruction order is determined according to the Sel0 and Se11 signals.

8. The digital soft start circuit with feedback regulation function according to claim 7, characterized in that: The four-way single-bit stable response sequence before reconstruction is R0, R1, R2 and R3; When Se11 Sel0=00, O r =R1, R2, R3, R0; When Se11 Sel0=01, O r =R2, R0, R3, R1; When Se11 Sel0=10, O r =R0, R3, R1, R2; When Se11 Sel0=11, O r =R0, R1, R2, R3; O r It represents the reconstructed four-way single-bit stable response sequence.

9. The digital soft start circuit with feedback regulation function according to claim 8, characterized in that: The DRXOR unit includes three XOR gates and a selector; the first two bits of the reconstructed stable response sequence are input to one input end of the selector through the third XOR gate, the second and third bits of the signal are input to the other input end of the selector through the fourth XOR gate, and the fourth bit of the signal is input to the selector end as a select signal; The output terminal of the selector and the selection signal are output through the fifth XOR gate to output the result signal R final .

10. The digital soft start circuit with feedback regulation function according to claim 7, characterized in that: The first 4 bits of the excitation signal are output through the second XOR gate to output the second selection signal Se11. Each delay circuit includes 7 delay branches, and S0 delay branches include 6 cascaded two-stage inverters.

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