FPGA (Field Programmable Gate Array) chip anti-counterfeiting method and FPGA with anti-counterfeiting function
By setting up an anti-counterfeiting ID generator and PUF circuit in the FPGA chip, generating a unique identification code and combining with database verification, the problem of imitation and renovation of FPGA chips is solved, and high-security chip authentication and use monitoring are achieved.
Patent Information
- Application Number
- CN202411934880.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-05-13
AI Technical Summary
The prior art is difficult to effectively identify and prevent the imitation and renovation of FPGA chips, resulting in the damage to the legitimate rights and interests of regular manufacturers and users.
An anti-counterfeiting ID generator is set up in the FPGA chip, and a PUF circuit is used to generate a unique and unpredictable identification code through unique logic resources and wiring resources. It is combined with the FPGA manufacturer database for verification and correlation to ensure the authenticity and usage history of the chip.
By generating unique and unpredictable identification codes, illegal manufacturers are effectively prevented from producing imitation FPGA chips, and let users determine whether they have purchased refurbished chips by themselves, protecting the legitimate interests of FPGA manufacturers and consumers.
Smart Images
Figure CN119989432A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and in particular to a technology for identifying counterfeit and refurbished FPGA chips. Background Art
[0002] FPGA stands for Field Programmable Gate Array, which is a hardware chip that can be repeatedly programmed and configured through EDA software. Users can customize its internal hardware circuits according to their needs to achieve specific functions.
[0003] As FPGA chips are widely used in electronic and communication systems, some unscrupulous merchants have used illegal means such as imitation, recycling and refurbishment to put a batch of counterfeit FPGAs on the market, damaging the legitimate rights and interests of regular FPGA manufacturers and users. Therefore, it is necessary to invent technology that can identify counterfeit FPGAs.
[0004] Physically Unclonable Functions (PUF) is an emerging embedded detection method that mainly generates a specific structure to extract and amplify the random deviations caused by the internal logic and wiring processes of the integrated circuit during the manufacturing process, so as to generate a random response corresponding to the circuit in the integrated circuit, thereby identifying an unpredictable unique identification code for a specific integrated circuit entity. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide an FPGA chip anti-counterfeiting method and an FPGA with anti-counterfeiting function, which can effectively solve the problem of counterfeiting and refurbishment of FPGA.
[0006] The technical solution adopted by the present invention to solve the technical problem is an FPGA chip anti-counterfeiting method, which is characterized by comprising the following steps:
[0007] (1) An anti-counterfeiting ID generator is provided in the FPGA, wherein the anti-counterfeiting ID generator includes a predetermined number of ID generation branches, each of which is composed of two multiplexers, two counters, and a comparator, wherein the output ends of the two counters are respectively connected to the two input ends of the comparator, the input end of each counter is connected to the output end of a multiplexer, and the output end of the multiplexer is connected to the selection signal end;
[0008] (2) The FPGA manufacturer database records the anti-counterfeiting ID generated by the anti-counterfeiting ID generator;
[0009] (3) The user reads the FPGA's anti-counterfeiting ID and uploads it to the FPGA manufacturer's database for query and verification; if the FPGA manufacturer's database does not find the uploaded anti-counterfeiting ID, the user is prompted that the verification has failed.
[0010] Furthermore, the method further comprises the following steps:
[0011] (4) When a user develops an FPGA, the user information and the FPGA anti-counterfeiting ID are submitted to the FPGA manufacturer's database. The FPGA manufacturer's database performs an association check. If the FPGA anti-counterfeiting ID is not associated with other users, the user is associated with the FPGA anti-counterfeiting ID. If the FPGA anti-counterfeiting ID is already associated with other users, the user is prompted that the FPGA has been associated with other users.
[0012] The present invention also provides an FPGA with an anti-counterfeiting function, characterized in that it includes an anti-counterfeiting ID generator, which includes a predetermined number of ID generation branches, each ID generation branch is composed of two multiplexers, two counters and a comparator, the output ends of the two counters are respectively connected to the two input ends of the comparator, the input end of each counter is connected to the output end of a multiplexer, and the output end of the multiplexer is connected to the selection signal end.
[0013] The present invention utilizes the unique logic resources and wiring resources in the FPGA chip to realize the PUF circuit. The result of the PUF circuit operation is used as the identification code of the FPGA chip. Due to the random deviation of the process during the manufacturing process of the FPGA chip, the result of the PUF circuit operation in each FPGA chip is different and unique, and the result is not predictable, so it has extremely high security. The present invention can effectively prevent illegal manufacturers from producing and manufacturing counterfeit FPGAs for normal use, and at the same time allow users to judge whether they have purchased refurbished FPGA chips, effectively protecting the legitimate interests of FPGA manufacturers and consumers. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 This is a schematic diagram of a 16-to-1 multiplexer.
[0015] Figure 2 This is a schematic diagram of a self-looping multiplexer.
[0016] Figure 3 This is the circuit structure diagram of the ID generation branch.
[0017] Figure 4 This is a schematic diagram of the process of generating an ID.
[0018] Figure 5 This is a circuit diagram of a cyclic multiplexer PUF that generates a 32-bit ID.
[0019] Figure 6 It is a design block diagram of the FPGA chip anti-counterfeiting system of the present invention.
[0020] Figure 7 It is a flow chart of the present invention for verifying authenticity and recording the number of connections. DETAILED DESCRIPTION
[0021] A multiplexer is an electronic device that selects one signal from multiple input signals for output. It can select one output from multiple input signals according to the value of the control signal to achieve data selection. Figure 1 The figure shows a 16-to-1 multiplexer, which selects one of the 16 input signals as the output value according to the 4-bit SEL signal value.
[0022] like Figure 2 As shown, the present invention formulates the input value of a 16-bit multiplexer as follows Figure 2 The multiplexer will start to cycle through the output values from 0000 to 1111.
[0023] like Figure 3 As shown in the figure, the circuit for generating a bit ID has two cyclic multiplexers A and B, two counters and a comparator. The process of generating a bit ID is as follows: Figure 4 As shown, for the two circular multiplexers A and B, since the circular multiplexers are composed of LUT and MUX devices in the FPGA, the speed of completing a cycle depends on the propagation delay of these devices. The random errors in the process cause differences between each LUT device and MUX device. Therefore, there is a difference in the time it takes for the two circular multiplexers A and B to complete a cycle from 0000 to 1111. For any multiplexer, each time a cycle is completed, the corresponding counter counts once. After a period of time T, the values of the two counters are compared to obtain a comparison result. As shown Figure 4 In the example, the A multiplexer cycles faster than the B multiplexer, so after T time, the counter value of A is 2500, and the counter value of B is 2000. We can set the counter value of A to be greater than the counter value of B to get an ID value of 1, otherwise the counter value of A is less than the counter value of B, and the ID value is 0.
[0024] like Figure 5 , using 32 groups Figure 3 The circuit can obtain a cyclic multiplexer PUF circuit that generates 32-bit ID information. The circuit can amplify random errors in the process, which are almost unpredictable. The output response of the circuit is actually a PUF response to the chip.
[0025] Anti-counterfeiting system block diagram Figure 6 As shown in the figure, it consists of FPGA development EDA software and a server. The process of verifying authenticity and recording the number of connections is as follows Figure 7 The process of building and running the anti-counterfeiting system is as follows:
[0026] 1. Develop the following for FPGA chip: Figure 5 The PUF circuit is compiled in the FPGA development EDA software to obtain the BITSTREAM file of the PUF circuit.
[0027] 2. For genuine FPGA chips manufactured, a specific BITSTREAM file is burned and programmed into them before leaving the factory, so that the FPGA chip generates a specific PUF circuit, which will generate an ID data unique to the FPGA chip.
[0028] 3. The manufacturer will create a database with the ID data of each genuine FPGA chip and encrypt and store it in the server.
[0029] 4. When a user uses a certain model of FPGA chip from an FPGA manufacturer for programming and development, while using EDA software to connect to the FPGA chip, the EDA development software will burn a BITSTREAM file consistent with step 2 into it, and after reading the ID generated by the PUF circuit formed inside the FPGA chip, it will be encrypted and sent to the server.
[0030] 5. After receiving the encrypted information transmitted by the EDA development software, the manufacturer's server decrypts the encrypted ID and compares it with the known FPGA chips in the database to obtain the authenticity information. If it is detected to be the ID of the manufacturer's genuine FPGA chip, the connection count of the FPGA chip record of the ID is increased by one. Finally, the authenticity information and connection count are sent to the EDA software.
[0031] 6. After verifying the authenticity of the FPGA chip, if it is a counterfeit chip, the EDA software will immediately disconnect from the FPGA chip to prevent the counterfeit chip from being used. If it is a genuine chip, the EDA software will maintain the connection with the FPGA chip and display the number of times the FPGA chip with the ID has been used to the FPGA chip user, allowing the user to confirm whether they have purchased a refurbished FPGA chip.
[0032] 7. After completing the above steps, the user can use the FPGA chip for programming and development without disconnecting the FPGA chip. At the same time, the user can know whether his FPGA chip is a second-hand or refurbished chip.
Claims
1. FPGA chip anti-counterfeiting method, characterized in that: The steps include: (1) An anti-counterfeiting ID generator is provided in the FPGA, wherein the anti-counterfeiting ID generator includes a predetermined number of ID generation branches, each of which is composed of two multiplexers, two counters, and a comparator, wherein the output ends of the two counters are respectively connected to the two input ends of the comparator, the input end of each counter is connected to the output end of a multiplexer, and the output end of the multiplexer is connected to the selection signal end; (2) The FPGA manufacturer database records the anti-counterfeiting ID generated by the anti-counterfeiting ID generator; (3) The user reads the FPGA's anti-counterfeiting ID and uploads it to the FPGA manufacturer's database for query and verification; if the FPGA manufacturer's database does not find the uploaded anti-counterfeiting ID, the user is prompted that the verification has failed.
2. The FPGA chip anti-counterfeiting method according to claim 1, characterized in that: The following steps are also included: (4) When a user develops an FPGA, the user information and the FPGA anti-counterfeiting ID are submitted to the FPGA manufacturer's database. The FPGA manufacturer's database performs an association check. If the FPGA anti-counterfeiting ID is not associated with other users, the user is associated with the FPGA anti-counterfeiting ID. If the FPGA anti-counterfeiting ID is already associated with other users, the user is prompted that the FPGA has been associated with other users.
3. FPGA with anti-counterfeiting function, characterized in that: It includes an anti-counterfeiting ID generator, which includes a predetermined number of ID generation branches, each of which is composed of two multiplexers, two counters and a comparator. The output ends of the two counters are respectively connected to the two input ends of the comparator, and the input end of each counter is connected to the output end of a multiplexer, and the output end of the multiplexer is connected to the selection signal end.