Circuits and methods for power management

Abstract

The invention relates to a circuit and a method for power management. A circuit includes a memory circuit, and a power management circuit having a first circuit. The first circuit is configured to control supply of a first supply voltage to the memory circuit according to a first power mode control signal in response to a first state of a first power management control signal and a first state of a second power management control signal. The first circuit is further configured to store a state of the first power mode control signal in response to a second state of the first power management control signal, and control supply of the first supply voltage to the memory circuit in accordance with the stored state of the first power mode control signal. The power management circuit is configured to disable a portion of the first circuit in response to a second state of the second power management control signal.

Description

Technical Field

[0001] The present disclosure relates to circuits and methods for power management. Background Art

[0002] Integrated circuits (ICs) are widely used in various digital devices and / or applications in different fields. As ICs become more complex, various power modes or schemes are considered to reduce power consumption while ensuring proper functionality of the designed IC. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor circuit is provided, comprising: a memory circuit; and a power management circuit, comprising a first circuit, wherein the first circuit is configured to: in response to a first state of a first power management control signal and a first state of a second power management control signal, control the supply of a first supply voltage to the memory circuit according to a first power mode control signal, in response to a second state of the first power management control signal, store the state of the first power mode control signal, and control the supply of the first supply voltage to the memory circuit according to the stored state of the first power mode control signal, and the power management circuit is configured to: in response to the second state of the second power management control signal, disable a portion of the first circuit.

[0004] According to one embodiment of the present disclosure, a power management circuit is provided, comprising: a first input terminal configured to receive a first power management control signal; a second input terminal configured to receive a second power management control signal; a third input terminal configured to receive a first power mode control signal; a first level shifter circuit having: an input terminal coupled to the third input terminal, and an output terminal; a latch circuit having: a control input terminal coupled to the first input terminal, a data input terminal coupled to the output terminal of the first level shifter circuit, and an output terminal configured to control the supply of a first supply voltage to an external circuit; a second level shifter circuit having: an input terminal coupled to the third input terminal, and an output terminal configured to control the supply of a second supply voltage to the external circuit; and a first header circuit, the first header circuit having a control input terminal coupled to the second input terminal, the first header circuit being coupled between: a first node of a first power supply voltage, and at least one of the first level shifter circuit or the second level shifter circuit.

[0005] According to one embodiment of the present disclosure, a power management method is provided, comprising: through a power management circuit: outputting a first supply voltage to a memory array of a memory circuit, the first supply voltage corresponding to a first power supply voltage, and outputting a second supply voltage to a peripheral circuit of the memory circuit, the second supply voltage corresponding to a second power supply voltage, the second power supply voltage being different from the first power supply voltage; stopping outputting the second supply voltage in response to at least one of a first power mode control signal or a second power mode control signal; storing a state of the first power mode control signal; and after storing the state of the first power mode control signal, disconnecting the first power supply voltage from at least one circuit of the power management circuit; and shutting down the second power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1 is a schematic block diagram of a circuit according to some embodiments.

[0008] Figure 2 is a table including various power modes for circuits according to some embodiments.

[0009] Figure 3 is a schematic circuit diagram of a power management circuit according to some embodiments.

[0010] FIG. 4A to FIG. 4B is a schematic timing diagram of various operations of the circuit according to some embodiments.

[0011] FIG. 5A to FIG. 5D is a schematic circuit diagram of various circuits according to some embodiments.

[0012] Figure 6 is a flow chart of a method according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides different embodiments or examples for realizing the features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and not limitations. Other components, materials, values, steps, arrangements, etc. are considered. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. (One or more) source / drain may refer to a source or drain individually or collectively, depending on the context.

[0014] Additionally, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0015] The IC includes several power domains of different power supply voltages for different circuits and / or different purposes. For example, the memory circuit in one or more embodiments includes a memory array and a peripheral circuit. The memory array is located in a first power domain of a first power supply voltage (e.g., VDDM) or powered by a first power domain of a first power supply voltage (e.g., VDDM). The peripheral circuit is at least partially located in a second power domain of a second power supply voltage (e.g., VDD) or powered by a second power domain of a second power supply voltage (e.g., VDD), which is different from VDDM. The first power domain of VDDM is sometimes referred to as the VDDM power domain, and the second power domain of VDD is sometimes referred to as the VDD power domain. In at least one embodiment, the memory circuit includes independent VDDM and VDD power supplies or power sources, each configured to provide a corresponding VDDM or VDD independently of each other. This configuration is sometimes referred to as an array dual rail (ADR) configuration.

[0016] In some embodiments, VDD is turned off in a state sometimes referred to as VDD buck-off to reduce power consumption. When the power mode control signal is in the VDD power domain and may become unavailable when VDD is turned off, the state of the power mode control signal is stored in the VDDM power domain in response to a first power management control signal, and the power mode of the memory circuit during VDD buck is controlled based on the stored state of the power mode control signal. In at least one embodiment, the interface circuit between the VDD power domain and the VDDM power domain is disabled in response to a second power management control signal. According to some embodiments, the reason is to isolate the VDDM power domain that remains on from the VDD power domain that is to be turned off. In one or more embodiments, power consumption is reduced in a more flexible arrangement than other methods.

[0017] Figure 1 is a schematic block diagram of a circuit 100 according to some embodiments. Figure 1 In the example configuration of , circuit 100 is a memory device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits other than the memory device for other functions. Circuit configurations other than memory devices are within the scope of various embodiments.

[0018] Circuit 100 includes a memory circuit 110 and a power management circuit 120. The power management circuit 120 is configured to control the supply of various supply voltages to the memory circuit 110 in multiple power modes. The memory circuit 110 is an example of an external circuit that is configured to operate with and receive a supply voltage provided by the power management circuit 120. External circuits other than memory circuits are within the scope of various embodiments. Examples of such external circuits include, but are not limited to, radio frequency or cellular transceiver circuits, global positioning system (GPS) receiver circuits, network interface circuits, central processing units (CPUs), multi-core CPUs, neural processing units (NPUs), graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, voice processing units, and the like. Various embodiments in which the external circuit is a memory circuit are described in detail herein. In some embodiments, the power management circuit 120 is configured to control the supply of various supply voltages to external circuits other than the memory circuit in a manner similar to that described in detail herein.

[0019] Memory circuit 110 includes memory array 102 and peripheral circuit 103. In some embodiments, except for memory array 102 and any other memory arrays included in memory circuit 110, the remaining circuits and components of memory circuit 110 are collectively referred to as memory controller or peripheral circuit 103.

[0020] The memory array 102 includes a plurality of memory cells MC, a plurality of word lines (WL0 to WLn), and a plurality of bit lines (BL0 to BLm), where n and m are natural numbers. In the memory array 102, the memory cells MC are arranged into a plurality of columns corresponding to the bit lines and a plurality of rows corresponding to the word lines. The columns and rows in the memory array are sometimes referred to as memory columns and memory rows. Each memory cell MC is electrically coupled to a corresponding word line and a corresponding bit line. In some embodiments, each memory cell MC is electrically coupled to more than one word line and / or more than one bit line. The word line is configured to transmit the address of the memory cell MC to be accessed in a read operation or a write operation. The word line is sometimes referred to as an "address line". The bit line is configured to transmit data read from the memory cell MC or data to be written into the memory cell MC, which is identified by the address on the corresponding word line. The bit line is sometimes referred to as a "data line". Various numbers of word lines and / or bit lines in the memory array 102 are within the scope of various embodiments. In some embodiments, the memory cell MC includes a static random access memory (SRAM) cell. In some embodiments, the memory cell MC includes a dynamic random access memory (DRAM) cell, other volatile RAM memory cells, etc. In some embodiments, the memory cell MC includes a resistive random access memory (RRAM) cell, a ferroelectric RAM (F-RAM) cell, a magnetoresistive RAM (MRAM) cell, a phase change memory (PCM) cell, other non-volatile RAM memory cells, etc.

[0021] In some embodiments, the peripheral circuit 103 includes one or more circuits, including but not limited to a row decoder, a column decoder, a precharge circuit, a selection circuit, a sense amplifier, a word line driver circuit, a bit line driver circuit, an address latch, a pulse generator, a timing circuit, a control circuit, a clock generator and / or a driver, an input / output (I / O) circuit for exchanging data, addresses, clocks and / or controls with an external device, etc. For example, the row decoder is configured to decode the row address of one or more memory cells MC selected to be accessed, and the word line driver circuit is configured to supply a set of access voltages to (one or more) selected word lines, and (one or more) selected word lines correspond to the decoded row address. The column decoder is configured to decode the column address of one or more memory cells MC selected to be accessed, and the selection circuit is configured to electrically couple one or more of the bit line driver circuit and / or the sense amplifier to (one or more) selected bit lines, and (one or more) selected bit lines correspond to the decoded column address. The bit line driver circuit or the sense amplifier is configured to supply a voltage to the selected bit line or detect a voltage on the selected bit line in a read operation or a write operation. The described memory circuit configurations are examples, and other memory circuit configurations are within the scope of the various embodiments.

[0022] The memory circuit 110 includes an ADR configuration having a first power domain of a first power supply voltage and a second power domain of a second power supply voltage, the first power supply voltage being different from the second power supply voltage. For example, as described herein, the first power supply voltage is VDDM, the first power domain is the VDDM power domain, the second power supply voltage is VDD, and the second power domain is the VDD power domain. VDDM and VDD are positive power supply voltages that are different from each other. For example, VDDM has a first voltage swing between its low level and high level. VDD has a second voltage swing between its low level and high level, and the second voltage swing is different from the first voltage swing. A signal in the VDDM power domain has a voltage swing corresponding to the first voltage swing. A signal in the VDD power domain has a voltage swing corresponding to the second voltage swing and is different from the voltage swing of a signal in the VDDM power domain. In at least one embodiment, VDDM is higher than VDD. In some embodiments, VDDM is lower than VDD. Whether VDDM is higher or lower than VDD is a design consideration, depending on various factors, including but not limited to application, power requirements, speed requirements, etc.

[0023] The memory array 102 is located in the VDDM power domain or powered by the VDDM power domain. The peripheral circuit 103 includes a peripheral circuit 104 and a peripheral circuit 106. The peripheral circuit 104 is located in the VDDM power domain or powered by the VDDM power domain, and the peripheral circuit 106 is located in the VDD power domain or powered by the VDD power domain.

[0024] In some embodiments, being in or powered by the VDDM power domain means that the memory cell MC and various circuits and / or components of the peripheral circuit 104 are electrically coupled to the VDDM power supply, and / or one or more VDDM power rails, and / or one or more nodes having a voltage VDDM. In other words, the operating voltage of the memory cell MC and the peripheral circuit 104 is VDDM. Signals transmitted between the memory cell MC and various circuits and / or components of the peripheral circuit 104 are also in the VDDM power domain.

[0025] In some embodiments, being in or powered by the VDD power domain means that the various circuits and / or components of the peripheral circuit 106 are electrically coupled to the VDD power supply, and / or one or more VDD power rails, and / or one or more nodes having a voltage VDD. In other words, the operating voltage of the various circuits and / or components of the peripheral circuit 106 is VDD. In at least one embodiment, the precharge circuit, sense amplifier, and I / O circuit are in the VDD power domain. Signals transmitted between the various circuits and / or components of the peripheral circuit 106 are also in the VDD power domain. Figure 1 In the configuration of , examples of I / O signals transmitted and / or received by the I / O circuit include a clock signal (CLK), an address (Addr) of a memory cell to be accessed, input data (Data) to be written to the accessed memory cell, output data (Qout) read from the accessed memory cell, a chip enable (CEB) signal, and a write enable (WEB) signal. The CEB signal is a signal for enabling or disabling the memory circuit 110. The signal WEB is a signal for enabling or disabling writing to one or more memory cells MC. The I / O signals are in the VDD power domain. Other I / O signals are within the scope of various embodiments.

[0026] In some embodiments, some circuits and / or components of the peripheral circuit 103 are configured to interface between the VDDM power domain and the VDD power domain. Such circuits and / or components are sometimes referred to as interface circuits. The interface circuit is configured to receive a signal in one of the VDDM power domain and the VDD power domain, and output a corresponding signal in the other of the VDDM power domain and the VDD power domain. An example interface circuit is a word line driver circuit (WLD) 107. WLD 107 is configured to output an access voltage of the VDDM power domain to one or more word lines corresponding to a decoded row address in response to a control signal in the VDD power domain, for accessing one or more selected memory cells MC. Another example interface circuit is a level shifter circuit, such as an input level shifter (IDR) 108, or various level shifter circuits in one or more power management circuits described herein. The level shifter circuit is configured to receive a signal in one of the VDDM power domain and the VDD power domain and generate a level shifted signal corresponding to the received signal in the other of the VDDM power domain and the VDD power domain. The illustration of WLD 107 and IDR 108 in peripheral circuit 104 is an example. In some embodiments, one or more interface circuits are configured at the interface between memory array 102 and peripheral circuit 106 and / or at the interface between peripheral circuit 104 and peripheral circuit 106.

[0027] The power management circuit 120 is configured to control the supply of various supply voltages to the memory array 102. For example, the power management circuit 120 is configured to control the supply of a first supply voltage VDDAI corresponding to VDDM to the memory array 102, the supply of a second supply voltage VDDMHD corresponding to VDDM to the peripheral circuit 104, and the supply of a third supply voltage VDDHD corresponding to VDD to the peripheral circuit 106. In some embodiments, controlling the supply of the supply voltage means that the power management circuit 120 is configured to controllably provide (output) the supply voltage to the memory circuit 110, or stop providing (outputting) the supply voltage to the memory circuit 110 in response to one or more control signals at one or more corresponding input terminals of the power management circuit 120.

[0028] Specifically, the power management circuit 120 includes a first input terminal 121 to a fourth input terminal 124, and is configured to receive control signals AOCLHENB, AOCISO, SD, and SLP respectively. The signal AOCLHENB and the signal AOCISO are located in the VDDM power domain. The signal SD and the signal SLP are located in the VDD power domain. In at least one embodiment, the signal AOCLHENB is referred to as a first power management control signal, the signal AOCISO is referred to as a second power management control signal, the signal SD is referred to as a first power mode control signal, and the signal SLP is referred to as a second power mode control signal. In some embodiments, one or more of the signals AOCLHENB, the signal AOCISO, the signal SD, and the signal SLP are generated by an external circuit outside the circuit 100. In some embodiments, one or more of the signals AOCLHENB, the signal AOCISO, the signal SD, and the signal SLP are generated by a control circuit included in the circuit 100.

[0029] The power management circuit 120 also includes a first level shifter circuit 130, a second level shifter circuit 140, a latch circuit 150, an inverter 132, an inverter 134, an inverter 144, an inverter 152, an inverter 154, a header circuit 136, a header circuit 146, a header circuit 162, a header circuit 164, a header circuit 166, a switch 138, a switch 148, and a logic circuit 142. The header circuit 162, the header circuit 164, and the header circuit 166 are sometimes referred to as output header circuits. Figure 1In the example configuration of , each of header circuits 136, 146, 162, 164, 166 includes a P-type transistor, for example, a P-channel metal oxide semiconductor (PMOS) transistor, and each of switches 138, 148 includes an N-type transistor, for example, an N-channel metal oxide semiconductor (NMOS) transistor. Other configurations of header circuits and / or switches are within the scope of various embodiments. Other transistor configurations are within the scope of various embodiments. Example transistor configurations include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFET / NFETs), FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc. In some embodiments, a P-type transistor may be replaced by one or more N-type transistors, and vice versa. For simplicity, header circuit 136, header circuit 146, header circuit 162, header circuit 164, header circuit 166 are sometimes referred to herein as PMOS transistor 136, PMOS transistor 146, PMOS transistor 162, PMOS transistor 164, PMOS transistor 166, and switch 138, switch 148 are sometimes referred to herein as NMOS transistor 138, NMOS transistor 148.

[0030] Inverters 132, 134, 144, logic circuit 142, and header circuit 166 are located in the VDD power domain, as indicated by the label "VDD" in the figure. Latch circuit 150, inverter 152, 154, and header circuits 136, 146, 162, 164 are located in the VDDM power domain, as indicated by the label "VDDM" in the figure. Switches 138, 148 are also in the VDDM power domain. Level shifter circuits 130, 140 are interface circuits between the VDD power domain and the VDDM power domain.

[0031] The level shifter circuit 130 has an input terminal 131 and an output terminal 133, and the input terminal 131 is coupled to the input terminal 123. Figure 1 In the example configuration in FIG. 1 , the input 131 of the level shifter circuit 130 is coupled to the input 123 of the power management circuit 120 via inverters 132 and 134 .

[0032] The inverter 132 has an input terminal and an output terminal, the input terminal is coupled to the input terminal 123 to receive the signal SD, and the inverter 132 is configured to output the inverse signal SDB of the signal SD at the output terminal. The inverter 134 has an input terminal and an output terminal, the input terminal is coupled to the output terminal of the inverter 132 to receive the signal SDB, and the inverter 134 is configured to output the inverse signal SDBB ​​of the signal SDB at the output terminal. In at least one embodiment, the signal SDBB ​​is the same as the signal SD except for the time delay. The signal SDB and the signal SDBB ​​are located in the VDD power domain. The output terminals of the inverters 132 and 134 are coupled to the input terminal 131 of the level shifter circuit 130.

[0033] The described inverters 132 and 134 are examples of a first connection circuit that is coupled between the input 123 of the power management circuit 120 and the input 131 of the level shifter circuit 130. Other configurations of the first connection circuit are within the scope of various embodiments. For example, in at least one embodiment, the first connection circuit is a conductor. In some embodiments, one or more of the inverters 132 and 134 are omitted or included in the level shifter circuit 130.

[0034] The level shifter circuit 130 is configured to receive VDDM through a header circuit 136. Specifically, a header circuit or PMOS transistor 136 is coupled between a first node 137 of VDDM and the level shifter circuit 130 and has a control input coupled to the input 122. For example, a first source / drain of the PMOS transistor 136 is coupled to the node 137, a second source / drain of the PMOS transistor 136 is coupled to the level shifter circuit 130, and a gate of the PMOS transistor 136 is coupled to the input 122 to receive the signal AOCISO.

[0035] A switch or NMOS transistor 138 is coupled between a reference node of a reference voltage (e.g., ground voltage VSS) and an output 133 of the level shifter circuit 130, and has a control input coupled to the input 122. For example, a first source / drain of the NMOS transistor 138 is coupled to the output 133 of the level shifter circuit 130, a second source / drain of the NMOS transistor 138 is coupled to VSS, and a gate of the NMOS transistor 138 is coupled to the input 122 to receive the signal AOCISO.

[0036] In response to a first state (e.g., a low level) of the signal AOCISO, the PMOS transistor 136 is turned on and the NMOS transistor 138 is turned off. The turned-on PMOS transistor 136 connects VDDM to the level shifter circuit 130 to power or enable the level shifter circuit 130. The level shifter circuit 130 is configured to generate a first level-shifted signal SD1 when enabled or powered, which is a level-shifted version of the signal SDB. The signal SD1 is in the VDDM power domain and corresponds to the signal SD.

[0037] In response to the second state (e.g., high level) of the signal AOCISO, the PMOS transistor 136 is turned off and the NMOS transistor 138 is turned on. The turned-off PMOS transistor 136 disconnects VDDM from the level shifter circuit 130, thereby disabling the level shifter circuit 130. The turned-on NMOS transistor 138 connects the output terminal 133 of the disabled level shifter circuit 130 to VSS and sets the signal SD1 to a predetermined voltage, namely, VSS.

[0038] The level shifter circuit 140 has an input terminal 141 and an output terminal 143, and the input terminal 141 is coupled to the input terminal 123. Figure 1 In the example configuration in FIG. 1 , an input terminal 141 of the level shifter circuit 140 is coupled to input terminals 123 and 124 of the power management circuit 120 via a logic circuit 142 and an inverter 144 .

[0039] The logic circuit 142 has an input terminal and an output terminal, the input terminal is respectively coupled to the input terminal 123 and the input terminal 124 of the power management circuit 120 to receive the signal SD and the signal SLP, and the logic circuit 142 is configured to output the combined power mode control signal SDSLP at the output terminal. In at least one embodiment, the logic circuit 142 is configured to generate the signal SDSLP by performing a logic operation on the signal SD and the signal SLP. In the example configuration described herein, the logic circuit 142 is configured to perform a NOR operation on the signal SD and the signal SLP to generate the signal SDSLP. Other logic operations (e.g., OR, AND, NAND, XOR, etc.) are within the scope of various embodiments. The inverter 144 has an input terminal and an output terminal, the input terminal is coupled to the output terminal of the logic circuit 142 to receive the signal SDSLP, and the inverter 144 is configured to output the inverted signal SDSLPB of the signal SDSLP at the output terminal. The signal SDSLP and the signal SDSLPB are located in the VDD power domain. The outputs of logic circuit 142 and inverter 144 are coupled to input 141 of level shifter circuit 140 .

[0040] The described logic circuit 142 and inverter 144 are examples of a second connection circuit that is coupled between input 123, input 124 of the power management circuit 120 and input 141 of the level shifter circuit 140. Other configurations of the second connection circuit are within the scope of various embodiments. In some embodiments, the inverter 144 is omitted or included in the level shifter circuit 140.

[0041] The level shifter circuit 140 is configured to receive VDDM through a header circuit 146. Specifically, a header circuit or PMOS transistor 146 is coupled between a second node 147 of VDDM and the level shifter circuit 140 and has a control input coupled to the input 122. For example, a first source / drain of the PMOS transistor 146 is coupled to the node 147, a second source / drain of the PMOS transistor 146 is coupled to the level shifter circuit 140, and a gate of the PMOS transistor 146 is coupled to the input 122 to receive the signal AOCISO.

[0042] A switch or NMOS transistor 148 is coupled between a reference node of a reference voltage (e.g., ground voltage VSS) and an output 143 of the level shifter circuit 140, and has a control input coupled to the input 122. For example, a first source / drain of the NMOS transistor 148 is coupled to the output 143 of the level shifter circuit 140, a second source / drain of the NMOS transistor 148 is coupled to VSS, and a gate of the NMOS transistor 148 is coupled to the input 122 to receive the signal AOCISO.

[0043] In response to a first state (e.g., a low level) of the signal AOCISO, the PMOS transistor 146 is turned on and the NMOS transistor 148 is turned off. The turned-on PMOS transistor 146 connects VDDM to the level shifter circuit 140 to power or enable the level shifter circuit 140. The level shifter circuit 140 is configured to generate a second level-shifted signal SDSLP1 when enabled or powered, which is a level-shifted version of the signal SDSLP. The signal SDSLP1 is in the VDDM power domain and corresponds to the signal SD and the signal SLP.

[0044] In response to the second state (e.g., high level) of the signal AOCISO, the PMOS transistor 146 is turned off and the NMOS transistor 148 is turned on. The turned-off PMOS transistor 146 disconnects VDDM from the level shifter circuit 140, thereby disabling the level shifter circuit 140. The turned-on NMOS transistor 148 connects the output terminal 143 of the disabled level shifter circuit 140 to VSS and sets the signal SDSLP1 to a predetermined voltage, namely, VSS.

[0045] The latch circuit 150 has a control input C, a data input D, and an output Q. The control input C is coupled to the input 121 of the power management circuit 120 to receive the signal AOCLHENB, and the data input D is coupled to the output 133 of the level shifter circuit 130 to receive the signal SD1. The control input C is sometimes referred to as the clock input of the latch circuit 150. The latch circuit 150 is configured to generate a latch output signal SD2 at the output Q based on the signal SD1 at the data input D and the signal AOCLHENB at the control input C.

[0046] Specifically, in response to a first state (e.g., a low level) of the signal AOCLHENB at the control input terminal C, the latch circuit 150 is configured to be in a “transparent” or pass-through state and pass the signal SD1 at the data input terminal D to the output terminal Q. For example, in the “transparent” state, the signal SD2 at the output terminal Q of the latch circuit 150 corresponds to the signal SD1 at the data input terminal D.

[0047] In response to the second state (e.g., high level) of the signal AOCLHENB at the control input terminal C, the latch circuit 150 is configured to be in a latched state, and is configured to latch or store the state of the signal SD1 when the signal AOCLHENB switches from the first state to the second state. Because the signal SD1 corresponds to the signal SD, the latch circuit 150 is configured to latch or store the state of the signal SD. In the latched state, the latch circuit 150 is configured to output the signal SD2 based on the latched or stored state of the signal SD until the signal AOCLHENB switches from the second state back to the first state.

[0048] The inverter 152 has an input terminal and an output terminal, the input terminal is coupled to the output terminal Q of the latch circuit 150 to receive the signal SD2, and the inverter 152 is configured to output an inverted signal CS1 of the signal SD2 at the output terminal. In some embodiments, the inverter 152 is omitted.

[0049] The header circuit or PMOS transistor 162 has a gate coupled to the output of the inverter 152 to receive the signal CS1. A first source / drain of the PMOS transistor 162 is coupled to a node 163 of VDDM. A second source / drain of the PMOS transistor 162 is coupled to the memory array 102 to controllably supply VDDM as a supply voltage VDDA1 to the memory array 102 in response to the signal CS1. For example, in response to a low level of the signal CS1, the PMOS transistor 162 is turned on and outputs the supply voltage VDDA1 to the memory array 102. In response to a high level of the signal CS1, the PMOS transistor 162 is turned off and stops outputting the supply voltage VDDA1 to the memory array 102.

[0050] The inverter 154 has an input terminal coupled to the output terminal 143 of the level shifter circuit 140 to receive the signal SDSLP1 and an output terminal configured to output an inverted signal CS2 of the signal SDSLP1. In some embodiments, the inverter 154 is omitted.

[0051] The header circuit or PMOS transistor 164 has a gate coupled to the output of the inverter 154 to receive the signal CS2. A first source / drain of the PMOS transistor 164 is coupled to a node 165 of VDDM. In at least one embodiment, the node 165 is the same node as the node 163, or belongs to the same power rail as the node 163. A second source / drain of the PMOS transistor 164 is coupled to the peripheral circuit 104 to controllably supply VDDM as a supply voltage VDDMHD to the peripheral circuit 104 in response to the signal CS2. For example, in response to a low level of the signal CS2, the PMOS transistor 164 is turned on and outputs the supply voltage VDDMHD to the peripheral circuit 104. In response to a high level of the signal CS2, the PMOS transistor 164 is turned off and stops outputting the supply voltage VDDMHD to the peripheral circuit 104.

[0052] The header circuit or PMOS transistor 166 has a gate coupled to the output of the inverter 144 to receive the signal CS3. Figure 1In the example configuration in FIG. 1 , the signal CS3 is the signal SDSLPB. The first source / drain of the PMOS transistor 166 is coupled to the node 167 of VDD. The second source / drain of the PMOS transistor 166 is coupled to the peripheral circuit 106 to controllably supply VDD as the supply voltage VDDHD to the peripheral circuit 106 in response to the signal CS3. For example, in response to a low level of the signal CS3 or the signal SDSLPB, the PMOS transistor 166 is turned on and outputs the supply voltage VDDHD to the peripheral circuit 106. In response to a high level of the signal CS3 or the signal SDSLPB, the PMOS transistor 166 is turned off and stops outputting the supply voltage VDDHD to the peripheral circuit 106.

[0053] The level shifter circuit 130 and the latch circuit 150 are examples of a first circuit configured to control the supply of the supply voltage VDDAI to the memory circuit 110 according to the signal AOCLHENB, the signal AOCISO, and the signal SD. As described herein, in response to a first state (e.g., a low level) of the signal AOCLHENB and a first state (e.g., a low level) of the signal AOCISO, the first circuit is configured to control the supply of the supply voltage VDDA1 to the memory circuit 110 according to the signal SD, which is level-shifted by the enabled level shifter circuit 130, then passes through the latch circuit 150 in a “transparent” state, and is supplied as the signal CS1 to turn on or off the PMOS transistor 162. For example, in response to the first state (e.g., a low level) of the signal SD, the signal CS1 has a corresponding low level, the PMOS transistor 162 is turned on, and the supply voltage VDDA1 is output to the memory circuit 110. In response to the second state (eg, high level) of the signal SD, the signal CS1 has a corresponding high level, the PMOS transistor 162 is turned off, and stops outputting the supply voltage VDDA1 to the memory circuit 110 .

[0054] In response to the second state (e.g., high level) of the signal AOCLHENB, the first circuit is configured to store the state of the signal SD in the latch circuit 150 in the latched state, and output the signal SD2 based on the stored state of the signal SD to turn on or off the PMOS transistor 162, thereby controlling the supply of the power supply voltage VDDAI according to the stored state of the signal SD. For example, in response to the stored state of the signal SD being the first state (e.g., low level), the signal CS1 has a corresponding low level, the PMOS transistor 162 is turned on, and the supply voltage VDDA1 is output to the memory circuit 110. In response to the stored state of the signal SD being the second state (e.g., high level), the signal CS1 has a corresponding high level, the PMOS transistor 162 is turned off, and the supply voltage VDDA1 is stopped from being output to the memory circuit 110.

[0055] In response to the second state (e.g., high level) of the signal AOCISO, a portion of the first circuit is disabled. For example, as described herein, the level shifter circuit 130 is disabled in response to the high level of the signal AOCISO, which turns off the PMOS transistor 136 and disconnects the VDDM from the level shifter circuit 130. The NMOS transistor 138 is turned on in response to the high level of the signal AOCISO, and sets the signal SD1 to a predetermined voltage VSS. As a result, in one or more embodiments, the VDDM power domain is isolated from the VDD power domain at the disabled level shifter circuit 130, and the signal in the VDD power domain does not affect the signal in the VDDM power domain.

[0056] The level shifter circuit 140 is an example of a second circuit configured to control the supply of the supply voltage VDDMHD to the memory circuit 110 according to the signal AOCISO, the signal SD, and the signal SLP. As described herein, in response to the first state (e.g., low level) of the signal AOCISO, the level shifter circuit 140 is enabled, and is configured to control the supply of the supply voltage VDDMHD to the memory circuit 110 according to the signal SDSLP. The signal SDSLP corresponds to a combination of the signal SD and the signal SLP, is level-shifted by the enabled level shifter circuit 140, and is supplied as the signal CS2 to turn on or off the PMOS transistor 164. For example, in response to the signal SD and the signal SLP having a first state (e.g., low level), the signal SDSLP has a corresponding high level, the signal SDSLP1 has a corresponding high level, and the signal CS2 has a corresponding low level, which turns on the PMOS transistor 164 to output the supply voltage VDDMHD to the memory circuit 110. In response to either signal SD and signal SLP having a second state (e.g., a high level), signal SDSLP has a corresponding low level, signal SDSLP1 has a corresponding low level, and signal CS2 has a corresponding high level, which turns off PMOS transistor 164 to stop outputting supply voltage VDDMHD to memory circuit 110.

[0057] In response to the second state (e.g., high level) of the signal AOCISO, the level shifter circuit 140 is disabled due to the high level of the signal AOCISO, which turns off the PMOS transistor 146 and disconnects the VDDM from the level shifter circuit 140. The NMOS transistor 148 is turned on in response to the high level of the signal AOCISO, and sets the signal SDSLP1 to a predetermined voltage VSS. As a result, in one or more embodiments, the VDDM power domain is isolated from the VDD power domain at the disabled level shifter circuit 140, and the signal in the VDD power domain does not affect the signal in the VDDM power domain.

[0058] The logic circuit 142 is an example of a third circuit configured to control the supply of the supply voltage VDDHD to the memory circuit 110 according to the signal SD and the signal SLP. For example, in response to the signal SD and the signal SLP having a first state (e.g., a low level), the signal SDSLP has a corresponding high level, and the signal CS3 has a corresponding low level, which turns on the PMOS transistor 166 to output the supply voltage VDDHD to the memory circuit 110. In response to either the signal SD or the signal SLP having a second state (e.g., a high level), the signal SDSLP has a corresponding low level, and the signal CS3 has a corresponding high level, which turns off the PMOS transistor 166 to stop outputting the supply voltage VDDHD to the memory circuit 110.

[0059] Signal SD and signal SLP correspond to a first power mode and a second power mode of memory circuit 110. Both the first power mode and the second power mode are reduced power modes in which the power consumption of memory circuit 110 is reduced compared to the normal operation mode. The second power mode corresponding to signal SLP has higher power consumption than the first power mode corresponding to signal SD. For example, the first power mode corresponding to signal SD is a shutdown mode in which the entire memory circuit 110 (including memory array 102) is powered off, and the second power mode corresponding to signal SLP is a sleep mode in which the peripheral circuit 103 is powered off, but the memory array 102 remains powered on for retaining data in the memory cells of the memory array 102. Other power modes are within the scope of various embodiments. In some embodiments, one or more of signal SD and signal SLP are generated to cause memory circuit 110 to enter a corresponding reduced power mode for reducing the power consumption of memory circuit 110.

[0060] In some embodiments, disabling interface circuits (e.g., level shifter circuit 130 and / or level shifter circuit 140) according to signal AOCISO further reduces power consumption of circuit 100. In at least one embodiment, both interface circuits in power management circuit 120 and interface circuits in memory circuit 110 are configured to be disabled according to signal AOCISO to further reduce power consumption. In some embodiments, all interface circuits in circuit 100 are configured to be disabled according to signal AOCISO.

[0061] In some embodiments, power consumption can be further reduced by turning off VDD in a state referred to herein as VDD buck. For example, circuit 100 includes a header circuit 180 configured to controllably turn off VDD. Figure 1In an example configuration, header circuit 180 includes a PMOS transistor. Other header circuit configurations are within the scope of various embodiments. Figure 1 In the example configuration of FIG. 1 , PMOS transistor 180 is external to power management circuit 120 and memory circuit 110 . In at least one embodiment, PMOS transistor 180 is included in power management circuit 120 or memory circuit 110 .

[0062] The PMOS transistor 180 has a first source / drain, a second source / drain, and a gate, the first source / drain being coupled to the power rail 181, the second source / drain being coupled to the power rail 183, and the gate being configured to receive the control signal VDD_off. The power rail 181 is configured to receive the power supply voltage True VDD (TVDD). The power rail 181 is sometimes referred to as the “TVDD power rail”. In some embodiments, TVDD is a positive voltage generated by an external voltage source external to the circuit 100. In some embodiments, TVDD is generated by an internal voltage source included in the circuit 100. When the PMOS transistor 180 is turned on by the low level of the control signal VDD_off, the TVDD on the TVDD power rail 181 is provided as the VDD on the power rail 183 through the turned-on PMOS transistor 180. The power rail 183 is sometimes referred to as the “VDD power rail”. In some embodiments, the VDD on the power rail 183 is referred to as a virtual VDD. When the PMOS transistor 180 is turned off by the high level of the control signal VDD_off, the VDD power rail 183 is disconnected from the TVDD power rail 181, and VDD is turned off for the circuit to be coupled to the VDD power rail 183. In some embodiments, when the PMOS transistor 180 is turned off, the VDD power rail 183 is floating. In some embodiments, the control signal VDD_off is generated by an external circuit outside the circuit 100. In some embodiments, the control signal VDD_off is generated by a control circuit included in the circuit 100. In some embodiments, the VDD power rail 183 is configured to supply VDD to one or more circuits in the circuits of the VDD power domain described herein, including but not limited to the inverter 132, the inverter 134, the inverter 144, the logic circuit 142, the header circuit 166, the circuits in the peripheral circuit 106, etc. During the VDD step-down period, when the PMOS transistor 180 is turned off, the circuits of the VDD power domain coupled to the VDD power rail 183 are powered off, further reducing the power consumption of the circuit 100.

[0063] Figure 2 2 is a table 200 including various power modes of circuit 100 according to some embodiments. The logic values ​​and on or off states of the various supply voltages in table 200 are examples. Other logic values ​​and / or on or off states are within the scope of various embodiments.

[0064] The power mode corresponding to the first row of table 200 is the normal operation mode 201. Specifically, in response to the signal AOCISO, the signal SD, the signal SLP, and the signal AOCLHENB all having a low level corresponding to logic "0", the power management circuit 120 is configured to output the power voltage VDDHD, the power voltage VDDMHD, and the power voltage VDDAI to the peripheral circuit 106, the peripheral circuit 104, and the memory array 102, respectively, so that the memory circuit 110 operates in normal operation.

[0065] The power mode corresponding to the second row of the table 200 is the sleep mode 202. Compared with the normal operation mode 201, each of the signal SLP and the signal AOCLHENB in ​​the sleep mode 202 has a high level corresponding to logic "1". The high level of the signal SLP causes the signal SDSLP to have a low level, resulting in the signal CS2, the signal CS3 having a high level. As a result, the supply voltage VDDHD, the supply voltage VDDMHD are turned off, and the peripheral circuit 103 is powered off. The high level of the signal AOCLHENB causes the latch circuit 150 to enter a latched state and store the state of the signal SD, that is, a low level. As a result, the signal CS1 has a low level, and the supply voltage VDDA1 is maintained to be supplied to the memory array 102 for data retention.

[0066] The power mode corresponding to the third row of the table 200 is the shutdown mode 203. Compared with the normal operation mode 201, the signal SD in the shutdown mode 203 has a high level corresponding to logic "1". The high level of the signal SD causes the signal SDSLP to have a low level, resulting in the signal CS2, the signal CS3 having a high level. As a result, the supply voltage VDDHD, the supply voltage VDDMHD are turned off, and the peripheral circuit 103 is powered off. The high level of the signal SD further causes the signal SD1 and the signal SD2 to have a low level, resulting in the signal CS1 having a high level. As a result, the supply voltage VDDA1 is turned off, and the memory array 102 is powered off. In the shutdown mode 203, the levels of the signal SLP and the signal AOCLHENB are irrelevant (or in a "don't care" state), and are schematically shown as "-" in the table 200.

[0067] The power mode corresponding to the fourth row of Table 200 is another shutdown mode 204 in the power management state. The power management state corresponds to the signal AOCISO, which has a high level corresponding to logic "1". Similar to the shutdown mode 203, the signal SD in the other shutdown mode 204 has a high level, causing the memory circuit 110 to be powered off. The high level of the signal AOCISO disables the level shifter circuit 130 and the level shifter circuit 140 to further reduce power consumption compared to the shutdown mode 203. The VDD that is turned on in the normal operating mode 201, the sleep mode 202 and the shutdown mode 203 (wherein the signal AOCISO has a low level) can be further turned off. The ability to shut down VDD or enter VDD step-down in another shutdown mode 204 is schematically represented as "on / off" in Table 200. In Figure 2 In the example configuration in , the signal SLP has a low level. In at least one embodiment, the signal SLP is in a "don't care" state.

[0068] The power mode corresponding to the fifth row of table 200 is another sleep mode 205 in the power management state, corresponding to the signal AOCISO having a high level. The signal SD, the signal SLP, and the signal AOCLHENB are the same as in the sleep mode 202. As discussed for the other shutdown mode 204, because the level shifter circuit 130, the level shifter circuit 140 is disabled and / or the ability to shut down VDD is turned off, the other sleep mode 205 further reduces power consumption compared to the sleep mode 202. Figure 2 In the example configuration in , VDDM is always on in all power modes (power mode 201 to power mode 205).

[0069] Figure 3 is a schematic circuit diagram of a power management circuit 300 according to some embodiments. In some embodiments, the power management circuit 300 corresponds to the power management circuit 120. For simplicity, the same reference numerals are used to represent Figure 1 , Figure 3 The corresponding components in .

[0070] The power management circuit 300 includes a level shifter circuit 330 , a level shifter circuit 340 , a NOR gate 342 , and a latch circuit 350 , which corresponds to the level shifter circuit 130 , the level shifter circuit 140 , the logic circuit 142 , and the latch circuit 150 .

[0071] The level shifter circuit 330 includes a first inverter, a second inverter, and a pair of PMOS transistors P3 and P4. The first inverter is configured by a PMOS transistor P1 and an NMOS transistor N1, and the second inverter is configured by a PMOS transistor P2 and an NMOS transistor N2. The input terminal of the first inverter corresponds to the input terminal 131 and is configured by the gates of the transistors P1 and N1. The gates of the transistors P1 and N1 are electrically coupled together and electrically coupled to the input terminal of the inverter 134. The output terminal of the first inverter is configured by the first source / drain of the transistors P1 and N1. The first source / drain of the transistors P1 and N1 are electrically coupled together and electrically coupled to the gate of the transistor P4. The second source / drain of the transistor P1 is electrically coupled to the first source / drain of the transistor P3. The second source / drain of the transistor N1 is electrically coupled to VSS. The input terminal of the second inverter also corresponds to the input terminal 131, and is configured by the gates of transistors P2 and N2, which are electrically coupled together and electrically coupled to the output terminal of the inverter 134. The output terminal of the second inverter corresponds to the output terminal 133, and is configured by the first source / drain of transistors P2 and N2, which are electrically coupled together and electrically coupled to the gate of transistor P3. The second source / drain of transistor P2 is electrically coupled to the first source / drain of transistor P4. The second source / drain of transistor N2 is electrically coupled to VSS. The second source / drain of transistors P3 and P4 is electrically coupled to VDDM.

[0072] In operation, when the signal SDB has a high level, the transistor P1 is turned off, the transistor N1 is turned on, and the output terminal of the inverter 134 is at a low level. The output terminal of the first inverter is electrically coupled to VSS through the turned-on transistor N1 and turns on the transistor P4. The low level at the output terminal of the inverter 134 turns on the transistor P3 and turns off the transistor N2. VDDM is applied to the gate of the transistor P3 through the turned-on transistor P2 and the transistor P4 and turns off the transistor P3. The signal SD1 has a high level. When the signal SDB has a low level, the transistor P1 is turned on, the transistor N1 is turned off, and the output terminal of the inverter 134 is at a high level. The high level at the output terminal of the inverter 134 turns off the transistor P3 and turns on the transistor N2. The gate of the transistor P3 is electrically coupled to VSS through the turned-on transistor N2, the transistor P3 is turned on, and the signal SD1 has a low level. VDDM is applied to the gate of transistor P4 through transistor P1 and transistor P3 which are turned on and turns off transistor P4.

[0073] The level shifter circuit 340 has a configuration similar to the level shifter circuit 330, and a detailed description of the level shifter circuit 340 is omitted. The described level shifter circuit configuration is an example. Other level shifter circuit configurations are within the scope of various embodiments. For example, the level shifter circuit in one or more embodiments has an inverter configuration, such as for Figure 5D As described.

[0074] The latch circuit 350 includes PMOS transistors (transistors P5 to P8), NMOS transistors (transistors N5 to N8), and inverters INV1 and INV2. Transistors P5 and N5 are coupled to a third inverter having an input terminal (which corresponds to the data input terminal of the latch circuit 350), and are configured by the gates of transistors P5 and N5, the gates of which are electrically coupled together and electrically coupled to the output terminal of the level shifter circuit 330 to receive the signal SD1. The output terminal of the third inverter is configured by the first source / drain of transistors P5 and N5, and the first source / drain of transistors P5 and N5 are electrically coupled together to the first source / drain of transistors P6 and N6, and the input terminal of inverter INV2. The second source / drain of transistor P5 is electrically coupled to the first source / drain of transistor P7. The gate of transistor P7 corresponds to the control input of latch circuit 350, and is coupled to input 121 to receive signal AOCLHENB, and is coupled to the input of inverter INV1 and the gate of transistor N6. The second source / drain of transistor P7 is coupled to VDDM. The second source / drain of transistor N5 is electrically coupled to the first source / drain of transistor N7. The gate of transistor N7 is coupled to the output of inverter INV1 and the gate of transistor P6. The second source / drain of transistor N7 is coupled to VSS. The second source / drain of transistor P6 is electrically coupled to the first source / drain of transistor P8. The gate of transistor P8 corresponds to the output of latch circuit 350, and is coupled to the output of inverter INV2 and the gate of transistor N8. The second source / drain of transistor P8 is coupled to VDDM. The second source / drain of transistor N6 is electrically coupled to the first source / drain of transistor N8. A second source / drain of transistor N8 is coupled to VSS.

[0075] In operation, when the signal AOCLHENB has a low level, the transistor P7 and the transistor N7 are turned on, and the transistor P6 and the transistor N6 are turned off. VDDM and VSS are applied to the third inverter configured by the transistor P5 and the transistor N5 through the turned-on transistor P7 and the transistor N7. The signal SDL at the output of the third inverter is an inverted signal of the signal SD1. The signal SDL is further inverted by the inverter INV2 and is output from the latch circuit 350 as the signal SD2. In other words, the latch circuit 350 is in a "transparent" state and passes the signal SD1 at the data input terminal to the output terminal as the signal SD2.

[0076] When the signal AOCLHENB has a high level, the transistor P7 and the transistor N7 are turned off, and the transistor P6 and the transistor N6 are turned on. The turned-off transistors P7 and N7 isolate the signal SDL from the signal SD1. As a result, the signal SDL corresponds to the latched previous state of the signal SD. For example, when the previous state of the signal SD is a low level (corresponding to the supply voltage VDDA1 to be maintained), the signal SD1 has a corresponding high level, and the signal SDL has a corresponding low level. When the signal AOCLHENB is switched to a high level, the low level of the signal SDL is latched. The latched low level of the signal SDL causes the signal SD2 to have a corresponding high level, which turns off the transistor P8 and turns on the transistor N8. VSS is applied through the turned-on transistors N8 and N6, and the latched low level of the signal SDL is maintained. As a result, the high level of the signal SD2 is also maintained, and the output of the supply voltage VDDA1 is maintained. When signal AOCLHENB switches back to a low level, latch circuit 350 returns to the “transparent” state, and signals SDL and SD2 are updated based on the current state of signal SD.

[0077] For another example, when the previous state of the signal SD is a high level (corresponding to stopping the output of the supply voltage VDDAI), the signal SD1 has a corresponding low level, and the signal SDL has a corresponding high level. When the signal AOCLHENB switches to a high level, the high level of the signal SDL is latched. The latched high level of the signal SDL causes the signal SD2 to have a corresponding low level, which turns on the transistor P8 and turns off the transistor N8. VDDM is applied through the turned-on transistors P8 and P6, and maintains the latched high level of the signal SDL. As a result, the low level of the signal SD2 is also maintained, and the output of the supply voltage VDDA1 is stopped. When the signal AOCLHENB switches back to a low level, the latch circuit 350 returns to the "transparent" state, and the signals SDL and SD2 are updated based on the current state of the signal SD.

[0078] Other operations and / or power modes of the power management circuit 300 are similar to those for Figure 1 to Figure 2 In at least one embodiment, one or more advantages described herein may be achieved by the power management circuit 300 and / or a circuit (eg, a memory circuit) including the power management circuit 300.

[0079] Figure 4A 4 is a schematic timing diagram of operation 400A of the circuit according to some embodiments. In some embodiments, operation 400A described herein is performed in circuit 100 to cause memory circuit 110 to enter shutdown mode and wake up from shutdown mode. In at least one embodiment, power management circuit 300 is used in a similar manner to perform operation 400A. Figures 1 to 3 and Figure 4A For example, the clock signal CLK and the output data Qout in FIG4 correspond to Figure 1 4 corresponds to one or more inputs input / output by the peripheral circuit 103, for example, WEB, CEB, Addr, data, etc.

[0080] In operation 400A, before time t0, VDD is turned on, and each of the signal AOCISO, the signal AOCLHENB, and the signal SD has a low level. Each of the other input pins, the clock signal CLK, the output data Qout, and the signal SLP has a low level or a high level, or switches between a low level and a high level, as schematically shown by the mark "L / H". In some embodiments, the signal SLP has a low level corresponding to the normal operation mode 201. In at least one embodiment, the signal SLP has a high level corresponding to the sleep mode 202.

[0081] At time t0 , the signal SD switches from a low level to a high level, causing the circuit to enter a shutdown mode from a normal operation mode 201 or from a sleep mode 202 .

[0082] At time t1, after a minimum time delay tsdx from time t0, in response to the high level of signal SD, the supply voltage VDDHD and / or the supply voltage VDDMHD are stopped from being output to the memory circuit 110. When the peripheral circuit 103 is partially or fully powered off, the signal levels of other input pins and the clock signal CLK are in a "don't care" state, such as Figure 4ASchematically illustrated by the symbol "X". For example, a signal in the "don't care" state may have a low level or a high level, or may be floating. Because the signal SD has a high level, the signal level of the signal SLP is in the "don't care" state. After a minimum time delay tsdqh from time t0, the signal level of the output data Qout becomes a "don't care" state. After a minimum time delay tsdq from time t0, the output data Qout stops switching. In at least one embodiment, because the output data Qout stops switching, power consumption is reduced. In some embodiments, the output data Qout stops switching by setting the output pin of the peripheral circuit 103 corresponding to the output data Qout to a predetermined voltage (e.g., VSS). In some embodiments, the output pin is set to a predetermined voltage by a switch in a manner similar to that described for switches 138 and 148.

[0083] At time t2, after a minimum time delay tsd2aoclhenb from time t0 (i.e., the time from SD to AOCLHENB), the signal AOCLHENB switches from a low level to a high level. When the signal AOCLHENB switches from a low level to a high level, the state of the signal SD is latched in the latch circuit 150. As described herein, Figure 4A In the example configuration in , the latched state of the signal SD is a high level, which stops the supply voltage VDDAI from being output to the memory array 102 .

[0084] At time t3, after a minimum time delay of taoc1henb2aociso from time t2 (i.e., the time from AOCLHENB to AOCISO), the signal AOCISO switches from a low level to a high level. The high level of the signal AOCISO disables the level shifter circuit 130 and the level shifter circuit 140 in the power management circuit 120. In some embodiments, in response to the high level of the signal AOCISO, all interface circuits in the circuit 100 are disabled. Figure 4AAs can be seen in FIG. 1 , because time t3 arrives after time t2, the state of signal SD is switched to high-level signal AOCLHENB and latched in latch circuit 150 before level shifter circuit 130 and level shifter circuit 140 are disabled by signal AOCISO switched to high level. In some embodiments, tsd2aoclhenb corresponds to or is determined based on the setup time of latch circuit 150, and / or tsd2aoclhenb2aocis corresponds to or is determined based on the hold time of latch circuit 150. The setup time is the predetermined minimum amount of time required to stabilize the signal at the data input terminal before an active clock edge (e.g., the rising edge of signal AOCLHENB switching from low level to high level). The hold time is the predetermined minimum amount of time required to stabilize the signal at the data input terminal after the active clock edge. After signal AOCISO reaches a high level, another shutdown mode 204 is implemented. VDD can now be turned off to further reduce power consumption.

[0085] If targeted Figure 1 As described, at time t4, after a minimum time delay of 1 t from time t3, VDD is turned off, for example in response to a high level of signal VDD_off. Circuit 100 enters a VDD step-down state. During the VDD step-down state, the signal level of signal SD becomes a "don't care" state.

[0086] At time t5, VDD is turned on, and circuit 100 leaves the VDD step-down state, for example in response to the low level of signal VDD_off. In some embodiments, VDD is automatically turned on or off by an external circuit outside circuit 100 or a control circuit of circuit 100.

[0087] At time t6, after a minimum time delay txaociso from time t5, the signal AOCISO switches from a high level to a low level to start waking up from the shutdown mode. The level shifter circuits 130, 140 are enabled in response to the low level of the signal AOCISO.

[0088] At time t7, after a minimum time delay taocisosaochenb from time t6 (i.e., the time from AOCISO to AOCLHENB), the signal AOCLHENB switches from a high level to a low level. In response to the low level of the signal AOCLHENB, the latch circuit 150 switches from the latched state to the "transparent" state. The minimum duration taoclhenbh of the high level of the signal AOCLHENB between time t2 and time t7 is longer than the minimum duration taocisoh of the high level of the signal AOCISO between time t3 and time t6.

[0089] At time t8, the signal SLP is set to a low level to prepare for normal operation. The signal levels of the other input pins and the clock signal CLK exit the "don't care" state.

[0090] At time t9, after a minimum time delay taoclhenb2sd (i.e., time from AOCLHENB to SD) from time t7 and / or a minimum time delay txsd from time t8, the signal SD switches from a high level to a low level. In response to the low level of the signal SD, the supply voltages VDDAI, VDDMHD, and VDDHD are output to the memory circuit 110 to enter normal operation. The output data Qout starts switching again.

[0091] At time t10 , after a minimum time delay tsdwk from time t9 , circuit 100 is allowed to enter sleep mode if necessary.

[0092] At time t11 , after a minimum time delay tsdwk2clk from time t9 , the clock signal CLK resumes switching after being set to a low level during tsdwk2clk.

[0093] At time t12 , after a minimum time delay tsd1 from time t9 , the circuit 100 is allowed to enter shutdown mode if necessary.

[0094] Figure 4B 4 is a schematic timing diagram of operation 400B of the circuit according to some embodiments. In some embodiments, operation 400B described herein is performed in circuit 100 to cause memory circuit 110 to enter shutdown mode and wake up from sleep mode. In at least one embodiment, power management circuit 300 is used in a similar manner to perform operation 400B. Figures 1 to 3 , Figure 4A and Figure 4B The corresponding signal in .

[0095] In operation 400B, time t19 corresponds to the time when the clock signal CLK resumes switching after waking up from a previous shutdown or sleep mode. For example, time t19 corresponds to time t11 in operation 400A.

[0096] Between time t19 and time t20, VDD is turned on, and each of the signal AOCISO, the signal AOCLHENB, the signal SD, and the signal SLP has a low level, corresponding to the normal operation mode 201. Each of the other input pins, the clock signal CLK, and the output data Qout has a low level or a high level, or switches between a low level and a high level.

[0097] At time t20 , the signal SLP switches from a low level to a high level, causing the circuit to enter the sleep mode from the normal operation mode 201 .

[0098] At time t21, after a minimum time delay tslpx from time t20, in response to the high level of the signal SLP, the supply voltage VDDHD and / or the supply voltage VDDMHD are stopped from being output to the memory circuit 110. When the peripheral circuit 103 is partially or completely powered off, the signal levels of other input pins and the clock signal CLK are in a "don't care" state. After time t20qh, the signal level of the output data Qout becomes a "don't care" state. After a minimum time delay tslpq from time t02, the output data Qout stops switching. In at least one embodiment, because the output data Qout stops switching, power consumption is reduced. In some embodiments, the output data Qout stops switching by setting the output pin of the peripheral circuit 103 corresponding to the output data Qout to a predetermined voltage (e.g., VSS).

[0099] At time t22, after a minimum time delay tslp2aoclhenb (i.e., the time from SLP to AOCLHENB) from time t20, the signal AOCLHENB switches from a low level to a high level. When the signal AOCLHENB switches from a low level to a high level, the state of the signal SD (i.e., a low level) is latched in the latch circuit 150. As described herein, the latched state of the signal SD is a low level, which ensures that the supply voltage VDDAI is output to the memory array 102.

[0100] At time t23, after a minimum time delay of taoc1 and b2aociso from time t22, signal AOCISO switches from a low level to a high level. The high level of signal AOCISO disables level shifter circuits 130 and 140 in power management circuit 120. In some embodiments, in response to the high level of signal AOCISO, all interface circuits in circuit 100 are disabled. Figure 4BAs can be seen in FIG. 1 , because time t23 arrives after time t22, the state of signal SD is switched to high-level signal AOCLHENB and latched in latch circuit 150 before level shifter circuit 130 and level shifter circuit 140 are disabled by signal AOCISO switched to high level. In some embodiments, tslp2aoclhenb corresponds to the setup time of latch circuit 150 or is determined based on the setup time, and / or tslp2aoclhenb2aociso corresponds to the hold time of latch circuit 150 or is determined based on the hold time. After signal AOCISO reaches high level, another sleep mode 205 is implemented. VDD can now be turned off to further reduce power consumption.

[0101] At time t24, after a minimum time delay of taocisox from time t23, VDD is turned off. Circuit 100 enters a VDD step-down state. During the VDD step-down state, the signal levels of signal SD and signal SLP become a "don't care" state.

[0102] At time t25 , VDD is turned on, and the circuit 100 leaves the VDD step-down state.

[0103] At time t26, after a minimum time delay txaociso from time t5, the signal AOCISO switches from a high level to a low level to start waking up from the shutdown mode. The level shifter circuits 130, 140 are enabled in response to the low level of the signal AOCISO.

[0104] At time t27, after a minimum time delay taocisosaoclhenb from time t26, signal AOCLHENB switches from a high level to a low level. In response to the low level of signal AOCLHENB, latch circuit 150 switches from a latched state to a "transparent" state. The minimum duration taoclhenbh of the high level of signal AOCLHENB between time t22 and time t27 is longer than the minimum duration taocisoh of the high level of signal AOCISO between time t23 and time t26.

[0105] At time t28, the signal levels of the other input pins and the clock signal CLK exit the “don't care” state.

[0106] At time t29, after a minimum time delay taoclhenb2slp (i.e., time from AOCLHENB to SLP) from time t27 and / or a minimum time delay txslp from time t28, the signal SLP switches from a high level to a low level. In response to the low level of the signal SLP, the supply voltage VDDMHD, the supply voltage VDDHD are output to the memory circuit 110 to enter normal operation. The output data Qout starts switching again.

[0107] At time t31 , after a minimum time delay of tslpwk2clk from time t29 , the clock signal CLK resumes switching after being set to a low level during tslpwk2clk.

[0108] At time t32, after a minimum time delay tslp1 from time t29, circuit 100 is allowed to enter sleep mode if necessary. In some embodiments, one or more of the minimum time delays and / or durations described herein are configured, for example by chip design, to ensure correct and / or reliable operation.

[0109] Figure 5A is a schematic circuit diagram of a power management circuit 500A according to some embodiments. In some embodiments, the power management circuit 500A corresponds to one or more of the power management circuits 120 and the power management circuit 300. For simplicity, the same reference numerals are used to represent Figure 1 , Figure 3 , Figure 5A The corresponding components in .

[0110] Compared with the power management circuit 300, the power management circuit 500A includes a different latch circuit configuration. Specifically, the power management circuit 500A includes a latch circuit 550 corresponding to the latch circuit 350. The latch circuit 550 is different from the latch circuit 350 in that the latch circuit 550 includes a transmission gate TG1, while the latch circuit 350 includes a transistor P5, a transistor P7, a transistor N5, and a transistor N7. The power management circuit 500A also includes an inverter 552 having an input terminal and an output terminal, the input terminal being coupled to the output terminal of the level shifter circuit 330, and the output terminal being coupled to the data input terminal of the latch circuit 550.

[0111] In the latch circuit 550, the transmission gate TG1 includes a PMOS transistor P9 and an NMOS transistor N9, which are coupled in parallel. The gate of the transistor P9 corresponds to the control input terminal of the latch circuit 550, and is coupled to the input terminal 121 to receive the signal AOCLHENB, and is coupled to the input terminal of the inverter INV1 and the gate of the transistor N6. The gate of the transistor N9 is coupled to the output terminal of the inverter INV1 and the gate of the transistor P6. The first source / drain of the transistor P9 and the transistor N9 are coupled together and configure the data input terminal of the latch circuit 550. The second source / drain of the transistor P9 and the transistor N9 are coupled together and coupled to the input terminal of the inverter INV2. In some embodiments, the power management circuit 500A is configured to operate in a manner similar to that described for one or more power management circuits in the power management circuit 120 and the power management circuit 300. In at least one embodiment, one or more advantages described herein may be achieved by the power management circuit 500A and / or circuits including the power management circuit 500A.

[0112] Figure 5B is a schematic circuit diagram of a power management circuit 500B according to some embodiments. In some embodiments, the power management circuit 500B corresponds to one or more of the power management circuits 120, the power management circuit 300, and the power management circuit 500A. For simplicity, the same reference numerals are used to represent Figure 1 , Figure 3 , Figure 5A , Figure 5B The corresponding components in .

[0113] Compared with the power management circuit 500A, the power management circuit 500B includes a different latch circuit configuration. Specifically, the power management circuit 500B includes a latch circuit 555 corresponding to the latch circuit 550. The latch circuit 555 is different from the latch circuit 550 in that the latch circuit 555 includes a transmission gate TG2 and inverters INV3 and INV4, while the latch circuit 550 includes transistors P6, P8, N6, N8, and inverter INV2.

[0114] In the latch circuit 555, the transmission gate TG2 includes a PMOS transistor P10 and an NMOS transistor N10, and the PMOS transistor P9 and the NMOS transistor N9 are coupled in parallel. The gate of the transistor P10 is coupled to receive the signal AOCLHENB. For example, the gate of the transistor P10 is coupled to the input terminal 121. The gate of the transistor N10 is coupled to receive the signal AOCLHENB_C, which is the inverse signal of the signal AOCLHENB. For example, the gate of the transistor N10 is coupled to the output terminal of the inverter INV1. The first source / drain of the transistor P10 and the transistor N10 are coupled together to the second source / drain of the transistor P9, the transistor N9, and the input terminal of the inverter INV3. The second source / drain of the transistor P10 and the transistor N10 are coupled together and coupled to the output terminal of the inverter INV4. The output terminal of the inverter INV3 and the input terminal of the inverter INV4 are coupled together and correspond to the output terminal of the latch circuit 555. A signal SDL corresponding to the latched state of the signal SD is located at the input of the inverter INV3. In some embodiments, the power management circuit 500B is configured to operate in a manner similar to that described for one or more of the power management circuits 120, 300, etc. In at least one embodiment, one or more advantages described herein may be achieved by the power management circuit 500B and / or a circuit including the power management circuit 500B. Figure 3 , Figure 5A , Figure 5B The latch circuit configurations described are examples. Other latch circuit configurations are within the scope of the various embodiments.

[0115] Figure 5C is a schematic circuit diagram of a power management circuit 500C according to some embodiments. In some embodiments, the power management circuit 500C corresponds to one or more of the power management circuits 120, the power management circuit 300, the power management circuit 500A, and the power management circuit 500B. For simplicity, the same reference numerals are used to represent Figure 1 , Figure 3 , FIG. 5A to FIG. 5C The corresponding components in .

[0116] Compared to the power management circuit 300 , the power management circuit 500C includes a header circuit or PMOS transistor 536 that is configured to operate as and replace the PMOS transistors 136 , 146 in the power management circuit 300 .

[0117] In the power management circuit 500C, the PMOS transistor 536 has a first source / drain, a second source / drain, and a gate, the first source / drain being coupled to VDDM at a node 137, the second source / drain being coupled to the level shifter circuit 130, the level shifter circuit 140, and the gate being coupled to the input terminal 122 to receive the signal AOCISO. In response to the signal AOCISO having a high level, the PMOS transistor 536 is turned off and both the level shifter circuit 130, the level shifter circuit 140 are disabled. In some embodiments, the power management circuit 500C is configured to operate in a manner similar to that described for one or more of the power management circuits 120, the power management circuit 300. In at least one embodiment, one or more advantages described herein may be achieved by the power management circuit 500C and / or a circuit including the power management circuit 500C.

[0118] Figure 5D is a schematic circuit diagram of a level shifter circuit 500D according to some embodiments. The level shifter circuit 500D has an inverter configuration. In some embodiments, the level shifter circuit 500D corresponds to one or more of the level shifter circuit 130, the level shifter circuit 140, the level shifter circuit 330, the level shifter circuit 340, and / or the interface circuit described herein.

[0119] The level shifter circuit 500D includes a PMOS transistor MP and an NMOS transistor MN. The transistor MP includes a gate 591 and source / drains 592, 593. The gate 591 is electrically coupled to the input terminal In of the level shifter circuit 500D. The source / drain 592 is electrically coupled to the node of VDDM. The source / drain 593 is electrically coupled to the output terminal Out of the level shifter circuit 500D. The transistor MN includes a gate 594 and source / drains 595, 596. The gate 594 is electrically coupled to the gate 591 and the input terminal In. The source / drain 595 is electrically coupled to the node of the reference voltage (e.g., VSS). The source / drain 596 of the transistor MN is electrically coupled to the source / drain 593 of the transistor MP and the output terminal Out.

[0120] The level shifter circuit 500D is configured to receive an input signal at an input terminal In, generate an inverted signal of the input signal, and output the inverted signal as an output signal at an output terminal Out. The input signal at the input terminal In is located in the VDD power domain. The output signal at the output terminal Out is located in the VDDM power domain. As a result, the level shifter circuit 500D is configured to perform level shifting between the VDD power domain and the VDDM power domain. In at least one embodiment, one or more advantages described herein may be achieved by a power management circuit including the level shifter circuit 500D, and / or by a circuit including such a power management circuit and / or an interface circuit corresponding to the level shifter circuit 500D.

[0121] Figure 6 6 is a flow chart of method 600 according to some embodiments. In some embodiments, method 600 is performed by circuit 100 and one or more circuits including power management circuit 300, power management circuit 500A, power management circuit 500B, or power management circuit 500C. In at least one embodiment, method 600 is performed according to one or more of the power modes in table 200 and / or one or more of operations 400A, 400B.

[0122] At operation 605, the power management circuit outputs a first supply voltage corresponding to the first power supply voltage to a memory array of the memory circuit, and outputs a second supply voltage corresponding to the second power supply voltage to a peripheral circuit of the memory circuit. Figure 1 , Figure 4A , Figure 4B As described, the power management circuit 120 outputs the first supply voltage VDDAI corresponding to the first power supply voltage VDDM to the memory array 102 of the memory circuit 110, and outputs the second supply voltage VDDHD corresponding to the second power supply voltage VDD to the peripheral circuit 106 of the memory circuit 110. In some embodiments, the power management circuit 120 also outputs the third supply voltage VDDMHD to the peripheral circuit 104 of the memory circuit 110.

[0123] At operation 615, in response to at least one of the first power mode control signal or the second power mode control signal, the output of the second power supply voltage is stopped. Figure 1 , Figure 4A , Figure 4BAs described, in response to either the first power mode control signal SD or the second power mode control signal SLP having a predetermined level (e.g., a high level), the logic circuit 142 generates a combined power mode control signal SDSLP having a corresponding level (e.g., a low level). The power mode control signal SDSLP having a low level turns off the header circuit 166 and stops the output of the supply voltage VDDHD. In some embodiments, the power mode control signal SDSLP having a low level also turns off the header circuit 164 and stops the output of the supply voltage VDDMHD.

[0124] At operation 625, the state of the first power mode control signal is stored. Figure 1 , Figure 4A , Figure 4B As described above, in response to the signal AOCLHENB having a predetermined level (eg, a high level), the latch circuit 150 latches the state of the signal SD. Figure 4A In the described example scenario, the latched state of the signal SD corresponds to a high level of the signal SD, which stops the output of all supply voltages (including the supply voltage VDDAI) and causes the memory circuit 110 to enter the shutdown mode. Figure 4B In another example scenario described, the latched state of the signal SD corresponds to a low level of the signal SD, which maintains the output of the supply voltage VDDAI and causes the memory circuit 110 to enter a sleep mode, retaining the data in the memory array 102 .

[0125] At operation 635, the first supply voltage is disconnected from at least one circuit in the power management circuit. Figure 1 , Figure 4A , Figure 4B As described, in response to the signal AOCISO having a predetermined level (e.g., a high level), the level shifter circuit 130 and the level shifter circuit 140 of the power management circuit 120 are disconnected from VDDM by turning off the corresponding header circuit 136 and the header circuit 146. As a result, the power consumption of the circuit 100 is reduced.

[0126] At operation 645, the second power supply voltage is turned off. Figure 1 , Figure 4A , Figure 4B As described, in response to a signal VDD_off having a predetermined level (e.g., a high level), the header circuit 180 is turned off and VDD is removed from the VDD power rail 183. VDD is turned off for various circuits powered by the VDD power rail 183. In some embodiments, the VDD power domain is turned off. This state is called VDD bucking and allows further reduction in power consumption.

[0127] At this stage, the circuit 100 enters a shutdown mode or a sleep mode in a power management state with VDD reduced (depending on the level or state of the signal SD and / or the signal SLP at operation 615), as described for another shutdown mode 204 or another sleep mode 205 in Table 200, respectively.

[0128] In some embodiments, by not setting the signal VDD_off to a high level, the VDD step-down state is not triggered. In other words, operation 645 is omitted.

[0129] In some embodiments, by not switching the signal AOCISO to a high level, the power management state is not entered. In other words, operations 635 and 645 are omitted. At this stage, the circuit 100 enters the shutdown mode or the sleep mode (depending on the level or state of the signal SD and / or the signal SLP at operation 615), as described for the shutdown mode 203 or the sleep mode 202 in Table 200.

[0130] To wake up from a shutdown mode or a sleep mode that the circuit 100 has entered, one or more of operations 655 to 675 are performed.

[0131] At operation 655, the second power supply voltage (eg, VDD) is turned back on by controlling the signal VDD_off. Operation 655 is performed where the VDD voltage reduction has been performed by operation 645. In at least one embodiment where operation 645 is omitted, operation 655 is also omitted.

[0132] At operation 665, the first power supply voltage (e.g., VDDM) is reconnected to at least one circuit of the power management circuit. For example, the level shifter circuits 130, 140 are enabled again by turning on the corresponding header circuits 136, 146 in response to the signal AOCISO switching to a low level. In at least one embodiment where operation 635 is omitted, operation 665 is also omitted.

[0133] At operation 675, the output of the first supply voltage and the second supply voltage from the power management circuit is restored. For example, the signal AOCLHENB is switched to a low level to set the latch circuit 150 in a "transparent" state. The signal SD and the signal SLP are switched to a low level to output the supply voltage VDDAI, the supply voltage VDDMHD, and the supply voltage VDDHD to the memory circuit 110. At this stage, the circuit 100 is configured to Figure 2 The described normal operating mode 201 operates.

[0134] In some embodiments, it is possible to switch from one reduced power mode to another reduced power mode. For example, in at least one embodiment, by switching the signal SD to a high level, the circuit 100 switches from the sleep mode 202 to the shutdown mode 203. As described herein, by switching the signal AOCISO to a high level, the circuit 100 can be switched from the shutdown mode 203 to another shutdown mode 204 with or without the need for another VDD step-down. For another example, in at least one embodiment, the circuit 100 wakes up from the shutdown mode (e.g., 203 or 204) to the sleep mode (e.g., 202 or 205). Various switches in the described power modes using one or more of the described signals (e.g., signal SD, signal SLP, signal AOCISO, signal AOCLHENB, signal VDD_off) in one or more of the described orders are within the scope of various embodiments. In at least one embodiment, one or more advantages described herein can be achieved by the method 600.

[0135] The various low levels and high levels described herein are examples. It is within the scope of various embodiments to modify one or more of the described circuits or signals to include a low level instead of the described high level, and vice versa. The described methods include example operations, but they do not necessarily need to be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations can be appropriately added, replaced, changed in order, and / or eliminated. Embodiments combining different features and / or different embodiments are within the scope of the present disclosure, and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0136] In some embodiments, the circuit includes a memory circuit and a power management circuit, the power management circuit including a first circuit. The first circuit is configured to: in response to a first state of a first power management control signal and a first state of a second power management control signal, control a first supply voltage to be supplied to the memory circuit according to a first power mode control signal. The first circuit is also configured to: in response to a second state of the first power management control signal, store a state of the first power mode control signal, and control the supply of the first supply voltage to the memory circuit according to the stored state of the first power mode control signal. The power management circuit is configured to: in response to a second state of the second power management control signal, disable a portion of the first circuit.

[0137] In some embodiments, the power management circuit includes a first third input terminal to a third input terminal, a first level shifter circuit and a second level shifter circuit, a latch circuit, and a first header circuit. The first input terminal is configured to receive a first power management control signal. The second input terminal is configured to receive a second power management control signal. The third input terminal is configured to receive a first power mode control signal. The first level shifter circuit has an input terminal and an output terminal, and the input terminal is coupled to the third input terminal. The latch circuit has a control input terminal, a data input terminal, and an output terminal, the control input terminal is coupled to the first input terminal, the data input terminal is coupled to the output terminal of the first level shifter circuit, and the output terminal is configured to control the supply of the first supply voltage to the external circuit. The second level shifter circuit has an input terminal and an output terminal, the input terminal is coupled to the third input terminal, and the output terminal is configured to control the supply of the second supply voltage to the external circuit. The first header circuit has a control input terminal coupled to the second input terminal. The first header circuit is coupled between a first node of the first power supply voltage and at least one of the first level shifter circuit or the second level shifter circuit.

[0138] In some embodiments, a method includes: outputting a first supply voltage to a memory array of a memory circuit by a power management circuit, and outputting a second supply voltage to a peripheral circuit of the memory circuit. The first supply voltage corresponds to a first power supply voltage. The second supply voltage corresponds to a second power supply voltage, and the second power supply voltage is different from the first power supply voltage. In response to at least one of a first power mode control signal or a second power mode control signal, stopping the output of the second supply voltage. Storing a state of the first power mode control signal. After storing the state of the first power mode control signal, disconnecting the first power supply voltage from at least one circuit of the power management circuit and turning off the second power supply voltage.

[0139] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0140] Example 1 is a semiconductor circuit comprising: a memory circuit; and a power management circuit comprising a first circuit, wherein the first circuit is configured to: in response to a first state of a first power management control signal and a first state of a second power management control signal, control the supply of a first supply voltage to the memory circuit according to a first power mode control signal, in response to a second state of the first power management control signal, store the state of the first power mode control signal, and control the supply of the first supply voltage to the memory circuit according to the stored state of the first power mode control signal, and the power management circuit is configured to: in response to the second state of the second power management control signal, disable a portion of the first circuit.

[0141] Example 2 is the circuit described in Example 1, wherein the first circuit is configured to store the state of the first power mode control signal in response to the second state of the first power management control signal before the portion of the first circuit is disabled in response to the second state of the second power management control signal.

[0142] Example 3 is the circuit described in Example 1, wherein the first circuit includes: a first level shifter circuit configured to generate a first level shift signal corresponding to the first power mode control signal to control the supply of the first supply voltage to the memory circuit; the power management circuit also includes: a second level shifter circuit configured to generate a second level shift signal corresponding to the first power mode control signal to control the supply of the second supply voltage to the memory circuit, and the power management circuit is configured to disable the first level shifter circuit and the second level shifter circuit in response to a second state of the second power management control signal.

[0143] Example 4 is the circuit described in Example 3, wherein the first circuit also includes a latch circuit configured to generate a latch output signal to control the supply of the first supply voltage to the memory circuit based on the following items: the first level shift signal, and the first power management control signal.

[0144] Example 5 is the circuit described in Example 3, wherein the power management circuit further includes a logic circuit configured to generate a combined power mode control signal based on: the first power mode control signal, and a second power mode control signal, the power management circuit is configured to control the supply of a third supply voltage to the memory circuit based on the combined power mode control signal, and the second level shifter circuit is configured to generate the second level shift signal based on the combined power mode control signal to control the supply of the second supply voltage to the memory circuit.

[0145] Example 6 is the circuit of Example 3, wherein the power management circuit is further configured to set the first level-shifted signal and the second level-shifted signal to a predetermined voltage in response to a second state of the second power management control signal.

[0146] Example 7 is a power management circuit, comprising: a first input terminal, configured to receive a first power management control signal; a second input terminal, configured to receive a second power management control signal; a third input terminal, configured to receive a first power mode control signal; a first level shifter circuit, having: an input terminal, coupled to the third input terminal, and an output terminal; a latch circuit, having: a control input terminal, coupled to the first input terminal, a data input terminal, coupled to the output terminal of the first level shifter circuit, and an output terminal, configured to control the supply of a first supply voltage to an external circuit; a second level shifter circuit, having: an input terminal, coupled to the third input terminal, and an output terminal, configured to control the supply of a second supply voltage to the external circuit; and a first header circuit, the first header circuit having a control input terminal coupled to the second input terminal, the first header circuit being coupled between: a first node of a first power supply voltage, and at least one of the first level shifter circuit or the second level shifter circuit.

[0147] Example 8 is the power management circuit described in Example 7, further comprising: a switch having a control input terminal coupled to the second input terminal, the switch being coupled between: a reference node of a reference voltage, and an output terminal of the first level shifter circuit or the second level shifter circuit.

[0148] Example 9 is the power management circuit described in Example 7, further including: a first switch, the first switch having a control input terminal coupled to the second input terminal, the first switch being coupled between: a reference node of a reference voltage, and an output terminal of the first level shifter circuit; and a second switch, the second switch having a control input terminal coupled to the second input terminal, the second switch being coupled between: a reference node of the reference voltage, and an output terminal of the second level shifter circuit.

[0149] Example 10 is the power management circuit described in Example 7, further including: a fourth input terminal configured to receive a second power mode control signal; and a logic circuit having: an input terminal correspondingly coupled to the third input terminal and the fourth input terminal, and an output terminal configured to control the supply of a third supply voltage to the external circuit.

[0150] Example 11 is the power management circuit of Example 10, wherein an output of the logic circuit is coupled to an input of the second level shifter circuit.

[0151] Example 12 is the power management circuit described in Example 7, further including: at least one circuit coupled to a second node of a second power supply voltage, the second power supply voltage being different from the first power supply voltage; and a second header circuit coupled to the second node and configured to controllably disconnect the second power supply voltage from the second node.

[0152] Example 13 is the power management circuit described in Example 12, wherein the at least one circuit includes at least one of the following: a first connection circuit coupled between the third input terminal and the input terminal of the first level shifter circuit, a second connection circuit coupled between the third input terminal and the input terminal of the second level shifter circuit, or an output terminal header circuit configured to controllably supply a third supply voltage to the external circuit, the third supply voltage corresponding to the second power supply voltage.

[0153] Example 14 is a power management method, comprising: through a power management circuit: outputting a first supply voltage to a memory array of a memory circuit, the first supply voltage corresponding to a first power supply voltage, and outputting a second supply voltage to a peripheral circuit of the memory circuit, the second supply voltage corresponding to a second power supply voltage, the second power supply voltage being different from the first power supply voltage; stopping outputting the second supply voltage in response to at least one of a first power mode control signal or a second power mode control signal; storing a state of the first power mode control signal; and after storing the state of the first power mode control signal, disconnecting the first power supply voltage from at least one circuit of the power management circuit; and shutting down the second power supply voltage.

[0154] Example 15 is the method of Example 14, wherein the outputting further comprises: outputting a third supply voltage to the peripheral circuit, the third supply voltage corresponding to the first power supply voltage, and the stopping further comprises: stopping outputting the third supply voltage.

[0155] Example 16 is the method described in Example 15, further comprising: disconnecting the first power supply voltage from at least one interface circuit in the peripheral circuit, wherein the at least one interface circuit is connected between a first power domain of the first power supply voltage and a second power domain of the second power supply voltage.

[0156] Example 17 is the method described in Example 14, further comprising: stopping outputting the first supply voltage in response to a stored state of the first power mode control signal corresponding to a first state; and continuing to output the first supply voltage in response to a stored state of the first power mode control signal corresponding to a second state, the second state being different from the first state.

[0157] Example 18 is the method of Example 17, wherein the first state corresponds to a first power mode of the memory circuit, and ceasing to output the second supply voltage is in response to the first power mode control signal.

[0158] Example 19 is the method described in Example 18, wherein the second state corresponds to a second power mode of the memory circuit, the second power mode has higher power consumption than the first power mode, and stopping outputting the second supply voltage is in response to the second power mode control signal.

[0159] Example 20 is the method described in Example 14, further comprising: turning on the second power supply voltage; and after turning on the second power supply voltage, reconnecting the first power supply voltage to at least one circuit of the power management circuit; and restoring the output of the first supply voltage and the second supply voltage.

Claims

1. A semiconductor circuit comprising: Memory circuit; as well as A power management circuit comprises a first circuit, wherein: The first circuit is configured as follows: In response to a first state of the first power management control signal and a first state of the second power management control signal, controlling the supply of a first supply voltage to the memory circuit according to a first power mode control signal, In response to a second state of the first power management control signal, storing a state of the first power mode control signal, and controlling supply of the first supply voltage to the memory circuit according to the stored state of the first power mode control signal, and The power management circuit is configured to: In response to a second state of the second power management control signal, Disabling a portion of the first circuit.

2. The circuit according to claim 1, wherein The first circuit is configured to store a state of the first power mode control signal in response to a second state of the first power management control signal before the portion of the first circuit is disabled in response to a second state of the second power management control signal.

3. The circuit according to claim 1, wherein: The first circuit comprises: a first level shifter circuit configured to generate a first level shift signal corresponding to the first power mode control signal to control supply of the first supply voltage to the memory circuit; The power management circuit further comprises: a second level shifter circuit configured to generate a second level shift signal corresponding to the first power mode control signal to control supply of a second supply voltage to the memory circuit, and The power management circuit is configured to disable the first level shifter circuit and the second level shifter circuit in response to a second state of the second power management control signal.

4. The circuit according to claim 3, wherein: The first circuit also includes a latch circuit configured to generate a latch output signal to control supply of the first supply voltage to the memory circuit based on: the first level-shifted signal, and The first power management control signal.

5. The circuit according to claim 3, wherein: The power management circuit further includes a logic circuit configured to generate a combined power mode control signal based on: the first power mode control signal, and A second power mode control signal, The power management circuit is configured to control supply of a third supply voltage to the memory circuit based on the combined power mode control signal, and The second level shifter circuit is configured to generate the second level shift signal based on the combined power mode control signal to control supply of the second supply voltage to the memory circuit.

6. The circuit according to claim 3, wherein: The power management circuit is further configured to set the first level-shifted signal and the second level-shifted signal to a predetermined voltage in response to a second state of the second power management control signal.

7. A power management circuit, comprising: A first input terminal configured to receive a first power management control signal; A second input terminal configured to receive a second power management control signal; A third input terminal is configured to receive a first power mode control signal; A first level shifter circuit having: input terminal, coupled to the third input terminal, and Output terminal; A latch circuit having: a control input terminal, coupled to the first input terminal, a data input terminal coupled to the output terminal of the first level shifter circuit, and an output terminal configured to control supply of a first supply voltage to an external circuit; A second level shifter circuit having: input terminal, coupled to the third input terminal, and an output terminal configured to control the supply of a second supply voltage to the external circuit; as well as a first header circuit having a control input coupled to the second input, the first header circuit being coupled between: a first node of a first power supply voltage, and At least one of the first level shifter circuit or the second level shifter circuit.

8. The power management circuit according to claim 7, further comprising: a switch having a control input coupled to the second input, the switch being coupled between: reference node for the reference voltage, and An output terminal of the first level shifter circuit or the second level shifter circuit.

9. The power management circuit according to claim 7, further comprising: a first switch having a control input coupled to the second input, the first switch being coupled between: reference node for the reference voltage, and an output terminal of the first level shifter circuit; as well as a second switch having a control input coupled to the second input, the second switch being coupled between: the reference voltage at the reference node, and An output terminal of the second level shifter circuit.

10. A power management method, comprising: Through the power management circuit: outputting a first supply voltage to a memory array of a memory circuit, the first supply voltage corresponding to a first power supply voltage, and outputting a second supply voltage to a peripheral circuit of the memory circuit, the second supply voltage corresponding to a second power supply voltage, the second power supply voltage being different from the first power supply voltage; In response to at least one of the first power mode control signal or the second power mode control signal, stop outputting the second supply voltage; storing a state of the first power mode control signal; as well as After storing the state of the first power mode control signal, disconnecting the first supply voltage from at least one circuit of the power management circuit; and The second power supply voltage is turned off.

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