Point-to-point path verification method and apparatus, electronic device, and medium

Abstract

This disclosure relates to a point-to-point path verification method, apparatus, electronic device, and medium. The method includes: acquiring configuration information of a module to be verified; writing the configuration information of the module to be verified into a verification document and saving the verification document as a JSON file; the verification document contains at least one verification test item; each verification test item includes multiple verification test paths; parsing the JSON file to extract the configuration information of the module to be verified; generating multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and according to the configuration information; integrating the UVM components and the UVM incentive files into a UVM verification platform based on a UVM environment setup script; and, in response to a target verification test command, testing and verifying multiple test paths of the target verification test item on the UVM verification platform; the number of the target verification test item is greater than or equal to one.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit verification technology, and in particular to a point-to-point path verification method, apparatus, electronic device and medium. Background Technology

[0002] With the rapid development of digital integrated circuits and the increasing complexity of chip functions, chip verification has become increasingly important in the chip design cycle. To ensure the functional correctness and performance compliance of chips, comprehensive verification of the chip's internal pathways and interfaces must be completed in a short period of time. This requires not only efficient verification methods and technologies, but also advanced tools and automated processes to improve verification efficiency, placing high demands on the automation and reusability of the verification environment.

[0003] In related technologies, test vectors are manually written for the signal interfaces of the module to be verified, and the accessibility of the interface is determined by checking the response of the module. This method has low reusability, low verification efficiency, and results in a long verification cycle.

[0004] Therefore, improving verification efficiency and avoiding repetitive verification work caused by the duplication of peripheral functions is an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a point-to-point path verification method, apparatus, electronic device, and medium.

[0006] Firstly, this disclosure provides a point-to-point path verification method, including:

[0007] Obtain the configuration information of the module to be verified;

[0008] The configuration information of the module to be verified is written into the verification document, and the verification document is saved as a JSON file; the verification document contains at least one verification test item; each verification test item includes multiple verification test paths;

[0009] The JSON file is parsed to extract the configuration information of the module to be verified;

[0010] Based on the preset configuration script, and according to the configuration information, multiple general verification methodology UVM components and UVM incentive files are generated;

[0011] Based on the UVM environment setup script, the UVM components and the UVM incentive files are integrated into the UVM verification platform;

[0012] In response to the target verification test command, the UVM verification platform performs tests and verifications on multiple test paths of the target verification test item; the number of the target verification test item is greater than or equal to 1.

[0013] As an optional implementation of this disclosure, the configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data, and reference clock source.

[0014] As an optional implementation of this disclosure, the step of generating multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and the configuration information includes:

[0015] Input the configuration information into the configuration script to generate multiple UVM components and UVM incentive files containing the configuration information;

[0016] The UVM components include: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component, and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM components for test verification.

[0017] As an optional implementation of this disclosure, the step of testing and verifying multiple test paths of the target verification test item on the UVM verification platform in response to the target verification test command includes:

[0018] The monitor's function is to collect input and output data from the device under test.

[0019] In response to the target verification test command, identify at least one path to be tested;

[0020] The terminal signals of each path under test are acquired through the monitor component;

[0021] The source signals of each path to be tested are obtained through the reference model component;

[0022] The scoring board component detects the source and terminal signals of each path under test to determine whether each path under test has been successfully verified.

[0023] As an optional implementation of this disclosure, the step of detecting the source and terminal signals of each test path based on the scoring board component to determine whether each test path has been successfully verified includes:

[0024] If the source signal of the target test path is consistent with the terminal signal of the target test path, then the target test path is determined to have been successfully verified.

[0025] If the source signal and the terminal signal of the target test path are inconsistent, the verification of the target test path is determined to be unsuccessful.

[0026] Secondly, embodiments of this disclosure provide a point-to-point path verification device, comprising:

[0027] The acquisition module is used to obtain the configuration information of the module to be verified.

[0028] A configuration module is used to write the configuration information of the module to be verified into a verification document and save the verification document as a JSON file; the verification document contains at least one verification test item; each verification test item includes multiple verification test paths;

[0029] The parsing module is used to parse the JSON file and extract the configuration information of the module to be verified;

[0030] The generation module is used to generate multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and the configuration information.

[0031] An integration module is used to build scripts based on the UVM environment, integrating the UVM components and the UVM incentive files into the UVM verification platform;

[0032] The verification module is used to perform test verification on multiple test paths of the target verification test item on the UVM verification platform in response to the target verification test command; the number of the target verification test item is greater than or equal to 1.

[0033] As an optional implementation of this disclosure, the configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data, and reference clock source.

[0034] As an optional implementation of this disclosure, the generation module is specifically used for:

[0035] Input the configuration information into the configuration script to generate multiple UVM components and UVM incentive files containing the configuration information;

[0036] The UVM components include: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component, and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM components for test verification.

[0037] As an optional implementation of this disclosure, the verification module includes:

[0038] The determination unit is used to determine at least one path to be tested in response to a target verification test command;

[0039] The first acquisition unit is used to acquire the terminal signals of each path to be tested through the monitor component;

[0040] The second acquisition unit is used to acquire the source signals of each path to be tested through the reference model component;

[0041] The detection unit is used to detect the source signal and terminal signal of each path to be tested based on the scoring board component, and to determine whether each path to be tested has been successfully verified.

[0042] As an optional implementation of this disclosure, the detection unit is specifically used for:

[0043] If the source signal of the target test path is consistent with the terminal signal of the target test path, then the target test path is determined to have been successfully verified.

[0044] If the source signal and the terminal signal of the target test path are inconsistent, the verification of the target test path is determined to be unsuccessful.

[0045] Thirdly, embodiments of this disclosure provide an electronic device, including: a memory and a processor; the memory stores a computer program, and the processor executes the computer program to implement the point-to-point path verification method described in the first aspect or any embodiment of the first aspect.

[0046] Fourthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the point-to-point path verification method as described in any embodiment of the first aspect.

[0047] The technical solution provided in this disclosure has the following advantages compared with the prior art: It obtains the configuration information of the module to be verified, writes the configuration information of the module to be verified into a verification document, saves the verification document as a JSON file, parses the JSON file to extract the configuration information of the module to be verified, generates multiple general verification methodology UVM components and UVM stimulus files based on a preset configuration script and the configuration information, builds a script based on the UVM environment, integrates the UVM components and UVM stimulus files into the UVM verification platform, and, in response to the target verification test command, tests and verifies multiple test paths of the target verification test item on the UVM verification platform. Since the verification document contains at least one verification test item, each verification test item includes multiple verification test paths, and the number of target verification test items is greater than or equal to one, the UVM verification platform can simultaneously test and verify multiple test paths of multiple target verification test items, improving verification efficiency and avoiding a large amount of repetitive verification caused by the duplication of peripheral functions. Furthermore, since the configuration parameters of the verification document are extracted by the script, and each UVM component with configuration information is automatically generated, manual configuration is unnecessary, avoiding errors caused by manual configuration and improving verification accuracy. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0049] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating a point-to-point path verification method provided in an embodiment of this disclosure;

[0051] Figure 2 This is a schematic diagram of a UVM verification platform architecture provided in an embodiment of this disclosure;

[0052] Figure 3 This is a schematic diagram of the structure of a point-to-point pathway verification device provided in an embodiment of this disclosure;

[0053] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0054] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0055] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0056] The terms "first" and "second" and other relational terms used in this disclosure and claims are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0057] In this disclosure, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. Furthermore, in the description of the embodiments in this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0058] Point-to-point path verification typically involves verifying the correctness and integrity of data transmission between two modules, such as the correctness and integrity of data transmission between a first peripheral and a second peripheral. The first peripheral could be a USART module, and the second peripheral could be a GPIO module. It should be noted that the first and second peripherals can also be other communication modules or other modules with specific functions; no specific restrictions are imposed here.

[0059] In some embodiments, such as Figure 1 As shown, a point-to-point path verification method is provided, including the following steps S11-S16:

[0060] S11. Obtain the configuration information of the module to be verified.

[0061] Specifically, the configuration information of the module to be verified is obtained according to the test plan.

[0062] Optionally, the configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data, and reference clock source.

[0063] Specifically, the verification module name describes each module to be verified; the verification test item name describes each test item to be verified; the source signal refers to the original signal emitted from the signal source, carrying the information to be transmitted; the terminal signal refers to the place where the signal is received, used to receive the source signal. The base address of a register refers to the starting address of a memory-mapped device or register-mapped device in the physical address space; it is the reference point for all register offset addresses. The register offset address is an offset relative to the base address, used to access specific registers or registers in a memory-mapped device. When accessing a specific register, the base address and the offset address are added to generate the physical address of the register to be accessed, and then read or write operations are performed through this physical address. The peripheral base address is determined based on the verification module name; the peripheral offset address can be set according to the peripheral base address and the range of registers; the reference clock source is used to ensure the synchronous operation of the UVM components.

[0064] Access the memory-mapped peripheral registers, extract the base address and offset address of the peripheral registers, and generate the UVM stimulus file.

[0065] The configuration data includes: enabling clock, peripheral communication configuration, and I / O multiplexing configuration.

[0066] For example, enabling the clock allows a peripheral to begin operating. To enable the clock for a peripheral, the corresponding register bit in the RCC (Register Control Code) needs to be set. Peripheral communication configuration typically involves configuring GPIO pin functions, initializing the peripheral (e.g., setting the peripheral's operating mode, clock frequency, etc.), and configuring the communication rate. For example, for serial communication such as UART, the baud rate, data bits, stop bits, and parity bits need to be configured. For the multi-functional multiplexing of the I / O interface, multiple test stimuli are constructed to test different functions of the I / O interface under test. Each test stimulus corresponds to the state value of a register. Test cases cyclically set different register state parameters and execute the corresponding test stimuli to implement the verification process for all multiplexed functions of the chip's I / O interface.

[0067] S12. Write the configuration information of the module to be verified into the verification document, and save the verification document as a JSON file.

[0068] The verification document contains at least one verification test item; each verification test item includes multiple verification test paths.

[0069] Specifically, the verification document contains at least one verification test item, and each verification test item includes multiple verification test paths. After writing the configuration information of the module to be verified into the verification document, the verification document is saved as a JSON file. JSON (JavaScript Object Notation) is a lightweight data-interchange format that is easy to read and write, and also easy for machines to parse and generate. It is based on a subset of JavaScript, but JSON is language-independent, and many programming languages ​​support data exchange in JSON format.

[0070] For example, suppose the verification test items are USART? _TX? _GPIO? _, where ? represents the quantity, i.e., 0 to n. For instance, USART's tx0 corresponds to GPIO's PB0; USART1's rx0 corresponds to GPIO's PB1; USART's tx1 corresponds to GPIO's PB2; USART1's rx1 corresponds to GPIO's PD0; USART's tx2 corresponds to GPIO's PD1; and USART1's rx2 corresponds to GPIO's PD2. The only difference between these verification test items is the port, but the verification method is the same. For example, if tx0 is toggleed, PB0 will also be toggleed.

[0071] S13. Parse the JSON file and extract the configuration information of the module to be verified.

[0072] Specifically, a Python script is used to parse the JSON file and extract the configuration information of the module to be verified, namely, the verification module name, the verification test item name, the source signal, the terminal signal, the peripheral base address, the peripheral offset address, the configuration data, and the reference clock source.

[0073] S14. Based on the preset configuration script, generate multiple general verification methodology UVM components and UVM incentive files according to the configuration information.

[0074] Specifically, based on a pre-written configuration script and configuration information, multiple UVM components with configuration information and UVM incentive files are generated.

[0075] For example, after extracting the configuration information of each verification test item in the verification document, an environment component, agent component, driver component, monitor component, reference model component, scoreboard component, and test component with configuration information are generated.

[0076] In some embodiments, step S14 (generating multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and the configuration information) can be implemented in the following way:

[0077] Input the configuration information into the configuration script to generate multiple UVM components and UVM incentive files containing the configuration information.

[0078] The UVM components include: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component, and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM components for test verification.

[0079] Specifically, UVM components include: driver components, monitor components, reference model components, sequencer components, proxy components, scoreboard components, environment components, and test components. These components collectively constitute the structure of the UVM verification platform, making the design verification process more efficient and systematic. Each component has its specific responsibilities and functions; through the collaborative work of these components, comprehensive verification of integrated circuit designs can be achieved.

[0080] The driver component is responsible for retrieving transactions from the sequencer component and driving them to the port of the device under test. The driver component is a parameterized class, and the types of its parameters need to be declared when it is defined.

[0081] The monitor component, which functions in reverse to the driver component, receives data from the port of the device under test, converts the received data into transaction-level sequence items, and then sends them to the scoreboard for comparison.

[0082] The reference model component is used to simulate the function of the device under test (DUT) and sends the data generated by the reference model to the scoreboard component for comparison with the data collected by the monitor component, thereby verifying the correctness of the DUT.

[0083] The sequencer component, located between the driver and monitor components, is used to manage and coordinate the flow of transactions.

[0084] Agent components, which typically include one or more drivers, monitors, and sequencers, are used to abstract and encapsulate test behaviors associated with a specific protocol or interface.

[0085] The scoreboard component is used to collect and compare data from the monitor with the expected results from the sequencer component to verify whether the device under test is behaving correctly.

[0086] The environment component, as a container, holds multiple proxy components and other components for implementing different test configurations.

[0087] The test component is a user-defined top-level structure that inherits from uvm_test. The test component aims to provide different configurations, environment structure configurations, test mode configurations, etc., and then creates the environment, instantiates the test sequence, and mounts the target sequencer component.

[0088] S15. Based on the UVM environment setup script, integrate the UVM components and the UVM incentive file into the UVM verification platform.

[0089] Specifically, a script based on the UVM environment is used to integrate UVM components and UVM incentive files into the UVM verification platform.

[0090] S16. In response to the target verification test command, perform test verification on multiple test paths of the target verification test item on the UVM verification platform.

[0091] The number of target verification test items is greater than or equal to one. The target verification test command is used to verify whether multiple test paths of the target verification test item transmit data correctly.

[0092] Specifically, in response to the target verification test command input by the user, the UVM verification platform performs tests and verifications on multiple test paths of the target verification test item.

[0093] In some embodiments, step S16 (in response to a target verification test command, performing test verification on multiple test paths of the target verification test item on the UVM verification platform) can be implemented in the following manner:

[0094] A. In response to the target verification test command, identify at least one path to be tested.

[0095] B. Acquire the terminal signals of each path to be tested through the monitor component.

[0096] C. Obtain the source signals of each path to be tested through the reference model component.

[0097] D. Based on the scoring board component, detect the source and terminal signals of each path to be tested to determine whether each path to be tested has been successfully verified.

[0098] Step D above can be achieved in the following ways:

[0099] (1) If the source signal of the target test path is consistent with the terminal signal of the target test path, then the target test path is determined to be successfully verified.

[0100] (2) If the source signal of the target test path and the terminal signal of the target test path are inconsistent, the target test path is determined to have failed verification.

[0101] Specifically, in response to the target verification test command, at least one path to be tested is identified. The terminal signal of each path to be tested is acquired through the monitor component, and the source signal of each path to be tested is acquired through the reference model component. After acquiring the terminal signal of each path to be tested, the monitor component sends the terminal signal of each path to be tested to the scoring board component. After acquiring the source signal of each path to be tested, the reference model component sends the source signal of each path to be tested to the scoring board component. The scoring board component detects the source signal and terminal signal of each path to be tested. If the source signal and terminal signal of the target path to be tested are consistent, the target path to be tested is determined to be verified successfully. If the source signal and terminal signal of the target path to be tested are inconsistent, the target path to be tested is determined to be verified unsuccessfully.

[0102] For example, refer to Figure 2 As shown, Figure 2 This is a schematic diagram of the UVM verification platform architecture. `test_cfg` is the verification document, containing configuration information. The C stimulus file is the UVM stimulus file mentioned above, and this information is stored in flash memory. The module to be verified is the SOC design-under-test (SUTC) part. The source signal of the test path is the interface signal corresponding to the USART module, and the terminal signal is the interface signal corresponding to the GPIO module. The environment components include proxy components, reference model components, and scoreboard components. The proxy components include driver components and monitor components. It should be noted that the proxy components also include a sequencer component. Assuming the reference model component acquires the source signal of the target test path as the data corresponding to the TX0 interface of the USART module, and the monitor component acquires the terminal signal of the target test path as the data corresponding to the IO0 interface of the GPIO module, if the data corresponding to the TX0 interface of the USART module matches the data corresponding to the IO0 interface of the GPIO module, then the target test path is verified successfully; if the data corresponding to the TX0 interface of the USART module does not match the data corresponding to the IO0 interface of the GPIO module, then the target test path verification fails.

[0103] The point-to-point path verification method disclosed herein obtains the configuration information of the module to be verified, writes the configuration information of the module to be verified into a verification document, saves the verification document as a JSON file, parses the JSON file to extract the configuration information of the module to be verified, generates multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and the configuration information, and integrates the UVM components and UVM incentive files into the UVM verification platform based on a UVM environment setup script. Responding to the target verification test command, the UVM verification platform performs testing and verification on multiple paths to be tested for the target verification test item. Since the verification document contains at least one verification test item, each verification test item includes multiple verification test paths, and the number of target verification test items is greater than or equal to one, the UVM verification platform can simultaneously test and verify multiple paths to be tested for multiple target verification test items, improving verification efficiency and avoiding a large amount of repetitive verification caused by redundant peripheral functions. Furthermore, since the configuration parameters of the verification document are extracted by the script and each UVM component with configuration information is automatically generated, manual configuration is unnecessary, avoiding errors caused by manual configuration and improving verification accuracy.

[0104] In some embodiments, refer to Figure 3 As shown, a point-to-point path verification device 300 is provided, comprising:

[0105] Module 310 is used to obtain the configuration information of the module to be verified;

[0106] The configuration module 320 is used to write the configuration information of the module to be verified into a verification document and save the verification document as a JSON file; the verification document contains at least one verification test item; each verification test item includes multiple verification test paths;

[0107] Parsing module 330 is used to parse the JSON file and extract the configuration information of the module to be verified;

[0108] The generation module 340 is used to generate multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and the configuration information.

[0109] The integration module 350 is used to build scripts based on the UVM environment, integrating the UVM components and the UVM incentive files into the UVM verification platform.

[0110] The verification module 360 ​​is used to perform test verification on multiple test paths of the target verification test item on the UVM verification platform in response to the target verification test command; the number of the target verification test item is greater than or equal to 1.

[0111] As an optional implementation of this disclosure, the configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data, and reference clock source.

[0112] As an optional implementation of this disclosure, the generation module is specifically used for:

[0113] Input the configuration information into the configuration script to generate multiple UVM components and UVM incentive files containing the configuration information;

[0114] The UVM components include: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component, and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM components for test verification.

[0115] As an optional implementation of this disclosure, the verification module includes:

[0116] The determination unit is used to determine at least one path to be tested in response to a target verification test command;

[0117] The first acquisition unit is used to acquire the terminal signals of each path to be tested through the monitor component;

[0118] The second acquisition unit is used to acquire the source signals of each path to be tested through the reference model component;

[0119] The detection unit is used to detect the source signal and terminal signal of each path to be tested based on the scoring board component, and to determine whether each path to be tested has been successfully verified.

[0120] As an optional implementation of this disclosure, the detection unit is specifically used for:

[0121] If the source signal of the target test path is consistent with the terminal signal of the target test path, then the target test path is determined to have been successfully verified.

[0122] If the source signal and the terminal signal of the target test path are inconsistent, the verification of the target test path is determined to be unsuccessful.

[0123] The point-to-point path verification device provided in this disclosure acquires the configuration information of the module to be verified, writes the configuration information of the module to be verified into a verification document, saves the verification document as a JSON file, parses the JSON file to extract the configuration information of the module to be verified, and generates multiple general verification methodology UVM components and UVM stimulus files based on a preset configuration script and the configuration information. A script is built based on the UVM environment to integrate the UVM components and UVM stimulus files into the UVM verification platform. Responding to the target verification test command, the device performs testing and verification on multiple paths to be tested for the target verification test item on the UVM verification platform. Since the verification document contains at least one verification test item, each verification test item includes multiple verification test paths, and the number of target verification test items is greater than or equal to one, the UVM verification platform can simultaneously test and verify multiple paths to be tested for multiple target verification test items, improving verification efficiency and avoiding a large amount of repetitive verification caused by redundant peripheral functions. Furthermore, since the configuration parameters of the verification document are extracted by the script and each UVM component with configuration information is automatically generated, manual configuration is unnecessary, avoiding errors caused by manual configuration and improving verification accuracy.

[0124] Specific limitations regarding the point-to-point path verification device can be found in the limitations of the point-to-point path verification method described above, and will not be repeated here. Each module in the aforementioned point-to-point path verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independent of the processor, or stored in the processor of the electronic device in software form, so that the processor can call and execute the corresponding operations of each module.

[0125] This disclosure also provides an electronic device. Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Figure 4As shown, the electronic device provided in this embodiment includes a memory 41 and a processor 42. The memory 41 stores computer programs; the processor 42 executes the steps of any embodiment of the point-to-point access verification method for the electronic device provided in the above method embodiments when the computer program is invoked. The electronic device includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the electronic device provides computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. When the computer program is executed by the processor, it implements a point-to-point access verification method for an electronic device. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad provided on the casing of a computer device, or an external keyboard, touchpad, or mouse, etc.

[0126] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. Specific electronic devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0127] In some embodiments, the point-to-point path verification device provided in this disclosure can be implemented in the form of a computer, and the computer program can be implemented in, for example, Figure 4 The computer program, comprised of various program modules, causes the processor to execute the steps in the point-to-point path verification methods of the various embodiments of this disclosure described herein.

[0128] This disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the point-to-point path verification method for the electronic device provided in the above-described method embodiments.

[0129] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code.

[0130] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0131] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0132] Computer-readable media include both permanent and non-permanent, removable and non-removable storage media. Storage media can store information using any method or technology; the information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media do not include transient computer-readable media, such as modulated data signals and carrier waves.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0134] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A point-to-point path verification method, characterized in that, The method includes: Obtain the configuration information of the module to be verified; The configuration information of the module to be verified is written into the verification document, and the verification document is saved as a JSON file; the verification document contains at least one verification test item; each verification test item includes multiple verification test paths; The JSON file is parsed to extract the configuration information of the module to be verified; Based on the preset configuration script, and according to the configuration information, multiple general verification methodology UVM components and UVM incentive files are generated; Based on the UVM environment setup script, the UVM components and the UVM incentive files are integrated into the UVM verification platform; In response to the target verification test command, the UVM verification platform performs tests and verifications on multiple test paths of the target verification test item; the number of the target verification test item is greater than or equal to 1.

2. The method according to claim 1, characterized in that, The configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data, and reference clock source.

3. The method according to claim 2, characterized in that, The process, based on a preset configuration script and the configuration information, generates multiple general verification methodology UVM components and UVM incentive files, including: Input the configuration information into the configuration script to generate multiple UVM components and UVM incentive files containing the configuration information; The UVM components include: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component, and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM components for test verification.

4. The method according to claim 3, characterized in that, In response to the target verification test command, the UVM verification platform performs tests and verifications on multiple test paths of the target verification test item, including: The monitor's function is to collect input and output data from the device under test. In response to the target verification test command, identify at least one path to be tested; The terminal signals of each path under test are acquired through the monitor component; The source signals of each path to be tested are obtained through the reference model component; The scoring board component detects the source and terminal signals of each path under test to determine whether each path under test has been successfully verified.

5. The method according to claim 4, characterized in that, The step of detecting the source and terminal signals of each test path based on the scoring board component to determine whether each test path has been successfully verified includes: If the source signal of the target test path is consistent with the terminal signal of the target test path, then the target test path is determined to have been successfully verified. If the source signal and the terminal signal of the target test path are inconsistent, the verification of the target test path is determined to be unsuccessful.

6. A point-to-point pathway verification device, characterized in that, include: The acquisition module is used to obtain the configuration information of the module to be verified. A configuration module is used to write the configuration information of the module to be verified into a verification document and save the verification document as a JSON file; the verification document contains at least one verification test item; each verification test item includes multiple verification test paths; The parsing module is used to parse the JSON file and extract the configuration information of the module to be verified; The generation module is used to generate multiple general verification methodology UVM components and UVM incentive files based on a preset configuration script and the configuration information. An integration module is used to build scripts based on the UVM environment, integrating the UVM components and the UVM incentive files into the UVM verification platform; The verification module is used to perform test verification on multiple test paths of the target verification test item on the UVM verification platform in response to the target verification test command; the number of the target verification test item is greater than or equal to 1.

7. The apparatus according to claim 6, characterized in that, The configuration information includes: verification module name, verification test item name, source signal, terminal signal, peripheral base address, peripheral offset address, configuration data, and reference clock source.

8. The apparatus according to claim 7, characterized in that, The process, based on a preset configuration script and the configuration information, generates multiple general verification methodology UVM components and UVM incentive files, including: Input the configuration information into the configuration script to generate multiple UVM components and UVM incentive files containing the configuration information; The UVM components include: an environment component, an agent component, a driver component, a monitor component, a reference model component, a scoreboard component, and a test component; the UVM stimulus file is generated based on the peripheral base address and the peripheral offset address, and is used to control the test process based on the UVM components for test verification.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the point-to-point path verification method according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the point-to-point path verification method as described in any one of claims 1 to 5.

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