Integrated circuit simulation method and hybrid simulation system

Abstract

The invention provides an integrated circuit simulation method and a hybrid simulation system. The method comprises the steps that target hardware equipment is simulated through a QEMU simulator, and a standby simulation model is obtained; expanding the number of registers of the hardware model in the Model IP, wherein the expanded hardware model comprises a native hardware register and a newly added hardware register; obtaining a system simulation model based on the to-be-used simulation model and the expanded hardware model; when a simulation request is received, circuit simulation is carried out through the system simulation model; if the simulation request comprises a user-defined analysis instruction, the drive program further accesses the newly-added hardware register through the newly-added simulation equipment register so as to read target monitoring information recorded in the newly-added hardware register. According to the method, the conditions of logic relation change, data type mismatching and the like caused by introduction of a new unpredictable problem during modification of a native code can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit simulation, and in particular to an integrated circuit simulation method and a hybrid simulation system. Background Art

[0002] Software and hardware co-simulation plays a key role in ensuring simulation efficiency, ensuring solution quality, reducing product risks, and saving R&D costs. For example, the technical solution of QEMU (Quick Emulator) and model co-simulation is divided into three parts: Ubuntu Linux system computer, QEMU environment, and RTL Model (Register-Transfer Level Model). During the simulation verification phase, the driver is run in the QEMU environment, and register read and write access / memory data exchange / interrupt processing requirements are sent to the RTL Model. When problems occur during the execution process, the physical device is switched to solve the variable problems that occur during operation.

[0003] However, in the simulation verification stage, the RTL Model has been basically finalized. If the driver wants to obtain some status information or performance statistics that are not originally supported in the RTL Model, it can only modify the Verilog code of the RTL Model, save the new status information or performance statistics to the registers of the RTL Model and map them to the registers of the QEMU environment, and then modify the supporting software to process the register logic of the QEMU environment so that the software driver can read the status and performance information of the RTL Model registers through the registers of the QEMU environment. This method is easy to introduce new unpredictable problems, resulting in changes in logical relationships, data type mismatches, etc. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides an integrated circuit simulation method, which solves the problem in the prior art that when the driver wants to obtain some status information or performance statistics that are not originally supported in the RTL Model, new unpredictable problems are easily introduced, resulting in changes in logical relationships, data type mismatches, etc.

[0005] According to an embodiment of the present invention, a first aspect provides an integrated circuit simulation method, which is applied to a hybrid simulation system, wherein the hybrid simulation system includes a physical computer, a QEMU simulator, and a Model IP, wherein the QEMU simulator and the Model IP run as two processes of the physical computer; the Model IP includes a hardware model based on a target hardware device, and the hardware model has been compiled into an executable file;

[0006] The integrated circuit simulation method comprises:

[0007] The target hardware device is simulated by the QEMU simulator to obtain a standby simulation model; the standby simulation model includes native simulation device registers, newly added simulation device registers and a driver, and the driver is provided with access logic to the newly added simulation device registers;

[0008] Expand the number of registers of the hardware model in the Model IP, the expanded hardware model includes native hardware registers and newly added hardware registers; wherein the newly added hardware registers communicate with the newly added analog device registers, and the native hardware registers communicate with the native analog device registers, and the communication method is the same;

[0009] Obtaining a system simulation model based on the standby simulation model and the expanded hardware model;

[0010] When a simulation request is received, circuit simulation is performed through the system simulation model; wherein, if the simulation request includes a custom analysis instruction, the driver also accesses the newly added hardware register through the newly added analog device register to read the target monitoring information recorded in the newly added hardware register; the target monitoring information is status statistics and / or performance statistics that are not supported by the native hardware register pointed to by the custom analysis instruction.

[0011] Optionally, if the simulation request includes a custom analysis instruction, before accessing the newly added hardware register through the newly added simulation device register, the following steps are included:

[0012] The newly added hardware register is defined according to the target simulation request, so that the newly added hardware register monitors performance indicators corresponding to status information and / or performance statistics not supported by the native hardware register.

[0013] Optionally, when the number of the newly added hardware registers is greater than 1 and the performance indicator includes a plurality of registers, each of the newly added hardware registers is defined so that one newly added hardware register monitors one performance indicator.

[0014] Optionally, the native hardware register is independent of the newly added hardware register, and the native analog device register is independent of the newly added analog device register;

[0015] The native hardware registers are arranged based on the address space of the native simulation device registers, which is the same as or different from the address space arrangement of the newly added hardware registers based on the address space arrangement of the newly added simulation device registers.

[0016] Optionally, if a target simulation request is received, the address space types of the newly added simulation device register and the native simulation device register are also reset.

[0017] Optionally, if the target hardware device is a PCIE device, the communication method between the native hardware register and the native simulation device register, and the communication method between the newly added hardware register and the newly added simulation device register are both implemented based on the RP protocol.

[0018] Optionally, if the target hardware device is an I2C interface device, the communication method between the native hardware register and the native analog device register, and the communication method between the newly added hardware register and the newly added analog device register are both implemented based on the I2C protocol.

[0019] Optionally, if the target hardware device is an SPI interface device, the communication method between the native hardware register and the native analog device register, and the communication method between the newly added hardware register and the newly added analog device register are both implemented based on the SPI protocol.

[0020] Optionally, if the target hardware device is a UART interface device, the communication method between the native hardware register and the native analog device register, and the communication method between the newly added hardware register and the newly added analog device register are both implemented based on the UART protocol.

[0021] A second aspect provides a hybrid simulation system, comprising a physical computer, a QEMU simulator and a Model IP, wherein the QEMU simulator and the Model IP run as two processes of the physical computer; the Model IP comprises a hardware model based on a target hardware device, and the hardware model has been compiled into an executable file;

[0022] The QEMU simulator is used to simulate the target hardware device to obtain a standby simulation model; the standby simulation model includes native simulation device registers, newly added simulation device registers and a driver, and the driver is provided with access logic to the newly added simulation device registers;

[0023] The Model IP is used to expand the number of registers of the hardware model, and the expanded hardware model includes native hardware registers and newly added hardware registers; wherein the newly added hardware registers communicate with the newly added analog device registers, and the native hardware registers communicate with the native analog device registers, and the communication method is the same;

[0024] The standby simulation model and the expanded hardware model serve as system simulation models, and when a simulation request is received, circuit simulation is performed through the system simulation model; wherein, if the simulation request includes a custom analysis instruction, the driver also accesses the newly added hardware register through the newly added analog device register to read the target monitoring information recorded in the newly added hardware register; the target monitoring information is status statistics and / or performance statistics that are not supported by the native hardware register pointed to by the custom analysis instruction.

[0025] The beneficial effects of the present invention are: by adding new analog registers and new hardware registers, new functions such as state detection and performance statistics are realized, and new unpredictable problems are avoided by modifying the Verilog code of the RTL Model, which leads to changes in logical relationships, data type mismatches, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The figure is a schematic diagram of the implementation flow of the integrated circuit simulation method according to an embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram of the structure of a hybrid simulation system according to another embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, an embodiment of the present invention proposes an integrated circuit simulation method, which is applied to a hybrid simulation system. The hybrid simulation system includes a physical computer, a QEMU simulator and a Model IP. The QEMU simulator and the Model IP run as two processes of the physical computer; the Model IP includes a hardware model based on a target hardware device, and the hardware model has been compiled into an executable file.

[0030] It should be noted that Model IP is a reusable circuit design module or functional block, and the hardware model included in the Model IP in the embodiment of the present invention is provided by a third party that produces or sells the target hardware device.

[0031] See also Figure 1 , the integrated circuit simulation method includes but is not limited to the following steps:

[0032] S1. Simulate the target hardware device through the QEMU simulator to obtain a standby simulation model; the standby simulation model includes native simulation device registers, newly added simulation device registers and a driver, and the driver is provided with access logic to the newly added simulation device registers;

[0033] S2. Expand the number of registers of the hardware model in the Model IP, where the expanded hardware model includes native hardware registers and newly added hardware registers; wherein the newly added hardware registers communicate with the newly added analog device registers, and the native hardware registers communicate with the native analog device registers, and the communication methods are the same;

[0034] S3, obtaining a system simulation model based on the standby simulation model and the expanded hardware model;

[0035] S4. When a simulation request is received, circuit simulation is performed through the system simulation model; wherein, if the simulation request includes a custom analysis instruction, the driver also accesses the newly added hardware register through the newly added analog device register to read the target monitoring information recorded in the newly added hardware register; the target monitoring information is status statistics and / or performance statistics that are not supported by the native hardware register pointed to by the custom analysis instruction.

[0036] For the above step S1, a new analog device register is added, mainly in step S3, to read the target monitoring information recorded in the newly added hardware register, that is, the status information and / or performance statistics that are not supported by the native hardware register. This is because the native analog register is used for register access, and the logic in the standby simulation model is fixed, so that the spatial arrangement of the native analog register is also determined, and the register function corresponding to each address is determined. Therefore, when a new access object appears, that is, a newly added hardware register, the embodiment of the present invention reads the newly added analog device register, which is separated from the function of the native analog device register, thereby avoiding a large number of logic modifications in the standby simulation model.

[0037] For example: the address space of 0x0000 to 0x1000 is the native simulation register for register access, and the 0x00 register is the control register, and the 0x04 register is the interrupt register. On this basis, if a new register access is added to the native simulation register, the new register access should be arranged after 0x1000, for example, 0x1000 to 0x2000. This method of obtaining new simulation registers through overall rearrangement will result in a large number of logic modifications.

[0038] For the above step S2, similarly, the hardware model is expanded to obtain new hardware registers, which also avoids a large number of logical modifications to the hardware model to implement the custom analysis instructions.

[0039] For the above step S2, the custom analysis instruction is an instruction formulated by the user according to specific analysis requirements, and the target monitoring information is the status statistics and / or performance statistics that are not supported by the native hardware registers pointed to by the custom analysis instruction. Therefore, after the user formulates the custom analysis instruction according to specific requirements, the embodiment of the present invention defines new hardware registers and new simulation device registers according to the custom analysis instruction, so that the user can obtain target monitoring information, such as operating status (start / stop / abnormal), cache hit rate, instruction execution speed, etc., to meet the user's specific analysis needs, and then intuitively and accurately understand the model operation performance, and help debug and optimize the model.

[0040] In addition, in an embodiment of the present invention, the native hardware registers added in the above steps S1 and S2 are independent of the newly added hardware registers, and the native analog device registers are independent of the newly added analog device registers; the address space arrangement of the native hardware registers based on the native analog device registers is the same as or different from the address space arrangement of the newly added hardware registers based on the newly added analog device registers. Exemplarily, the space in BAR2 is completely independent of the space in BAR0, and the address spaces do not affect each other. The address space of the newly added registers can be arranged arbitrarily, for example, the address space of the newly added registers is arranged as the space of 0x0000 to 0x1000 of BAR2, which does not affect the space of 0x0000 to 0x1000 of BAR0.

[0041] In order to realize the access of the driver to the newly added analog device register in the standby simulation model, the above step S1 customizes the access logic of the driver to the newly added analog device register; in order to realize the communication between the newly added analog device register and the newly added hardware register in the expanded hardware model, in the above step S2, the communication of the newly added hardware register is defined, that is, the communication between the native hardware register and the native analog device register. The function definition of the newly added analog device register and the function definition of the newly added hardware register are implemented before the system simulation model performs circuit simulation when the simulation request in step S4 includes a custom analysis instruction, including:

[0042] The newly added hardware register and the newly added analog device register are defined according to the custom analysis instruction, so that the newly added hardware register and the newly added analog device register monitor and record the target monitoring information.

[0043] In a preferred implementation, when the number of the newly added hardware registers is greater than 1 and the performance index includes multiple ones, each of the newly added hardware registers is defined so that one newly added hardware register monitors one performance index. By designing multiple newly added registers for monitoring different performance indexes, data confusion or inaccuracy is avoided, which helps to accurately analyze the performance of the CPU under different loads of the system.

[0044] For the above step S4, in a specific application, the native analog device registers usually include at least two, and the native hardware registers usually include at least two, one for register access and one for memory exchange. After the newly added hardware registers and the newly added analog device registers are obtained through the above steps S1 and S2, the native analog device registers and the native hardware registers can maintain their original functions, or the function of one of the registers can be modified according to actual conditions before the newly added hardware registers and the newly added analog device registers are needed. Based on this, before the above step S4, it includes:

[0045] If the simulation request includes a custom analysis instruction, the address space types of the newly added simulation device register and the native simulation device register are reset.

[0046] It can be understood that when the simulation request does not include a custom analysis instruction, the driver reads the simulation information and statistical information recorded by the native hardware registers through the native simulation device registers, and outputs the simulation results in combination with the simulation information and statistical information recorded by the native simulation device registers.

[0047] According to the above steps S1 to S4, the embodiment of the present invention implements functions such as new state detection and performance statistics by adding new analog registers and new hardware registers, avoiding the introduction of new unpredictable problems by modifying the Verilog code of the RTL Model, resulting in changes in logical relationships, data type mismatches, etc. This method has the advantages of real-time state performance monitoring, non-invasiveness, and customizability. In practical applications, by adding additional registers specifically for state and performance detection, there are also many benefits to the driver software, such as avoiding modification of the native supporting driver logic, only adding the operation logic of BAR2, decoupling from the original code, clear logic, and when problems occur, only the new logic in the standby simulation model and the expanded hardware model needs to be checked.

[0048] It should be noted that the integrated circuit simulation method provided in the embodiment of the present invention does not limit the type of target hardware device. Here, several types of target hardware devices are proposed and explained as examples. In one embodiment, if the target hardware device is a PCIE device, the communication mode between the native hardware register and the native analog device register, and the communication mode between the newly added hardware register and the newly added analog device register are both implemented based on the RP protocol. In another embodiment, if the target hardware device is an I2C interface device, the communication mode between the native hardware register and the native analog device register, and the communication mode between the newly added hardware register and the newly added analog device register are both implemented based on the I2C protocol. In one embodiment, if the target hardware device is an SPI interface device, the communication mode between the native hardware register and the native analog device register, and the communication mode between the newly added hardware register and the newly added analog device register are both implemented based on the SPI protocol. In another embodiment, if the target hardware device is a UART interface device, the communication mode between the native hardware register and the native analog device register, and the communication mode between the newly added hardware register and the newly added analog device register are both implemented based on the UART protocol.

[0049] like Figure 2 As shown, another embodiment of the present invention provides a hybrid simulation system, including a physical computer 21, a QEMU simulator 22 and a Model IP23, wherein the QEMU simulator 22 and the Model IP23 are run as two processes of the physical computer 21; the Model IP23 includes a hardware model based on a target hardware device, and the hardware model has been compiled into an executable file; the QEMU simulator 22 is used to simulate the target hardware device to obtain a standby simulation model; and the Model IP23 is used to expand the number of registers of the hardware model to obtain an expanded hardware model. The standby simulation model and the expanded hardware model are used as system simulation models to perform integrated circuit simulation.

[0050] In the embodiment of the present invention, the target hardware device is a PCIE device, and the physical computer 21 is an Ubuntu PC. Figure 2Detailed description: The simulation model to be used includes native simulation device registers BAR0 and BAR1, newly added simulation device register BAR2 and driver, and the extended hardware model includes native hardware registers reg_old0 and reg_old1, and newly added hardware registers reg_new1 and reg_new2; among them, BAR0 is used to access reg_old0 and reg_old1, and communication is established based on the RP communication protocol. The newly added hardware registers reg_new1 and reg_new2 are used to implement some status information or performance statistics that are not supported by the native hardware registers reg_old0 and reg_old1. Therefore, the newly added simulation device register BAR2 is used to access the newly added hardware registers reg_new1 and reg_new2, and communication is established based on the RP communication protocol. Among them, the RP protocol uses sockets and shared memory to communicate, which can convert requests / accesses to PCIE into sockets for data transmission and reception; its specific implementation is in the code library libsystemctlm-soc. When a simulation request is received, circuit simulation is performed based on the system simulation model composed of the stand-by simulation model and the expanded hardware model; if the simulation request includes a custom analysis instruction, the driver also accesses the newly added hardware registers through the newly added analog device registers to read the target monitoring information recorded in the newly added hardware registers; the target monitoring information is the status statistics and / or performance statistics that are not supported by the native hardware registers pointed to by the custom analysis instructions.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. An integrated circuit simulation method, characterized in that: Applied to a hybrid simulation system, the hybrid simulation system includes a physical computer, a QEMU simulator and a Model IP, the QEMU simulator and the Model IP run as two processes of the physical computer; the Model IP includes a hardware model based on a target hardware device, and the hardware model has been compiled into an executable file; The integrated circuit simulation method comprises: The target hardware device is simulated by the QEMU simulator to obtain a standby simulation model; the standby simulation model includes native simulation device registers, newly added simulation device registers and a driver, and the driver is provided with access logic to the newly added simulation device registers; Expand the number of registers of the hardware model in the Model IP, the expanded hardware model includes native hardware registers and newly added hardware registers; wherein the newly added hardware registers communicate with the newly added analog device registers, and the native hardware registers communicate with the native analog device registers, and the communication method is the same; Obtaining a system simulation model based on the standby simulation model and the expanded hardware model; When a simulation request is received, circuit simulation is performed through the system simulation model; wherein, if the simulation request includes a custom analysis instruction, the driver also accesses the newly added hardware register through the newly added analog device register to read the target monitoring information recorded in the newly added hardware register; the target monitoring information is status statistics and / or performance statistics that are not supported by the native hardware register pointed to by the custom analysis instruction.

2. The integrated circuit simulation method according to claim 1, wherein: If the simulation request includes a custom analysis instruction, before accessing the newly added hardware register through the newly added simulation device register, the following steps are included: The newly added hardware register is defined according to the target simulation request, so that the newly added hardware register monitors performance indicators corresponding to status information and / or performance statistics not supported by the native hardware register.

3. The integrated circuit simulation method according to claim 2, wherein: When the number of the newly added hardware registers is greater than 1 and the performance indicators include multiple ones, each of the newly added hardware registers is defined so that one newly added hardware register monitors one performance indicator.

4. The integrated circuit simulation method according to claim 1, wherein: The native hardware registers are independent from the newly added hardware registers, and the native analog device registers are independent from the newly added analog device registers; The native hardware registers are arranged based on the address space of the native simulation device registers, which is the same as or different from the address space arrangement of the newly added hardware registers based on the address space arrangement of the newly added simulation device registers.

5. The integrated circuit simulation method according to claim 1, wherein: If a target simulation request is received, the address space types of the newly added simulation device register and the native simulation device register are also reset.

6. The integrated circuit simulation method according to any one of claims 1 to 5, characterized in that: If the target hardware device is a PCIE device, the communication method between the native hardware register and the native simulation device register, and the communication method between the newly added hardware register and the newly added simulation device register are both implemented based on the RP protocol.

7. The integrated circuit simulation method according to any one of claims 1 to 5, characterized in that: If the target hardware device is an I2C interface device, the communication method between the native hardware register and the native simulation device register, and the communication method between the newly added hardware register and the newly added simulation device register are both implemented based on the I2C protocol.

8. The integrated circuit simulation method according to any one of claims 1 to 5, characterized in that: If the target hardware device is an SPI interface device, the communication method between the native hardware register and the native analog device register, and the communication method between the newly added hardware register and the newly added analog device register are both implemented based on the SPI protocol.

9. The integrated circuit simulation method according to any one of claims 1 to 5, characterized in that: If the target hardware device is a UART interface device, the communication method between the native hardware register and the native analog device register, and the communication method between the newly added hardware register and the newly added analog device register are both implemented based on the UART protocol.

10. A hybrid simulation system, characterized in that: It includes a physical computer, a QEMU simulator and a Model IP, wherein the QEMU simulator and the Model IP run as two processes of the physical computer; the Model IP includes a hardware model based on a target hardware device, and the hardware model has been compiled into an executable file; The QEMU simulator is used to simulate the target hardware device to obtain a standby simulation model; the standby simulation model includes native simulation device registers, newly added simulation device registers and a driver, and the driver is provided with access logic to the newly added simulation device registers; The Model IP is used to expand the number of registers of the hardware model, and the expanded hardware model includes native hardware registers and newly added hardware registers; wherein the newly added hardware registers communicate with the newly added analog device registers, and the native hardware registers communicate with the native analog device registers, and the communication method is the same; The standby simulation model and the expanded hardware model serve as system simulation models, and when a simulation request is received, circuit simulation is performed through the system simulation model; wherein, if the simulation request includes a custom analysis instruction, the driver also accesses the newly added hardware register through the newly added analog device register to read the target monitoring information recorded in the newly added hardware register; the target monitoring information is status statistics and / or performance statistics that are not supported by the native hardware register pointed to by the custom analysis instruction.

Images